Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the same, the semiconductor device including: first and second active regions (ARs) respectively included in first and second analog cell regions that abut, a region where the first and third analog cell regions abut (an analog cell boundary (ACB) region) extending from near a top boundary of the first AR to near a bottom boundary of the second AR; via-to-PGBM_1st segment contact structures (VBs) respectively located under the first or second AR, a long axis of each VB and a short axis of each of the first and second ARs having about the same length; and PG segments (PGBM_1st segments) in a first buried metallization (first BM) layer, the PGBM_1st segments located under a substantial portion of each VB, and a Y midline of the PGBM_1st segments located at or near where the first and second analog cell regions abut, thus at or near a middle of the ACB region.

Description

Technical Field

[0001] Embodiments of this application relate to a semiconductor device and a method for forming the same. Background Technology

[0002] The integrated circuit (IC) industry produces a variety of analog and digital semiconductor devices to solve problems in different fields. Advances in semiconductor process technology nodes have gradually reduced component size and narrowed spacing, leading to a gradual increase in transistor density. ICs are becoming increasingly smaller.

[0003] Typically, in IC architecture, guard ring structures are used to provide electrical and / or spatial isolation between adjacent circuit elements. For example, in mixed-signal ICs, guard ring structures are positioned between digital and analog circuit regions, or between digital circuit regions and radio frequency (RF) component regions, to reduce the impact of noise (e.g., carrier injection) from the digital circuit regions on the analog circuit regions or RF component regions. Summary of the Invention

[0004] According to one aspect of an embodiment of this application, a semiconductor device is provided, comprising: 1. a semiconductor device comprising: a first active region and a second active region, namely a first AR region and a second AR region, having a long axis extending in a first direction and correspondingly included in a first analog cell region and a second analog cell region, the first analog cell region and the second analog cell region being adjacent to each other with respect to a second direction perpendicular to the first direction, the region adjacent to the first analog cell region and the second analog cell region being an analog cell boundary region, the analog cell boundary region extending from the top boundary of the first AR to the bottom boundary of the second AR; a pair of gate segments, each pair comprising a collinear first gate segment and a second gate segment correspondingly located above the first AR and the second AR, the first gate segment and the second gate segment extending in the second direction; a metal-to-source / drain region contact structure, namely an MD contact structure, correspondingly located above the first AR and the second AR, and dispersed between the pairs of gate segments. At least some of the MD contact structures are gap-crossing MD contact structures that continuously extend across the gap between the first AR and the second AR to be located above each of the first AR and the second AR; through-hole-to-PGBM_1st segment contact structures, i.e. VB, having a long axis extending in a second direction, the VB being located below the first AR or the second AR respectively, the long axis of each VB and the short axis of each of the first AR and the second AR having the same length; and embedded grid segments in the first embedded metallization layer, i.e. PGBM_1st segments, located below the VB, the PGBM_1st segments overlapping a large portion of the lower layer of each of the VB, the centerline of the PGBM_1st segments relative to the second direction being located at or near the adjoining position of the first analog cell region and the second analog cell region, the centerline of the PGBM_1st segments relative to the second direction being located at or near the middle of the analog cell boundary region.

[0005] According to another aspect of the embodiments of this application, a semiconductor device is provided, comprising: a first active region and a second active region, namely a first AR region and a second AR region, having a long axis extending in a first direction and correspondingly included in a first analog cell region and a second analog cell region, the first analog cell region and the second analog cell region being adjacent to each other with respect to a second direction perpendicular to the first direction, the region adjacent to the first analog cell region and the second analog cell region being an analog cell boundary region, the analog cell boundary region extending from the top boundary of the first AR to the bottom boundary of the second AR; a pair of gate segments, each pair including a collinear first gate segment and a second gate segment correspondingly located above the first AR and the second AR, the first gate segment and the second gate segment extending in the second direction; a first metal-to-source / drain region contact structure, the metal-to-source / drain region being a MD The first metal-to-source / drain region contact structure is a first MD contact structure, correspondingly located above the first AR and the second AR and scattered between pairs of gate segments. At least some of the first MD contact structures are gap-crossing MD contact structures, which continuously extend across the gap between the first AR and the second AR to be located above each of the first AR and the second AR. A feedthrough via extends in a first direction, located in the gap and below the first MD contact structure. The feedthrough via is located at or near the adjoining position of the first analog cell region and the second analog cell region relative to the centerline of the second direction. The feedthrough via is located at or near the middle of the analog cell boundary region relative to the centerline of the second direction. And a buried grid segment in the first buried metallization layer, namely the PGBM_1st segment, is located below the feedthrough via.

[0006] According to another aspect of the embodiments of this application, a method for forming a semiconductor device is provided, the method comprising: forming a first active region and a second active region in a substrate, the first active region being a first active region (AR) and the second active region being a second active region (AR), the first AR and the second AR having a long axis extending in a first direction and correspondingly included in a first analog cell region and a second analog cell region, the first analog cell region and the second analog cell region being adjacent to each other with respect to a second direction perpendicular to the first direction, the region adjacent to the first analog cell region and the second analog cell region being an analog cell boundary region extending from the top boundary of the first AR to the bottom boundary of the second AR; forming a pair of gate segments, each pair including a collinear first gate segment and a second gate segment correspondingly located above the first AR and the second AR, the first gate segment and the second gate segment extending in the second direction; forming a metal-to-source / drain region contact structure to obtain a first workpiece, the metal-to-source / drain region contact structure being an MD contact structure, the MD contact structure correspondingly located above the first AR and the second AR. The formation of an MD contact structure above an AR and between pairs of gate segments includes forming at least some of the MD contact structures as gaps across the MD contact structure, the gaps across the MD contact structure continuously extending across the gap between the first AR and the second AR; forming via-to-PGBM_1st segment contact structures, i.e., VBs, correspondingly located below the first AR or the second AR, the VBs having a long axis extending in a second direction, the long axis of each VB and the short axis of each of the first AR and the second AR having the same length; and forming a buried grid segment in a first buried metallization layer below the VBs, the buried grid segment in the first buried metallization layer being a PGBM_1st segment, the PGBM_1st segment being stacked with a majority of the lower layer of each of the VBs, the centerline of the PGBM_1st segment relative to the second direction being located at or near the position adjacent to the first analog cell region and the second analog cell region, the centerline of the PGBM_1st segment relative to the second direction being located at or near the middle of the analog cell boundary region. Attached Figure Description

[0007] In the accompanying drawings, one or more embodiments are shown by way of example rather than limitation, wherein elements with the same reference numerals denote the same elements throughout. Unless otherwise disclosed, the drawings are not drawn to scale.

[0008] Figures 1A-1B These are corresponding block diagrams of semiconductor devices according to some embodiments.

[0009] Figure 2A , Figure 2D , Figure 2G and Figure 2I-Figure 2T These are corresponding layout diagrams based on some embodiments.

[0010] Figures 2B-2C , Figures 2E-2F and Figure 2H These are corresponding cross-sectional views based on some embodiments.

[0011] Figures 3-4 This is a corresponding flowchart of a method for manufacturing a semiconductor device according to some embodiments.

[0012] Figure 5 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0013] Figure 6 This is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Examples or examples of components, materials, values, steps, operations, arrangements, etc., are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. Other components, materials, values, steps, operations, arrangements, etc., may be considered. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spacing relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing relation terms are intended to include different orientations of the device during use or operation. Devices may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing relation descriptors used herein can be interpreted accordingly. In some embodiments, the term standard cell structure refers to a standardized building block included in a library of various standard cell structures. In some embodiments, various standard cell structures are selected from their library and used as components in layout diagrams representing circuits.

[0016] In some embodiments, the semiconductor device includes two analog cell regions adjacent to each other relative to, for example, the Y-axis (analog-cell boundary (ACB)). The ACB region is included within the larger analog cell region. For example, the larger analog region includes an active analog cell region surrounded by a corresponding guard ring structure, etc. The ACB region includes first and second active regions (ARs), which have long axes extending in a first direction (e.g., parallel to the X-axis), wherein the first and second ARs are correspondingly included within the adjacent first and second analog cell regions. The ACB region extends from below the first AR to below the second AR. In such embodiments, the ACB region includes a buried power grid (PG) segment. The buried PG segment is located at or near the midline (Y-center line) of the second direction (e.g., parallel to the Y-axis), at the location adjacent to the first and second analog cell regions, and the Y-center line of the buried PG segment is located at or near the center (114 / 214A) of the ACB region.

[0017] According to another method, in the corresponding ACB area of ​​the larger corresponding analog area: the layer containing the first AR and the second AR (AR layer) has essentially no electrical grid sections carrying electrical signals / voltages (such as VDD, VSS, etc.) or conductive sections carrying corresponding data signals and / or control signals; and the lower layer below the AR layer has essentially no electrical grid sections carrying electrical signals / voltages (such as VDD, VSS, etc.) or conductive sections carrying corresponding data signals and / or control signals. As a result, according to this other method, the front side of the larger corresponding analog area suffers from wiring congestion because the front side must accommodate electrical grid sections carrying electrical signals / voltages (such as VDD, VSS, etc.) and conductive sections carrying corresponding data signals and / or control signals. As part of the insights that guided the inventors in developing at least some embodiments, the inventors recognized that such empty spaces in some AR areas can be reused to facilitate the use of the back-side electrical grid. More specifically, the inventors recognized that at least some of the ACB regions in the active analog unit region of the larger analog region, and / or other blank spaces in at least some of the ACB regions in some types of guard ring blocks (e.g., the internal guard ring block of the internal guard ring unit region) that include the guard ring structure of the larger analog region, can be reused to facilitate the use of the back-side power grid.

[0018] In some embodiments, some previously unused space within the ACB area is reused for structural purposes, facilitating the use of a back-side electrical grid within the ACB area and thus in the larger analog area. This grid includes sections electrically coupled to power system signals / voltages (such as VDD, VSS, etc.). Using such a structure within the ACB area frees up front-side space in the larger analog area that would otherwise be occupied by grid sections. The space freed up by using the back-side electrical grid reduces front-side wiring congestion, thereby facilitating the conductive sections of wiring carrying corresponding data signals and / or control signals.

[0019] In some embodiments, two adjacent analog cells including the ACB region are located within an active analog block of an analog cell region, wherein the active analog block is surrounded by a guard ring structure, and wherein the guard ring structure is composed of various types of guard ring blocks. In some embodiments, the two adjacent analog cells including the ACB region are pseudo-analog cell regions within an inner guard ring block of an inner guard ring cell region, wherein the inner guard ring block is contained within various types of guard ring blocks including guard ring structures, and wherein the guard ring structure surrounds the active analog block of the analog cell region. In some embodiments, a pseudo-analog cell region is an analog cell region that does not include / does not represent functional circuitry.

[0020] In some embodiments, the semiconductor device has an analog cell boundary (ACB) region having a buried power grid (PG) segment. The semiconductor device includes first and second active regions (ARs) having long axes extending in a first direction (e.g., parallel to the X-axis) and being correspondingly included in the first and second analog cell regions. The ACB region extends from below the first AR to below the second AR. In some such embodiments (e.g., Figure 2A , Figure 2I and Figure 2J The semiconductor device further includes: a via-to-PGNM_1st segment contact structure (VB) having a long axis extending in a second direction perpendicular to the first direction (e.g., parallel to the Y-axis), the VB being correspondingly located below the first AR or the second AR, the long axis of each VB and the short axis of each of the first AR and the second AR having approximately the same length; and a first type of PG segment (PGBM_1st segment) in a first buried metallization (BM_1st) layer, located below the VB, the PGBM_1st segment (first PGMB segment) being located below a large portion of each VB. In some such embodiments (e.g., Figure 2D , Figure 2G , Figure 2K , Figure 2L , Figure 2M and Figure 2NThe semiconductor device also includes: a feedthrough via (FTV) extending in a first direction, located in the gap between the first AR and the second AR and below the MD contact structure; and a second type of PGBM_1st segment located below the FTV.

[0021] The FTV is located at or near the midline (Y-center) of the second direction (e.g., parallel to the Y-axis) adjacent to the first and second analog cell regions, and the Y-center of the FTV is located at or near the center of the ACB region.

[0022] Some embodiments relate to corresponding methods for manufacturing such semiconductor devices.

[0023] Figure 1A This is a block diagram of a semiconductor device 100 according to some embodiments.

[0024] Figure 1B It is a block diagram showing an exploded view of a portion of a semiconductor device 100 according to some embodiments.

[0025] exist Figure 1A In the middle. Semiconductor device 100 includes a guard ring region 101, which includes a guard ring structure correspondingly surrounding active analog blocks 102(1)-102(4). More specifically, in addition to including active analog blocks 102(1)-102(4), guard ring region 101 includes: inner guard ring blocks 104(1)-104(5); vertically adjacent outer guard ring blocks 106(1)-106(6), wherein vertical adjacency is relative to, for example, the Y-axis; horizontally adjacent outer guard ring blocks 108(1)-108(6), wherein horizontal adjacency is relative to, for example, the X-axis; and vertically adjacent and / or horizontally adjacent (i.e., corner) outer guard ring blocks 110(1)-110(4).

[0026] Each of the active analog blocks 102(1)-102(4) includes an analog cell region, which in some embodiments includes one or more feedthrough (FTC) cell regions; see also Figure 1B Each of the inner protective ring blocks 104(1)-104(5) includes one or more inner protective ring unit regions, and in some embodiments, includes one or more FTC unit regions; see also Figure 1BEach of the vertically adjacent outer protective ring blocks 106(1)-106(6) includes one or more vertically adjacent outer protective ring unit areas. Each of the horizontally adjacent outer protective ring blocks 108(1)-108(6) includes one or more horizontally adjacent outer protective ring unit areas. Each vertically adjacent and / or horizontally adjacent (i.e., corner) outer protective ring block 110(1)-110(4) includes one or more vertically adjacent and / or horizontally adjacent (i.e., corner) outer protective ring unit areas.

[0027] exist Figure 1A In the active analog block 102(1), a protective ring structure (relative to the clockwise direction) is surrounded by a protective ring structure, which includes: a corner protective ring block 110(1); horizontally adjacent outer protective ring blocks 108(1) and 108(2); inner protective ring blocks 104(1), 104(3) and 104(2); and vertically adjacent outer protective ring blocks 106(3) and 106(1). The active analog block 102(2) is surrounded by a protective ring structure (relative to the clockwise direction), which includes: horizontally adjacent outer protective ring blocks 108(2) and 108(3); a corner protective ring block 110(2); vertically adjacent outer protective ring blocks 106(2) and 106(4); and inner protective ring blocks 104(4), 104(3) and 104(1).

[0028] The active analog block 102(3) is surrounded by a protective ring structure (relative to the clockwise direction), which includes: vertically adjacent outer protective ring blocks 106(3); inner protective ring blocks 104(2), 104(3) and 104(5); horizontally adjacent outer protective ring blocks 108(5) and 108(4); corner protective ring block 110(3); and vertically adjacent outer protective ring block 106(5). The active analog block 102(4) is surrounded by a protective ring structure (relative to the clockwise direction), which includes: inner protective ring blocks 104(3) and 104(4); vertically adjacent outer protective ring blocks 106(4) and 106(6); corner protective ring block 110(4); horizontally adjacent outer protective ring blocks 108(6) and 108(5); and inner protective ring block 104(5).

[0029] about Figure 1A In some embodiments, the active analog block is surrounded by a guard ring structure to protect the active analog block from noise generated by digital circuit blocks (not shown) even in the digital circuit cell area (not shown) near the outside of the guard ring structure, as discussed below.

[0030] Digital circuits include, for example, field-effect transistors (FETs), such as metal-oxide-semiconductor FETs (MOSFETs). In such digital circuits, the voltage value at the gate terminal of the MOSFET is selectively switched between rails, causing the MOSFET to be substantially completely off or substantially completely on in a binary manner. For example, the voltage value at the gate terminal of the MOSFET is selectively switched between a voltage value equal to a first reference value (Vr, e.g., VDD) and a second reference value (e.g., VSS, Vgnd, etc.). When on, a given portion of the substrate corresponding to the channel of the MOSFET substantially completely depletes most of the carriers in the substrate, such that the given portion of the substrate is called the depletion region, and the corresponding temporary operating mode of the MOSFET is called the depletion mode or saturation mode. When a channel is formed / induced, not only are the majority carriers temporarily depleted in the depletion region, but the minority carriers in the depletion region are also temporarily increased, i.e., the density of minority carriers in the depletion region is temporarily increased, which temporarily forms or induces a conductive channel in the substrate.

[0031] In analog circuits including MOSFETs, the amount of current flowing through the MOSFET, i.e., the degree to which the MOSFET is turned on, varies continuously. This continuous / analog current flow in a MOSFET controlling analog circuits contrasts with the binary current flow in a MOSFET controlling digital circuits. In analog circuits, the transient current flowing through a MOSFET varies continuously and proportionally to the voltage value at the MOSFET's gate terminal (gate voltage), making the corresponding transient operating mode of the MOSFET known as ohmic mode. More specifically, the degree to which the depletion region becomes depleted varies proportionally to the magnitude of the gate voltage, and falls within the range of substantially incomplete depletion to substantially complete depletion. In ohmic mode, the MOSFET gain is sensitive to the potential difference between the gate voltage and the substrate voltage. In ohmic mode, small changes in the substrate voltage can have a large impact on the degree to which the depletion region becomes depleted and therefore the amount of current conducted through the channel.

[0032] Generally, the structure of FETs (such as MOSFETs) is susceptible to the temporary formation of parasitic bipolar junction transistors (BJTs) because, in some cases, binary operation tends to promote carrier injection. In the first case, the binary operation of a FET in a digital circuit results in majority carrier injection, which can temporarily form a vertical parasitic BJT. In the second case, the binary operation of a FET in a digital circuit results in minority carrier injection, which can temporarily form a lateral (horizontal) parasitic BJT. Latch-up is a phenomenon experienced by FETs (such as MOSFETs) as a result of the temporary formation of parasitic BJTs. During latch-up, a low-impedance path is formed between the positive system voltage (e.g., the first reference voltage (Vr)) and the second system reference voltage (e.g., the second reference voltage (Vgnd)), leading to excessive current.

[0033] The temporary formation of parasitic BJTs is a problem in both digital and analog circuits. Furthermore, before carrier injection rises to a level that leads to parasitic BJT formation, carrier injection due to the binary operation of FETs in digital circuits poses additional problems for the operation of FETs in adjacent analog circuits. These additional problems arise from the migration of carriers injected from the digital circuit's FET to the vicinity of the analog circuit's FET in the substrate. The migrated carriers skew the potential difference between the gate voltage of the digital circuit's FET and the voltage value of the substrate near the FET. Similarly, in ohmic mode, small changes in the voltage value of the substrate near the analog circuit's FET can have a large impact on the degree to which the depletion region of the analog circuit's FET becomes depleted, thus significantly affecting the amount of current conducted through the channel of the analog circuit's FET.

[0034] about Figure 1A In other applications, guard ring structures are used to reduce the impact of noise (e.g., carrier injection) from digital circuits on adjacent analog circuits. By surrounding the active analog block of the analog circuit with a guard ring structure, i.e., placing / positioning the active analog block within the guard ring structure, the analog circuitry of the analog cell area of ​​the active analog block is protected from noise (e.g., carrier injection) from adjacent digital circuits (even if outside the guard ring structure).

[0035] again, Figure 1B This is a block diagram showing an exploded view of portions of a semiconductor device 100 according to some embodiments. More specifically, Figure 1B Used as an exploded view of the active simulation block 102(1), and optionally as an exploded view of the inner protective ring block 104(4).

[0036] As part of the insights that guided the inventors in developing at least some embodiments (as discussed above), the inventors recognized that (1) according to another method, other blank spaces in at least some analog cell boundary (ACB) regions in the active analog cell region of a larger analog area and / or (2) according to another method, other blank spaces in at least some ACB regions of some types of protective ring blocks (e.g., internal protective ring blocks of internal protective ring cell regions) that include a protective ring structure of a larger analog area can be reused to facilitate the use of the back-side power grid.

[0037] exist Figure 1B In some embodiments, Figure 1A The active analog blocks 102(1)-102(4) include Figure 1B An example of ACB region 114. Active simulation blocks 102(1)-102(4) correspond to an active simulation block containing an active simulation cell region according to another method. An example of ACB region 114 corresponds to the ACB region of the active simulation cell region within an active simulation block according to another method.

[0038] In some embodiments, Figure 1A The internal protective ring blocks 104(1)-104(5) include Figure 1B An example of ACB region 114. The inner guard ring blocks 104(1)-104(5) correspond to the inner guard ring block of a guard ring structure according to another method, wherein the inner guard ring block according to the other method contains an active analog cell region according to the other method. An example of ACB region 114 corresponds to the ACB region of the cell region within an active analog block according to the other method. In some embodiments, Figure 1A The internal protective ring blocks 104(1)-104(5) represent at least some of the internal protective ring blocks of a protective ring structure including a larger simulation area according to another method.

[0039] Figure 1B This includes cell regions 112(1)-112(4) that are adjacent to each other relative to, for example, the Y-axis. Relative to, for example, the X-axis, cell regions 112(1)-112(4) are substantially aligned. However, for ease of... Figure 1B The unit areas 112(1)-112(4) are visually separated from each other. As a convenient figure, they are shown as unit areas 112(1)-112(4) being slightly offset from each other relative to the X-axis.

[0040] Cell region 112(2) includes boundary regions 115(2) and 115(3). Relative to the Y-axis: boundary region 115(2) includes a first space occupied by active region (AR) 118(1) and a second space between the top boundary of cell region 112(2) and AR 118(1); boundary region 115(3) includes a first space occupied by AR 118(2) and a second space between the bottom boundary of cell region 112(2) and AR 118(2). Cell region 112(3) includes boundary regions 115(4) and 115(5). Relative to the Y-axis: Boundary region 115(4) includes a first space occupied by AR 118(3) and a second space between the top boundary of cell region 112(3) and AR 118(3); and boundary region 115(5) includes a first space occupied by AR 118(4) and a second space between the bottom boundary of cell region 112(3) and AR 118(4). Cell region 112(1) similarly includes boundary region 115(1), etc. Cell region 112(4) similarly includes boundary region 115(6), etc.

[0041] exist Figure 1B In the middle, the ACB region 114 includes boundary regions 115(3) and 115(4). The ACB region 114 is occupied by feedthrough cell (FTC) region 116(2). Figure 1B It also includes FTC regions 116(1) and 116(3). FTC regions 116(1)-116(3) are basically aligned relative to the X-axis. However, for ease of... Figure 1B The FTC regions 116(1)-116(3) are visually separated from each other, and the FTC regions 116(1)-116(3) are shown as slightly offset from each other relative to the X-axis.

[0042] exist Figure 1B In the context of the exploded view used as active analog block 102(1), cell regions 112(1)-112(4) represent active analog cell regions. In some embodiments, the active analog cell region is an analog cell region that includes / represents functional circuitry, for example... Figure 2Q The active analog unit area 246.

[0043] exist Figure 1B In the context of the exploded view used as the internal protective ring block 104(4), Figure 1B In this context, cell regions 112(1)-112(4) represent the inner guard ring cell regions. In some embodiments, the pseudo-analog cell region is an analog cell region that does not include / represents functional circuitry, for example... Figure 2P The pseudo-unit region 244.

[0044] exist Figure 1BIn the FTC region, each of FTC regions 116(1)-116(3) includes a feed through-hole (FTV) 120; see also Figure 2D , Figure 2G , Figure 2I , Figure 2J , Figure 2K , Figure 2L , Figure 2M and Figure 2N In some embodiments, each of the FTC regions 116(1)-116(3) further includes a through-hole to-PGBM_1st segment contact structure (VB); see also Figure 2J In some embodiments, each of FTC zones 116(1)-116(3) does not include FTV 120, but includes VB; see also Figure 2A , Figure 2I and Figure 2K Etc. In some embodiments, each of FTC zones 116(1)-116(3) further includes a via-to-MD (VD) rail; see also Figure 2G , Figure 2J , Figure 2L and Figure 2N wait.

[0045] exist Figure 1B In this embodiment, cell regions 112(1)-112(4) have a height H1 relative to the Y-axis. Similarly, each of the FTC regions 116(1)-116(3) has a height H1. In some embodiments, H1 is greater than about 20 nanometers (nm). In some embodiments, H1 is about 31 nm. In some embodiments, H1 is about 90 nm.

[0046] Figure 2A This is a layout diagram of FTC cell area 216A according to some embodiments.

[0047] Figures 2B-2C Based on some embodiments Figure 2A The layout diagram of the FTC cell region 216A is shown in the corresponding cross sections 221B and 221C of the FTC region in the semiconductor device.

[0048] Figure 2A Use and Figures 1A-1B Similar numbering schemes, although the former uses 2 serial numbers while the latter uses 1. Considering the differences in the mentioned numerical sequences, Figure 2A Zhongyu Figure 1A-Figure 1B Features with similar characteristics use similar numbers. For example, Figure 2A Item 214 in the middle is similar to Figure 1B The ACB region of section 114 in the diagram. The discussion will focus on... Figure 2B Compared to Figure 1A-Figure 1BThe difference lies in the former, not in the similarities between the latter.

[0049] Typically, a layout diagram represents a semiconductor device. The shapes in the layout diagram represent corresponding components within the semiconductor device. The layout diagram itself is a top view. The shapes in the layout diagram are two-dimensional relative to, for example, the X and Y axes, while the semiconductor device represented is three-dimensional. Typically, relative to the Z-axis, a semiconductor device is organized as a stack of layers in which corresponding structures (i.e., to which the corresponding structures belong) are positioned. Therefore, more specifically, each shape in the layout diagram represents a component in a corresponding layer of the corresponding semiconductor device. Typically, a layout diagram represents the relative depth of shapes and layers, i.e., their position along the Z-axis, by superimposing a second shape on a first shape such that the second shape at least partially overlaps the first shape. For simplicity of discussion, i.e., as is advantageous for discussion, the layout diagram (e.g., Figure 2A Some elements in the diagrams (and other layouts disclosed herein) are referred to as appearing to be corresponding structures in the corresponding semiconductor devices rather than patterns / shapes themselves.

[0050] Layout diagrams vary in the amount of detail they represent. In some cases, such as for simplification, selected layers in a layout diagram are combined / abstracted into a single layer. Alternatively and / or additionally, in some cases, not all layers of the semiconductor device are presented; that is, selected layers in the layout diagram are omitted, for example, for the sake of simplicity. Figure 2A The other layout diagrams disclosed herein are examples in which the selected layer is omitted. For example, Figure 2A Other layout diagrams disclosed herein omit: the metallization layer and the corresponding interconnect layer on the front side of the substrate including the active region (AR); and, in addition to the first buried metallization layer (BM_1st), the corresponding interconnect buried layer on the back side of the substrate including the active region (AR). In some embodiments, Figure 2A The layout diagram is a part of the larger layout diagram.

[0051] In addition to FTC cell area 216A Figure 2A It also includes cell regions 212(1) and 212(2) stacked on top of each other relative to a first direction (e.g., a direction parallel to the Y-axis). Cell region 212(1) includes boundary region 215(1). Cell region 212(2) includes boundary region 215(2).

[0052] Cell region 212(1) includes an active region (AR) 218(1), at least half of which is included in a boundary region 215(1) relative to a second direction (Y-axis). Cell region 212(2) includes AR 218(2), at least half of which is included in a boundary region 215(2) relative to a second direction (Y-axis). The major axis of each of AR regions 218(1)-218(2) extends in a first direction (X-axis). AR 218(1) is separated from AR 218(2) by a gap 219 relative to a second direction perpendicular to the first direction (e.g., parallel to the Y-axis).

[0053] exist Figure 2A In the middle, relative to the second direction (Y-axis), ACB region 214 extends from the top boundary of approximately AR 218(1) to the bottom boundary of approximately the second AR 218(2). ACB region 114 is basically occupied by FTC region 216A.

[0054] and Figure 1B The exploded view used as an active simulation block 102(1) is similar to the exploded view used as an internal protective ring block 104(4). Figure 2A Cell regions 212(1)-212(2) represent active analog blocks (e.g., Figure 1A The active simulation cell region in the active simulation block 102(1)-102(2)) and optionally represent the internal guard ring block (e.g. Figure 1A The internal protective ring unit area in the internal protective ring block 104(1)-104(5), etc.

[0055] Cell regions 212(1) and 212(2) include various gate segments 232(x) having a long axis extending along a second direction (Y-axis). Cell region 212(1) includes: gate segments 232(2)_T, 232(3)_T, 232(4)_T, 232(5)_T, and 232(6)_T covering AR 218(1); and portions of gate segments 231(1) and 232(8) covering AR 218(1). Cell region 212(2) includes: gate segments 232(2)_B, 232(3)_B, 232(4)_B, 232(5)_B, and 232(6)_B covering AR 218(2); and portions of gate segments 231(1) and 232(8) covering AR 218(2).

[0056] AR 218(1) and 218(2) have corresponding left and right edges relative to the first direction (X-axis). Gate segment 232(1) is substantially centered above the left edge of each of AR 218(1) and AR 218(2) relative to the first direction (X-axis). Gate segment 232(8) is substantially centered above the right edge of each of AR 218(1) and AR 218(2) relative to the first direction (X-axis).

[0057] Cell regions 212(1) and 212(2) have corresponding left and right edges relative to a first direction (X-axis). In some embodiments, the left edge of cell region 212(1) is at or near the left edge of AR 218(1). In some embodiments, the right edge of cell region 212(1) is at or near the right edge of AR 218(1). In some embodiments, the left edge of cell region 212(2) is at or near the left edge of AR 218(2). In some embodiments, the right edge of cell region 212(2) is at or near the right edge of AR 218(2). In some embodiments, the left edges of cell regions 212(1) and 212(1) are correspondingly centered above gate segment 232(1) or near the center line of gate segment 2321 to the left, relative to the first direction (X-axis). In some embodiments, the right edges of cell regions 212(1) and 212(2) are substantially centered above gate region 232(8) or close to the center line of gate region 232(8) to the right, relative to the first direction (X-axis).

[0058] Gate segments 232(2)_T and 232(2)_B are aligned as a pair of gate segments relative to the first direction (X-axis). Similarly, 232(3)_T and 232(3)_B, 232(4)_T and 232(4)_B, 232(5)_T and 232(5)_B, 232(6)_T and 232(6)_B, and 232(7)_T and 232(7)_B are aligned with their corresponding gate segments. A portion of each component of each pair of gate segments is included in FTC region 216A. In some embodiments, one or more pairs of gate segments 232(2)_T and 232(2)_B, 232(3)_T and 232(3)_B, 232(4)_T and 232(4)_B, 232(5)_T and 232(5)_B, 232(6)_T and 232(6)_B, and 232(7)_T and 232(7)_B are replaced by corresponding gate segments that extend continuously through AR 218(1), gap 219, and AR 218(2).

[0059] exist Figure 2AIn the second direction (Y-axis): the portion of each of the gate segments 232(2)_T, 232(3)_T, 232(4)_T, 232(5)_T, 232(6)_T and 232(7)_T that extends downward by a predetermined distance beyond AR 218(1) into the gap 219 is referred to herein as its gate extension; the portion of each of the gate segments 232(2)_B, 232(3)_B, 232(4)_B, 232(5)_B, 232(6)_B and 232(7)_B that extends upward by a predetermined distance beyond AR 218(2) into the gap 219 is referred to herein as its gate extension. In some embodiments, at least most of gate segments 232(2)_T, 232(3)_T, 232(4)_T, 232(5)_T, 232(6)_T, and 232(7)_T have gate extensions. In some embodiments, at least most of gate segments 232(2)_B, 232(3)_B, 232(4)_B, 232(5)_B, 232(6)_B, and 232(7)_B have gate extensions. In some embodiments, each gate extension facilitates electrical coupling between the gate segment to which it is a part and the lower portion of the corresponding AR. For example, the gate extension facilitates electrical coupling between gate segment 232(2)_T and the lower portion of AR 218(1). In some embodiments, the length of the gate extension, i.e., the predetermined distance by which the gate extension extends beyond the AR in the gap 219, is determined according to the design rules and dimensions of the corresponding semiconductor process technology node for manufacturing semiconductor devices based on FTC region 216A.

[0060] Cell regions 218(1) and 218(2) have corresponding top and bottom edges relative to the second direction (Y-axis). In some embodiments, relative to the second direction (Y-axis), the bottom edge of cell region 212(1) approaches downward to the bottom edge of the gate extensions of gate segments 232(2)_T, 232(3)_T, 232(4)_T, 232(5)_T, 232(6)_T and 232(7)_T. In some embodiments, relative to the second direction (Y-axis), the top edge of cell region 212(2) approaches upward to the top edge of the gate extensions of gate segments 232(2)_B, 232(3)_B, 232(4)_B, 232(5)_B, 232(6)_B and 232(7)_B. In some embodiments where at least most of the gate segments 232(2)_T, 232(3)_T, 232(4)_T, 232(5)_T, 232(6)_T, and 232(7)_T have gate extensions, the boundary (Y-boundary) between cell regions 212(1) and 212(2) relative to the second direction (Y-axis) is approximately located at the midpoint between the bottom edge of AR 218(1) and the top edge of AR 218(2), where the Y-boundary corresponds to the bottom edge of cell 212(1) and the top edge of cell 212(2). In some embodiments, such a Y-boundary represents the middle of ACB region 214 relative to the second direction (Y-axis).

[0061] In some embodiments, one or more instances of gate segments, such as gate segments 232(1) and / or 232(8), are replaced by isolation dummy gates (IDGs) (not shown). An isolation dummy gate, such as one created from an isolation dummy gate pattern (not shown), is a dielectric structure comprising one or more dielectric materials and serving as an electrical isolation structure. Therefore, the isolation dummy gate is not a conductive structure and thus does not function as, for example, the gate electrode of an active transistor. In some embodiments, the isolation dummy gate is referred to as a dielectric gate structure. In some embodiments, the isolation dummy gate is an example of a structure included in a CPODE layout scheme. In some embodiments, CPODE is an abbreviation for continuous poly ondiffusion edge. In some embodiments, CPODE is an abbreviation for continuous poly onoxide definition edge. In some embodiments, the isolation dummy gate is based on a gate structure as a precursor. In some embodiments, an isolation dummy gate is formed by: first forming a gate structure (e.g., a dummy gate structure), sacrificing / removing (e.g., etching) the gate structure to form a trench, (optionally) removing a portion of the substrate previously under the gate structure to deepen the trench, and then filling the trench with one or more dielectric materials such that the physical dimensions of the resulting electrically isolated structure (i.e., the isolation dummy gate) are similar to the dimensions of the sacrificed precursor (i.e., the gate structure or a combination of the gate structure and a portion of the substrate).

[0062] exist Figure 2A In the cell region 212(1), the corresponding portions of AR 218(1) are particularly covered by metal-to-source / drain (MD) contact structures 234(2), 234(3), 234(4), 234(5), 234(6), 234(7), and 234(8). The cell region 212(2) is particularly covered by the corresponding portions of AR 218(2) of the MD contact structures 234(2), 234(3), 234(4), 234(5), 234(6), 234(7), and 234(8). Figure 2A It also includes an MD contact structure 234(1) located to the left of the MD contact structure 234(2) and an MD contact structure 234(9) located to the right of the MD contact structure 234(8). The major axis of each of the MD contact structures 234(1)-234(9) extends in the second direction (Y-axis). A portion of each of the MD contact structures 234(1)-234(9) is included in the FTC region 216A.

[0063] Each of the MD contact structures 234(1)-234(9) is a gap-crossing MD contact structure that extends continuously across the gap 219. In some embodiments, not all MD contact structures 234(1)-234(9) are gap-crossing MD contact structures; see [link to relevant documentation]. Figure 2D , Figure 2G wait.

[0064] Relative to the first direction (X-axis), MD contact structures 234(1)-234(9) are distributed in pairs of gate segments. For example, relative to the first direction (X-axis), MD contact structure 234(4) is located between a pair of gate segments 232(3)_T and 232(3)_B and a pair of gate segments 232(4)_T, 232(4)_B.

[0065] exist Figure 2A In this FTC cell 216A, a via-to-gate contact structure (VG) 236 is also included, which is substantially (relative to the first direction (X-axis)) centered above the gate segments 232(2)_T, 232(3)_T, 232(4)_T, 232(5)_T, 232(6)_T, 232(7)_T, 232(2)_B, 232(3)_B, 232(4)_B, 232(5)_B, 232(6)_B, and 232(7)_B. An example of the VG 236 above the gate segments 232(2)_T, 232(3)_T, 232(4)_T, 232(5)_T, 232(6)_T, and 232(7)_T is in cell region 212(1). An example of VG 236 above gate segments 232(2)_B, 232(3)_B, 232(4)_B, 232(5)_B, 232(6)_B and 232(7)_B is in cell segment 212(2). Figure 2A Each instance of VG 236 in the array does not overlap with each of AR218(1) and 218(2). Relative to the proximal side of the gap 219 near each of AR 218(1) and 218(2), Figure 2A Each instance of VG 236 in the middle is located on the far side of AR 218(1) or 218(2) away from the gap 219.

[0066] There are no instances of VG 236 on gate segments 232(1) and 232(8). In some embodiments, instances of VG 236 are located at... Figure 2A The different locations are shown. In some embodiments, the number of instances of VG 236 differs. Figure 2A As shown.

[0067] FTC unit 216A also includes a via-to-MD contact structure (VD) 238 that is substantially centered above the MD contact structures 234(3)-234(7) in a first direction (X-axis). Three instances of VD 238 are located above each of the MD contact structures 234(3), 234(5), and 234(7). With respect to each of the MD contact structures 234(3), 234(5), and 234(7), one instance of VD 238 is located above AR 218(1), one instance of VD 238 is located above gap 219, and one instance of VD 238 is located above AR 218(2). Four instances of VD 238 are located above each of the MD contact structures 234(4) and 234(6). For each of the MD contact structures 234(4) and 234(6), one instance of VD 238 is above AR 218(1), two instances of VD 238 are above gap 219, and one instance of VD 238 is above AR 218(2). The three instances of VD 238 are partially located in each of units 212(1)-212(2).

[0068] There are no instances of VD 238 above the MD contact structures 234(1), 234(2), 234(8), and 234(9). In some embodiments, instances of VD 238 are located with... Figure 2A The different locations are shown. In some embodiments, the number of instances of VD 238 is... Figure 2A The difference is shown.

[0069] exist Figure 2A In the gap 219, some instances of VD 238 are located within the gap 219. Among the instances of VD 238 in the gap 219, some instances are substantially equidistant from the bottom edge of AR 218(1) and the top edge of AR 218(2) relative to the second direction (Y-axis), examples of which include: instances of VD 238 in the gap 219 above MD contact structure 234(3); instances of VD 238 in the gap 219 above MD contact structure 234(5); and instances of VD 238 in the gap 219 above MD contact structure 234(3).

[0070] In some embodiments, the boundary (Y-boundary) between cell regions 212(1) and 212(2) relative to the second direction (Y-axis) intersects an instance of VD 238 in gap 219, which is substantially equidistant between the bottom edge of AR 218(1) and the top edge of AR 218(2), wherein the Y-boundary corresponds to the bottom edge of cell 212(1) and the top edge of cell 212(2). In some embodiments, instances of VD 238 in gap 219 that are substantially equidistant between the bottom edge of AR 218(1) and the top edge of AR 218(2) are also substantially centered on the Y-boundary between cell regions 212(1) and 212(2). In some embodiments, such a Y-boundary represents the middle of ACB region 214 relative to the second direction (Y-axis). In instances of VD 238 in gap 219, some (1) are above a common MD contact structure and (2) are substantially equidistant from the Y-boundary between cell regions 212 (1) and 212 (2) relative to the second direction (Y-axis). Examples include: instances of VD 238 in gap 219 above MD contact structure 234 (4); and instances of VD 238 in gap 219 above MD contact structure 234 (6). In some embodiments, such a Y-boundary represents the center of ACB region 214 relative to the second direction (Y-axis).

[0071] exist Figure 2A In this FTC unit 216A, there are also through-hole to-PGBM_1st segment contact structures (VB) 228(1)-228(6), each of which has a long axis extending in a second direction (Y-axis). VB 228(1)-228(3) are in unit area 212(1) and below AR 218(1). VB 228(4)-228(6) are in unit area 212(2) and below AR 218(2). Relative to the first direction (X-axis): VB 228(1) and 228(4) are aligned with MD contact structure 234(3); VB 228(2) and 228(5) are aligned with MD contact structure 234(5); and VB 228(3) and 228(6) are aligned with MD contact structure 234(7). Each of VB 228(1)-228(6) is also basically under the corresponding instance of VD238.

[0072] Relative to the second direction (Y-axis), the length of the major axis of each of VB 228(1)-228(3) is approximately the same as the length of the minor axis of AR 218(1). Relative to the second direction (Y-axis), the length of the major axis of each of VB 228(4)-228(6) is approximately the same as the length of the minor axis of AR 218(2). In some embodiments, the length of the major axis of each of VB 228(1)-228(6) is approximately the same as the length of the minor axis of each of AR 218(1)-218(2) relative to the second direction (Y-axis).

[0073] No instances of VB are found on MD contact structures 234(1), 234(2), 234(8), and 234(9). In some embodiments, VB 228(4)-228(6) are located with Figure 2A The different locations are shown. In some embodiments, the number of VB instances is... Figure 2A The difference is shown.

[0074] exist Figure 2A In this embodiment, FTC cell 216A also includes a PG segment (PGBM_1st segment) 230A in a first buried metallization (BM_1st) layer located below VB. In some embodiments, according to the numbering convention of the corresponding process node for manufacturing semiconductor devices based on FTC region 216A, the BM_1st layer is buried metallization layer zero BM0 or buried metallization layer one BM1, and correspondingly, the first layer (not shown) of the buried interconnect BV_1st is BVIA0 or BVIA1. Figure 2A In the other layout diagrams disclosed herein, it is assumed that BM_1st is BM0 and that BV_1st is VIA0.

[0075] Relative to the second direction (Y-axis): at least a majority of the underlap of each of PGBM_1st segment 230A and VB 228(1)-228(6); and substantially co-exists with ACB region 214 except for a first non-underlapped region between the top edge of PGBM_1st segment 230A and the top boundary of AR 218(1) and a second non-underlapped region between the bottom edge of PGBM_1st segment 230A and the bottom edge of AR 216(2). In some embodiments, relative to the second direction (Y-axis), PGBM_1st segment 230A substantially co-exists with ACB region 214, i.e., PGBM_1st segment 230A substantially does not present non-underlapped regions relative to AR 218(1)-218(2), such as the corresponding first and second non-underlapped regions mentioned above. In some embodiments, ACB area 214 is described as having an embedded PG segment, namely PGBM_1st segment 230A.

[0076] exist Figure 2A In this design, the shape of PGBM_1st segment 230A resembles a cross having a major axis extending in a first direction (X-axis) and a minor axis extending in a second direction (Y-axis). The cross shape of PGBM_1st segment 230A has a central portion, referred to herein as the trunk portion, from which top arms, bottom arms, and left and right arms extend. Relative to the second direction (Y-axis), the top and bottom arms of the cross shape of PGBM_1st segment 230A extend parallel to the minor axis of PGBM_1st segment 230A. Relative to the first direction (X-axis), the left and right arms of the cross shape of PGBM_1st segment 230A extend parallel to the major axis of PGBM_1st segment 230A. Relative to the top, bottom, left, and right arms, the cross shape of PGBM_1st segment 230A has a central portion referred to herein as the trunk portion.

[0077] Relative to the first direction (X-axis) and the second direction (Y-axis): the cross-shaped top arm of the PGBM_1st segment 230A is stacked with the gate segments 232(2)_T, 232(3)_T, 232(4)_T, 232(5)_T, 232(6)_T and 232(7)_T and the MD contact structure 234(2)-234(8); and the cross-shaped bottom arm of the PGBM_1st segment 230A is stacked with the gate segments 232(2)_B, 232(3)_B, 232(4)_B, 232(5)_B, 232(6)_B and 232(7)_B and the MD contact structure 234(2)-234(8).

[0078] Relative to the first direction (X-axis): the left arm of PGBM_1st segment 230A is stacked under the gate segment 232(1) and MD contact structure 234(1); and the right arm of PGBM_1st segment 230A is stacked under the gate segment 232(8) and MD contact structure 234(9).

[0079] In some embodiments, the left arm of PGBM_1st segment 230A is compared to Figure 2A The diagram shows a further leftward extension beyond the MD contact structure 234(1). In some embodiments, the right arm of the PGBM_1st segment 230A is longer than... Figure 2A The diagram shows a further rightward extension beyond the MD contact structure 234(9).

[0080] The cross-shaped body of the PGBM_1st segment 230A is stacked with the MD contact structure 234(2)-234(8) below. The cross-shaped body of the PGBM_1st segment 230A is basically not stacked with the gate segments 232(1), 232(2)_T and 232(2)_B, 232(3)_T and 232(3)_B, 232(4)_T and 232(4)_B, 232(5)_T and 232(5)_B, 232(6)_T and 232(6)_B, 232(7)_T and 232(7)_B and 232(8) below.

[0081] exist Figure 2A In some embodiments, the midline (Y-center line) of the PGBM_1st segment 230A relative to the second direction (Y-axis) is located or near the boundary (Y-boundary) between unit regions 212(1) and 212(2) relative to the second direction (Y-axis). In some embodiments, the Y-boundary corresponds to the bottom edge of unit 212(1) and the top edge of unit 212(2). In some embodiments, the Y-center line of the PGBM_1st segment 230A represents the middle of the ACB region 214 relative to the second direction (Y-axis).

[0082] about Figure 2B Section 221B corresponds to Figure 2A The cross-section line 2B-2B' in the middle. Regarding... Figure 2C Section 221C corresponds to Figure 2A The cross-section line 2C-2C' in the middle.

[0083] exist Figure 2B In this embodiment, AR 218(1) includes source / drain (S / D) regions 222(1) and 222(2) in AR 218(2). Each of the S / D regions 222(1) and 222(2) has a second concentration of positive (P-type) and / or negative (N-type) dopants, different from the first concentration, relative to the initial (first) concentration of positive (P-type) and / or negative (N-type) dopants originally present in the non-S / D regions of AR 218(1). The region 224 between the source / drain (S / D) regions 222(1) and 222(2), and the gate segment 232(2) together constitute transistor 226, where region 224 represents the reversible region commonly referred to as the channel region. In some embodiments, transistor 226 is a FET. In some embodiments, transistor 226 is more specifically a MOSFET. In some embodiments, transistor 226 is a transistor type other than a FET.

[0084] about Figure 2BAR is not present in gap 219, that is, neither AR 218(1) nor AR218(2) is present in gap 219. Therefore, relative to a third direction (e.g., Z-axis) perpendicular to each of the first direction (X-axis) and the second direction (Y-axis), Figure 2B The layer occupied by AR 218(1) in Figure 2C The middle part is shown as substrate 217.

[0085] exist Figure 2B In the middle, section 221B also includes a conductive segment 240(1) (M_1st segment) in the first metallization (M_1st) layer. The M_1st segment 240(1) is above the instance of VD 238. The major axis of the M_1st segment 240(1) extends in the second direction (Y-axis), similar to the major axis of the MD contact structure 234(4). The M_1st segment 240(1) is substantially collinear with the MD contact structure 234(3).

[0086] exist Figure 2C In the middle section 221C, there is also an M_1st segment 240(2) located above the instance of VD 238. The major axis of the M_1st segment 240(2) extends in a second direction (Y-axis), similar to the major axis of the MD contact structure 234(4). The M_1st segment 240(2) is substantially collinear with the MD contact structure 234(3). In some embodiments, the M_1st segments 240(1) and 240(2) are portions of a longer M_1st segment.

[0087] In some embodiments, according to the numbering convention for corresponding process nodes in manufacturing semiconductor devices based on cross-sections 216B and 216C, the M_1st layer is metallization layer 0, M0 or metallization layer 1, M1, and correspondingly, the first layer (not shown) of interconnect V_1st is VIA0 or VIA1. Figures 2B-2C In the other sections disclosed herein, it is assumed that M_1st is M0 and V_1st is VIA0.

[0088] about Figures 2A-2C Examples of size ranges include the following. The dimensions are normalized relative to VG 236, where VG 236 has a width W_VG relative to a first direction (X-axis) and a height H_VG relative to a second direction (Y-axis). Typically, VG 236 is essentially a square.

[0089] In some embodiments, each of AR 218(1)-218(2) has a height H_AR within the range of (≈((8 / 3)*H_VG)) ≤ H_AR ≤ (≈((29 / 6)*H_VG)) relative to the second direction (Y-axis). The dimensions of AR 218(1)-218(2) are proportional to the dimensions of the corresponding cell regions 202(1)-202(2) relative to the first direction (X-axis).

[0090] In some embodiments, relative to the first direction (X-axis), each of the gate segments 232(1), 232(2)_T and 232(2)_B, 232(3)_T and 232(3)_B, 232(4)_T and 232(4)_B, 232(5)_T and 232(5)_B, 232(6)_T and 232(6)_B, 232(7)_T and 232(7)_B and 232(8) has the following width W_GS1: W_GS1≈((1 / 4)*W_VG).

[0091] Relative to the first direction (X-axis), the distance between two adjacent gate segments in gate segments 232(1), 232(2)_T and 232(2)_B, 232(3)_T and 232(3)_B, 232(4)_T and 232(4)_B, 232(5)_T and 232(5)_B, 232(6)_T and 232(6)_B, 232(7)_T and 232(7)_B, and 232(8) is uniform and approximately 1.0 CPP, where CPP is a unit of distance measurement. In some embodiments, CCP is an abbreviation for contacted poly pitch. The value of CPP is determined by the design rules and dimensions of the corresponding semiconductor process technology node. In an embodiment such as W_GS≈((1 / 4)*W_VG), an example of CPP is as follows: CPP≈(4*W_VG).

[0092] In some embodiments, each of the MD contact structures 234(1)-234(9) has a width V_MD as follows relative to the first direction (X-axis): W_MD≈((4 / 3)*W_VG).

[0093] In some embodiments, each VD 238 has a width V_VD relative to the first direction (X-axis) as follows: ((13 / 12)*W_VG)≈W_VD. In such embodiments, each VD 238 has a height H_VD relative to the second direction (Y-axis) as follows: ((13 / 12)*H_VG)≈H_VD.

[0094] In some embodiments, each of VB 228(1)-228(6) has a height H_VB within the following range relative to the second direction (Y-axis): (≈((8 / 3)*W_VG))≤W_VB≤(≈((29 / 6)*H_VG)). In some embodiments, H_VB≈H_AR.

[0095] Figure 2D This is a layout diagram of FTC cell region 216D according to some embodiments.

[0096] Figures 2E-2F Based on some embodiments Figure 2D The layout diagram of the FTC cell region 216D is shown in the corresponding cross sections 221E and 221F of the FTC region in the semiconductor device. Regarding... Figure 2E Section 221E corresponds to Figure 2D The cross-section line 2E-2E' in the middle. Regarding... Figure 2F Section 221F corresponds to Figure 2D The cross-section line 2F-2F' in the middle.

[0097] Figures 2D-2F Correspondingly similar to Figures 2A-2C The discussion will focus on Figures 2D-2F Relative to the corresponding Figures 2A-2C The difference lies in the former, not in the similarities between the latter.

[0098] and Figure 2A The PGBM_1st segment 230A is different. Figure 2D The PGBM_1st segment 230A is rectangular. Therefore, in some embodiments, Figure 2D The PGBM_1 segment 230A is described as having Figure 2A The cross-shaped torso and left and right arms of PGBM_1st segment 230A, but excluding... Figure 2A The PGBM_1st segment 230A has a cross-shaped top arm and bottom arm. Relative to the second direction (Y-axis), there is a gap between the top edge of the PGBM_1st segment 230D and the bottom edge of AR 218(1), and a gap between the bottom edge of the PGBM_1st segment 230D and the top edge of AR 218(2). In some embodiments, the PGBM_1st segment 230D is described as not overlapping each of the lower layers in AR 218(1) and 218(2).

[0099] exist Figure 2DIn some embodiments, the midline (Y-center) of the PGBM_1st segment 230D relative to the second direction (Y-axis) is located or near the boundary (Y-boundary) between unit regions 212(1) and 212(2) relative to the second position (Y-axis). In some embodiments, the Y-boundary corresponds to the bottom edge of unit 212(1) and the top edge of unit 212(2). In some embodiments, the Y-center of the PGBM_1st segment 230D represents the center of ACB region 214 relative to the second direction (Y-axis).

[0100] and Figure 2A Unlike the FTC 216A, Figure 2D The FTC 216 does not include VB 228(1)-228(6). Instead, it includes a feed through-hole (FTV) 220. The FTV 220 is in the gap 219 and above the PGBM_1 section (230D). The FTV 220 has a long axis extending in a first direction (X-axis).

[0101] exist Figure 2D In the FTC region 216, MD contact structures 234(10)-234(13) are also included.

[0102] Figure 2A The MD contact structure 234(4) has been replaced by its shorter version (i.e., MD contact structure 234(4)') in combination with MD contact structures 234(10) and 234(12). MD contact structures 234(4)', 234(10) and 234(12) are substantially collinear. Figure 2A The MD contact structure 234(6) has been replaced by its shorter version (i.e., MD contact structure 234(6)') in combination with MD contact structures 234(11) and 234(13). MD contact structures 234(6)', 234(11) and 234(13) are substantially collinear.

[0103] Relative to the second direction (Y-axis), and with Figure 2A Compared to contact structures 234(4) and 234(6), MD contact structures 234(4)' and 234(6)' overlap with AR 218(1), but do not extend beyond the bottom edge of AR 218(2) into the gap 219. Relative to the second direction (Y-axis), and with... Figure 2A Compared to the portion of contact structures 234(4) and 234(6) within unit region 212(2), MD contact structures 234(12) and 234(13) overlap with AR 218(2), but do not extend beyond the top edge of AR 218(3) into gap 219.

[0104] MD contact structures 234(10) and 234(11) are located above FTV 220. Each of MD contact structures 234(10) and 234(11) overlaps with FTV 220 relative to the second direction (Y-axis), but does not extend beyond the top or bottom edge of FTV 220.

[0105] about Figures 2D-2F Not with Figures 2A-2C Examples of shared component size ranges include the following. Again, regarding VG 236, sizes are normalized.

[0106] In some embodiments, relative to the second direction (Y-axis), FTV 220 has a height H_FTV within the following range: (≈((5 / 3)*H_VG))≤H_FTV≤(≈((10 / 3)*H_VG)). In some embodiments, H_FTV≈((31 / 12)*H_VG).

[0107] In some embodiments, the width of FTV 220 is sufficient to overlap with MD contact structures 234(3), 234(10), 234(5), 234(11), and 234(7) relative to the first direction (X-axis). In some embodiments, FTV 220 has sufficient width relative to the first direction (X-axis) to extend substantially to the left of MD contact structure 234(3) to (or beyond) the left edge of MD contact structure 234(2), or additionally substantially to the left of MD contact structure 234(2) to (or beyond) the left edge of MD contact structure 234(1), etc. In some embodiments, FTV 220 has sufficient width relative to the first direction (X-axis) to extend substantially to the right of MD contact structure 234(7) to (or beyond) the right edge of contact structure 234(8), or additionally substantially to the right of MD contact structure 234(8) to (or beyond) the right edge of MD contact structure 234(9), etc.

[0108] exist Figure 2D In some embodiments, the centerline (Y-centerline) of FTV 220 relative to the second direction (Y-axis) is located or near the boundary (Y-boundary) between unit regions 212(1) and 212(2) relative to the second direction (Y-axis). In some embodiments, the Y-boundary corresponds to the bottom edge of unit 212(1) and the top edge of unit 212(2). In some embodiments, the Y-centerline of FTV 220 represents the center of ACB region 214 relative to the second direction (Y-axis).

[0109] exist Figure 2DIn the gap 219, some instances of VD 238 are located in the gap 219 and are substantially equidistant from the bottom edge of AR 218(1) and the top edge of AR218(2) relative to the second direction (Y-axis). Examples of VD 238 include: instances of VD 238 located above MD contact structure 234(3) in the gap 219; instances of VD 238 located above MD contact structure 234(10) in the gap 219; instances of VD 238 located above MD contact structure 234(5) in the gap 219; instances of VD 238 located above MD contact structure 234(11) in the gap 219; and instances of VD 238 located above MD contact structure 234(3) in the gap 219.

[0110] In some embodiments, the boundary (Y-boundary) between cell regions 212(1) and 212(2) relative to the second direction (Y-axis) intersects with an instance of VD 238 in gap 219, the instance being substantially equidistant between the bottom edge of AR 218(1) and the top edge of AR 218(2), wherein the Y-boundary corresponds to the bottom edge of cell 212(1) and the top edge of cell 212(2). In some embodiments, the instances of VD 238 in gap 219 that are substantially equidistant between the bottom edge of AR 218(1) and the top edge of AR 218(2) are also substantially centered on the Y-boundary between cell regions 212(1) and 212(2). In some embodiments, such a Y-boundary represents the center of ACB region 214 relative to the second direction (Y-axis).

[0111] exist Figure 2E In the middle, section 221E also includes an M_1st segment 240(3) located above the instance of VD 238. The major axis of the M_1st segment 240(3) extends in the second direction (Y-axis), similar to the major axis of the MD contact structure 234(4)'. The M_1st segment 240(3) is substantially collinear with the MD contact structure 234(3)'.

[0112] exist Figure 2F In the section 221F, section 221F also includes M_1st segments 240(4) and 240(5) located above the corresponding instance of VD 238. The major axis of M_1st segment 240(4) extends in a second direction (Y-axis), similar to the major axis of MD contact structure 234(3). The major axis of M_1st segment 240(5) extends in a second direction (Y-axis), similar to the major axis of MD contact structure 234(10). M_1st segment 240(4) is substantially collinear with MD contact structure 234(3). M_1st segment 240(5) is substantially collinear with MD contact structure 234(10). In some embodiments, M_1st segments 240(3) and 240(5) are portions of a longer M_1st segment.

[0113] Figures 2E-2F Each of the gate segments 233(2) is shown with a dashed line (dashed line). Gate segment 233(3) is about Figures 2M-2N And it represents a variation of gate segment 232(3).

[0114] Figure 2G This is a layout diagram of FTC cell area 216G according to some embodiments.

[0115] Figure 2H Based on some embodiments Figure 2G The layout diagram of the FTC cell region 216G is shown in the cross section 221H of the FTC region in the semiconductor device. Regarding... Figure 2H Section 221H corresponds to Figure 2G The cross-section line 2H-2H' in the diagram is similar to... Figure 2D , Figure 2G The cross-section line E-E' in the middle corresponds to Figure 2E The cross section is 221E.

[0116] Figures 2G-2H Correspondingly similar to Figure 2D and Figure 2F The discussion will focus on Figure 2G and Figure 2H Relative to the corresponding Figure 2D and Figure 2F The difference lies in the former, not in the similarities between the latter.

[0117] Compared to Figure 2D FTC216D, Figure 2G The FTC26G also includes a through-hole to-MD (VD) track (VDR) 242. VDR 242 is located in gap 219 and above the PGBM_1st segment (230D). The long axis of VDR 242 extends in a first direction (X-axis). Relative to a second direction (Y-axis), VDR 242 is substantially centered on FTV 220. Figure 2G In China, based on Figure 2G Compared to Figure 2D Due to the similarity, VDR 242 replaces the instance of VD 238 that would otherwise be essentially in gap 219.

[0118] exist Figure 2GIn some embodiments, the centerline (Y-centerline) of VDR 242 relative to the second direction (Y-axis) is located or near the boundary (Y-boundary) between unit regions 212(1) and 212(2) relative to the second direction (Y-axis). In some embodiments, the Y-boundary corresponds to the bottom edge of unit 212(1) and the top edge of unit 212(2). In some embodiments, the Y-centerline of FTV 220 represents the center of ACB region 214 relative to the second direction (Y-axis).

[0119] Figure 2H Gate segment 233(3) is shown as an imaginary line (dashed line). Gate segment 233(3) is about Figure 2N And it represents a variation of gate segment 232(3).

[0120] exist Figure 2G In the middle, relative to the second direction (Y-axis), the height (H_VDR) of VDR 242 is almost the same as the height H_FTV.

[0121] exist Figure 2H In the section 221H, there are also M_1st segments 240(6) and 240(7) located above the corresponding instance of VD 238. The major axis of M_1st segment 240(6) extends in the second direction (Y-axis), similar to the major axis of MD contact structure 234(3). The major axis of M_1st segment 240(7) extends in the second direction (Y-axis), similar to the major axis of MD contact structure 234(10). M_1st segment 240(6) is substantially collinear with MD contact structure 234(3). M_1st segment 240(7) is substantially collinear with MD contact structure 234(10). In some embodiments, M_1st segments 240(3) and 240(7) are portions of a longer M_1st segment.

[0122] about Figures 2G-2H Not with Figures 2A-2F Examples of shared component size ranges include the following. Again, regarding VG 236, sizes are normalized.

[0123] In some embodiments, the height (H_VDR) of VDR 242 is within the following range: (≈((5 / 6)*H_VG))≤H_VDR≤(≈(5*H_VG)). In some embodiments, H_VDR≈2*H_VG.

[0124] exist Figure 2GIn some embodiments, VDR 242 has sufficient width relative to the first direction (X-axis) such that the left edge of VDR 242 is substantially aligned with the left edges of the corresponding gate segments 232(2)_T and 232(1)_B. In some embodiments, VDR 242 has sufficient width relative to the first direction (X-axis) such that the right edge of VDR 242 is substantially aligned with the right edges of the corresponding gate segments 232(7)_T and 232(7)_B.

[0125] In some embodiments, the VDR 242 has sufficient width relative to the first direction (X-axis) to extend substantially to the left of the left edge of the corresponding gate segments 232(2)_T and 232(2)_B to (or beyond) the left edge of the MD contact structure 234(2), or additionally substantially to the left of the gate segment 232(1) to (or beyond) the left edge of the MD contact structure 234(1), and so on.

[0126] In some embodiments, the VDR 242 has sufficient width relative to the first direction (X-axis) to extend substantially to the right of the right edge of the corresponding gate segments 232(7)_T and 232(7)_B to (or beyond) the right edge of the MD contact structure 234(8), or additionally substantially to the right of the gate segment 232(8) to (or beyond) the right edge of the MD contact structure 234(9), and so on.

[0127] Figure 2I This is a layout diagram of FTC cell region 216I according to some embodiments.

[0128] Figure 2I Similar to Figure 2A And to a lesser extent similar to Figure 2D .about Figure 2I The cross-section line 2B-2B' corresponds to Figure 2B The section line 2F-2F' corresponds to the attached Figure 2F The discussion will focus on Figure 2I Compared to Figure 2A The difference lies in the former, not in the similarities between the latter.

[0129] Compared to Figure 2D FTC cell region 216A, Figure 2I The FTC cell region 216I also includes Figure 2D FTV 220.

[0130] Figure 2J This is a layout diagram of FTC cell area 216J according to some embodiments.

[0131] Figure 2J Similar to Figure 2I .about Figure 2J The cross-section line 2B-2B' corresponds to Figure 2B The cross-sectional line 2H-2H' corresponds to the attached Figure 2H The discussion will focus on Figure 2J Compared to Figure 2I The difference lies in the former, not in the similarities between the latter.

[0132] Compared to Figure 2G FTC cell region 216A, Figure 2J The FTC cell region 216J also includes Figure 2G The FTV 220 and VDR242. Figure 2J In China, based on Figure 2J Compared to Figure 2I Due to the similarity, VDR 242 replaces the instance of VD 238 that would otherwise be essentially in gap 219.

[0133] Figure 2K This is a layout diagram of FTC cell area 216K according to some embodiments.

[0134] Figure 2K Similar to Figure 2D .about Figure 2K The cross-section line 2E-2E' corresponds to Figure 2E ,section Figure 2F-2F 'correspond Figure 2F The discussion will focus on Figure 2K Compared to Figure 2D The difference lies in the former, not in the similarities between the latter.

[0135] exist Figure 2K In the FTC cell region 216K: Figure 2D The combination of MD contact structures 234(4)', 234(10) and 234(12) of the FTC unit region 216D has been Figure 2A The MD contact structure 234(4) is replaced; and Figure 2D The combination of MD contact structures 234(6)', 234(11) and 234(13) of the FTC unit region 216D has been... Figure 2A Replace the MD contact structure 234(6).

[0136] Figure 2L This is a layout diagram of the FTC cell area 216L according to some embodiments.

[0137] Figure 2L Similar to Figure 2K .about Figure 2L The cross-section line 2E-2E' corresponds to Figure 2E The cross-sectional line 2H-2H' corresponds to Figure 2H The discussion will focus on Figure 2L Compared to Figure 2K The difference lies in the former, not in the similarities between the latter.

[0138] exist Figure 2L In FTC cell region 216L: Figure 2G The combination of MG contact structures 234(4)', 234(10) and 234(12) of the FTC cell region 216G has been Figure 2A The MG contact structure 234(4) is replaced; and Figure 2G The combination of MG contact structures 234(6)', 234(11) and 234(13) of the FTC cell region 216G has been Figure 2A Replacement of MG contact member 234(6). Figure 2L In China, based on Figure 2L Compared to Figure 2K Due to the similarity, VDR 242 replaced the instance of VD 238 that would have been essentially in gap 219.

[0139] Figure 2M This is a layout diagram of the FTC cell area 216M according to some embodiments.

[0140] Figure 2M Similar to Figure 2K .about Figure 2M The cross-section line 2E-2E' corresponds to Figure 2E The section line 2F-2F' corresponds to Figure 2F The discussion will focus on Figure 2M Compared to Figure 2K The difference lies in the former, not in the similarities between the latter.

[0141] exist Figure 2M In this context, paired gate segments 232(2)_T and 232(2)_B, 232(3)_T and 232(3)_B, 232(4)_T and 232(4)_B, 232(5)_T and 232(5)_B, 232(6)_T and 232(6)_B, and 232(7)_T and 232(7)_B have been replaced by corresponding gate segments 233(3), 233(4), 233(5), 233(6), 233(7), and 233(8). Each of the gate segments 233(3), 233(4), 233(5), 233(6), 233(7), and 233(8) extends continuously across AR 218(1), gap 219, and AR 218(2). Furthermore, as discussed below, Figure 2M The width of the gate segment in the middle is basically greater than Figure 2K The gate segment in it is wider.

[0142] about Figure 2MNot with Figures 2A-2L Examples of shared component size ranges include the following. Again, regarding VG 236, sizes are normalized.

[0143] In some embodiments, each of the gate segments 233(1)-233(8) has a width W_GS2 relative to the first direction (X-axis) as follows: W_GS2≈((11 / 6)*W_VG). In such embodiments where W_GS≈((11 / 6)*W_VG) relative to the first direction (X-axis), an example of CPP is as follows: CPP≈(35 / 6)*W_VG).

[0144] Figure 2N This is a layout diagram of FTC cell region 216N according to some embodiments.

[0145] Figure 2N Similar to Figure 2M And to a lesser extent similar to Figure 2G . Figure 2N The cross-section line E-E' in the middle corresponds to Figure 2E The cross section 221E, and Figure 2N The cross-section line H-H' in the middle corresponds to Figure 2H The cross section is 221H. Relative to... Figure 2M The FTC216M, Figure 2N The FTC 216N also includes Figure 2G VDR 242. In Figure 2N In China, based on Figure 2N Compared to Figure 2M Due to the similarity, VDR 242 replaces the instance of VD 238 that would otherwise be essentially in gap 219.

[0146] Figure 2O This is a layout diagram based on some embodiments.

[0147] exist Figure 2O middle, Figure 2D The FTC cell regions 216D are adjacent to each other relative to the first direction (X-axis).

[0148] Figure 2P This is a layout diagram based on some embodiments.

[0149] exist Figure 2P In the middle, the pseudo-simulation unit 244 is adjacent to the first direction (X-axis) in Figure 2D Between two instances of FTC cell region 216D.

[0150] Figure 2Q This is a layout diagram based on some embodiments.

[0151] exist Figure 2QIn the middle, the active analog unit 246 is adjacent to the first direction (X-axis) in Figure 2D Between two instances of FTC cell region 216D.

[0152] Figure 2R This is a layout diagram based on some embodiments.

[0153] Figure 2R It shows Figure 2D A variant 216' of the FTC cell region 216D, wherein the FTC cell region 216D' is substantially wider than the FTC cell region 216D relative to the first direction (X-axis).

[0154] Figure 2T This is a layout diagram based on some embodiments.

[0155] exist Figure 2T middle, Figure 2D The three instances of FTC cell region 216D are stacked adjacent to each other relative to the second direction (Y-axis).

[0156] Figure 3 This is a flowchart 300 of a method for manufacturing a semiconductor device according to some embodiments.

[0157] According to some embodiments, the method of flowchart 300 can, for example, be used with EDA system 500 ( Figure 5 (discussed below) and IC manufacturing system 600 ( Figure 6 (As discussed below) to achieve this. Examples of semiconductor devices that can be manufactured according to the method of flowchart 300 include Figure 1A Semiconductor devices, semiconductor devices based on the layout diagram disclosed herein, semiconductor devices based on the cross-section disclosed herein, etc.

[0158] exist Figure 3 In flowchart 300, the method includes blocks 302-304. At block 302, a layout diagram is generated, including one or more layout diagrams disclosed herein, etc. According to some embodiments, block 302 may, for example, use an EDA system 500 (… Figure 5 (This will be discussed below) to implement the process. The flow proceeds from box 302 to box 304.

[0159] At box 304, based on the layout diagram, at least one of the following is performed: (A) one or more photolithographic exposures, or (b) fabrication of one or more semiconductor masks, or (C) fabrication of one or more components in a layer of a semiconductor device. See below. Figure 6 Discussion of IC manufacturing system 600 in China.

[0160] Figure 4 This is a flowchart 400 of a method for manufacturing a semiconductor device according to some embodiments.

[0161] According to some embodiments, the method of flowchart 400 can, for example, be used with IC manufacturing system 600 (…). Figure 6 (This will be discussed below) to implement the method. Examples of semiconductor devices that can be manufactured according to the method in flowchart 400 include... Figure 1A Semiconductor devices, semiconductor devices based on the layout diagram disclosed herein, semiconductor devices based on the cross-section disclosed herein, etc.

[0162] Method 400 includes frames 410-432. At frame 410, a substrate is formed. An example of a substrate is... Figure 2C Substrate 217, etc. The process proceeds from box 410 to box 412.

[0163] At frame 412, first and second active regions (ARs) are formed in corresponding regions of the substrate. Examples of ARs include... Figures 2A-2N AR 218(1)-218(2), etc. The process proceeds from box 412 to box 414.

[0164] At box 414, an S / D region containing the doped region of the AR is formed at the location of the first AR and the second AR, wherein the second region between the corresponding S / D regions is a channel region. Examples of AR include... Figure 2B The S / D zones 222(1)-222(2), etc. Examples of channel zones are... Figure 2B The process proceeds from box 414 to box 416. (This refers to the channel area 224, etc.)

[0165] At frame 416, collinear pairs of first and second gate segments are formed above the first side of the substrate and above the corresponding channel region. Examples of gate segments include... Figure 2A The pairs 232(2)_T and 232(2)_B, 232(3)_T and 232(3)_B, 232(4)_T and 232(4)_B, 232(5)_T and 232(5)_B, 232(6)_T and 232(6)_B, and 232(7)_T and 232(7)_B formed on the front side of substrate 217.

[0166] In some embodiments, a single, longer gate segment is formed instead of each of a pair of first and second gate segments. The single gate segment is positioned above each of the first and second ARs and extends continuously through the gap between the first and second ARs. Examples of a single, longer gate segment include... Figures 2M-2N Gate segments 233(2)-233(7), etc. In such embodiments, each gate segment is substantially wider relative to the first direction (X-axis). Examples of wider gate segments include Figures 2M-2N Gate segments 233(1)-233(8), etc. The process proceeds from block 416 to block 418.

[0167] At frame 418, MD contact structures are formed above the first side of the substrate and above the corresponding S / D region. Each MD contact structure is located above each of the first AR and the second AR, and extends continuously through the gap between the first AR and the second AR.

[0168] Examples of MD contact structures include Figure 2A MD contact structures 234(2)-234(8) are formed on the front side of substrate 217.

[0169] In some embodiments, some, but not all, of the MD contact structures are replaced by three shorter MD contact structures, wherein: the first of the shorter MD contact structures is located above the first AR; the second of the shorter MD contact structures is located above a portion of the gap between the first AR and the second AR; and the third of the shorter MD contact structures is located above the second AR. An example of the first of the shorter MD contact structures is... Figure 2D and Figure 2G Examples of MD contact structures include 234(4)' and 234(6)'. An example of the second shorter MD contact structure is... Figure 2D and Figure 2G Examples of MD contact structures include 234(10) and 234(11). The third example of an MD contact structure is... Figure 2D and Figure 2G MD contact components 234(12) and 234(13), etc. The flow proceeds from box 418 to box 420.

[0170] At block 420, a VG is formed above the corresponding gate segment. Examples of VGs include... Figure 2A Examples of VG 236, etc. The process proceeds from box 420 to box 422.

[0171] At box 422, a VD is formed above the corresponding MD contact structure. Examples of VDs include... Figure 2A Examples of VD238, etc. The result of box 422 is the first version of the workpiece.

[0172] Based on the first version of the workpiece, appropriate further processing produces... Figure 2A FTC Zone 216A, Figure 2D FTC Zone 216D, Figure 2G FTC zone 216G, Figure 2I FTC area 216I, Figure 2J FTC Zone 216J Figure 2K FTC area 216K, Figure 2L FTC area 216L, Figure 2M FTC area 216M and Figure 2NAny of the FTC regions 216N. The process proceeds from box 422 to box 424.

[0173] At frame 424, a VDR is formed above the corresponding MD contact structure in the gap between the first AR and the second AR. An example of the gap is... Figure 2A , Figure 2D , Figure 2G and Figures 2I-2N The gap in the middle is 219. An example of VDR is... Figure 2G , Figure 2H , Figure 2J , Figure 2L and Figure 2N VDR 230 in the example. The result of box 424 is the second version of the workpiece.

[0174] Based on the second version of the workpiece, appropriate further processing produces... Figure 2G FTC zone 216G, Figure 2H FTC area 216H, Figure 2J FTC Zone 216J and Figure 2N Any of the FTC regions 216N. The process proceeds from box 424 to box 426.

[0175] At box 426, the workpiece is reversed. Before box 426, the first side of the workpiece faces upward and the second side faces downward. After box 426, the second side of the workpiece faces upward and the first side faces downward. Box 426 is included to better utilize the effects of gravity on some aspects of the process. The flow proceeds from box 426 to box 428.

[0176] In some embodiments, the process bypasses box 428, such that the process proceeds from box 424 to box 428, as indicated by alternative process arrow 450.

[0177] At box 428, a VB is formed above the second side of the substrate. If the process path includes box 426, the VB is formed above the corresponding S / D region. If the process path does not include box 426, the VB is formed below the corresponding S / D region. Examples of VB include... Figure 2A , Figure 2I and Figure 2J VB 228(1)-228(6), etc. The process proceeds from box 428 to box 430.

[0178] At box 430, an FTV is formed in the gap between the first AR and the second AR. If the flow path includes box 426, the FTV is formed above the corresponding MD contact structure. If the flow path does not include box 426, the FTV is formed below the corresponding MD contact structure. Examples of FTVs include... Figure 2D , Figure 2G and Figures 2I-2NWaiting for FTV 220.

[0179] In some embodiments, the centerline (Y-center) of the FTV relative to the second direction (Y-axis) is located at or near the position adjacent to the first (e.g., 212(1) etc.) and second (212(2) etc.) analog cell regions. The Y-center of the FTV (e.g., 220 etc.) is located at or near the ACB region (e.g., Figure 2A , Figure 2D , Figure 2G , Figures 2I-2N The middle part of 214). The process proceeds from box 430 to box 432.

[0180] At box 432, a PGBM_1st segment is formed at least in the gap between the first AR and the second AR. If the process path includes box 426, the PGBM_1st segment is formed above the corresponding MD contact structure and / or VB. If the process path does not include box 426, the PGBM_1st segment is formed below the corresponding MD contact structure and / or VB.

[0181] In some embodiments, the PGBM_1st segment is located at or near the midline (Y-center) of the second direction (Y-axis) adjacent to the first (e.g., 212(1) etc.) and second (212(2) etc.) analog cell regions. The Y-center of the PGBM_1st segment (e.g., 230A, 230D etc.) is located at or near the ACB region (e.g., Figure 2A , Figure 2D , Figure 2G , Figures 2I-2N The middle part of 214).

[0182] In some embodiments, the PGBM_1st segment is a higher type of PGBM_1st segment relative to the second direction (Y-axis), which overlaps / belows the first AR and the second AR. Examples of higher PGBM_1st segments include... Figure 2A and Figures 2I-2J Examples include the PGBM_1st segment 230A. In some embodiments, the PGBM_1st segment is a shorter type of PGBM_1st segment relative to the second direction (Y-axis) that does not overlap / overlay with the first AR and the second AR. Figure 2D , Figure 2G and Figures 2K-2N The PGBM_1st section 230D, etc.

[0183] In some embodiments, the process bypasses box 424, causing the process to proceed from box 422 to box 426, as indicated by alternative flow arrow 452. In some embodiments, the process bypasses boxes 424-426, causing the process to proceed from box 422 to box 428, as indicated by alternative flow arrow 454. Based on the flow path including alternative flow arrow 452 or alternative flow arrow 454, appropriate further processing is generated. Figure 2A FTC Zone 216A, Figure 2D FTC Zone 216D, Figure 2I FTC area 216I, Figure 2K FTC area 216K and Figure 2M Any one of the FTC zones 216M.

[0184] In some embodiments, the process bypasses boxes 424-428, such that the process proceeds from box 422 to box 430, as indicated by alternative process arrow 456. Based on the process path including alternative process arrow 456, appropriate further processing is generated. Figure 2D FTC Zone 216D, Figure 2K FTC area 216K and Figure 2M Any one of the FTC zones 216M.

[0185] In some embodiments, the process bypasses box 430, causing the process to proceed from box 428 to box 432, as indicated by alternative process arrow 458. In some embodiments, the process bypasses boxes 424-426, causing the process to proceed from box 422 to box 428, as indicated by alternative process arrow 454. Based on the process path including alternative process arrow 458, appropriate further processing is generated. Figure 2A FTC area 216A.

[0186] Figure 5 This is a block diagram of an electronic design automation (EDA) system 500 according to some embodiments.

[0187] In some embodiments, EDA system 500 includes an APR system. In some embodiments, EDA system 500 is a general-purpose computing device including a hardware processor 502 and a non-transitory computer-readable storage medium 504. Among other things, storage medium 504 encodes (i.e. stores) computer program code using computer program code 506 (i.e., a set of executable instructions). Execution of instructions 506 by hardware processor 502 represents (at least partially) implementation of, for example, according to one or more embodiments. Figures 3-4 EDA tools comprising part or all of the methods (processes and / or methods mentioned below). Storage medium 504 stores the layout diagrams disclosed herein, etc.

[0188] Processor 502 is electrically coupled to computer-readable storage medium 504 via bus 508. Processor 502 is also electrically coupled to I / O interface 510 via bus 508. Network interface 512 is also electrically connected to processor 502 via bus 508. Network interface 512 is connected to network 514, enabling processor 502 and computer-readable storage medium 504 to be connected to external components via network 514. Processor 502 is configured to execute computer program code 506 encoded in computer-readable storage medium 504 so that system 500 can be used to perform part or all of a process and / or method. In one or more embodiments, processor 502 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0189] In one or more embodiments, the computer-readable storage medium 504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 504 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 504 includes a compact disc read-only memory (CD-ROM), a compact disc read / write (CD-R / W), and / or a digital video disc (DVD).

[0190] In one or more embodiments, storage medium 504 stores computer program code 506 configured to enable system 500 (where execution (at least partially) represents an EDA tool) to perform part or all of the process and / or method. In one or more embodiments, storage medium 504 further stores information that contributes to the execution of the process and / or method. In one or more embodiments, storage medium 504 stores a library 507 of standard units, including such standard units disclosed herein. In some embodiments, storage medium 504 stores one or more layout diagrams 511.

[0191] EDA system 500 includes an I / O interface 510. The I / O interface 510 is coupled to external circuitry. In one or more embodiments, the I / O interface 510 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 502.

[0192] EDA system 500 also includes a network interface 512 coupled to processor 502. Network interface 512 allows system 500 to communicate with network 514, to which one or more other computer systems are connected. Network interface 512 includes a wireless network interface such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods are implemented in two or more systems 500.

[0193] System 500 is configured to receive information via I / O interface 510. The information received via I / O interface 510 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 502. The information is transmitted to processor 502 via bus 508. EDA system 500 is configured to receive information related to the user interface (UI) via I / O interface 510. This information is stored as UI 542 on computer-readable medium 504.

[0194] In some embodiments, part or all of the process and / or method is implemented as a standalone software application for execution by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by EDA system 500. In some embodiments, the process and / or method is provided by CADENCE DESIGN SYSTEMS, Inc. Use tools such as [tool name] or other suitable layout generation tools to generate layouts containing standard cells.

[0195] In some embodiments, these processes are implemented as the functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, one or more of external / removable and / or internal / built-in storage or storage units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), and semiconductor memories (e.g., ROM, RAM, memory cards, etc.).

[0196] Figure 6 This is a block diagram of an integrated circuit (IC) manufacturing system 600 and its associated IC manufacturing process according to some embodiments.

[0197] Based on Figure 3 The layout diagram generated by frame 302 is implemented in IC manufacturing system 600. Figure 3Block 304, wherein manufacturing system 600 is used to manufacture (A) one or more semiconductor masks or (B) at least one component in an initial semiconductor integrated circuit layer. In some embodiments, Figure 4 The method is implemented by IC manufacturing system 600 in order to perform Figure 3 Box 304.

[0198] exist Figure 6 In this IC manufacturing system 600, entities such as design studio 620, mask room 640, and IC manufacturing plant / manufacturer (“fab”) 650 interact with each other in the design, development, and manufacturing cycle and / or in services related to manufacturing IC devices 660. The entities in system 600 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design studio 620, mask room 640, and IC manufacturing plant 650 are owned by a single larger company. In some embodiments, two or more of the design studio 620, mask room 640, and IC manufacturing plant 650 coexist in a shared facility and use shared resources.

[0199] Design firm (or design team) 620 generates IC design layout 622. IC design layout 622 includes various geometric patterns designed for IC device 660. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 660 to be manufactured. The layers are bonded to form various IC components. For example, portions of IC design layout 622 include various IC components, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, to be formed on a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. Source / drain regions may refer individually or collectively to a source or drain electrode, depending on the context. Design firm 620 implements appropriate design procedures to form IC design layout 622. Design procedures include one or more of logic design, physical design, or location and routing. IC design layout 622 is presented in one or more data files containing geometric pattern information. For example, IC design layout 622 is represented in GDSII or DFII file format.

[0200] Mask chamber 630 includes data preparation 632 and mask fabrication 634. Mask chamber 640 uses IC design layout 622 to fabricate one or more masks for fabricating various layers of IC device 660 according to IC design layout 624. Mask chamber 630 performs mask data preparation 632, in which IC design layout 622 is converted into a representative data file (“RDF”). Mask data preparation 632 provides the RDF to mask fabrication 634. Mask fabrication 634 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (mask) or semiconductor wafer. Mask data preparation 632 manipulates the design layout to conform to the specific characteristics of the mask writer and / or the requirements of IC fabrication plant 650. Figure 6 In this embodiment, mask data preparation 632, mask manufacturing 634, and mask 645 are shown as separate elements. In some embodiments, mask data preparation 632 and mask manufacturing 634 are collectively referred to as mask data preparation.

[0201] In some embodiments, mask data preparation 632 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, and other process effects. OPC adjusts the IC design layout 622. In some embodiments, mask data preparation 632 includes further resolution enhancement techniques (RET), such as off-axis illumination, subresolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is further used, treating OPC as an inverse imaging problem.

[0202] In some embodiments, mask data preparation 632 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout that has already been processed in the OPC. These rules include certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask fabrication 634, which can undo some modifications performed by the OPC to satisfy the mask creation rules.

[0203] In some embodiments, mask data preparation 632 includes a lithography process inspection (LPC), which simulates a process performed by an IC manufacturing plant 650 to manufacture an IC device 660. The LPC simulates this process based on an IC design layout 622 to manufacture a simulated device, such as IC device 660. Process parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and combinations thereof. In some embodiments, after a simulated device has been manufactured via LPC, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 622.

[0204] For clarity, the above description of mask data preparation 632 has been simplified. In some embodiments, mask data preparation 632 includes additional features, such as logic operations (LOPs), to modify the IC design layout according to manufacturing rules. Furthermore, the processes applied to the IC design layout 622 during data preparation 632 can be performed in various different sequences.

[0205] After mask data preparation 632 and during mask fabrication 634, a mask 645 or a set of masks is fabricated based on a modified IC design layout. In some embodiments, a pattern is formed on the mask (photomask or mask stencil) using an electron beam (e-beam) or a mechanism of multiple e-beams based on the modified IC design layout. The mask is formed using various techniques. In some embodiments, a binary technique is used to form the mask. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the mask. In another example, a phase-shifting technique is used to form the mask. In a phase-shifting mask (PSM), various components in the pattern formed on the mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase-shifting mask is a decaying PSM or an alternating PSM. Masks produced by mask fabrication 634 are used in a variety of processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafers, in etching processes to form various etched regions in semiconductor wafers, and / or in other suitable processes.

[0206] IC manufacturing plant 650 is an IC manufacturing operation that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC wafer fab 650 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, and a third manufacturing facility may provide additional services for the casting operation.

[0207] IC manufacturing plant 650 uses a mask (or multiple masks) manufactured by mask chamber 640 to manufacture IC device 660 using manufacturing tool 652. Therefore, IC manufacturing plant 650 uses IC design layout 622 at least indirectly to manufacture IC device 660. In some embodiments, IC manufacturing plant 650 uses mask 635 to manufacture semiconductor wafer 653 to form IC device 660. Semiconductor wafer 653 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 653 also includes one or more of various doped regions, dielectric components, multilayer interconnects, etc. (formed in subsequent manufacturing steps).

[0208] In some embodiments, the semiconductor device includes: a first active region and a second active region (AR) having a long axis extending in a first direction and correspondingly included in a first analog cell region and a second analog cell region, the first analog cell region and the second analog cell region being adjacent to each other with respect to a second direction perpendicular to the first direction, the region adjacent to the first analog cell region and the second analog cell region being an analog cell boundary (ACB) region extending from approximately a top boundary of the first AR to approximately a bottom boundary of the second AR; a pair of gate segments, each pair including a collinear first gate segment and a second gate segment correspondingly located above the first AR and the second AR, the first gate segment and the second gate segment extending in the second direction; metal-to-source / drain (MD) contact structures correspondingly located above the first AR and the second AR and scattered between the pairs of gate segments, at least some of the MD contact structures being gap-crossing MD contacts. The structure includes: a gap-crossing MD contact structure extending continuously across the gap between the first AR and the second AR to be located above each of the first AR and the second AR; a via-to-PGBM_1st segment contact structure (VB) having a long axis extending in the second direction, the VB being correspondingly located below the first AR or the second AR, the long axis of each VB and the short axis of each of the first AR and the second AR having approximately the same length; and a PG segment (PGBM_1st segment) in a first embedded metallization (first BM) layer, located below the VB, the PGBM_1st segment overlapping a large portion of the underlying layer of each of the VB, the centerline of the PGBM_1st segment relative to the second direction being a Y-centerline, the Y-centerline being located at or near the adjacency of the first analog cell region and the second analog cell region, the Y-centerline of the PGBM_1st segment being located at or near the middle of the ACB region.

[0209] In some embodiments, the semiconductor device further includes: a via-to-gate contact structure (VG) correspondingly located above the first gate segment and the second gate segment; the VG is not located above the first AR and the second AR; and the VG is adjacent to the far side of the corresponding first AR and the second AR away from the gap, relative to the proximal side of the first AR and the second AR near the gap.

[0210] In some embodiments, the semiconductor device further includes a feedthrough via (FTV) extending in the first direction, located in the gap and above the PGBM_1st segment.

[0211] In some embodiments, the gap-crossing MD contact structure is also located above the FTV.

[0212] In some embodiments, the semiconductor device further includes a via-to-MD track (VDR) extending in the first direction, located in the gap and correspondingly located above the gap-crossing MD contact structure.

[0213] In some embodiments, the VDR is substantially centered on the FTV relative to the second direction.

[0214] In some embodiments, the gap-crossing MD contact structure is also above the VDR.

[0215] In some embodiments, the VB is aligned with the gap-crossing MD contact structure relative to the first direction.

[0216] In some embodiments, the semiconductor device includes: a first active region and a second active region (AR) having a long axis extending in a first direction and correspondingly included in a first analog cell region and a second analog cell region, the first analog cell region and the second analog cell region being adjacent to each other with respect to a second direction perpendicular to the first direction, the region adjacent to the first analog cell region and the second analog cell region being an analog cell boundary (ACB) region extending from approximately a top boundary of the first AR to approximately a bottom boundary of the second AR; a pair of gate segments, each pair including a collinear first gate segment and a second gate segment correspondingly located above the first AR and the second AR, the first gate segment and the second gate segment extending in the second direction; and a first metal-to-source / drain region (MD) contact structure correspondingly located in the... Above the first AR and the second AR and scattered between pairs of gate segments, at least some of the first MD contact structures are gap-crossing MD contact structures that continuously extend across the gap between the first AR and the second AR to be located above each of the first AR and the second AR; a feed-through via (FTV) extending in the first direction, located in the gap and below the MD contact structure, the centerline of the FTV relative to the second direction being a Y-centerline located at or near the adjacency of the first analog cell region and the second analog cell region; and a PG segment (PGBM_1st segment) in the first buried metallization (first BM) layer, located below the FTV.

[0217] In some embodiments, the PGBM_1st segment does not overlap with each of the lower layers in the first AR and the second AR.

[0218] In some embodiments, the gap-crossing MD contact structure is also on top of the FTV.

[0219] In some embodiments, the semiconductor device further includes a via-to-MD (VD) track (VDR) extending in the first direction, located in the gap and correspondingly located above the gap-crossing MD contact structure.

[0220] In some embodiments, the gap-crossing MD contact structure is also on the VDR.

[0221] In some embodiments, the VDR is substantially centered on the FTV relative to the second direction.

[0222] In some embodiments, each of the first gate segment and the second gate segment has substantially the same width as each of the MD contact structures, relative to the first direction.

[0223] In some embodiments, the semiconductor device further includes: a via-to-gate contact structure (VG) correspondingly located above the first gate segment and the second gate segment; the VG is not located above the first AR and the second AR; and, relative to the proximal side of the first AR and the second AR near the gap, the VG is adjacent to the distal side of the corresponding first AR and the second AR away from the gap.

[0224] In some embodiments, the semiconductor device further includes a second MD contact structure, which is located above the FTV, but not above each of the first AR and the second AR.

[0225] In some embodiments, a method of forming a semiconductor device includes: forming a first active region and a second active region (AR) in a substrate, the first AR and the second AR having a long axis extending in a first direction and correspondingly included in a first analog cell region and a second analog cell region, the first analog cell region and the second analog cell region being adjacent to each other with respect to a second direction perpendicular to the first direction, the region adjacent to the first analog cell region and the second analog cell region being an analog cell boundary (ACB) region extending from approximately a top boundary of the first AR to approximately a bottom boundary of the second AR; forming a pair of gate segments, each pair including a collinear first gate segment and a second gate segment correspondingly located above the first AR and the second AR, the first gate segment and the second gate segment extending in the second direction; forming a metal-to-source / drain (MD) contact structure to obtain a first workpiece, the MD contact structure correspondingly located above the first AR and the second AR and scattered between the pairs of gate segments, forming the MD contact structure including... At least some of the contact structures are formed as gap-crossing MD contact structures that continuously extend across the gap between the first AR and the second AR; a via-to-PGBM_1st segment contact structure (VB) is formed correspondingly below the first AR or the second AR, the VB having a long axis extending in the second direction, the long axis of each VB and the short axis of each of the first AR and the second AR having approximately the same length; and a PG segment (PGBM_1st segment) in a first embedded metallization (first BM) layer is formed below the VB, the PGBM_1st segment overlapping a large portion of the underlying layer of each of the VB, the centerline of the PGBM_1st segment relative to the second direction being a Y-centerline, the Y-centerline being located at or near the adjacency of the first analog cell region and the second analog cell region, the Y-centerline of the PGBM_1st segment being located at or near the middle of the ACB region.

[0226] In some embodiments, the first gate segment and the second gate segment, along with the MD contact structure, are located on a first side of the substrate relative to a third direction perpendicular to the first and second directions; the method further includes reversing the first workpiece relative to a third direction perpendicular to the first and second directions before forming the VB; and the VB and the PGBM_1st segment are located on a second side of the substrate relative to the third direction.

[0227] In some embodiments, the method further includes: forming a via-to-gate contact structure (VG) correspondingly above the first gate segment and the second gate segment before forming the VB; the VG is not located above the first AR and the second AR; and the VG is adjacent to the far side of the corresponding first AR and the second AR away from the gap, relative to the proximal side of the first AR and the second AR near the gap.

[0228] In some embodiments, the method further includes forming a feed through-hole (FTV) extending in the first direction, the FTV being located in the gap and above the PGBM_1st segment.

[0229] In some embodiments, the method further includes forming a through-hole-to-MD track (VDR) correspondingly above the gap-crossing MD contact structure, the VDR extending in the first direction and located in the gap.

[0230] In some embodiments, forming a VDR includes: the VDR being substantially centered on the FTV relative to the second direction.

[0231] In some embodiments, forming the VB includes aligning the VB with respect to the gap-crossing MD contact structure relative to the first direction.

[0232] In some embodiments, forming the first AR and the second AR includes: forming a source / drain (S / D) region, including a first region of the first AR and a first region of the first AR, wherein the second region of the first AR and the region of the second AR corresponding to the S / D region are channel regions.

[0233] In some embodiments, a method of forming a semiconductor device including an analog cell boundary buried metallization (ACB) region includes: forming first and second active regions (ARs) in a substrate, the first AR and the second AR having long axes extending in a first direction and correspondingly included in the first analog cell region and the second analog cell region, the first analog cell region and the second analog cell region being adjacent to each other with respect to the second direction perpendicular to the first direction, the region adjacent to the first analog cell region and the second analog cell region being an analog cell boundary (ACB) region, the ACB region extending from approximately a top boundary of the first AR to approximately a bottom boundary of the second AR; forming pairs of gate segments, each pair including correspondingly A collinear first gate segment and a second gate segment are located above the first AR and the second AR, the first gate segment and the second gate segment extending in the second direction; a first metal-to-source / drain (MD) contact structure is correspondingly formed on the first AR and the second AR, the formation of the first MD contact structure includes forming at least some of the first MD contact members as gap-crossing MD contact structures, the gap-crossing MD structures continuously extending through the gap between the first AR and the second AR; a feedthrough via (FTV) is formed extending in the first direction, the FTV is located in the gap; and a PG segment (PGBM_1st segment) is formed in a first buried metallization (first BM) layer below the FTV.

[0234] In some embodiments, the first and second gate segments and the MD contact structure are located on a first side of the substrate relative to a third direction perpendicular to the first and second directions; the method further includes reversing the first workpiece relative to a third direction perpendicular to the first and second directions before forming the FTV; and the FTV and the PGBM_1st segment are located on a second side of the substrate relative to the third direction.

[0235] In some embodiments, the step of forming the PGBM_1st segment includes: keeping the PGBM_1st segment off from each of the first AR and the second AR.

[0236] In some embodiments, the method further includes: forming via-to-gate contact structures (VG) correspondingly on the first and second gate segments prior to forming the FTV; the VG is not on the first AR and the second AR; and the VG is adjacent to the far side of the corresponding first AR and the second AR away from the gap relative to the proximal side of the proximity gap between the first AR and the second AR.

[0237] In some embodiments, the method further includes: forming a through-hole-to-MD track (VDR) correspondingly above the gap-crossing MD contact structure prior to forming the FTV, the VDR extending in a first direction and located in the gap.

[0238] In some embodiments, forming a VDR includes: the VDR being substantially centered on the FTV relative to the second direction.

[0239] In some embodiments, forming a pair of gate segments includes: with respect to a first direction, each of the first and second gate segments having substantially the same width as each of the MD contact structures.

[0240] In some embodiments, the method further includes: forming a second MD contact structure correspondingly in the gap before forming the FTV, but not on the first AR and the second AR.

[0241] In some embodiments, forming the first AR and the second AR includes: forming a source / drain (S / D) region, including a first region of the first AR and a first region of the first AR, wherein the second region of the first AR and the region of the second AR corresponding to the S / D region are channel regions.

[0242] Those skilled in the art will readily recognize that one or more of the disclosed embodiments achieve one or more of the aforementioned advantages. After reading the foregoing specification, those skilled in the art will be able to influence various variations, equivalent substitutions, and various other embodiments widely disclosed herein. Therefore, the protection granted by this application is limited only to the definitions contained in the appended claims and their equivalents.

Claims

1. A semiconductor device, comprising: The first active region and the second active region, namely the first AR region and the second AR region, have a long axis extending in a first direction and are correspondingly included in the first analog cell region and the second analog cell region. The first analog cell region and the second analog cell region are adjacent to each other with respect to a second direction perpendicular to the first direction. The area adjacent to the first analog cell region and the second analog cell region is the analog cell boundary region, which extends from the top boundary of the first AR to the bottom boundary of the second AR. A pair of gate segments, each pair including a collinear first gate segment and a second gate segment correspondingly located above the first AR and the second AR, the first gate segment and the second gate segment extending in the second direction; Metal-to-source / drain region contact structures, i.e. MD contact structures, are located above the first AR and the second AR respectively and are scattered between pairs of gate segments. At least some of the MD contact structures are gap-crossing MD contact structures that continuously extend across the gap between the first AR and the second AR to be located above each of the first AR and the second AR. The through-hole to PGBM_1st segment contact structure, i.e. VB, has a long axis extending in the second direction, the VB being located below the first AR or the second AR respectively, and the long axis of each VB and the short axis of each of the first AR and the second AR have the same length; as well as The embedded power grid section in the first embedded metallization layer, namely the PGBM_1st section, is located below the VB. The PGBM_1st section overlaps with most of the lower layer of each of the VB. The centerline of the PGBM_1st section relative to the second direction is located at or near the position where the first simulation cell area and the second simulation cell area are adjacent. The centerline of the PGBM_1st section relative to the second direction is located at or near the middle of the simulation cell boundary area.

2. The semiconductor device according to claim 1, further comprising: The via-to-gate contact structure, or VG, is located above the first gate segment and the second gate segment respectively; The VG is not located on the first AR and the second AR; and The VG is adjacent to the proximal side of the corresponding first AR and second AR, which is closer to the gap, relative to the proximal side of the gap.

3. The semiconductor device according to claim 1, further comprising: A through-hole extends in the first direction, is located in the gap and above the PGBM_1st segment.

4. The semiconductor device according to claim 3, further comprising: The through-hole-to-MD track, or VDR, extends in the first direction, is located in the gap, and is correspondingly located above the gap-crossing MD contact structure.

5. The semiconductor device according to claim 4, wherein: The VDR is centered on the feed through-hole relative to the second direction.

6. The semiconductor device according to claim 1, wherein: The VB is aligned with the gap-crossing MD contact structure relative to the first direction.

7. A semiconductor device, comprising: The first active region and the second active region, namely the first AR region and the second AR region, have a long axis extending in a first direction and are correspondingly included in the first analog cell region and the second analog cell region. The first analog cell region and the second analog cell region are adjacent to each other with respect to a second direction perpendicular to the first direction. The area adjacent to the first analog cell region and the second analog cell region is the analog cell boundary region, which extends from the top boundary of the first AR to the bottom boundary of the second AR. A pair of gate segments, each pair including a collinear first gate segment and a second gate segment correspondingly located above the first AR and the second AR, the first gate segment and the second gate segment extending in the second direction; First metal-to-source / drain region contact structure, the first metal-to-source / drain region contact structure being a first MD contact structure, correspondingly located above the first AR and the second AR and scattered between the pairs of gate segments, at least some of the first MD contact structures being gap-crossing MD contact structures, the gap-crossing MD contact structures continuously extending across the gap between the first AR and the second AR to be located above each of the first AR and the second AR; A through-hole extends in the first direction, is located in the gap and below the first MD contact structure, the through-hole is located at or near the adjoining position of the first and second analog cell regions relative to the centerline of the second direction, and the through-hole is located at or near the middle of the analog cell boundary region relative to the centerline of the second direction; and The embedded power grid section in the first embedded metallization layer, namely the PGBM_1st section, is located below the feedthrough hole.

8. The semiconductor device according to claim 7, The PGBM_1st segment does not overlap with each of the lower layers in the first AR and the second AR.

9. The semiconductor device according to claim 7, further comprising: The through-hole-to-MD track, or VDR, extends in the first direction, is located in the gap, and is correspondingly located above the gap-crossing MD contact structure.

10. The semiconductor device according to claim 9, wherein: The gap-crossing MD contact structure is also located above the VDR.

11. The semiconductor device according to claim 9, wherein: The VDR is centered on the feed through-hole relative to the second direction.

12. The semiconductor device according to claim 7, wherein: Relative to the first direction, each of the first gate segment and the second gate segment has substantially the same width as each of the MD contact structures.

13. The semiconductor device according to claim 7, further comprising: The via-to-gate contact structure, or VG, is located above the first gate segment and the second gate segment respectively; The VG is not located on the first AR and the second AR; and The VG is adjacent to the proximal side of the corresponding first AR and second AR, which is closer to the gap, relative to the proximal side of the gap.

14. The semiconductor device according to claim 7, further comprising: The second metal-to-source / drain region contact structure, i.e. the second MD contact structure, is located above the feedthrough via, but not above each of the first AR and the second AR.

15. A method of forming a semiconductor device, the method comprising: A first active region and a second active region are formed in a substrate. The first active region is a first active region (AR) and the second active region is a second active region (AR). The first AR and the second AR have a long axis extending in a first direction and are correspondingly included in a first analog cell region and a second analog cell region. The first analog cell region and the second analog cell region are adjacent to each other with respect to a second direction perpendicular to the first direction. The region adjacent to the first analog cell region and the second analog cell region is an analog cell boundary region. The analog cell boundary region extends from the top boundary of the first AR to the bottom boundary of the second AR. Forming a pair of gate segments, each pair including a collinear first gate segment and a second gate segment correspondingly located above the first AR and the second AR, the first gate segment and the second gate segment extending in the second direction; A first workpiece is obtained by forming a metal-to-source / drain region contact structure, wherein the metal-to-source / drain region contact structure is an MD contact structure, wherein the MD contact structure is correspondingly located above the first AR and the second AR and is scattered between pairs of gate segments, and forming the MD contact structure includes forming at least some of the MD contact structures as gap-crossing MD contact structures, wherein the gap-crossing MD contact structures continuously extend across the gap between the first AR and the second AR; Form a through-hole-to-PGBM_1st segment contact structure, i.e., VB, correspondingly located below the first AR or the second AR, the VB having a long axis extending in the second direction, the long axis of each VB and the short axis of each of the first AR and the second AR having the same length; as well as An embedded power grid section is formed in a first embedded metallization layer below the VB. The embedded power grid section in the first embedded metallization layer is a PGBM_1st section. The PGBM_1st section overlaps with most of the lower layer of each of the VB. The centerline of the PGBM_1st section relative to the second direction is located at or near the position where the first simulation unit area and the second simulation unit area are adjacent. The centerline of the PGBM_1st section relative to the second direction is located at or near the middle of the simulation unit boundary area.

16. The method of claim 15, wherein: The first gate segment, the second gate segment, and the MD contact structure are located on a first side of the substrate relative to a third direction perpendicular to the first and second directions. The method further includes: Before forming the VB, the first workpiece is reversed relative to a third direction perpendicular to the first and second directions; and Relative to the third direction, the VB and the PGBM_1st segment are located on the second side of the substrate.

17. The method of claim 15, further comprising: Before forming the VB, a via-to-gate contact structure is formed above the first gate segment and the second gate segment, that is, the via-to-gate contact structure is VG; The VG is not located on the first AR and the second AR; as well as The VG is adjacent to the proximal side of the corresponding first AR and second AR, which is closer to the gap, relative to the proximal side of the gap.

18. The method of claim 15, further comprising: A feed through-hole is formed extending in the first direction, the feed through-hole being located in the gap and above the PGBM_1st segment.

19. The method of claim 18, further comprising: A via-to-MD track, which is a VDR, is formed correspondingly above the gap-crossing MD contact structure. The VDR extends in the first direction and is located in the gap.

20. The method of claim 15, wherein, The formation of the VB includes: The VB is aligned with the gap-crossing MD contact structure relative to the first direction.

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