High voltage interconnection device with deep trench isolation

Abstract

The application provides a high-voltage interconnection device with deep trench isolation, which comprises an LDMOS region and a high-voltage circuit region connected by a high-voltage interconnection line, the LDMOS region comprises a second conductive type semiconductor contact region, a second conductive type semiconductor contact region, a first conductive type semiconductor contact region, a first conductive type well region, a second conductive type well region, a second conductive type drift region, a first conductive type semiconductor substrate, a polysilicon gate electrode and a field oxide layer; a high-voltage junction terminal is arranged around the high-voltage circuit region; the two ends of the high-voltage interconnection line are connected with the second conductive type semiconductor contact region and the high-voltage circuit region respectively; a dielectric oxide layer is arranged between the second conductive type semiconductor contact region and the high-voltage circuit region and around the high-voltage circuit region. The application realizes dielectric isolation by filling dielectric in the trench between the LDMOS region and the high-voltage circuit region; and the second conductive type buried layer is introduced at the bottom of the dielectric trench to optimize the in-body electric field distribution of the LDMOS device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power devices and relates to a high-voltage interconnect device with deep trench isolation. Background Technology

[0002] High-voltage integrated circuits (HICs) are monolithic integrated circuits composed of high-voltage electronic devices and traditional control logic circuits or analog circuits. They are widely used in motor control, electronic ballasts, automotive electronics, and other fields. A HIC consists of a high-voltage region and a low-voltage region. LDMOS is typically used as a level shifter between the two. In traditional structures, high-voltage interconnects cross the drift region of the LDMOS, affecting the junction electric field and reducing the breakdown voltage. To avoid the problems caused by high-voltage interconnects, external interconnects have been proposed. However, this structure uses PN isolation between the LDMOS region and the high-voltage circuit region, resulting in a larger layout area. Furthermore, when the area of ​​the LDMOS device is reduced, it usually results in a small radius of curvature on the surface. The small radius of curvature of the drain junction causes the electric field to concentrate in this region, leading to premature avalanche breakdown. Summary of the Invention

[0003] To address the shortcomings of the prior art, this invention proposes a high-voltage interconnect technology with deep trench isolation. A second conductivity type buried layer is introduced into the substrate between the LDMOS region and the high-voltage circuit region through trench injection and high-temperature push-junction. The resulting dielectric trench structure provides deep trench isolation between the LDMOS region and the high-voltage circuit region, reducing the layout area. Furthermore, the dielectric trench plays a positive role in dV / dt immunity, thereby suppressing the turn-on of parasitic PNP transistors. The buried layer transforms the small radius of curvature of the highly doped drain junction into a large radius of curvature of the low-doped junction, effectively reducing the electric field peak at the curvature junction and preventing premature avalanche breakdown at this location, thus solving the longitudinal breakdown voltage problem of the device.

[0004] To achieve the above-mentioned objectives, the technical solution of this invention is as follows:

[0005] A high-voltage interconnect device with deep trench isolation includes an LDMOS region and a high-voltage circuit region 33 connected by a high-voltage interconnect 4. The LDMOS region includes a second conductivity type semiconductor contact region A1 and a second conductivity type semiconductor contact region B2. A high-voltage junction terminal 26 is disposed between the second conductivity type semiconductor contact region A1 and the second conductivity type semiconductor contact region B2 and around the high-voltage circuit region 33. One end of the high-voltage interconnect 4 is connected to the second conductivity type semiconductor contact region B2 of the LDMOS region, and the other end is connected to the high-voltage circuit region 33. A dielectric oxide layer 3 is disposed between the second conductivity type semiconductor contact region B2 and the high-voltage circuit region 33 and around the high-voltage circuit region 33.

[0006] In a preferred embodiment, the AA' line extends from the second conductivity type semiconductor contact region A1 to the high voltage circuit region 33; the device cross-section along the AA' line includes:

[0007] Second conductivity type semiconductor contact region A1, second conductivity type semiconductor contact region B2, dielectric oxide layer 3, high voltage interconnect 4, first conductivity type semiconductor contact region A5, first conductivity type well region A6, second conductivity type well region A7, second conductivity type drift region 8, first conductivity type semiconductor substrate 9, polysilicon gate electrode A10, second conductivity type buried layer 11, first conductivity type semiconductor contact region B12, polysilicon gate electrode B13, first conductivity type semiconductor contact region C14, second conductivity type well region B15, second conductivity type semiconductor contact region C16, second conductivity type semiconductor contact region D17, polysilicon gate electrode C18, first conductivity type well region B19, second conductivity type semiconductor contact region E20, first conductivity type semiconductor contact region D21, thin dielectric layer 23;

[0008] Wherein, the first conductivity type well region A6 is located on the left side of the first conductivity type semiconductor substrate 9, the second conductivity type drift region 8 is located on the right side of the first conductivity type well region A6 in the first conductivity type semiconductor substrate 9, and the second conductivity type well region A7 is located on the right side of the second conductivity type drift region 8; the heavily doped first conductivity type semiconductor contact region A5 and the second conductivity type semiconductor contact region A1 are located in the first conductivity type well region A6, and the heavily doped second conductivity type semiconductor contact region B2 is located in the second conductivity type well region A7; the field oxide layer 22 is located above the second conductivity type drift region 8 and partially above the first conductivity type well region A6; the polysilicon gate electrode A10 covers the field oxide layer 22 and is located on the right side of the first conductivity type well region A6. Above the first conductivity type well region A6 and extending above the second conductivity type drift region 8; the dielectric oxide layer 3 is formed by filling the dielectric after grooving; the dielectric oxide layer 3 is located to the right of the second conductivity type well region A7, passes through the second conductivity type drift region 8 and extends to the bottom of the first conductivity type semiconductor substrate 9; the second conductivity type buried layer 11 is located in the first conductivity type semiconductor substrate 9 at the bottom of the dielectric oxide layer 3; the second conductivity type well region B15 and the first conductivity type well region B19 are located in the second conductivity type drift region 8 to the right of the dielectric oxide layer 3; the heavily doped first conductivity type semiconductor contact region B12, the first conductivity type semiconductor contact region C14 and the second conductivity type semiconductor contact region E20 are located in the second conductivity type... In the type-shaped well region B15, the first conductivity type semiconductor contact region B12 and the second conductivity type semiconductor contact region E20 are located on the left side inside the second conductivity type well region B15, the first conductivity type semiconductor contact region C14 is located on the right side inside the second conductivity type well region B15, and the heavily doped second conductivity type semiconductor contact regions C16 and D17 and the first conductivity type semiconductor contact region D21 are located in the first conductivity type well region B19; the second conductivity type semiconductor contact region C16 is located on the left side inside the first conductivity type well region B19, and the second conductivity type semiconductor contact regions D17 and D21 are located on the right side inside the first conductivity type well region B19. Dielectric layer 23 is located above the second conductivity type well region B15 and the first conductivity type well region B19; one end of the thin dielectric layer 23 above the second conductivity type well region B15 is located above the first conductivity type semiconductor contact region B12, and the other end is located above the first conductivity type semiconductor contact region C14; one end of the thin dielectric layer 23 above the first conductivity type well region B19 is located above the second conductivity type semiconductor contact region C16, and the other end is located above the second conductivity type semiconductor contact region D17; polysilicon gate electrode C18 is located above the thin dielectric layer 23; high-voltage interconnect 4 is connected between the second conductivity type semiconductor contact region B2 and the first conductivity type semiconductor contact region B12, and the heavily doped doping concentration is greater than 1E19cm. -3 .

[0009] As a preferred embodiment, a filler 24 is introduced into the dielectric oxide layer 3. The filler 24 can be one of polysilicon, low-K dielectric, or high-K dielectric.

[0010] In a preferred embodiment, the high-voltage circuit region includes a bipolar transistor, wherein a second conductivity type well region B15 is located above a second conductivity type drift region 8, a first conductivity type well region C31 is located on the left side of the second conductivity type well region B15, a second conductivity type contact region G30 is located on the right side of the second conductivity type well region B15, and a first conductivity type semiconductor contact region E28 and a second conductivity type contact region F29 are located in the first conductivity type well region C31; a dielectric oxide layer 3 is introduced between the second conductivity type well region B15 and the first conductivity type well region B19, and on the left side of the first conductivity type well region A6, the dielectric oxide layer 3 on the left side of the first conductivity type well region A6 extends through the first conductivity type well region A6 and extends to the first conductivity type semiconductor substrate 9 at its bottom, and the remaining dielectric oxide layers 3 extend through the second conductivity type drift region 8 and extend to the first conductivity type semiconductor substrate 9 at their bottom; a second conductivity type buried layer 11 is located in the first conductivity type semiconductor substrate 9 at the bottom of the dielectric oxide layer 3.

[0011] As a preferred embodiment, the bottom of the dielectric oxide layer 3 is either a first conductivity type buried layer B27 or no buried layer, and the first conductivity type buried layer B27 is connected to the second conductivity type drift region 8.

[0012] As a preferred embodiment, a multi-layered, nested dielectric oxide layer 3 is provided between the second conductivity type semiconductor contact region B2 and the high voltage circuit region 33, and around the high voltage circuit region 33.

[0013] As a preferred embodiment, a first conductivity type buried layer 25 is introduced into the second conductivity type drift region 8 by ion implantation. The first conductivity type buried layer 25 is located inside the second conductivity type drift region 8 and its upper surface is in close contact with the field oxide layer 22 or there is a gap between it and the field oxide layer 22, forming a RESURF structure.

[0014] The present invention also provides a high-voltage interconnect device with deep trench isolation, comprising an LDMOS region and a high-voltage circuit region 33 connected by a high-voltage interconnect 4. The LDMOS region includes a second conductivity type semiconductor contact region A1 and a second conductivity type semiconductor contact region B2. A high-voltage junction terminal 26 is disposed between the second conductivity type semiconductor contact region A1 and the second conductivity type semiconductor contact region B2 and around the high-voltage circuit region 33. One end of the high-voltage interconnect 4 is connected to the second conductivity type semiconductor contact region B2 of the LDMOS region, and the other end is connected to the high-voltage circuit region 33. A dielectric oxide layer 3 is disposed between the second conductivity type semiconductor contact region B2 and the high-voltage circuit region 33, thereby saving layout area.

[0015] The high-voltage junction terminal 26 and the LDMOS region are arranged in a rectangular shape, and the dielectric oxide layer 3 surrounds the high-voltage circuit region 33, the drain region of the LDMOS region, and the drift region 8 of the second conductivity type.

[0016] Alternatively, the dielectric oxide layer 3 may surround the drain region and the second conductivity type drift region 8 of the LDMOS region, but not the high voltage circuit region 33, or the dielectric oxide layer 3 may surround the entire LDMOS region, but not the high voltage circuit region 33.

[0017] As a preferred embodiment, the second conductivity type well region A7 has multiple dielectric oxide layers 3 arranged parallel to the device surface direction on the right side.

[0018] The beneficial effects of this invention are as follows:

[0019] A second type of buried layer is introduced into the substrate between the LDMOS region and the high-voltage circuit region through trench injection and high-temperature push junction. The resulting dielectric trench structure forms a deep trench isolation between the LDMOS region and the high-voltage circuit region to reduce the layout area. The dielectric trench also plays a positive role in dV / dt immunity, thereby suppressing the turn-on of parasitic PNP transistors. In the working state, the second type of buried layer is in a non-fully depleted state, making the high-voltage circuit region surrounded by the dielectric trench completely equipotential. This transforms the small radius of curvature of the highly doped drain curvature junction in the LDMOS region into a large radius of curvature of the low-doped junction, effectively reducing the electric field peak at the curvature junction and preventing premature avalanche breakdown of the device at this location, thus solving the longitudinal breakdown voltage problem of the device. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the high-voltage integrated circuit structure of the present invention;

[0021] Figure 2 For along Figure 1 Cross-sectional view of the device with the AA' line in the middle;

[0022] Figure 3 This is a cross-sectional view of the high-voltage integrated circuit in Example 2;

[0023] Figure 4 This is a cross-sectional view of the high-voltage integrated circuit in Example 3;

[0024] Figure 5 This is a cross-sectional view of a high-voltage integrated circuit in Example 4, where the bottom of the dielectric oxide layer is a buried layer B of the first conductivity type.

[0025] Figure 6 This is a cross-sectional view of a high-voltage integrated circuit without a buried layer at the bottom of the dielectric oxide layer in Example 4.

[0026] Figure 7 This is a schematic diagram of the high-voltage integrated circuit structure in Example 5;

[0027] Figure 8 For along Figure 5 Cross-sectional view of the device with the AA' line in the middle;

[0028] Figure 9 This is a cross-sectional view of a high-voltage integrated circuit in Example 6, where the first conductivity type buried layer 25 is located inside the second conductivity type drift region 8 and its upper surface is in close contact with the field oxide layer 22.

[0029] Figure 10 A cross-sectional view of a high-voltage integrated circuit with a spacing between the first conductivity type buried layer 25 and the field oxide layer 22 in Example 6;

[0030] Figure 11 This is a schematic diagram of the high-voltage integrated circuit structure in Example 7; wherein: the high-voltage junction terminal 26 and the LDMOS region are arranged in a rectangular shape, and the dielectric oxide layer 3 surrounds the high-voltage circuit region 33, the drain region of the LDMOS region, and the drift region 8 of the second conductivity type;

[0031] Figure 12 This is a schematic diagram of the high-voltage integrated circuit structure in Example 7; wherein: the dielectric oxide layer 3 surrounds the drain region of the LDMOS region and the drift region 8 of the second conductivity type, but does not surround the high-voltage circuit region 33;

[0032] Figure 13 This is a schematic diagram of the high-voltage integrated circuit structure in Example 7; wherein, the dielectric oxide layer 3 surrounds the entire LDMOS region, but does not surround the high-voltage circuit region 33.

[0033] 1 is a semiconductor contact region A of the second conductivity type; 2 is a semiconductor contact region B of the second conductivity type; 3 is a dielectric oxide layer; 4 is a high-voltage interconnect; 5 is a semiconductor contact region A of the first conductivity type; 6 is a well region A of the first conductivity type; 7 is a well region A of the second conductivity type; 8 is a drift region of the second conductivity type; 9 is a semiconductor substrate of the first conductivity type; 10 is a polysilicon gate electrode A; 11 is a buried layer of the second conductivity type; 12 is a semiconductor contact region B of the first conductivity type; 13 is a polysilicon gate electrode B; 14 is a semiconductor contact region C of the first conductivity type; 15 is a well region B of the second conductivity type; 16 is a semiconductor contact region C of the second conductivity type. 17 is the second conductivity type semiconductor contact region D, 18 is the polysilicon gate electrode C, 19 is the first conductivity type well region B, 20 is the second conductivity type semiconductor contact region E, 21 is the first conductivity type semiconductor contact region D, 22 is the field oxide layer, 23 is the thin dielectric layer, 24 is the filler, 25 is the first conductivity type buried layer A, 26 is the high voltage junction termination, 27 is the first conductivity type buried layer B, 28 is the first conductivity type semiconductor contact region E, 29 is the second conductivity type contact region F, 30 is the second conductivity type contact region G, 31 is the first conductivity type well region C, 32 is the second conductivity type well region C, and 33 is the high voltage circuit region. Detailed Implementation

[0034] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] Example 1

[0036] The high-voltage integrated circuit described in Example 1, such as Figure 1 As shown, the system includes an LDMOS region and a high-voltage circuit region 33 connected by a high-voltage interconnect 4. The LDMOS region includes a second conductivity type semiconductor contact region A1 and a second conductivity type semiconductor contact region B2. A high-voltage junction terminal 26 is provided between the second conductivity type semiconductor contact region A1 and the second conductivity type semiconductor contact region B2, and around the high-voltage circuit region 33. One end of the high-voltage interconnect 4 is connected to the second conductivity type semiconductor contact region B2 of the LDMOS region, and the other end is connected to the high-voltage circuit region 33. A dielectric oxide layer 3 is provided between the second conductivity type semiconductor contact region B2 and the high-voltage circuit region 33, and around the high-voltage circuit region 33.

[0037] Figure 2 For along Figure 1 The cross-sectional view of the device along line AA', where line AA' extends from the second conductivity type semiconductor contact region A1 to the high voltage circuit region 33; the device cross-section along line AA' includes:

[0038] Second conductivity type semiconductor contact region A1, second conductivity type semiconductor contact region B2, dielectric oxide layer 3, high voltage interconnect 4, first conductivity type semiconductor contact region A5, first conductivity type well region A6, second conductivity type well region A7, second conductivity type drift region 8, first conductivity type semiconductor substrate 9, polysilicon gate electrode A10, second conductivity type buried layer 11, first conductivity type semiconductor contact region B12, polysilicon gate electrode B13, first conductivity type semiconductor contact region C14, second conductivity type well region B15, second conductivity type semiconductor contact region C16, second conductivity type semiconductor contact region D17, polysilicon gate electrode C18, first conductivity type well region B19, second conductivity type semiconductor contact region E20, first conductivity type semiconductor contact region D21, thin dielectric layer 23;

[0039] Wherein, the first conductivity type well region A6 is located on the left side of the first conductivity type semiconductor substrate 9, the second conductivity type drift region 8 is located on the right side of the first conductivity type well region A6 in the first conductivity type semiconductor substrate 9, and the second conductivity type well region A7 is located on the right side of the second conductivity type drift region 8; the heavily doped first conductivity type semiconductor contact region A5 and the second conductivity type semiconductor contact region A1 are located in the first conductivity type well region A6, and the heavily doped second conductivity type semiconductor contact region B2 is located in the second conductivity type well region A7; the field oxide layer 22 is located above the second conductivity type drift region 8 and partially above the first conductivity type well region A6; the polysilicon gate electrode A10 covers the field oxide layer 22 and is located on the right side of the first conductivity type well region A6. Above the first conductivity type well region A6 and extending above the second conductivity type drift region 8; the dielectric oxide layer 3 is formed by filling the dielectric after grooving; the dielectric oxide layer 3 is located to the right of the second conductivity type well region A7, passes through the second conductivity type drift region 8 and extends to the bottom of the first conductivity type semiconductor substrate 9; the second conductivity type buried layer 11 is located in the first conductivity type semiconductor substrate 9 at the bottom of the dielectric oxide layer 3; the second conductivity type well region B15 and the first conductivity type well region B19 are located in the second conductivity type drift region 8 to the right of the dielectric oxide layer 3; the heavily doped first conductivity type semiconductor contact region B12, the first conductivity type semiconductor contact region C14 and the second conductivity type semiconductor contact region E20 are located in the second conductivity type... In the type-shaped well region B15, the first conductivity type semiconductor contact region B12 and the second conductivity type semiconductor contact region E20 are located on the left side inside the second conductivity type well region B15, the first conductivity type semiconductor contact region C14 is located on the right side inside the second conductivity type well region B15, and the heavily doped second conductivity type semiconductor contact regions C16 and D17 and the first conductivity type semiconductor contact region D21 are located in the first conductivity type well region B19; the second conductivity type semiconductor contact region C16 is located on the left side inside the first conductivity type well region B19, and the second conductivity type semiconductor contact regions D17 and D21 are located on the right side inside the first conductivity type well region B19. Dielectric layer 23 is located above the second conductivity type well region B15 and the first conductivity type well region B19; one end of the thin dielectric layer 23 above the second conductivity type well region B15 is located above the first conductivity type semiconductor contact region B12, and the other end is located above the first conductivity type semiconductor contact region C14; one end of the thin dielectric layer 23 above the first conductivity type well region B19 is located above the second conductivity type semiconductor contact region C16, and the other end is located above the second conductivity type semiconductor contact region D17; polysilicon gate electrode C18 is located above the thin dielectric layer 23; high-voltage interconnect 4 is connected between the second conductivity type semiconductor contact region B2 and the first conductivity type semiconductor contact region B12, and the heavily doped doping concentration is greater than 1E19cm. -3 .

[0040] Its basic working principle is as follows: Taking the first conductivity type semiconductor material as P-type as an example, the dielectric trench generated by deep trench etching replaces the PN isolation to reduce the layout area and suppress the turn-on of parasitic PNP transistors. In the working state, the second conductivity type buried layer is in a non-fully depleted state, making the high voltage circuit region surrounded by the dielectric trench completely equipotential. When the applied gate voltage is zero, the PN junction formed by the first conductivity type semiconductor substrate 9 and the second conductivity type drift region 8, and the first conductivity type semiconductor substrate 9 and the second conductivity type buried layer 11, begins to deplete under the action of reverse bias. The presence of the second conductivity type buried layer 11 can transform the small radius of curvature of the heavily doped drain curvature junction in the LDMOS region into a large radius of curvature of the lightly doped one, reducing the electric field peak of the curvature junction and avoiding premature breakdown at the drain end. This can shorten the drift region distance and solve the lateral breakdown voltage problem of the device. At the same time, the high voltage interconnect 4 connecting the LDMOS region and the high voltage circuit region adopts external interconnection to reduce the impact of the high voltage interconnect 4 on the LDMOS region device.

[0041] Example 2

[0042] like Figure 3 The figure shown is a cross-sectional view of a high-voltage integrated circuit in Example 2. The difference between this example and Example 1 is that a filler 24 is introduced into the dielectric oxide layer 3. The filler 24 is one of polysilicon, low-K dielectric, or high-K dielectric. Its working principle is basically the same as that of Example 1.

[0043] Example 3

[0044] like Figure 4 The diagram shows a cross-sectional view of a high-voltage integrated circuit according to Embodiment 3. The structure of this example differs from Embodiment 1 in that the high-voltage circuit region includes a bipolar transistor. A second conductivity type well region B15 is located above a second conductivity type drift region 8. A first conductivity type well region C31 is located on the left side of the second conductivity type well region B15. A second conductivity type contact region G30 is located on the right side of the second conductivity type well region B15. A first conductivity type semiconductor contact region E28 and a second conductivity type contact region F29 are located within the first conductivity type well region C31. A dielectric oxide layer 3 is introduced between the second conductivity type well region B15 and the first conductivity type well region B19, and on the left side of the first conductivity type well region A6. The dielectric oxide layer 3 on the left side of the first conductivity type well region A6 extends through the first conductivity type well region A6 and to the bottom of the first conductivity type semiconductor substrate 9. The remaining dielectric oxide layers 3 extend through the second conductivity type drift region 8 and to the bottom of the first conductivity type semiconductor substrate 9. A second conductivity type buried layer 11 is located in the first conductivity type semiconductor substrate 9 at the bottom of the dielectric oxide layer 3.

[0045] The high-voltage circuit area uses dielectric tank isolation instead of PN isolation, and... Figure 2In comparison, the isolation effect of the high-voltage circuit area is improved, effectively saving layout area. Its working principle is basically the same as that of Example 1.

[0046] Example 4

[0047] like Figure 5 and Figure 6 The image shown is a cross-sectional view of a high-voltage integrated circuit according to Embodiment 4. The structural difference between this example and Embodiment 1 is that the bottom of the dielectric oxide layer 3 can be a buried layer B27 of the first conductivity type, as shown below. Figure 5 As shown, or without a buried layer, such as Figure 6 As shown; the first conductive type buried layer B27 can communicate with the second conductive type drift region 8, and its working principle is basically the same as that of Example 1.

[0048] Example 5

[0049] like Figure 7 and Figure 8 The diagram shown is a schematic diagram and cross-sectional view of a high-voltage integrated circuit structure according to Embodiment 5. The difference between this example and Embodiment 1 is that a multi-layered nested dielectric oxide layer 3 is provided between the second conductivity type semiconductor contact region B2 and the high-voltage circuit region 33, and around the high-voltage circuit region 33. This improves the isolation effect, and its working principle is basically the same as that of Embodiment 1.

[0050] Example 6

[0051] like Figure 9 and Figure 10 The image shown is a cross-sectional view of a high-voltage integrated circuit according to Embodiment 6. The structural difference between this example and Embodiment 1 is that a first conductivity type buried layer 25 is introduced into the second conductivity type drift region 8 via ion implantation. The first conductivity type buried layer 25 is located inside the second conductivity type drift region 8 and its upper surface is in close contact with the field oxide layer 22. Figure 9 As shown, or with a gap between it and the field oxide layer 22, such as Figure 10 As shown, a RESURF structure is formed, which can increase the doping concentration of the second conductivity type drift region 8 to reduce the specific on-resistance of the device. Its working principle is basically the same as that of Example 1.

[0052] Example 7

[0053] like Figure 11 , Figure 12 and Figure 13The diagram shows a high-voltage integrated circuit structure according to Embodiment 7, including an LDMOS region and a high-voltage circuit region 33 connected by a high-voltage interconnect 4. The LDMOS region includes a second conductivity type semiconductor contact region A1 and a second conductivity type semiconductor contact region B2. A high-voltage junction terminal 26 is provided between the second conductivity type semiconductor contact region A1 and the second conductivity type semiconductor contact region B2, and around the high-voltage circuit region 33. One end of the high-voltage interconnect 4 is connected to the second conductivity type semiconductor contact region B2 of the LDMOS region, and the other end is connected to the high-voltage circuit region 33. A dielectric oxide layer 3 is provided between the second conductivity type semiconductor contact region B2 and the high-voltage circuit region 33.

[0054] The high-voltage junction terminal 26 and the LDMOS region are arranged in a rectangular shape, and the dielectric oxide layer 3 surrounds the high-voltage circuit region 33, the drain region of the LDMOS region, and the drift region 8 of the second conductivity type; as shown Figure 11 As shown;

[0055] Alternatively, the dielectric oxide layer 3 may surround the drain region and the second conductivity type drift region 8 of the LDMOS region, but not the high voltage circuit region 33, such as... Figure 12 As shown;

[0056] Alternatively, the dielectric oxide layer 3 may surround the entire LDMOS region, but not the high-voltage circuit region 33. For example... Figure 13 As shown, this saves on land area;

[0057] Below the dielectric oxide layer 3, there may be a first type of buried layer B2 or no buried layer, as described in Example 4. Its working principle is basically the same as that in Example 1.

Claims

1. A high-voltage interconnect device with deep trench isolation, characterized in that: The system includes an LDMOS region and a high-voltage circuit region (33) connected by a high-voltage interconnect (4). The LDMOS region includes a second conductivity type semiconductor contact region A (1) and a second conductivity type semiconductor contact region B (2). A high-voltage junction terminal (26) is provided between the second conductivity type semiconductor contact region A (1) and the second conductivity type semiconductor contact region B (2) and around the high-voltage circuit region (33). One end of the high-voltage interconnect (4) is connected to the second conductivity type semiconductor contact region B (2) of the LDMOS region, and the other end is connected to the high-voltage circuit region (33). A dielectric oxide layer (3) is provided between the second conductivity type semiconductor contact region B (2) and the high-voltage circuit region (33) and around the high-voltage circuit region (33).

2. The high-voltage interconnect device according to claim 1, characterized in that: The AA' line is the direction from the second conductivity type semiconductor contact area A(1) to the high voltage circuit area (33); The device cross-section along line AA' includes: Second type semiconductor contact region A (1), second type semiconductor contact region B (2), dielectric oxide layer (3), high voltage interconnect (4), first type semiconductor contact region A (5), first type well region A (6), second type well region A (7), second type drift region (8), first type semiconductor substrate (9), polysilicon gate electrode A (10), second type buried layer (11), first type semiconductor contact region B (12), polysilicon gate electrode B (13), first type semiconductor contact region C (14), second type well region B (15), second type semiconductor contact region C (16), second type semiconductor contact region D (17), polysilicon gate electrode C (18), first type well region B (19), second type semiconductor contact region E (20), first type semiconductor contact region D (21), thin dielectric layer (23); Among them, the first conductivity type well region A (6) is located on the left side of the first conductivity type semiconductor substrate (9), the second conductivity type drift region (8) is located on the right side of the first conductivity type well region A (6) in the first conductivity type semiconductor substrate (9), and the second conductivity type well region A (7) is located on the right side of the second conductivity type drift region (8); the heavily doped first conductivity type semiconductor contact region A (5) and the second conductivity type semiconductor contact region A (1) are located in the first conductivity type well region A (6), and the heavily doped second conductivity type semiconductor contact region B (2) is located in the second conductivity type well region A (7); the field oxide layer (22) is located above the second conductivity type drift region (8) and partially above the first conductivity type well region A (6); the polysilicon gate electrode... A electrode A (10) covers the field oxide layer (22) and is located above the first conductivity type well region A (6) and extends to the second conductivity type drift region (8); the dielectric oxide layer (3) is formed by filling the dielectric after grooving; the dielectric oxide layer (3) is located to the right of the second conductivity type well region A (7), passes through the second conductivity type drift region (8) and extends to the first conductivity type semiconductor substrate (9) at the bottom; the second conductivity type buried layer (11) is located in the first conductivity type semiconductor substrate (9) at the bottom of the dielectric oxide layer (3); the second conductivity type well region B (15) and the first conductivity type well region B (19) are located in the second conductivity type drift region (8) to the right of the dielectric oxide layer (3); the heavily doped first conductivity type semiconductor contact region B ( 12) The first conductivity type semiconductor contact region C(14) and the second conductivity type semiconductor contact region E(20) are located in the second conductivity type well region B(15). The first conductivity type semiconductor contact region B(12) and the second conductivity type semiconductor contact region E(20) are located on the left side inside the second conductivity type well region B(15). The first conductivity type semiconductor contact region C(14) is located on the right side inside the second conductivity type well region B(15). The heavily doped second conductivity type semiconductor contact region C(16), the second conductivity type semiconductor contact region D(17), and the first conductivity type semiconductor contact region D(21) are located in the first conductivity type well region B(19). The second conductivity type semiconductor contact region C(16) is located in the first conductivity type well region B(19). (19) On the left side inside, the second type of conductive semiconductor contact area D (17) and the first type of conductive semiconductor contact area D (21) are located on the right side inside the first type of conductive well area B (19), and the thin dielectric layer (23) is located above the second type of conductive well area B (15) and the first type of conductive well area B (19); one end of the thin dielectric layer (23) above the second type of conductive well area B (15) is located above the first type of conductive semiconductor contact area B (12), and the other end is located above the first type of conductive semiconductor contact area C (14); one end of the thin dielectric layer (23) above the first type of conductive well area B (19) is located above the second type of conductive semiconductor contact area C (16), and the other end is located above the second type of conductive semiconductor contact area D (17);The polysilicon gate electrode C (18) is located above the thin dielectric layer (23); the high voltage interconnect (4) is connected between the second conductivity type semiconductor contact region B (2) and the first conductivity type semiconductor contact region B (12), and the heavily doped doping concentration is greater than 1E19cm; -3 .

3. A high-voltage interconnect device with deep trench isolation according to claim 2, characterized in that: A filler (24) is introduced into the dielectric oxide layer (3), and the filler (24) is one of polysilicon, low-K dielectric, or high-K dielectric.

4. A high-voltage interconnect device with deep trench isolation according to claim 2, characterized in that: The high-voltage circuit region includes a bipolar transistor, wherein a second conductivity type well region B (15) is located above a second conductivity type drift region (8), a first conductivity type well region C (31) is located to the left of the second conductivity type well region B (15), a second conductivity type contact region G (30) is located to the right of the second conductivity type well region B (15), and a first conductivity type semiconductor contact region E (28) and a second conductivity type contact region F (29) are located in the first conductivity type well region C (31); the second conductivity type well region B (15) and the first conductivity type A dielectric oxide layer (3) is introduced between the well regions B (19) and to the left of the first conductivity type well region A (6). The dielectric oxide layer (3) to the left of the first conductivity type well region A (6) passes through the first conductivity type well region A (6) and extends to the bottom of the first conductivity type semiconductor substrate (9). The remaining dielectric oxide layers (3) pass through the second conductivity type drift region (8) and extend to the bottom of the first conductivity type semiconductor substrate (9). The second conductivity type buried layer (11) is located in the first conductivity type semiconductor substrate (9) at the bottom of the dielectric oxide layer (3).

5. A high-voltage interconnect device with deep trench isolation according to claim 2, characterized in that: The bottom of the dielectric oxide layer (3) is either a first conductivity type buried layer B (27) or no buried layer, and the first conductivity type buried layer B (27) is connected to the second conductivity type drift region (8).

6. A high-voltage interconnect device with deep trench isolation according to claim 1, characterized in that: A multi-layered nested dielectric oxide layer (3) is provided between the second conductivity type semiconductor contact area B (2) and the high voltage circuit area (33) and around the high voltage circuit area (33).

7. A high-voltage interconnect device with deep trench isolation according to claim 2, characterized in that: A first conductivity type buried layer (25) is introduced into the second conductivity type drift region (8) by ion implantation. The first conductivity type buried layer (25) is located inside the second conductivity type drift region (8) and its upper surface is in close contact with the field oxide layer (22) or there is a gap between it and the field oxide layer (22), forming a RESURF structure.

8. A high-voltage interconnect device with deep trench isolation, characterized in that: The system includes an LDMOS region and a high-voltage circuit region (33) connected by a high-voltage interconnect (4). The LDMOS region includes a second conductivity type semiconductor contact region A (1) and a second conductivity type semiconductor contact region B (2). A high-voltage junction terminal (26) is provided between the second conductivity type semiconductor contact region A (1) and the second conductivity type semiconductor contact region B (2) and around the high-voltage circuit region (33). One end of the high-voltage interconnect (4) is connected to the second conductivity type semiconductor contact region B (2) of the LDMOS region, and the other end is connected to the high-voltage circuit region (33). A dielectric oxide layer (3) is provided between the second conductivity type semiconductor contact region B (2) and the high-voltage circuit region (33). The high voltage junction terminal (26) and the LDMOS region are arranged in a rectangular shape, and the dielectric oxide layer (3) surrounds the high voltage circuit region (33) and the drain region and the second conductivity type drift region (8) of the LDMOS region; Alternatively, the dielectric oxide layer (3) surrounds the drain region of the LDMOS region and the drift region of the second conductivity type (8), but does not surround the high voltage circuit region (33); Alternatively, the dielectric oxide layer (3) surrounds the entire LDMOS region, but not the high-voltage circuit region (33).

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