Display device and method for manufacturing a display device

Abstract

According to one embodiment, a manufacturing method of a display device includes the steps of preparing a process substrate, forming a lower electrode over a substrate, forming a rib portion having an opening overlapping with the lower electrode, forming a partition wall including a lower portion positioned over the rib portion and an upper portion positioned over the lower portion and protruding from a side surface of the lower portion, forming an organic layer over the lower electrode in the opening, forming an upper electrode over the organic layer, forming a transparent layer over the upper electrode, and forming an inorganic layer over the transparent layer, in the step of forming the upper electrode, a first evaporation source is inclined with respect to a normal line of the process substrate, and a material emitted from the first evaporation source is evaporated onto the process substrate while the process substrate is transported, and in the step of forming the inorganic layer, a second evaporation source is inclined with respect to the normal line of the process substrate in a direction opposite to the first evaporation source, and a material emitted from the second evaporation source is evaporated onto the process substrate while the process substrate is transported.

Description

[0001] Refer to related applications

[0002] This application claims priority based on Japanese Patent Application No. 2022-074873, filed on April 28, 2022, all the contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a display device and a method for manufacturing the display device. Background Technology

[0004] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have become practical. These display elements include pixel circuits comprising thin-film transistors, a lower electrode connected to the pixel circuits, an organic layer covering the lower electrode, and a top electrode covering the organic layer. In addition to the light-emitting layer, the organic layer also includes functional layers such as hole transport layers or electron transport layers.

[0005] In the process of manufacturing such display components, technologies are needed to suppress the decline in reliability. Summary of the Invention

[0006] The purpose of this embodiment is to provide a display device and a method for manufacturing the display device that can suppress reliability degradation.

[0007] According to one embodiment, a method for manufacturing a display device includes the following steps: preparing a processing substrate, wherein a lower electrode is formed on top of a substrate, a rib having an opening overlapping the lower electrode is formed, and a partition wall is formed including a lower portion located above the rib and an upper portion located above the lower portion and protruding from the side of the lower portion; an organic layer is formed in the opening above the lower electrode; an upper electrode is formed on the organic layer; a transparent layer is formed on the upper electrode; an inorganic layer is formed on the transparent layer; and in the step of forming the upper electrode, a first evaporation source is inclined relative to the normal of the processing substrate, and material ejected from the first evaporation source is vapor-deposited while the processing substrate is being transported; and in the step of forming the inorganic layer, a second evaporation source is inclined relative to the normal of the processing substrate in the opposite direction to the first evaporation source, and material ejected from the second evaporation source is vapor-deposited onto the processing substrate while the processing substrate is being transported.

[0008] According to one embodiment, a display device includes: a substrate; a lower electrode disposed above the substrate; a rib having an opening overlapping the lower electrode; a partition wall having a lower portion disposed above the rib and an upper portion disposed above the lower portion and protruding from a side of the lower portion; an organic layer disposed in the opening above the lower electrode; an upper electrode disposed above the organic layer; a transparent layer disposed above the upper electrode; an inorganic layer disposed above the transparent layer; and a sealing layer covering the inorganic layer and in contact with the lower portion of the partition wall, wherein the upper electrode has a first end and a second end opposite to the first end, the first end being covered by the inorganic layer, and the second end protruding from the inorganic layer and covered by the sealing layer.

[0009] According to one embodiment, a display device capable of suppressing reliability degradation and a method for manufacturing the display device can be provided. Attached Figure Description

[0010] Figure 1 This is a diagram illustrating an example of the configuration of a display device DSP.

[0011] Figure 2 This is a diagram showing an example of the layout of sub-pixels SP1, SP2, and SP3.

[0012] Figure 3 It shows along Figure 2 A schematic cross-sectional view of the device displaying the AB line.

[0013] Figure 4 This is a diagram showing an example of the configuration of display elements 201 to 203.

[0014] Figure 5 It shows along Figure 2 A schematic cross-sectional view of the CD line display device.

[0015] Figure 6 It shows along Figure 2 A schematic cross-sectional view of the display device for the EF line.

[0016] Figure 7 This is a diagram used to illustrate the EVA vapor deposition apparatus.

[0017] Figure 8 This is a diagram used to illustrate the vapor deposition apparatus EVB.

[0018] Figure 9 This is a diagram illustrating a manufacturing method for forming the upper electrode UE and the inorganic layer IL.

[0019] Figure 10 This is a diagram illustrating another manufacturing method for forming the upper electrode UE and the inorganic layer IL.

[0020] Figure 11 This is a flowchart illustrating an example of a manufacturing method for a display device DSP.

[0021] Figure 12 This figure shows an example of a manufacturing apparatus that can be applied to the process of forming the first thin film 31, the process of forming the second thin film 32, and the process of forming the third thin film 33.

[0022] Figure 13 This is a diagram showing another example of a manufacturing apparatus that can be applied to the process of forming the first thin film 31, the process of forming the second thin film 32, and the process of forming the third thin film 33.

[0023] Figure 14 This is a diagram illustrating a manufacturing method for a DSP used in display devices.

[0024] Figure 15 This is a diagram illustrating a manufacturing method for a DSP used in display devices.

[0025] Figure 16 This is a diagram used to illustrate the formation process of the first thin film 31.

[0026] Figure 17 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0027] Figure 18 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0028] Figure 19 This is a diagram used to illustrate the removal process of the first thin film 31.

[0029] Figure 20 This is a diagram used to illustrate the manufacturing method of a display device DSP. Detailed Implementation

[0030] An embodiment is described with reference to the accompanying drawings.

[0031] This disclosure is merely an example, and appropriate modifications that remain consistent with the spirit of the invention and are readily apparent to those skilled in the art are of course included within the scope of this invention. Furthermore, to make the description clearer, the width, thickness, shape, etc., of various parts in the drawings are sometimes shown schematically compared to the actual form, but this is merely an example and does not limit the interpretation of the invention. Additionally, in this specification and the figures, the same reference numerals are used for components that perform the same or similar functions as those described with respect to previously presented figures, and sometimes repeated detailed descriptions are appropriately omitted.

[0032] In addition, for ease of understanding, the X, Y, and Z axes, which are orthogonal to each other, are shown. The direction along the X-axis is called the first direction, the direction along the Y-axis is called the second direction, and the direction along the Z-axis is called the third direction. Observing various elements parallel to the third direction Z is called a top view.

[0033] The display device in this embodiment is an organic electroluminescent display device that has an organic light-emitting diode (OLED) as a display element, and can be mounted on televisions, personal computers, in-vehicle devices, smartphones, mobile phones, etc.

[0034] Figure 1 This is a diagram illustrating an example of the configuration of a display device DSP.

[0035] The display device DSP has a display area DA for displaying images and a peripheral area SA surrounding the display area DA on an insulating substrate 10. The substrate 10 can be glass or a flexible resin film.

[0036] In this embodiment, the substrate 10 is rectangular when viewed from above. However, the shape of the substrate 10 when viewed from above is not limited to a rectangle, and may also be other shapes such as a square, a circle, or an ellipse.

[0037] The display area DA has multiple pixels PX arranged in a matrix in the first direction X and the second direction Y. Pixel PX includes multiple sub-pixels SP. In one example, pixel PX includes a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. The first color, the second color, and the third color are different colors from each other. In addition, pixel PX may include sub-pixels SP1, SP2, SP3, and sub-pixels SP of other colors such as white, or it may replace one of the sub-pixels SP1, SP2, SP3 with a sub-pixel SP of other colors such as white.

[0038] The sub-pixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are, for example, switching elements composed of thin-film transistors.

[0039] The gate electrode of pixel switch 2 is connected to scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to signal line SL, and the other is connected to the gate electrode of driving transistor 3 and capacitor 4. In driving transistor 3, one of the source and drain electrodes is connected to power line PL and capacitor 4, and the other is connected to the anode of display element 20.

[0040] Furthermore, the configuration of pixel circuit 1 is not limited to the example shown in the figure. For example, pixel circuit 1 may also have more thin-film transistors and capacitors.

[0041] Display element 20 is an organic light-emitting diode (OLED) that serves as a light-emitting element, sometimes referred to as an organic EL element.

[0042] Figure 2 This is a diagram showing an example of the layout of sub-pixels SP1, SP2, and SP3.

[0043] exist Figure 2 In the example, sub-pixels SP2 and SP3 are arranged in the second direction Y. Moreover, sub-pixels SP2 and SP3 are arranged in the first direction X with sub-pixel SP1.

[0044] With sub-pixels SP1, SP2, and SP3 arranged in this layout, the display area DA contains columns of sub-pixels SP2 and SP3 alternately arranged in the second direction Y, and columns of multiple sub-pixels SP1 repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0045] Furthermore, the layout of sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 For example, the sub-pixels SP1, SP2, and SP3 in each pixel PX can also be arranged in this order in the first direction X.

[0046] Ribs 5 and partitions 6 are configured in the display area DA. Ribs 5 have openings AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively.

[0047] The partition 6 overlaps with the rib 5 in a top view. The partition 6 includes a plurality of first partitions 6x extending along a first direction X and a plurality of second partitions 6y extending along a second direction Y. The plurality of first partitions 6x are respectively disposed between adjacent openings AP2 and AP3 in the second direction Y, and between two adjacent openings AP1 in the second direction Y. The second partitions 6y are respectively disposed between adjacent openings AP1 and AP2 in the first direction X, and between adjacent openings AP1 and AP3 in the first direction X.

[0048] exist Figure 2 In the example, the first partition 6x and the second partition 6y are connected to each other. Thus, the partition 6 as a whole is formed into a lattice shape surrounding the openings AP1, AP2, and AP3. The partition 6 can also be configured to have openings in the sub-pixels SP1, SP2, and SP3, similar to the rib 5.

[0049] Subpixels SP1, SP2, and SP3 serve as display elements 201, 202, and 203, respectively.

[0050] Sub-pixel SP1 has a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with opening AP1. Sub-pixel SP2 has a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with opening AP2. Sub-pixel SP3 has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with opening AP3.

[0051] exist Figure 2 In the example, the outlines of the lower electrodes LE1, LE2, and LE3 are shown with dashed lines, while the outlines of the organic layers OR1, OR2, and OR3, and the upper electrodes UE1, UE2, and UE3 are shown with dotted lines. The periphery of each of the lower electrodes LE1, LE2, and LE3 overlaps with the rib 5. Furthermore, the outlines of the lower electrodes, organic layers, and upper electrodes shown in the illustration are not limited to reflecting their exact shapes.

[0052] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 constitute the display element 201 of sub-pixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 constitute the display element 202 of sub-pixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 constitute the display element 203 of sub-pixel SP3.

[0053] The lower electrodes LE1, LE2, and LE3 correspond to the anode of the display element, for example. The upper electrodes UE1, UE2, and UE3 correspond to the cathode of the display element, or a common electrode.

[0054] The lower electrode LE1 is connected to the pixel circuit 1 of sub-pixel SP1 through the contact hole CH1 (see reference). Figure 1 The lower electrode LE2 is connected to the pixel circuit 1 of sub-pixel SP2 through contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of sub-pixel SP3 through contact hole CH3.

[0055] exist Figure 2 In the example, the area of ​​opening AP1 is larger than the area of ​​opening AP2, and the area of ​​opening AP2 is larger than the area of ​​opening AP3. In other words, the area of ​​the lower electrode LE1 exposed through opening AP1 is larger than the area of ​​the lower electrode LE2 exposed through opening AP2, and the area of ​​the lower electrode LE2 exposed through opening AP2 is larger than the area of ​​the lower electrode LE3 exposed through opening AP3.

[0056] For example, the display element 201 of sub-pixel SP1 is configured to emit light in the blue wavelength range. In addition, the display element 202 of sub-pixel SP2 is configured to emit light in the green wavelength range, and the display element 203 of sub-pixel SP3 is configured to emit light in the red wavelength range.

[0057] Figure 3 It is along Figure 2 A schematic cross-sectional view of the DSP display device with AB lines in the image.

[0058] The circuit layer 11 is disposed on the substrate 10 described above. The circuit layer 11 includes... Figure 1 The diagram shows various circuits such as pixel circuit 1, scan lines GL, signal lines SL, power lines PL, etc. Circuit layer 11 is covered by insulating layer 12. Insulating layer 12 functions as a planarization film to flatten the unevenness formed by circuit layer 11.

[0059] Lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12. Ribs 5 are disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the ribs 5. That is, the ends of the lower electrodes LE1, LE2, and LE3 are disposed between the insulating layer 12 and the ribs 5. Between adjacent lower electrodes among the lower electrodes LE1, LE2, and LE3, the insulating layer 12 is covered by the ribs 5.

[0060] The partition 6 includes a lower part (stem part) 61 disposed above the rib 5 and an upper part (hat part) 62 disposed above the lower part 61. The lower part 61 of the partition 6 shown on the left side of the figure is located between opening AP1 and opening AP2. The lower part 61 of the partition 6 shown on the right side of the figure is located between opening AP2 and opening AP3. The upper part 62 has a wider width than the lower part 61. Therefore, in Figure 3 The two ends of the upper part 62 protrude more than the sides of the lower part 61. This shape of the partition 6 can also be described as a pendant shape. The part of the upper part 62 that protrudes toward the opening AP1 compared to the lower part 61 is called the protrusion 621, the part that protrudes toward the opening AP2 compared to the lower part 61 is called the protrusion 622, and the part that protrudes toward the opening AP3 compared to the lower part 61 is called the protrusion 623.

[0061] The organic layer OR1 covers the lower electrode LE1 through contact with the lower electrode LE1 from the opening AP1 and overlaps a portion of the rib 5. The upper electrode UE1 is opposite to the lower electrode LE1 and is disposed on the organic layer OR1. Moreover, the upper electrode UE1 is in contact with the side of the lower portion 61. The organic layer OR1 and the upper electrode UE1 are located below the upper portion 62.

[0062] The organic layer OR2 covers the lower electrode LE2 through contact with the opening AP2 and overlaps a portion of the rib 5. The upper electrode UE2 is opposite to the lower electrode LE2 and is disposed on the organic layer OR2. Moreover, the upper electrode UE2 is in contact with the side of the lower portion 61. The organic layer OR2 and the upper electrode UE2 are located below the upper portion 62.

[0063] The organic layer OR3 extends from the opening AP3, covers the lower electrode LE3 through contact with it, and overlaps a portion of the rib 5. The upper electrode UE3 is opposite to the lower electrode LE3 and is disposed on top of the organic layer OR3. Furthermore, the upper electrode UE3 is in contact with the side of the lower portion 61. The organic layer OR3 and the upper electrode UE3 are located below the upper portion 62.

[0064] exist Figure 3 In the example shown, sub-pixels SP1, SP2, SP3 include capping layers (optical adjustment layers) CP1, CP2, CP3 for adjusting the optical properties of the light emitted by the light-emitting layers of organic layers OR1, OR2, OR3.

[0065] Cap layer CP1 is located at opening AP1, below the upper part 62, and disposed above the upper electrode UE1. Cap layer CP2 is located at opening AP2, below the upper part 62, and disposed above the upper electrode UE2. Cap layer CP3 is located at opening AP3, below the upper part 62, and disposed above the upper electrode UE3.

[0066] Subpixels SP1, SP2, and SP3 are respectively equipped with sealing layers SE1, SE2, and SE3.

[0067] Sealing layer SE1 is connected to capping layer CP1, and the lower part 61 and upper part 62 of partition 6, continuously covering all components of sub-pixel SP1. Sealing layer SE2 is connected to capping layer CP2, and the lower part 61 and upper part 62 of partition 6, continuously covering all components of sub-pixel SP1. Sealing layer SE3 is connected to capping layer CP3, and the lower part 61 and upper part 62 of partition 6, continuously covering all components of sub-pixel SP1.

[0068] Sealing layers SE1, SE2, and SE3 are covered by protective layer 13.

[0069] exist Figure 3 In the example shown, a portion of the organic layer OR1, a portion of the upper electrode UE1, and a portion of the capping layer CP1 are located between the partition 6 and the sealing layer SE1, disposed above the upper portion 62, and separated from the portion located below the upper portion 62.

[0070] In addition, a portion of the organic layer OR2, a portion of the upper electrode UE2, and a portion of the capping layer CP2 are located between the partition 6 and the sealing layer SE2, disposed above the upper part 62, and separated from the portion located below the upper part 62.

[0071] In addition, a portion of the organic layer OR3, a portion of the upper electrode UE3, and a portion of the capping layer CP3 are located between the partition 6 and the sealing layer SE3, disposed above the upper part 62, and separated from the portion located below the upper part 62.

[0072] Insulation layer 12 is an organic insulation layer. Ribs 5 and sealing layers SE1, SE2, and SE3 are inorganic insulation layers.

[0073] Sealing layers SE1, SE2, and SE3 are formed, for example, using the same inorganic insulating material.

[0074] Rib 5 is formed using silicon nitride (SiNx), an example of an inorganic insulating material. Alternatively, rib 5 can be formed as a monolayer of silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3), using other inorganic insulating materials. Furthermore, rib 5 can also be formed as a laminate based on at least two combinations of silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide layers.

[0075] Encapsulating layers SE1, SE2, and SE3 are formed using silicon nitride (SiNx), an example of an inorganic insulating material. Alternatively, encapsulating layers SE1, SE2, and SE3 can also be formed as a monolayer of silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3) using other inorganic insulating materials. Furthermore, encapsulating layers SE1, SE2, and SE3 can also be formed as a laminate based on at least two combinations of silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide layers. Therefore, encapsulating layers SE1, SE2, and SE3 can be formed using the same material as rib 5.

[0076] The lower part 61 of the partition 6 is formed of a conductive material and is electrically connected to each of the upper electrodes UE1, UE2, and UE3. Both the lower part 61 and the upper part 62 of the partition 6 may also be conductive.

[0077] The thickness of rib 5 is sufficiently small compared to the thickness of partition 6 or insulating layer 12. In one example, the thickness of rib 5 is greater than 200 nm and less than 400 nm.

[0078] The thickness of the lower part 61 of the partition 6 (from the upper surface of the rib 5 to the lower surface of the upper part 62) is greater than the thickness of the rib 5.

[0079] The thicknesses of sealing layer SE1, sealing layer SE2, and sealing layer SE3 are basically equal.

[0080] The lower electrodes LE1, LE2, and LE3 can be formed of transparent conductive materials such as ITO, and have a layered structure of metallic materials such as silver (Ag) and transparent conductive materials. The upper electrodes UE1, UE2, and UE3 are formed of metallic materials such as an alloy of magnesium and silver (MgAg). The upper electrodes UE1, UE2, and UE3 can also be formed of transparent conductive materials such as ITO.

[0081] Each of the organic layers OR1, OR2, and OR3 includes multiple functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, an electron transport layer, and an electron injection layer. Additionally, organic layer OR1 includes a light-emitting layer EM1. Organic layer OR2 includes a light-emitting layer EM2. Light-emitting layer EM2 is formed of a different material than light-emitting layer EM1. Organic layer OR3 includes a light-emitting layer EM3. Light-emitting layer EM3 is formed of a different material than light-emitting layers EM1 and EM2.

[0082] The materials forming the light-emitting layer EM1, the light-emitting layer EM2, and the light-emitting layer EM3 are materials that emit light in different wavelength ranges.

[0083] In one example, the light-emitting layer EM1 is formed using a material that emits light in the blue wavelength range, the light-emitting layer EM2 is formed using a material that emits light in the green wavelength range, and the light-emitting layer EM3 is formed using a material that emits light in the red wavelength range.

[0084] The capping layers CP1, CP2, and CP3 are formed, for example, from a multilayer of transparent thin films. The multilayer, as a thin film, can include thin films formed of inorganic materials and thin films formed of organic materials. Furthermore, these multiple thin films have different refractive indices. The materials constituting the multilayer are different from the materials of the upper electrodes UE1, UE2, and UE3, and also different from the materials of the sealing layers SE1, SE2, and SE3. Alternatively, the capping layers CP1, CP2, and CP3 can be omitted.

[0085] The protective layer 13 is formed of a multilayer of transparent thin films, for example, as thin films, including thin films formed of inorganic materials and thin films formed of organic materials.

[0086] A common voltage is supplied to the partition 6. This common voltage is then supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the sides of the lower part 61. Pixel voltages are supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0087] If a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the luminescent layer EM1 in the organic layer OR1 emits light in the blue wavelength range. If a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the luminescent layer EM2 of the first part OR2a in the organic layer OR2 emits light in the green wavelength range. If a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the luminescent layer EM3 in the organic layer OR3 emits light in the red wavelength range.

[0088] Figure 4 This diagram shows an example of the configuration of display elements 201 to 203. Furthermore, the case where the lower electrode corresponds to the anode and the upper electrode corresponds to the cathode will be explained here as an example.

[0089] The display element 201 includes an organic layer OR1 between the lower electrode LE1 and the upper electrode UE1.

[0090] In the organic layer OR1, the hole injection layer HIL1, the hole transport layer HTL1, the electron blocking layer EBL1, the light emitting layer EM1, the hole blocking layer HBL1, the electron transport layer ETL1, and the electron injection layer EIL1 are stacked in this order.

[0091] The capping layer CP1 includes a transparent layer TL1 and an inorganic layer IL1. The transparent layer TL1 is disposed on the upper electrode UE1. The inorganic layer IL1 is disposed on the transparent layer TL1. The sealing layer SE1 is disposed on the inorganic layer IL1.

[0092] The display element 202 includes an organic layer OR2 between the lower electrode LE2 and the upper electrode UE2.

[0093] In the organic layer OR2, the hole injection layer HIL2, the hole transport layer HTL2, the electron blocking layer EBL2, the light-emitting layer EM2, the hole blocking layer HBL2, the electron transport layer ETL2, and the electron injection layer EIL2 are stacked in this order.

[0094] The capping layer CP2 includes a transparent layer TL2 and an inorganic layer IL2. The transparent layer TL2 is disposed above the upper electrode UE2. The inorganic layer IL2 is disposed above the transparent layer TL2. The sealing layer SE2 is disposed above the inorganic layer IL2.

[0095] The display element 203 includes an organic layer OR3 between the lower electrode LE3 and the upper electrode UE3.

[0096] In the organic layer OR3, the hole injection layer HIL3, the hole transport layer HTL3, the electron blocking layer EBL3, the light-emitting layer EM3, the hole blocking layer HBL3, the electron transport layer ETL3, and the electron injection layer EIL3 are stacked in this order.

[0097] The capping layer CP3 comprises a transparent layer TL3 and an inorganic layer IL3. The transparent layer TL3 is disposed above the upper electrode UE3. The inorganic layer IL3 is disposed above the transparent layer TL3. The sealing layer SE3 is disposed above the inorganic layer IL3.

[0098] The transparent layers TL1, TL2, and TL3 are organic layers formed from, for example, organic materials, and are also high-refractive-index layers having a higher refractive index than the upper electrodes UE1, UE2, and UE3. The inorganic layers IL1, IL2, and IL3 are, for example, transparent thin films formed from lithium fluoride (LiF), and are low-refractive-index layers having a lower refractive index than the transparent layers TL1, TL2, and TL3.

[0099] In addition, the capping layers CP1, CP2, and CP3 can be stacked in layers of three or more.

[0100] In addition to the functional layers mentioned above, the organic layers OR1, OR2, and OR3 may include other functional layers such as a carrier generation layer as needed, or at least one of the aforementioned functional layers may be omitted.

[0101] Furthermore, the aforementioned functional layers are formed individually for each display element 201 to 203. Therefore, the thickness of each of the aforementioned functional layers may vary depending on the individual display elements 201 to 203.

[0102] Furthermore, when focusing on the same functional layer, there are cases where the functional layer of one of the display elements 201 to 203 is formed using a different material than the functional layers of the other two display elements, and there are also cases where all the functional layers of the display elements 201 to 203 are formed using different materials from each other.

[0103] Furthermore, there are cases where the layer configuration of one of the display elements 201-203 differs from the layer configurations of the other two display elements, and there are also cases where the layer configurations of all display elements 201-203 differ from each other. For example, when focusing on a single functional layer, there are cases where one of the display elements 201-203 does not include that functional layer, and there are cases where only one of the display elements 201-203 includes that functional layer. Additionally, when focusing on a single functional layer, there are cases where the functional layer in one of the display elements 201-203 is configured as multiple layers, etc.

[0104] The transparent layers TL1 to TL3 are separated from each other and formed individually. Therefore, there are cases where all transparent layers TL1 to TL3 are formed using the same material, cases where one of the transparent layers TL1 to TL3 is formed using a different material than the other two transparent layers, and cases where all transparent layers TL1 to TL3 are formed using different materials. In addition, the thickness of each of the transparent layers TL1 to TL3 may be the same or different from each other.

[0105] The inorganic layers IL1 to IL3 are separated from each other and formed individually. Therefore, there are cases where all inorganic layers IL1 to IL3 are formed using the same material, cases where one of the inorganic layers IL1 to IL3 is formed using a different material than the other two, and cases where all inorganic layers IL1 to IL3 are formed using different materials. Furthermore, the thickness of each of the inorganic layers IL1 to IL3 may be the same or different.

[0106] In addition, there are cases where all the capping layers CP1 to CP3 have the same structure, cases where the structure of one of the capping layers CP1 to CP3 is different from the structure of the other two capping layers, and cases where all the capping layers CP1 to CP3 have different structures from each other.

[0107] exist Figure 4 In the examples shown, in display element 201, the upper electrode UE1 and the inorganic layer IL1 function as etch stop layers during dry etching of the sealing layer SE1. In display element 202, the upper electrode UE2 and the inorganic layer IL2 function as etch stop layers during dry etching of the sealing layer SE2. In display element 203, the upper electrode UE3 and the inorganic layer IL3 function as etch stop layers during dry etching of the sealing layer SE3.

[0108] If the etching rates of the etch stop layer and the capping layer are compared under the same conditions using dry etching, the etching rate of the etch stop layer (upper electrode and inorganic layer) is lower than that of the capping layer. Therefore, when dry etching is performed on a stack of layers with a capping layer stacked on top of the etch stop layer, the capping layer can be removed, and on the other hand, etching in the etch stop layer can be prevented.

[0109] The etching barrier layers function by forming upper electrodes UE1, UE2, and UE3, which are made of a different material than rib 5 and a different material than sealing layers SE1, SE2, and SE3. For example, while rib 5 and sealing layers SE1, SE2, and SE3 are made of silicon nitride, upper electrodes UE1, UE2, and UE3 are formed using an alloy of magnesium and silver, which are materials with high resistance to dry etching, compared to silicon nitride.

[0110] Furthermore, the inorganic layers IL1, IL2, and IL3, which function as etching inhibitor layers, are formed of a different material than rib 5, and also of a different material than the sealing layers SE1, SE2, and SE3. For example, while rib 5 and sealing layers SE1, SE2, and SE3 are formed of silicon nitride, the inorganic layers IL1, IL2, and IL3 are formed using lithium fluoride, a material with high resistance to dry etching, compared to silicon nitride.

[0111] Figure 5 It is along Figure 2 A schematic cross-sectional view of the DSP display device for the CD line. Figure 5 The cross-sectional view shown includes multiple sub-pixels SP1 arranged in the second direction Y. Furthermore, in Figure 5 in, omit Figure 3 The diagram shows the substrate, circuit layer, and protective layer.

[0112] Focusing on the sub-pixel SP1 located at the center of the diagram, in the YZ cross-section defined by the second direction Y and the third direction Z, the lower part 61 of the partition 6 has side surfaces S1A and S1B facing each other across the sub-pixel SP1. Side surface S1B, within the sub-pixel SP1, extends along a path provided with... Figure 2 The edge of the contact hole CH1 is shown. In the organic layer OR1, the two ends along the second direction Y are located above the rib 5 and separated from the sides S1A and S1B. That is, the rib 5 is exposed between the partition wall 6 and the organic layer OR1.

[0113] The upper electrode UE1 has an end UE1A along the second direction Y, and an end UE1B on the opposite side of end UE1A. End UE1A faces side S1A, and end UE1B faces side S1B. The upper electrode UE1 is covered by an organic layer OR1, and a rib 5 is covered between the organic layer OR1 and the partition wall 6. In the illustrated example, the upper electrode UE1 is in contact with both sides S1A and S1B. However, the contact area between the upper electrode UE1 and side S1B is larger than the contact area between the upper electrode UE1 and side S1A.

[0114] A capping layer CP1 is disposed on the upper electrode UE1. In the capping layer CP1, at least an inorganic layer IL1 covers the end UE1A of the upper electrode UE1 and is in contact with the side surface S1A. In the illustrated example, the inorganic layer IL1 exposes the end UE1B of the upper electrode UE1 and is separated from the side surface S1B. The end UE1B is covered by a sealing layer SE1.

[0115] The contact area between side S1A and inorganic layer IL1 is larger than the contact area between side S1A and upper electrode UE1. Furthermore, the contact area between side S1B and upper electrode UE1 is larger than the contact area between side S1B and inorganic layer IL1.

[0116] In this way, at least one of the upper electrode UE1 and the inorganic layer IL1 is disposed between the rib 5 and the sealing layer SE1, between the organic layer OR1 and the partition 6.

[0117] exist Figure 5 In the example shown, for instance, end UE1A corresponds to the first end, end UE1B corresponds to the second end, side S1A corresponds to the first side, and side S1B corresponds to the second side.

[0118] Figure 6 It is along Figure 2 A schematic cross-sectional view of the DSP display device with EF lines in the image. Figure 6 The cross-sectional view shown includes sub-pixels SP2 and SP3 arranged alternately in the second direction Y. Furthermore, in Figure 6 in, omit Figure 3 The diagram shows the substrate, circuit layer, and protective layer.

[0119] Focusing on sub-pixel SP3 located on the left side of the figure, in the YZ cross section, the lower part 61 of partition 6 has side surfaces S3A and S3B facing each other across sub-pixel SP3. Side surface S3B runs along a line provided in sub-pixel SP3. Figure 2 The edge of the contact hole CH3 is shown. In the organic layer OR3, the two ends along the second direction Y are located above the rib 5 and separated from the sides S3A and S3B. That is, it is exposed from the rib 5 between the partition wall 6 and the organic layer OR3.

[0120] The upper electrode UE3 has an end UE3A and an end UE3B opposite to the end UE3A along the second direction Y. End UE3A faces side S3A, and end UE3B faces side S3B. The upper electrode UE3 is covered with an organic layer OR3, and a rib 5 is covered between the organic layer OR3 and the partition wall 6. In the illustrated example, the upper electrode UE3 is in contact with both sides S3A and S3B. However, the contact area between the upper electrode UE3 and side S3B is larger than the contact area between the upper electrode UE3 and side S3A.

[0121] A capping layer CP3 is disposed on the upper electrode UE3. In the capping layer CP3, at least the inorganic layer IL3 covers the end UE3A of the upper electrode UE3, which is in contact with the side surface S3A. In the illustrated example, the inorganic layer IL3 exposes the end UE3B of the upper electrode UE3, which is separated from the side surface S3B. The end UE3B is covered by a sealing layer SE3.

[0122] The contact area between side S3A and inorganic layer IL3 is larger than the contact area between side S3A and upper electrode UE3. Furthermore, the contact area between side S3B and upper electrode UE3 is larger than the contact area between side S3B and inorganic layer IL3.

[0123] In this way, at least one of the upper electrode UE3 and the inorganic layer IL3 is disposed between the rib 5 and the sealing layer SE1, between the organic layer OR3 and the partition 6.

[0124] If we focus on the sub-pixel SP2 located on the right side of the diagram, then in the organic layer OR2, the two ends along the second direction Y are located above the rib 5 and separated from the partition 6.

[0125] The upper electrode UE2 is covered with an organic layer OR2, and the capping layer CP2 is disposed on the upper electrode UE2. The upper electrode UE2 is connected to the partition wall 6 in the center of the figure, and at least the inorganic layer IL2 (not shown) in the capping layer CP2 is connected to the partition wall 6 on the right side of the figure.

[0126] In this way, at least one of the upper electrode UE2 and the inorganic layer IL2 is disposed between the rib 5 and the sealing layer SE2, between the organic layer OR2 and the partition 6.

[0127] Next, the vapor deposition apparatus used to form the etch stop layer will be described.

[0128] Figure 7 This is a diagram used to illustrate the EVA vapor deposition apparatus.

[0129] The vapor deposition apparatus EVA includes a transport mechanism 100A, a vapor deposition source 110A, and a chamber 130A. The chamber 130A has a transport inlet 131A for loading the processed substrate SUB and a transport outlet 132A for unloading the processed substrate SUB. The display device manufacturing apparatus described in this specification is a single-row arrangement; the transport inlet 131A is connected to other vapor deposition apparatuses, and the transport outlet 132A is further connected to other vapor deposition apparatuses.

[0130] The transport mechanism 100A is configured to transport a processing substrate SUB. This processing substrate SUB has, for example, a circuit layer 11, an insulating layer 12, a lower electrode LE, a rib 5, a partition 6, and an organic layer OR formed on a substrate 10. The transport mechanism 100A transports the processing substrate SUB from the transport inlet 131A to the transport outlet 132A. The transport direction TD of the processing substrate SUB is, for example, parallel to the second direction Y in the aforementioned display device DSP.

[0131] The vapor deposition source 110A is configured to eject material MA for forming the etch stop layer ES. The vapor deposition source 110A is housed within a chamber 130A and fixed to the chamber 130A using a fixing device (not shown). The vapor deposition source 110A has a nozzle 120A that defines the ejection direction of the material MA. An outlet 121A is formed at the tip of the nozzle 120A. This vapor deposition source 110A is inclined relative to the normal N of the processed substrate SUB (or the normal N of the substrate 10).

[0132] The vapor deposition source 110A shown in the diagram is tilted to the right relative to the normal N. At this time, the nozzle 121A faces the inlet 131A. That is, the vapor deposition source 110A ejects material MA in the opposite direction of the arrow in the transport direction TD of the processed substrate SUB. The tilt angle θA of the vapor deposition source 110A can be defined as the angle between the normal N and the extending direction of the nozzle 120A in a cross-section defined by the transport direction TD of the processed substrate SUB and the normal N of the processed substrate SUB. The tilt angle θA of the vapor deposition source 110A is an acute angle formed clockwise relative to the normal N. The tilt angle θA is, for example, 5° or more and 40° or less.

[0133] In this vapor deposition apparatus EVA, the following processing is performed on the processing substrate SUB that is moved from the inlet 131A into the interior of the chamber 130A.

[0134] First, material MA is ejected from the evaporation source 110A. Then, the transport mechanism 100A transports the processing substrate SUB while depositing the material MA ejected from the evaporation source 110A onto the processing substrate SUB. At this time, the material MA ejected from the evaporation source 110A is deposited on the organic layer OR and extends to the lower part 61 of the partition wall 6 on the left side of the figure. As a result, an etch stop layer ES with this cross-section shown in dashed lines is formed, and the rib 5 between the organic layer OR and the partition wall 6 is covered by the etch stop layer ES.

[0135] Figure 8 This is a diagram used to illustrate the vapor deposition apparatus EVB.

[0136] The vapor deposition apparatus EVB includes a transport mechanism 100B, a vapor deposition source 110B, and a chamber 130B. The chamber 130B has a transport inlet 131B for transporting in the processing substrate SUB and a transport outlet 132B for transporting out the processing substrate SUB.

[0137] Figure 8 The vapor deposition apparatus EVB shown is Figure 7 The difference between the vapor deposition apparatus shown and the EVA is that the vapor deposition source 110B is tilted in the opposite direction to the normal N direction of the processing substrate SUB.

[0138] The vapor deposition source 110B is configured to eject material MB for forming the etch stop layer ES. The vapor deposition source 110B is housed within a chamber 130B and fixed to the chamber 130B using a fixing device (not shown). The vapor deposition source 110B has a nozzle 120B that defines the ejection direction of the material MB. An outlet 121B is formed at the tip of the nozzle 120B.

[0139] The vapor deposition source 110B shown in the diagram is tilted to the left relative to the normal N. At this time, the nozzle 121B faces the transfer outlet 132B. That is, the vapor deposition source 110B ejects material MB in the direction of the arrow in the transport direction TD of the processed substrate SUB. The tilt angle θB of the vapor deposition source 110B can be defined as the angle between the normal N and the extending direction of the nozzle 120B in a cross-section defined by the transport direction TD of the processed substrate SUB and the normal N of the processed substrate SUB. The tilt angle θB of the vapor deposition source 110B is an acute angle formed counterclockwise relative to the normal N. The tilt angle θB is, for example, 5° or more and 40° or less.

[0140] In this vapor deposition apparatus EVB, the processing substrate SUB that is moved from the inlet 131B into the interior of the chamber 130B is processed as follows.

[0141] First, material MB is ejected from the vapor deposition source 110B. Then, the transport mechanism 100B transports the processing substrate SUB while depositing the material MB ejected from the vapor deposition source 110B onto the processing substrate SUB. At this time, the material MB ejected from the vapor deposition source 110B is deposited on the organic layer OR and extends to the lower part 61 of the partition wall 6 on the right side of the figure. As a result, an etch stop layer ES with a cross-section shown in dashed lines is formed, and the rib 5 between the organic layer OR and the partition wall 6 is covered by the etch stop layer ES.

[0142] Figure 9 This is a diagram illustrating a manufacturing method for forming the upper electrode UE and the inorganic layer IL.

[0143] In the illustrated example, Figure 7 The vapor deposition apparatus EVA shown includes a vapor deposition source 110A, which corresponds to the first vapor deposition source, and is located upstream of the transport direction TD. Additionally, Figure 8 The vapor deposition apparatus EVB shown includes a vapor deposition source 110B, which corresponds to the second vapor deposition source, and is located downstream of the transport direction TD. Vapor deposition sources 110A and 110B are inclined as described above, and are inclined in opposite directions to each other.

[0144] An upper electrode UE is formed in the vapor deposition apparatus EVA, an inorganic layer IL is formed in the vapor deposition apparatus EVB, and a transparent layer TL is formed between the vapor deposition apparatus EVA and the vapor deposition apparatus EVB. That is, the material MA ejected from the vapor deposition source 110A is a mixture of magnesium and silver, and the material MB ejected from the vapor deposition source 110B is lithium fluoride.

[0145] The processing substrate SUB has one end SUBA and the other end SUBB facing each other along the direction in which the sub-pixels SP2 and SP3 are arranged. The transport direction TD of the processing substrate SUB is parallel to the direction in which the sub-pixels SP2 and SP3 are arranged.

[0146] In forming the upper electrode UE1, transparent layer TL1, and inorganic layer IL1 of sub-pixel SP1, one end SUBA is used as the front-end transport processing substrate SUB. First, the upper electrode UE1 is formed in the vapor deposition apparatus EVA. Then, after the transparent layer TL1 is formed, the inorganic layer IL1 is formed in the vapor deposition apparatus EVB.

[0147] In the case of forming the upper electrode UE3, transparent layer TL3, and inorganic layer IL3 of sub-pixel SP3, one end SUBA is also used as the front-end transport processing substrate SUB.

[0148] In the case of forming the upper electrode UE2, transparent layer TL2, and inorganic layer IL2 of sub-pixel SP2, the other end SUBB serves as the front-end transport processing substrate SUB. First, the upper electrode UE2 is formed in the vapor deposition apparatus EVA. Subsequently, after the transparent layer TL2 is formed, the inorganic layer IL2 is formed in the vapor deposition apparatus EVB.

[0149] Figure 10 This is a diagram illustrating another manufacturing method for forming the upper electrode UE and the inorganic layer IL.

[0150] In the illustrated example, Figure 8 The vapor deposition apparatus EVB shown includes a vapor deposition source 110B, equivalent to the first vapor deposition source, located upstream of the transport direction TD. Additionally, Figure 7 The vapor deposition apparatus EVA shown includes a vapor deposition source 110A, which is equivalent to the second vapor deposition source, and is located downstream of the transport direction TD. An upper electrode UE is formed in the vapor deposition apparatus EVB, and an inorganic layer IL is formed in the vapor deposition apparatus EVA. That is, the material MB ejected from the vapor deposition source 110B is a mixture of magnesium and silver, and the material MA ejected from the vapor deposition source 110A is lithium fluoride.

[0151] In the case of forming the upper electrode UE1, transparent layer TL1, and inorganic layer IL1 of sub-pixel SP1, the other end SUBB serves as the front-end transport processing substrate SUB. First, the upper electrode UE1 is formed in the vapor deposition apparatus EVB. Then, after forming the transparent layer TL1, the inorganic layer IL1 is formed in the vapor deposition apparatus EVA.

[0152] In the case of forming the upper electrode UE3, transparent layer TL3, and inorganic layer IL3 of sub-pixel SP3, the other end SUBB is also used as the front-end transport processing substrate SUB.

[0153] In forming the upper electrode UE2, transparent layer TL2, and inorganic layer IL2 of sub-pixel SP2, one end SUBA is used as the front-end transport processing substrate SUB. First, the upper electrode UE2 is formed in the vapor deposition apparatus EVB. Then, after the transparent layer TL2 is formed, the inorganic layer IL2 is formed in the vapor deposition apparatus EVA.

[0154] also, Figures 7-10 The vapor deposition apparatus EVA and EVB shown in the example are configured to transport the processing substrate SUB with the vapor deposition surface of the processing substrate SUB above the substrate 10 (face upward), and to eject materials MA and MB downward from the vapor deposition sources 110A and 110B, but are not limited to this configuration. For example, the vapor deposition apparatus EVA and EVB may also be configured to transport the processing substrate SUB with the vapor deposition surface of the processing substrate SUB below the substrate 10 (face downward), and to eject materials MA and MB upward from the vapor deposition sources 110A and 110B. Alternatively, the vapor deposition apparatus EVA and EVB may be configured to transport the processing substrate SUB with it vertically upright relative to the horizontal plane, and to eject materials MA and MB by placing the vapor deposition sources 110A and 110B horizontally.

[0155] Next, an example of a manufacturing method for a display device DSP will be described.

[0156] Figure 11 This is a flowchart illustrating an example of a manufacturing method for a display device DSP.

[0157] The manufacturing method shown here generally includes a process of preparing a processing substrate SUB having sub-pixels SP1, SP2, and SP3 (step ST1), a process of forming a display element 201 of sub-pixels SP1 (step ST2), a process of forming a display element 202 of sub-pixels SP2 (step ST3), and a process of forming a display element 203 of sub-pixels SP3 (step ST4).

[0158] In step ST1, firstly, a processing substrate SUB is prepared on the substrate 10, on which the lower electrode LE1 of sub-pixel SP1, the lower electrode LE2 of sub-pixel SP2, the lower electrode LE3 of sub-pixel SP3, the rib 5, and the partition wall 6 are formed. Figure 3 As shown, a circuit layer 11 and an insulating layer 12 are also formed between the substrate 10 and the lower electrodes LE1, LE2, and LE3.

[0159] In step ST2, firstly, a first thin film 31, including a light-emitting layer EM1, is formed over sub-pixels SP1, SP2, and SP3 (step ST21). Then, a first resist 41 patterned into a predetermined shape is formed on the first thin film 31 (step ST22). Next, a portion of the first thin film 31 is removed by etching using the first resist 41 as a mask (step ST23). Then, the first resist 41 is removed (step ST24). Thus, sub-pixels SP1 are formed. Sub-pixels SP1 are display elements 201 having the first thin film 31 with a predetermined shape.

[0160] In step ST3, firstly, a second thin film 32, including the second light-emitting layer EM2, is formed over sub-pixels SP1, SP2, and SP3 (step ST31). Then, a second resist 42 patterned into a predetermined shape is formed on the second thin film 32 (step ST32). Next, a portion of the second thin film 32 is removed by etching using the second resist 42 as a mask (step ST33). Then, the second resist 42 is removed (step ST34). Thus, sub-pixel SP2 is formed. Sub-pixel SP2 has a display element 202 with the second thin film 32 having a predetermined shape.

[0161] In step ST4, firstly, a third thin film 33, including a light-emitting layer EM3, is formed over sub-pixels SP1, SP2, and SP3 (step ST41). Then, a third resist 43 patterned into a predetermined shape is formed on the third thin film 33 (step ST42). Next, a portion of the third thin film 33 is removed by etching using the third resist 43 as a mask (step ST43). Then, the third resist 43 is removed (step ST44). Thus, sub-pixels SP3 are formed. Sub-pixels SP3 have a display element 203 with a third thin film 33 having a predetermined shape.

[0162] Furthermore, detailed illustrations of the second film 32, the second resist 42, the third film 33, and the third resist 43 are omitted.

[0163] Figure 12 This figure shows an example of a manufacturing apparatus that can be applied to the process of forming the first thin film 31, the process of forming the second thin film 32, and the process of forming the third thin film 33.

[0164] The processing substrate SUB, prepared in step ST1, is transported using one end SUBA as the front end.

[0165] First, the processing substrate SUB is fed into the vapor deposition apparatus 301. In the vapor deposition apparatus 301, a hole injection layer HIL1 is formed.

[0166] Subsequently, a hole transport layer HTL1 is formed in the vapor deposition apparatus 302.

[0167] Subsequently, an electron blocking layer EBL1 is formed in the vapor deposition apparatus 303.

[0168] Subsequently, an luminescent layer EM1 is formed in the vapor deposition apparatus 304.

[0169] Subsequently, a hole-blocking layer HBL1 is formed in the vapor deposition apparatus 305.

[0170] Subsequently, in the vapor deposition apparatus 306, the electron transport layer ETL1 is formed.

[0171] Subsequently, in the vapor deposition apparatus 307, an electron injection layer EIL1 is formed. Thus, an organic layer OR1 is formed.

[0172] After that, Figure 9 In the vapor deposition apparatus EVA1 shown, the upper electrode UE1 is formed.

[0173] Subsequently, a transparent layer TL1 is formed in the vapor deposition apparatus 308.

[0174] After that, Figure 9 In the vapor deposition apparatus EVB1 shown, an inorganic layer IL1 is formed. This forms a capping layer CP1.

[0175] Subsequently, a sealing layer SE1 is formed in the CVD (Chemical-Vapor Deposition) apparatus 309.

[0176] After that, after Figure 11 Following steps ST22 to ST24, the processing substrate SUB is moved into the vapor deposition apparatus 311 with one end SUB as the front end. In the vapor deposition apparatus 311, a hole injection layer HIL2 is formed.

[0177] Subsequently, a hole transport layer HTL2 is formed in the vapor deposition apparatus 312.

[0178] Subsequently, an electron blocking layer EBL2 is formed in the vapor deposition apparatus 313.

[0179] Subsequently, an luminescent layer EM2 is formed in the vapor deposition apparatus 314.

[0180] Subsequently, a hole-blocking layer HBL2 is formed in the vapor deposition apparatus 315.

[0181] Subsequently, in the vapor deposition apparatus 316, the electron transport layer ETL2 is formed.

[0182] Subsequently, in the vapor deposition apparatus 317, an electron injection layer EIL2 is formed. This forms the organic layer OR2.

[0183] After that, Figure 10 In the vapor deposition apparatus EVB2 shown, the upper electrode UE2 is formed.

[0184] Subsequently, a transparent layer TL2 is formed in the vapor deposition apparatus 318.

[0185] After that, Figure 10 In the vapor deposition apparatus EVA2 shown, an inorganic layer IL2 is formed. This forms a capping layer CP2.

[0186] Subsequently, a sealing layer SE2 is formed in the CVD apparatus 319.

[0187] After that, after Figure 11 Following steps ST32 to ST34, the processing substrate SUB is moved into the vapor deposition apparatus 321 with one end SUBA as the front end. In the vapor deposition apparatus 321, a hole injection layer HIL3 is formed.

[0188] Subsequently, a hole transport layer HTL3 is formed in the vapor deposition apparatus 322.

[0189] Subsequently, an electron blocking layer EBL3 is formed in the vapor deposition apparatus 323.

[0190] Subsequently, an luminescent layer EM3 is formed in the vapor deposition apparatus 324.

[0191] Subsequently, a hole-blocking layer HBL3 is formed in the vapor deposition apparatus 325.

[0192] Subsequently, in the vapor deposition apparatus 326, the electron transport layer ETL3 is formed.

[0193] Subsequently, in the vapor deposition apparatus 327, an electron-injected layer EIL3 is formed. This forms the organic layer OR3.

[0194] After that, Figure 9 In the vapor deposition apparatus EVA3 shown, the upper electrode UE3 is formed.

[0195] Subsequently, a transparent layer TL3 is formed in the vapor deposition apparatus 328.

[0196] After that, Figure 9 In the vapor deposition apparatus EVB3 shown, an inorganic layer IL3 is formed. This forms a capping layer CP3.

[0197] Subsequently, a sealing layer SE3 is formed in the CVD apparatus 329.

[0198] After that, proceed Figure 11 Steps ST42 to ST44 are shown.

[0199] The combination of vapor deposition apparatus EVA1 and vapor deposition apparatus EVB1, and the combination of vapor deposition apparatus EVA3 and vapor deposition apparatus EVB3, and Figure 9 The vapor deposition apparatus EVA and vapor deposition apparatus EVB shown are the same combination.

[0200] The combination of vapor deposition apparatus EVB2 and vapor deposition apparatus EVA2 and Figure 10 The vapor deposition apparatus EVB and vapor deposition apparatus EVA shown are the same combination.

[0201] Figure 13 This is a diagram showing another example of a manufacturing apparatus that can be applied to the process of forming the first thin film 31, the process of forming the second thin film 32, and the process of forming the third thin film 33.

[0202] The processing substrate SUB prepared in step ST1 is placed on the turntable TT and transported after being configured with one end of the SUB as the front end.

[0203] First, the processing substrate SUB is moved into the vapor deposition apparatus 301. In the vapor deposition apparatus 301, a hole injection layer HIL1 is formed.

[0204] Subsequently, a hole transport layer HTL1 is formed in the vapor deposition apparatus 302.

[0205] Subsequently, an electron blocking layer EBL1 is formed in the vapor deposition apparatus 303.

[0206] Subsequently, a light-emitting layer EM1 is formed in the vapor deposition apparatus 304. Vapor deposition apparatuses 314 and 324 pass through the processing substrate SUB without ejecting material.

[0207] Subsequently, a hole-blocking layer HBL1 is formed in the vapor deposition apparatus 305.

[0208] Subsequently, in the vapor deposition apparatus 306, the electron transport layer ETL1 is formed.

[0209] Subsequently, in the vapor deposition apparatus 307, an electron injection layer EIL1 is formed. Thus, an organic layer OR1 is formed.

[0210] After that, Figure 9 In the vapor deposition apparatus EVA shown, the upper electrode UE1 is formed.

[0211] Subsequently, a transparent layer TL1 is formed in the vapor deposition apparatus 308.

[0212] After that, Figure 9 In the vapor deposition apparatus EVB shown, an inorganic layer IL1 is formed. This forms a capping layer CP1.

[0213] Subsequently, a sealing layer SE1 is formed in the CVD apparatus 309.

[0214] After that, after Figure 11 After steps ST22 to ST24 shown, the processing substrate SUB is positioned on the turntable TT and transported after being positioned with the other end SUB as the front end.

[0215] Then, the processed substrate SUB is once again moved into the vapor deposition apparatus 301. In the vapor deposition apparatus 301, a hole injection layer HIL2 is formed.

[0216] Subsequently, a hole transport layer HTL2 is formed in the vapor deposition apparatus 302.

[0217] Subsequently, an electron blocking layer EBL2 is formed in the vapor deposition apparatus 303.

[0218] Subsequently, in the vapor deposition apparatus 314, the light-emitting layer EM2 is formed. The vapor deposition apparatuses 304 and 324 pass through the processing substrate SUB without ejecting material.

[0219] Subsequently, a hole-blocking layer HBL2 is formed in the vapor deposition apparatus 305.

[0220] Subsequently, in the vapor deposition apparatus 306, the electron transport layer ETL2 is formed.

[0221] Subsequently, in the vapor deposition apparatus 307, an electron-injected layer EIL2 is formed. This forms the organic layer OR2.

[0222] Subsequently, the upper electrode UE2 is formed in the vapor deposition apparatus EVA.

[0223] Subsequently, a transparent layer TL2 is formed in the vapor deposition apparatus 308.

[0224] Subsequently, an inorganic layer IL2 is formed in the vapor deposition apparatus EVB. This forms the capping layer CP2.

[0225] Subsequently, a sealing layer SE2 is formed in the CVD apparatus 309.

[0226] After that, after Figure 11 After steps ST32 to ST34 shown, the processing substrate SUB is placed on the turntable TT and transported after being arranged with one end of SUB as the front end.

[0227] Then, the processed substrate SUB is moved into the vapor deposition apparatus 301 again. In the vapor deposition apparatus 301, the hole injection layer HIL3 is formed.

[0228] Subsequently, a hole transport layer HTL3 is formed in the vapor deposition apparatus 302.

[0229] Subsequently, an electron blocking layer EBL3 is formed in the vapor deposition apparatus 303.

[0230] Subsequently, an emitting layer EM3 is formed in the vapor deposition apparatus 324. Vapor deposition apparatuses 304 and 314 pass through the processing substrate SUB without ejecting material.

[0231] Subsequently, a hole-blocking layer HBL3 is formed in the vapor deposition apparatus 305.

[0232] Subsequently, in the vapor deposition apparatus 306, the electron transport layer ETL3 is formed.

[0233] Subsequently, in the vapor deposition apparatus 307, an electron-injected layer EIL3 is formed. This forms the organic layer OR3.

[0234] Subsequently, the upper electrode UE3 is formed in the vapor deposition apparatus EVA.

[0235] Subsequently, a transparent layer TL3 is formed in the vapor deposition apparatus 308.

[0236] Subsequently, an inorganic layer IL3 is formed in the vapor deposition apparatus EVB. This forms the capping layer CP3.

[0237] Subsequently, a sealing layer SE3 is formed in the CVD apparatus 309.

[0238] After that, proceed Figure 11 Steps ST42 to ST44 are shown.

[0239] The following is for reference Figures 14-20 Explain steps ST1 and ST2. Furthermore, Figure 14 , Figure 15 , 17 18 and Figure 20 The sections shown are, for example, equivalent to those along... Figure 2 The cross-section of line AB in the diagram.

[0240] First, in step ST1, as follows Figure 14 As shown, a processing substrate SUB is prepared. The process for preparing the processing substrate SUB includes: forming a circuit layer 11 on a substrate 10; forming an insulating layer 12 on the circuit layer 11; forming a lower electrode LE1 of sub-pixel SP1, a lower electrode LE2 of sub-pixel SP2, and a lower electrode LE3 of sub-pixel SP3 on the insulating layer 12; forming a rib 5 having openings AP1, AP2, and AP3 overlapping each of the lower electrodes LE1, LE2, and LE3; and forming a partition wall 6 including a lower portion 61 disposed on the rib 5 and an upper portion 62 disposed on the lower portion 61 and protruding from the side of the lower portion 61. Furthermore, in Figure 15 , 17 18 and Figure 20The substrate 10 and circuit layer 11 beneath the insulating layer 12 are omitted from the figures.

[0241] Rib 5 is formed, for example, from silicon nitride.

[0242] Next, in step ST21, as follows Figure 15 As shown, a first thin film 31 is formed across sub-pixels SP1, SP2, and SP3. The process of forming the first thin film 31 includes: forming an organic layer OR1, including a light-emitting layer EM1, on a processing substrate SUB; forming an upper electrode UE1 on the organic layer OR1; forming a capping layer CP1 on the upper electrode UE1; and forming an encapsulating layer SE1 on the capping layer CP1. In other words, in the illustrated example, the first thin film 31 includes the organic layer OR1, the upper electrode UE1, the capping layer CP1, and the encapsulating layer SE1.

[0243] Organic layer OR1 is formed on lower electrodes LE1, LE2, and LE3, and also on partition 6. The portion of organic layer OR1 formed on the upper part 62 is separate from the portion formed on each lower electrode.

[0244] The upper electrode UE1 is formed on the organic layer OR1 directly above the lower electrodes LE1, LE2, and LE3, respectively, covering the rib 5 and connecting to the lower part 61 of the partition wall 6. Additionally, the upper electrode UE1 is also formed on the organic layer OR1 directly above the upper part 62. The portion of the upper electrode UE1 formed directly above the upper part 62 is separate from the portions formed directly above each of the lower electrodes.

[0245] The capping layer CP1 includes a transparent layer TL1 (not shown) and an inorganic layer IL1. The capping layer CP1 is formed directly above the upper electrode UE1, directly above the lower electrodes LE1, LE2, and LE3, and also directly above the upper electrode UE1, directly above the upper portion 62. The portion of the capping layer CP1 formed directly above the upper portion 62 is separate from the portion formed directly above each of the lower electrodes.

[0246] The sealing layer SE1 is formed to cover the capping layer CP1 and the spacer 6. That is, the sealing layer SE1 is formed directly above the capping layer CP1 above the lower electrodes LE1, LE2, and LE3, and also directly above the upper portion 62. In the sealing layer SE1, the portion formed directly above the upper portion 62 is connected to the portions formed directly above each lower electrode. The sealing layer SE1 is, for example, formed of silicon nitride.

[0247] Figure 16This diagram illustrates the formation process of the first thin film 31. Here, the formation process of the first thin film 31 formed on the lower electrode LE1 will be described as an example. The cross-sections of the first thin film 31 on the lower electrode LE1 are arranged in the formation order from left to right in the diagram.

[0248] First, an organic layer OR1 is formed on the lower electrode LE1. The organic layer OR1 is used as a reference. Figure 4 As described, it contains various functional layers and a light-emitting layer. The organic layer OR1 is formed by vapor deposition.

[0249] Subsequently, the upper electrode UE1 is formed on the organic layer OR1. The upper electrode UE1 is formed from an alloy of magnesium and silver using a vapor deposition method. The upper electrode UE1 can be referenced... Figure 7 The vapor deposition apparatus for EVA, or refer to the description. Figure 8 It is formed in the vapor deposition apparatus described above.

[0250] Subsequently, a transparent layer TL1 of a capping layer CP1 is formed on the upper electrode UE1. The transparent layer TL1 is formed, for example, by vapor deposition.

[0251] Subsequently, an inorganic layer IL1, consisting of a capping layer CP1, is formed on top of the transparent layer TL1. The inorganic layer IL1 is formed from lithium fluoride by vapor deposition.

[0252] Subsequently, a sealing layer SE1 is formed on top of the inorganic layer IL1. The sealing layer SE1 is formed, for example, by CVD.

[0253] Next, in step ST22, as follows Figure 17 As shown, a patterned first resist 41 is formed on the sealing layer SE1. The first resist 41 covers the first thin film 31 of sub-pixel SP1, exposing the first thin film 31 of sub-pixels SP2 and SP3. That is, the first resist 41 overlaps with the sealing layer SE1 located directly above the lower electrode LE1. Furthermore, the first resist 41 is positioned directly above the lower electrode LE1. On the partition 6 between sub-pixels SP1 and SP2, the first resist 41 is positioned on the sub-pixel SP1 side (left side of the figure) and exposes the sealing layer SE1 on the sub-pixel SP2 side (right side of the figure). Additionally, the first resist 41 exposes the sealing layer SE1 in sub-pixels SP2 and SP3.

[0254] Subsequently, in step ST23, as Figure 18As shown, the first resist 41 is used as a mask for etching, removing the first thin film 31 of sub-pixels SP2 and SP3 exposed from the first resist 41, leaving the first thin film 31 in sub-pixel SP1. As a result, the lower electrode LE2 is exposed in sub-pixel SP2, and the rib 5 surrounding the lower electrode LE2 is also exposed. Similarly, the lower electrode LE3 is exposed in sub-pixel SP3, and the rib 5 surrounding the lower electrode LE3 is also exposed. Furthermore, the partition 6 between sub-pixels SP1 and SP2 exposes the sub-pixel SP2 side. Additionally, the partition 6 between sub-pixels SP2 and SP3 is also exposed.

[0255] Figure 19 This diagram illustrates the removal process of the first thin film 31. Here, the removal process of the first thin film 31 formed on the lower electrode LE2 in the sub-pixel SP2 is described as an example. The cross-sections of the first thin film 31 on the lower electrode LE2 are arranged in the removal order from left to right in the diagram.

[0256] First, dry etching is performed using the first photoresist 41 as a mask to remove the sealing layer SE1 exposed from the first photoresist 41.

[0257] Subsequently, wet etching was performed using the first resist 41 as a mask to remove the inorganic layer IL1 of the capping layer CP1 exposed from the sealing layer SE1.

[0258] Subsequently, using the first resist 41 as a mask, dry etching was performed to remove the transparent layer TL1 of the capping layer CP1 exposed from the inorganic layer IL1.

[0259] Subsequently, wet etching was performed using the first resist 41 as a mask to remove the upper electrode UE1 exposed from the transparent layer TL1.

[0260] Subsequently, using the first photoresist 41 as a mask, dry etching was performed to remove the organic layer OR1 exposed from the upper electrode UE1, exposing the lower electrode LE2.

[0261] Similarly, the sealing layer SE1, capping layer CP1, upper electrode UE1, and organic layer OR1 in sub-pixel SP3 are also removed.

[0262] Subsequently, in step ST24, as Figure 20 As shown, the first resist 41 is removed. This exposes the sealing layer SE1 of the sub-pixel SP1. Through these steps ST21 to ST24, a display element 201 is formed in the sub-pixel SP1. The display element 201 is composed of a lower electrode LE1, an organic layer OR1 including a light-emitting layer EM1, an upper electrode UE1, and a capping layer CP1. Furthermore, the display element 201 is covered by the sealing layer SE1.

[0263] An organic layer OR1, including a light-emitting layer EM1, an upper electrode UE1, a capping layer CP1, and a sealing layer SE1 are formed on the partition 6 between sub-pixels SP1 and SP2. Furthermore, the portion of partition 6 on the sub-pixel SP1 side is covered by the sealing layer SE1. Figure 20 The laminated body on partition 6 shown has been completely removed.

[0264] According to this embodiment, before etching the sealing layer SE1, in sub-pixels SP2 and SP3, at least one of the upper electrode UE1 and the inorganic layer IL1 of the capping layer CP1 covers the rib 5 between the partition wall 6 and the organic layer OR1. Therefore, the sealing layer SE1 is not in contact with the rib 5. The upper electrode UE1 and the inorganic layer IL1 function as etching stop layers, and the etching rate of the upper electrode UE1 and the inorganic layer IL1 is lower than the etching rate of the sealing layer SE1. Therefore, during dry etching of the sealing layer SE1, after the sealing layer SE1 is completely removed, the dry etching can be prevented by the upper electrode UE1 or the inorganic layer IL1. Thus, the rib 5j is hardly damaged during dry etching of the sealing layer SE1. In addition, the formation of undesirable holes (water infiltration paths) penetrating the rib 5 up to the insulating layer 12 is suppressed. Moreover, discoloration of the lower electrode due to the influence of undesirable moisture is suppressed. In addition, it suppresses pixel defects caused by damage to organic EL elements or anodes, resulting in the organic EL elements not emitting light.

[0265] Therefore, it can suppress the decline in reliability.

[0266] As explained above, according to this embodiment, a display device and a method thereof can be provided that suppress reliability degradation and improve manufacturing yield.

[0267] Based on the display device and its manufacturing method described above as embodiments of the present invention, all display devices and their manufacturing methods that can be implemented by those skilled in the art with appropriate design modifications, as long as they contain the spirit of the present invention, also fall within the scope of the present invention.

[0268] Within the scope of the present invention, various modifications will be conceived by those skilled in the art, and these modifications should also be understood to fall within the scope of the present invention. For example, modifications obtained by those skilled in the art by appropriately adding or removing constituent elements, changing the design, or adding, omitting, or changing processes or conditions relative to the above embodiments, as long as they possess the essence of the present invention, are also included within the scope of the present invention.

[0269] Furthermore, any other effects resulting from the configurations described in the above embodiments, which are clearly derived from the description in this specification or which would be appropriately conceived by those skilled in the art, should naturally be understood as being brought about by the present invention.

Claims

1. A method for manufacturing a display device, comprising the following steps: Prepare a processing substrate, which has a lower electrode formed above a substrate, a rib having an opening overlapping the lower electrode, and a partition wall including a lower portion located above the rib and an upper portion located above the lower portion and protruding from the side of the lower portion. An organic layer is formed in the opening above the lower electrode; An upper electrode is formed on the organic layer; A transparent layer is formed on the upper electrode; as well as An inorganic layer is formed on top of the transparent layer. In the process of forming the upper electrode, The first evaporation source is tilted relative to the normal of the processed substrate. While transporting the processing substrate, material ejected from the first evaporation source is deposited onto the processing substrate. In the process of forming the inorganic layer The second evaporation source is tilted relative to the normal of the processed substrate in a direction opposite to that of the first evaporation source. While transporting the processing substrate, material ejected from the second evaporation source is deposited onto the processing substrate.

2. The method for manufacturing a display device according to claim 1, wherein, A sealing layer is also formed on the inorganic layer. A patterned resist is formed on the sealing layer. Using the resist as a mask, dry etching of the sealing layer is performed. During the dry etching of the sealing layer, the etching rate of the upper electrode and the inorganic layer is lower than that of the sealing layer.

3. The method for manufacturing a display device according to claim 2, wherein, The ribs and the sealing layer are formed of silicon nitride.

4. The method for manufacturing a display device according to claim 3, wherein, The upper electrode is formed of an alloy of magnesium (Mg) and silver (Ag).

5. The method for manufacturing a display device according to claim 4, wherein, The inorganic layer is formed of lithium fluoride (LiF).

6. A display device comprising: Substrate; A lower electrode disposed above the substrate; A rib having an opening that overlaps with the lower electrode; The partition has a lower portion disposed above the rib and an upper portion disposed above the lower portion and protruding from the side of the lower portion; as well as An organic layer is disposed in the opening above the lower electrode; An upper electrode disposed on the organic layer; A transparent layer disposed above the upper electrode; An inorganic layer disposed on top of the transparent layer; as well as A sealing layer, which covers the inorganic layer, is in contact with the lower part of the partition wall. The upper electrode has a first end and a second end on the opposite side of the first end. The first end is covered by the inorganic layer. The second end protrudes from the inorganic layer and is covered by the sealing layer.

7. The display device according to claim 6, wherein, The lower portion of the partition wall has a first side surface opposite to the first end and a second side surface opposite to the second end. The inorganic layer is in contact with the first side surface. The upper electrode is connected to the second side surface.

8. The display device according to claim 7, wherein, The contact area between the first side and the inorganic layer is larger than the contact area between the first side and the upper electrode. The contact area between the second side and the upper electrode is larger than the contact area between the second side and the inorganic layer.

9. The display device according to claim 6, wherein, The organic layer is separated from the partition wall. Between the organic layer and the partition wall, at least one of the upper electrode and the inorganic layer is disposed between the rib and the sealing layer.

10. The display device according to claim 6, wherein, The ribs and the sealing layer are formed of silicon nitride.

11. The display device according to claim 6, wherein, The upper electrode is formed of an alloy of magnesium (Mg) and silver (Ag).

12. The display device according to claim 6, wherein, The inorganic layer is formed of lithium fluoride (LiF).

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