System for multiple stacks in a processor lacking an effective address generator

Abstract

In one embodiment lacking an effective address generator, the method of the call operation includes pushing one or more parameters onto a first stack, pushing the contents of one or more registers onto a second stack, popping one or more of the parameters from the first stack into one or more of the registers whose contents were pushed onto the second stack, performing a register-to-register operation on the one or more registers whose contents were pushed onto the second stack, wherein the result of the register-to-register operation is stored in a result register that is one of the one or more registers whose contents were pushed onto the second stack, popping the contents of all of the one or more registers from the second stack into the respective registers from which they came, and returning control to the instruction following the call.

Description

[0001] Related applications

[0002] This patent application claims priority to U.S. Application Serial No. 63 / 180,601, filed April 27, 2021, and U.S. Application Serial No. 17 / 468,574, filed September 7, 2021, which are incorporated herein by reference. Technical Field

[0003] This method and apparatus relate to processors lacking a valid address generator. More specifically, this method and apparatus relate to systems with multiple stacks in a processor lacking a valid address generator. Background Technology

[0004] Modern microprocessors have address generators that allow, for example, a central processing unit (CPU) to interact with memory (e.g., read, write). These address generators are called effective address generators (EAGs). Due to the nature of their tasks, they are large-scale integrated circuit-like, complex, and power-intensive, and because of their flexibility in addressing modes, they cannot keep up with dedicated high-speed processors such as vector processing units.

[0005] The following demonstrates the execution of the subroutine "(A+B)". An exemplary fragment of pseudocode for "A / B" where A and B are passed as parameters to a subroutine. The first case (Case 1) performs the operation on a processor with EAG. This first case (Case 1) also illustrates how the memory address is generated by EAG.

[0006]

[0007] Do things with results

[0008] In this first case (Case 1), the memory address is generated by port 4 EAG, essentially similar to Intel. ® Addresses in x86 processors. This EAG comprises the following four items: 1. Segment address (in this example, there are data segment and stack segment).

[0009] 2. Base address register, which provides the offset in the segment and provides the local variable region.

[0010] 3. An index register that can be scaled (multiplied) by 0, 1, 2, 4, or 8, simplifying access to the array. (This is shown as (0 in this example) 0), because no array is being accessed, therefore no index is needed.

[0011] 4. Displacement, which provides the offset of each specific variable in the local variable space.

[0012] In this example, for illustrative purposes only, it is assumed that 32-bit register and memory contents, i.e., 4 bytes, are being processed. (8 bits / byte = 32 bits). Therefore, for four consecutive memory / register locations, the address and register increment by +0, +4, +8, and +12.

[0013] EAG: The entry shows how a valid address was reached.

[0014] For example, the entry: EAG: ds + r15 + (0 0) + 4 The first entry, ds, is the data segment set before entering the subroutine.

[0015] The second entry, r15, is set as the base address register for local variables.

[0016] Third entry (0) 0) is the index register scaling provided by EAG. In this case, index register scaling is not used, so the additional memory offset = (0) 0) = 0.

[0017] Item 4 is the direct offset calculated from other addresses.

[0018] Therefore, for example, if ds=0xA2440 and r15=0x4588, then EAG = 0xA2440 + 0x4588 + (0 0) + 4 = 0xA69CC

[0019] instruction: MOV[r15]+8, r0 copies the first parameter to local memory. Therefore, it is read, the contents of register r0 are obtained and copied to the data segment location in memory r15+8, where r15 was previously set as the base address register for local variables, and +8 is an 8-byte offset from the base address memory location r15.

[0020] Even pushing and popping to / from the stack uses EAG.

[0021] instruction:

[0022] Therefore, it is read, and r0 (which has the first parameter in this example) is popped from the stack, where the stack address is determined by the stack segment ss added to the stack pointer sp and the scaling factor (0). It is determined by 0) and direct offset 0.

[0023] Therefore, for example, if ss = 0xebefcf and sp = 0xf, then r0 will have the address 0xebefcf + 0xf + 0 + 0 = 0xebefde

[0024] As can be seen in this simple example, the address calculation of EAG involves four variables.

[0025] In short, EAG characteristics include: It can be used to push parameters to a function.

[0026] It can be used to save and restore registers.

[0027] It can provide a working area for memory for local variables in a function.

[0028] Provides access to the array.

[0029] Provides general memory processing.

[0030] Provides complex memory addressing.

[0031] Allows for sophisticated memory protection.

[0032] In short, EAG costs include: This is a very complex component of the processing system. It requires complex adders with many ports (e.g., four), some needing access to general-purpose register sets, some requiring pre-scaling before addition, some requiring highly specialized registers for access control, and some requiring direct access to instruction fields. It is typically a very cycle-time sensitive component, making cycle-time compliance difficult because it is located in the memory access path. It employs non-trivial bypass paths and pipeline interlocks to address register hazards and includes memory access protection provisions. Its presence influences the structure of most instructions in the processor instruction set. It is a major component of the functional architecture and a large and complex part of the design.

[0033] Therefore, the effective address generator is a complex, cumbersome, and power-intensive circuit block that may be effective for general-purpose processors, but is often unnecessarily overused for specialized processors such as vector processors or machine learning processors. Thus, the effective address generator does not provide optimal control. Summary of the Invention

[0034] The vector processor device includes a first stack and a second stack, the first stack being used to push parameters and the second stack being used to save and restore registers, wherein the first stack and the second stack can operate simultaneously.

[0035] In one example, the processor device includes a first stack and a second stack, the first stack being used to push parameters and the second stack being used to save and restore registers, wherein the first stack and the second stack can operate simultaneously, and wherein the vector processor lacks an effective address generator. Attached Figure Description

[0036] The techniques disclosed in this invention are illustrated by way of example, not limitation, in the accompanying drawings. Items with the same number do not necessarily have to be the same.

[0037] The accompanying drawings illustrate various non-exclusive examples of the technology disclosed in this invention.

[0038] Figure 1 An example of invoking an operation is shown.

[0039] Figure 2 An example of a call operation to the push result register is shown.

[0040] Figure 3 Examples of direct push and pop-up call operations are shown.

[0041] Figure 4 An example is shown in which register-to-register operations are performed in the form of a set of one or more parallel operations.

[0042] Figure 5 Examples of serial and parallel operations are shown.

[0043] Figure 6 An example of a first stack and a second stack operating essentially simultaneously is shown.

[0044] Figure 7 An example of a set of one or more serial operations is shown.

[0045] Figure 8 An example of another call to the operation is shown.

[0046] Figure 9 An exemplary flowchart of the invocation operation is shown.

[0047] Figure 10 An exemplary block diagram of a vector processor device is shown.

[0048] Figure 11 An exemplary block diagram of a vector processor device is shown, wherein a vector processing unit is configured to communicate with a shared memory portion of the memory.

[0049] Figure 12 An example of a distributed register layout is shown.

[0050] Figure 13 An example of a clustered register layout is shown.

[0051] Figure 14 Examples of using dedicated memory portions or shared memory portions are shown.

[0052] Figure 15 An example of a flash memory controller is shown.

[0053] Figure 16 Examples of flash memory controllers using dedicated or shared memory sections are shown.

[0054] Figure 17 An exemplary flowchart of a flash controller vector processor call operation is shown.

[0055] Figure 18 An exemplary flowchart of a flash controller vector processor including parameter stack-specific instructions is shown.

[0056] Figure 19 An exemplary flowchart of a flash controller vector processor including register stack-specific instructions is shown.

[0057] Figure 20 An exemplary flowchart of a flash controller vector processor that does not use a valid address generator is shown.

[0058] Figure 21 An example is shown in which the calls to parameter stack-specific instructions and register stack-specific instructions are independent of each other in time.

[0059] Figure 22 An example is shown in which the first plurality of calls to parameter stack-specific instructions and the second plurality of calls to register stack-specific instructions are independent of the state of the parameter stack contents and independent of the state of the register stack contents.

[0060] Figure 23 Examples of simultaneous operations that save or restore the contents of multiple parameter stacks and simultaneous operations that save or restore the contents of multiple register stacks are shown without using a valid address generator. Detailed Implementation

[0061] A system with multiple stacks in a processor

[0062] As disclosed in the background section, EAGs are unnecessarily complex and expensive for processors such as vector processors or machine learning processors. Using the techniques disclosed herein, systems with multiple stacks in processors lacking EAGs can keep up with high-speed processors such as vector processors.

[0063] Case 1 in the background art illustrates an example of using EAG.

[0064] The following demonstrates the execution of the subroutine "(A+B)". Example of a pseudocode snippet for "A / B" (Case 2), where A and B are passed as parameters to a subroutine. This second case (Case 2) performs the operation on a processor without EAG. The second case illustrates how memory addresses are generated without EAG and how the two stacks facilitate this.

[0065]

[0066] Do things with results

[0067] In this second case (Case 2), the memory address is either the parameter stack pointer (sp) or the register stack pointer (rp). Since Case 2 does not have an EAG, it is not particularly suitable for accessing arrays; however, if array processing is performed by a coprocessor (such as a vector processor or machine learning processor), this capability is not required, and dual stacks result in a preferred (and much simpler, more power-efficient, and faster) solution compared to EAG. Furthermore, the dual-stack approach simplifies the instruction set because instructions do not require EAG parameters.

[0068] In short, the characteristics of a dual-stack architecture include: Specifically, the parameters are pushed to the function.

[0069] Specifically, saving and restoring registers.

[0070] This eliminates the need for a working area to provide memory for local variables saved within a function, because registers can be saved and restored and are thus used in place of memory.

[0071] No access to the array is required because it is offloaded to the coprocessor.

[0072] General-purpose memory processing is not required because it is offloaded to the coprocessor.

[0073] Complex memory addressing is not required because it is offloaded to the coprocessor.

[0074] Complete yet very simple memory protection.

[0075] In short, the costs of dual stacks include: The top of a single stack register (per stack) replaces the entire adder of the EAG, along with all the complex ports, prescaling, register fault resolution, etc., of the EAG. The entire memory protection mechanism of the EAG is replaced in the dual-stack system with very simple basic checks and limit checks. Each stack has corresponding push and pop type instructions, instead of almost all instructions (as in the EAG) having to specify their address generation characteristics and modes. The simplicity of the dual-stack technology disclosed in this invention results in very small circuit size and power consumption, and easily meets processor cycle time requirements.

[0076] The dual-stack approach is a very specific technique dedicated to memory access control and eliminates the EAG (Extractive Access Controller) for the processor, which can offload certain functions that would otherwise be assisted by the EAG to a coprocessor (e.g., a vector processor, a machine learning processor, etc.).

[0077] Figure 1 An example of the call operation is shown in its entirety at 100. At 102, call operation 100 begins and proceeds to 104, where one or more arguments are pushed onto the first stack. Call operation 100 then proceeds to 106, where the contents of one or more registers are pushed onto a second stack, which is different from the first stack. Call operation 100 then proceeds to 108, where the call operation pops the contents of one or more of the arguments from the first stack into one or more registers whose contents were pushed onto the second stack in 106. Call operation 100 then proceeds to 110, where the call operation performs a register-to-register operation on the one or more registers whose contents were pushed onto the second stack, where the result of the register-to-register operation is stored in a result register, which is one of the registers whose contents were pushed onto the second stack. Call operation 100 then proceeds to 112, where the call operation pops the contents of all one or more registers from the second stack into their respective registers from which they originated. Call operation 100 then proceeds to 114, where the call operation returns control to the instruction following the call.

[0078] Although Figure 1 Operations are shown in sequence, such as the operation at 104 before 106, but the operations are not limited to this, and for example, operation 106 may occur before or at the same time as 104.

[0079] Figure 2An example of a call operation involving pushing a result register is shown at 200. At 202, call operation 200 begins and proceeds to 204, where one or more arguments are pushed onto the first stack. Call operation 200 then proceeds to 206, where the contents of one or more registers are pushed onto a second stack, which is different from the first stack. Call operation 200 then proceeds to 208, where the call operation pops one or more arguments from the first stack into one or more registers whose contents are pushed onto the second stack. Call operation 200 then proceeds to 210, where the call operation performs a register-to-register operation on one or more registers whose contents are pushed onto the second stack, where the result of the register-to-register operation is stored in a result register, which is one of the registers whose contents are pushed onto the second stack. Call operation 200 then proceeds to 212, where the call operation pushes the result register onto the first stack. Call operation 200 then proceeds to 214, where the call operation pops the contents of all or all registers from the second stack from the second stack into their respective registers from which they originated. Operation 200 is invoked and then proceeds to 216, where the invoked operation returns control to the instructions following the invocation.

[0080] Although Figure 2 Operations are shown in sequence, such as the operation at 204 before 206, but the operations are not limited to this, and for example, operation 206 may occur before or at the same time as 204, or they may overlap in time.

[0081] exist Figure 2 In the above, operation 212, which pushes the result register onto the first stack, allows another operation to simply pop the contents of the first stack and retrieve the result of the register-to-register operation, such as from... Figure 2 The operation indicated at position 210. That is, when control returns to the instruction following the call, such as in... Figure 2 In operation 216, the calling program knows that the top entry on the parameter stack holds the result. Therefore, a valid address generator is not needed to point to the result.

[0082] Figure 3 Example of direct push and pop-up calls is shown at position 300. Direct push and pop-up refer to operations that continue but do not use intermediate locations to store or temporarily store content before it reaches its final destination. That is, for example, a direct push of content from A to B can be represented as: The sequence is A→B, where there is no intermediate position.

[0083] The following examples are not direct pushes of content from A to B: The process is A→X→B, where X is an intermediate position, and the contents of A are stored there before reaching the destination B. At 302, call operation 300 begins and proceeds to 304, where one or more arguments are pushed directly onto the first stack. Call operation 300 then proceeds to 306, where the contents of one or more registers are pushed directly onto the second stack, which is different from the first stack. Call operation 300 then proceeds to 308, where the call operation pops one or more arguments from the first stack directly into one or more registers whose contents were pushed directly onto the second stack at 306. Call operation 300 then proceeds to 310, where the call operation performs a register-to-register operation on one or more registers whose contents were pushed directly onto the second stack, and the result of the register-to-register operation is stored in a result register, which is one of the registers whose contents were pushed directly onto the second stack at 306. Call operation 300 then proceeds to 312, where the call operation pops the contents of all one or more registers from the second stack directly into their respective registers from which they originated. Operation 300 is invoked and then proceeds to 314, where the invoked operation returns control to the instruction following the invocation.

[0084] Although Figure 3 Operations are shown in sequence, such as the operation at 304 before 306, but the operations are not limited to this, and for example, operation 306 may occur before or at the same time as 304, or they may overlap in time.

[0085] Figure 4At 400, an example of register-to-register operations performed as a set of one or more parallel operations is shown in its entirety. At 402, call operation 400 begins and proceeds to 404, where one or more arguments are pushed onto a first stack. Call operation 400 then proceeds to 406, where the contents of one or more registers are pushed onto a second stack, which is different from the first stack. Call operation 400 then proceeds to 408, where the call operation pops one or more of the arguments from 404 from the first stack into one or more of the registers whose contents were pushed onto the second stack. Call operation 400 then proceeds to 410, where the call operation performs register-to-register operations on one or more registers whose contents were pushed onto the second stack as a set of one or more parallel operations, where the result of the register-to-register operations is stored in a result register, which is one of the registers whose contents were pushed onto the second stack. Call operation 400 then proceeds to 412, where the call operation pops the contents of all or one registers from the second stack from the second stack into their respective registers from which they originated. The call proceeds to operation 400 and then to 414, where the call returns control to the instruction following the call.

[0086] Although Figure 4 Operations are shown in sequence, such as the operation at 404 before 406, but the operations are not limited to this, and for example, operation 406 may occur before or at the same time as 404, or they may overlap in time.

[0087] Figure 5At 500, an example of serial and parallel operations is illustrated. At 502, call operation 500 begins and proceeds to 504, where one or more arguments are pushed onto the first stack. Call operation 500 then proceeds to 506, where the contents of one or more registers are pushed onto a second stack, which is different from the first stack. Call operation 500 then proceeds to 508, where the call operation pops one or more of the arguments from 504 from the first stack into one or more registers whose contents are pushed onto the second stack. The call operation then proceeds to 510, where the call operation performs register-to-register operations on the one or more registers whose contents are pushed onto the second stack, in the form of one or more serial operations that do not overlap in time, and in the form of a set of one or more parallel operations that overlap in time, wherein the result of the register-to-register operations is stored in a result register, which is one of the registers whose contents are pushed onto the second stack. Call operation 500 then proceeds to 512, where the call operation pops the contents of one or more registers from the second stack into their respective registers. Call operation 500 then proceeds to 514, where the call operation returns control to the instruction following the call.

[0088] Although Figure 5 Operations are shown in sequence, such as the operation at 504 before 506, but the operations are not limited to this, and for example, operation 506 may occur before or at the same time as 504, or they may overlap in time.

[0089] Figure 6 At 600, an example of the first and second stacks operating substantially simultaneously is shown. At 602, a representative timeline is shown, with the earlier arrows located near the end of the marker at 602. The later arrows are closer to the nearest point in time. At 604, the operation of the first stack is represented. At 606, the operation of the second stack is represented. At 608, it is shown that the first and second stacks are operating substantially simultaneously, i.e., the parallel operations overlap in time.

[0090] Figure 7 At 700, an example of one or more serial operations is shown as a whole. At 702, a representative timeline is shown, with earlier arrows located near the end of the 702 mark. Later arrows are located closer to the nearest time. At 704-1, 704-2, ..., 704-N-1, 704-N, representations of register-to-register operations are shown, where N is an integer greater than 1. At 706, a register-to-register operation is shown as a set of one or more serial operations that do not overlap in time.

[0091] Figure 8 At 800, an example of another call to the call operation is shown, which may be executed during the previous call to this call operation. At 802, call operation 800 begins and proceeds to 804, where one or more arguments are pushed onto the first stack. Call operation 800 then proceeds to 806, where the contents of one or more registers are pushed onto a second stack, which is different from the first stack. Call operation 800 then proceeds to 808, where the call operation pops one or more of the arguments from 804 from the first stack into one or more registers whose contents were pushed onto the second stack at 806. Call operation 800 then proceeds to 810, where the call operation performs a register-to-register operation on the one or more registers whose contents were pushed onto the second stack, where the result of the register-to-register operation is stored in a result register, which is one of the registers whose contents were pushed onto the second stack. Call operation 800 then proceeds to 812, where the call operation pops the contents of all one or more registers from the second stack into their respective registers from which they originated. The call operation then proceeds to 814, where the call operation returns control to the instructions following the call.

[0092] The sequence 804, 806, 808, 810, 812 and 814 is represented as 820.

[0093] 830, 840, 850, 860, 870, and 880 each represent the sequence indicated at 820. That is, for example, 850 represents operation 820 (804 to 814). 830, 840, 850, 860, 870, and 880 also indicate that these operations 820 (804 to 814) can be executed at any of the indicated locations. For example, at 804, another call to the call operation can be executed, as indicated by 830. This shows that the currently executing call operation can be interrupted or invoked by another call operation (call) at any of steps 804 to 814, respectively shown as 830 to 880.

[0094] Although Figure 8 Operations are shown in sequence, such as the operation at 804 before 806, but the operations are not limited to this, and for example, operation 806 may occur before or at the same time as 804, or they may overlap in time.

[0095] Although Figure 8This illustrates a call operation being interrupted or invoked by another call operation, i.e., two levels deep, but the technique is not limited to this and can achieve more than two levels (nesting). That is, call operations with three or more levels deep are possible. Specifically, for each invocation of the call operation, the nesting level increases, and as each invocation eventually completes step 814, the nesting level decreases.

[0096] Figure 9 At 900, an exemplary flowchart of a call operation arranged to prevent nested calls when insufficient stack space exists in either the first or second stack is shown in its entirety. At 902, the call operation 900 begins and proceeds as indicated by 904 to a decision at 906 to determine whether this is another call to the call operation. Another call to the call operation can occur at any point in time. For example, and not limited to the specific examples described in detail, see [link to relevant documentation]. Figure 1 For example, another call to operation 100 can occur before, after, or during any of operations 104, 106, 108, 110, 112, or 114. See, for example, [link to relevant documentation]. Figure 2 At 900, another call to the operation may occur before, after, or during any of operations 204, 206, 208, 210, 212, 214, or 216. If the answer at 906 is "No," the program proceeds to 910 as indicated at 908, where the call operation continues. If the answer at 906 is "Yes," the call operation 900 proceeds to the decision at 914 as indicated by 912 to determine if there is remaining stack space on the first stack. If the answer at 914 is "No," the call operation 900 proceeds to 918 via 916, where another call to the operation is not allowed, and then the call operation 900 proceeds to 910 via 920, where the previous call operation continues. If the answer at 914 is "Yes," the call operation 900 proceeds to the decision at 924 as indicated by 922 to determine if there is remaining stack space on the second stack. If the answer at 924 is "No", then call operation 900 proceeds via 926 to 928, where another call operation is not allowed, and then call operation 900 proceeds via 930 to 910, where the previous call operation 900 continues. If the answer at 924 is "Yes", then proceeds via 932 to 934 to allow another call operation.

[0097] Although Figure 9 Operations are shown in sequence, such as the operation at 914 before 924, but the operations are not limited to this, and for example, operation 924 may occur before or at the same time as 914, or they may overlap in time.

[0098] Figure 10An exemplary block diagram of a vector processor device is shown overall at 1000. At 1002 is a parameter stack having control instruction 1004, a stack base address register 1006, a stack limit register 1008, and a stack pointer register 1009. At 1012 is a register stack having control instruction 1014, a stack base address register 1016, a stack limit register 1018, and a stack pointer register 1019. At 1030 is a memory having a dedicated memory portion 1032 and a shared memory portion 1034. Memory 1030 is optionally connected to a vector processing unit 1040 via 1042. At 1010 is the interface between parameter stack 1002 and memory 1030. At 1020 is the interface between register stack 1012 and memory 1030. Although individual stack base registers 1006, 1016 and stack limit registers 1008, 1018 and stack pointer registers 1009, 1019 are described relative to parameter stack 1002 and register stack 1012, this does not imply any limitation and multiple base registers and stack limit registers and stack pointer registers may be provided without exceeding the limits.

[0099] Figure 11 An exemplary block diagram of a vector processor device is shown overall at 1100, wherein a vector processing unit is configured to communicate with a shared memory portion of memory. At 1102 is a parameter stack having control instruction 1104, a stack base address register 1106, a stack limit register 1108, and a stack pointer register 1109. At 1112 is a register stack having control instruction 1114, a stack base address register 1116, a stack limit register 1118, and a stack pointer register 1119. At 1130 is a memory having a dedicated memory portion 1132 and a shared memory portion 1134. The shared memory portion 1134 is connected to the vector processing unit 1140 via 1142. At 1110 is the interface between the parameter stack 1102 and the memory 1130. At 1120 is the interface between the register stack 1112 and the memory 1130. Although individual stack base registers 1106, 1116 and stack limit registers 1108, 1118 and stack pointer registers 1109, 1119 are described relative to parameter stack 1102 and register stack 1112, this does not imply any limitation and multiple base registers and stack limit registers may be provided without exceeding the limits.

[0100] Figure 12An example of a distributed register arrangement is shown at 1200. At 1202 is a parameter stack with control instruction 1204, base address register 1206, stack limit register 1208, and stack pointer register 1209. Parameter stack 1202 is connected to memory 1210 via link 1211. Control instruction 1204 shows representative communication with distributed registers 1236-1, 1236-2, 1236-3, 1236-4, 1235-5, 1235-6, 1235-7, 1235-8, 1235-9, and 1235-N via 1235-1, 1236-2, 1236-3, 1236-4, 1236-5, 1236-6, 1236-7, 1236-8, 1236-9, and 1236-N, respectively, where N represents an integer greater than one. The distributed registers are represented as 1230. While a single stack base register 1206, stack limit register 1208, and stack pointer register 1209 are described relative to parameter stack 1202, this does not imply any limitation, and multiple base registers and stack limit registers can be provided without exceeding the limits.

[0101] Figure 13 An example of the clustered register arrangement is shown at 1300. At 1312 is a register stack with control instruction 1314, stack base address register 1316, stack limit register 1318, and stack pointer register 1319. Register stack 1312 is connected to memory 1330 via link 1320. Control instruction 1314 shows representative communications with cluster registers 1340-1, 1340-2, 1340-3, 1339-4, 1339-5, 1339-6, 1339-7, 1339-8, 1339-9, and 1339-N, respectively, where N represents an integer greater than one. The registers arranged in a cluster are represented as 1340. Although a single stack base register 1316, stack limit register 1318, and stack pointer register 1319 are described relative to register stack 1312, this does not imply any limitation and multiple stack base registers, stack limit registers, and stack pointer registers may be provided without exceeding the range.

[0102] Figure 14An example of using either a dedicated memory portion or a shared memory portion is shown at 1400. At 1402 is a parameter stack with control instruction 1404, stack base address register 1406, stack limit register 1408, and stack pointer register 1410. At 1412 is a register stack with control instruction 1414, stack base address register 1416, stack limit register 1418, and stack pointer register 1420. At 1430 is a memory with a dedicated memory portion 1432 and a shared memory portion 1434. The shared memory portion 1434 is optionally connected to the vector operation unit 1440 via 1442. At 1450 is the interface between the parameter stack 1402 and the dedicated memory portion 1432. At 1452 is the interface between the parameter stack 1402 and the shared memory portion 1434. At 1460 is the interface between the register stack 1412 and the dedicated memory portion 1432. At 1462 is the interface between register stack 1412 and shared memory portion 1434. Although individual base registers 1406 and 1416 and stack limit registers 1408 and 1418 are described relative to parameter stack 1402 and register stack 1412, this does not imply any limitation, and multiple stack base registers and stack limit registers may be provided without exceeding the limits.

[0103] Figure 15An example of a flash memory controller is shown overall at 1500. The flash memory controller 1500 includes a read module 1552, a write module 1554 coupled to the read module 1552, and a control module 1556 coupled to the read module 1552, data storage device 1558, and write module 1554. The flash memory controller has a neural network engine 1560 coupled to the read module 1552, data storage device 1558, and control module 1556. The neural network engine 1560 includes a vector processor 1562. The vector processor 1562 includes a memory 1530, which includes a dedicated memory portion 1532 and a shared memory portion 1534. The vector processor 1562 includes a parameter stack 1502 having a control instruction set 1504, a stack base address register 1506, a stack limit register 1508, and a stack pointer register 1509. The parameter stack 1502 is coupled to the memory 1530 and configured to communicate with the memory 1530 via link 1510. Vector processor 1562 includes a register stack 1512 having a control instruction set 1514, a base address register 1516, a stack limit register 1518, and a stack pointer register 1519. Register stack 1512 is configured to communicate with memory 1530 via link 1520. Vector arithmetic unit 1540 is coupled to memory 1530 via link 1542 and configured to communicate with memory 1530. Although individual stack base address registers 1506 and 1516 and stack limit registers 1508 and 1518 are described with respect to parameter stack 1502 and register stack 1512 respectively, this does not imply any limitation, and multiple stack base address registers and stack limit registers may be provided without exceeding the limits.

[0104] Figure 16 An example of a flash memory controller using a dedicated memory portion or a shared memory portion is shown overall at 1600. The flash memory controller 1600 includes a read module 1652, a write module 1654 coupled to the read module 1652, and a control module 1656 coupled to the read module 1652, data storage device 1658, and write module 1654. The flash memory controller has a neural network engine 1660 coupled to the read module 1652, data storage device 1658, and control module 1656. The neural network engine 1660 includes a vector processor 1662. The vector processor 1662 includes a memory 1630, which includes a dedicated memory portion 1632 and a shared memory portion 1634. The vector processor 1662 includes a parameter stack 1602 having a control instruction set 1604, a base address register 1606, a stack limit register 1608, and a stack pointer register 1609. The parameter stack 1602 is coupled to the dedicated memory portion 1632 via link 1670. The parameter stack 1602 is coupled to the shared memory portion 1634 via link 1672.

[0105] Vector processor 1662 includes a register stack 1612 having a control instruction set 1614, a stack base address register 1616, a stack limit register 1618, and a stack pointer register 1619. Register stack 1612 is configured to communicate with dedicated memory portion 1632 via link 1680 and with shared memory portion 1634 via link 1682. Vector arithmetic unit 1640 is coupled to memory 1630 via link 1642 and configured to communicate with memory 1630. Although individual stack base address registers 1606 and 1616, stack limit registers 1608 and 1618, and stack pointer registers 1609 and 1619 are described relative to parameter stack 1602 and register stack 1612, this does not imply any limitation, and multiple base address registers and stack limit registers may be provided without exceeding the limit.

[0106] Figure 17 An exemplary flowchart of a flash controller vector processor call operation is shown in its entirety at 1700. At 1702, call operation 1700 begins and proceeds to 1704, where one or more parameters are pushed onto the parameter stack. Call operation 1700 then proceeds to 1706, where the contents of one or more registers are pushed onto the register stack. Call operation then proceeds to 1708, where the call operation pops one or more parameters from the parameter stack into one or more registers whose contents were pushed onto the register stack. Call operation 1700 then proceeds to 1710, where the call operation performs a register-to-register operation on the one or more registers whose contents were pushed onto the register stack at 1706, where the result of the register-to-register operation is stored in a result register, which is one of the registers whose contents were pushed onto the register stack. Call operation 1700 then proceeds to 1712, where the call operation pushes the result register onto the parameter stack. The call operation then proceeds to 1714, where it pops the contents of one or more registers from the register stack into their respective registers. The call operation then proceeds to 1716, where it returns control to the instruction following the call.

[0107] Although Figure 17 Operations are shown in sequence, such as the operation at 1704 before 1706, but the operations are not limited to this, and for example, operation 1706 may occur before or at the same time as 1704, or they may overlap in time.

[0108] exist Figure 17In the 1712 operation, pushing the result register onto the parameter stack allows another operation to simply pop the parameter stack and retrieve the result of a register-to-register operation, such as from... Figure 17 The operation indicated at position 1710.

[0109] Figure 18 An exemplary flowchart of a flash memory controller vector processor, including parameter stack-specific instructions, is shown in its entirety at 1800. The flash memory controller includes a read module 1852, a write module 1854 coupled to the read module 1852, and a control module 1856 coupled to the read module 1852, data storage device 1858, and write module 1854. The flash memory controller has a neural network engine 1860 coupled to the read module 1852, data storage device 1858, and control module 1856. The neural network engine 1860 includes a vector processor 1862. The vector processor 1862 includes a vector processor operation 1802, which proceeds via 1803 to 1804 to determine whether the vector processor operation is a parameter stack-specific instruction. If the answer to 1804 is "no," then flowchart 1800 proceeds via 1807 to 1806 to continue with further vector processor operations. If the answer to 1804 is "yes", then flowchart 1800 proceeds via 1805 to 1820 to save or restore multiple contents of the parameter stack via a single call to a parameter stack-specific instruction, wherein the save or restore goes directly to or comes from the parameter stack and the first set of registers, and wherein the contents of the parameter stack are not stored in the first intermediate memory location. From 1820, proceeds via 1821 to 1806 to continue further vector processor operations.

[0110] The parameter stack-specific instructions have already encoded within them how much stack space they require to perform parameter pushing or popping. That is, the parameter stack-specific instructions can perform multiple parameter stack operations (push or pop) in a single call.

[0111] Figure 19An exemplary flowchart of a flash memory controller vector processor, including register stack-specific instructions, is shown in its entirety at 1900. The flash memory controller 1900 includes a read module 1952, a write module 1954 coupled to the read module 1952, and a control module 1956 coupled to the read module 1952, data storage device 1958, and write module 1954. The flash memory controller has a neural network engine 1960 coupled to the read module 1952, data storage device 1958, and control module 1956. The neural network engine 1960 includes a vector processor 1962. The vector processor 1962 includes a vector processor operation 1902, which proceeds via 1903 to 1904 to determine whether the vector processor operation is a parameter stack-specific instruction. If the answer to 1904 is "no," then flowchart 1900 proceeds via 1907 to 1908 to determine whether the vector processor operation is a register stack-specific instruction. If the answer to 1904 is "yes", then flowchart 1900 proceeds via 1905 to 1920 to save or restore multiple contents of the parameter stack via a single call to a parameter stack-specific instruction, wherein the save or restore goes directly to or from the parameter stack and the first set of registers, and wherein the contents of the parameter stack are not stored in the first intermediate memory location. Flowchart 1900 proceeds via 1921 from 1920 to 1908 to determine whether the vector processor operation is a register stack-specific instruction. If the answer to 1908 is "no", then flowchart 1900 proceeds via 1911 to 1912 to continue with more vector processor operations. If the answer to 1908 is "yes", then flowchart 1900 proceeds via 1909 to 1930 to save or restore multiple contents of the register stack via a single call to a register stack-specific instruction, wherein the save or restore goes directly to or from the register stack and the second set of registers, and wherein the contents of the register stack are not stored in the second intermediate memory location. Flowchart 1900 proceeds from 1930 to 1912 via 1931 to continue further vector processor operations.

[0112] Register stack-specific instructions have already encoded within themselves how much stack space they require to perform register pushes or pops. That is, register stack-specific instructions can perform multiple register stack operations (push or pop) in a single call.

[0113] Although Figure 19 Operations are shown in sequence, such as the operation at 1904 before 1908, but the operations are not limited to this, and for example, operation 1908 may occur before or at the same time as 1904, or they may overlap in time.

[0114] Figure 20An exemplary flowchart of a flash controller vector processor without using an effective address generator is shown overall at 2000. The flash controller 2000 includes a read module 2052, a write module 2054 coupled to the read module 2052, and a control module 2056 coupled to the read module 2052, data storage device 2058, and write module 2054. The flash controller has a neural network engine 2060 coupled to the read module 2052, data storage device 2059, and control module 2056. The neural network engine 2060 includes a vector processor 2062. The vector processor 2062 includes a vector processor operation 2002, which proceeds via 2003 to 2004 to determine whether the vector processor operation is a parameter stack-specific instruction. If the answer to 2004 is "no," then flowchart 2000 proceeds via 2007 to 2008 to determine whether the vector processor operation is a register stack-specific instruction. If the answer to 2004 is "yes", then flowchart 2000 proceeds via 2005 to 2020 to save or restore multiple contents of the parameter stack via a single call to a parameter stack-specific instruction, wherein the save or restore goes directly to or comes from the parameter stack and the first set of registers, and wherein the contents of the parameter stack are not stored in the first intermediate memory location, and wherein the multiple operations of saving or restoring multiple contents of the parameter stack do not use an effective address generator. Flowchart 2000 proceeds via 2021 from 2020 to 2008 to determine whether the vector processor operation is a register stack-specific instruction. If the answer to 2008 is "no", then flowchart 2000 proceeds via 2011 to 2012 to continue with more vector processor operations. If the answer to 2008 is "yes", then flowchart 2000 proceeds via 2009 to 2030 to save or restore multiple contents of the register stack via a single call to a register stack-specific instruction, wherein the save or restore goes directly to or comes from the register stack and the second set of registers, and wherein the contents of the register stack are not stored in the second intermediate memory location, and wherein the multiple operations of saving or restoring multiple contents of the register stack do not use an effective address generator. Flowchart 2000 proceeds via 2031 from 2030 to 2012 to continue further vector processor operations, and flowchart 2000 proceeds via 2013 to 2002 to perform another vector processor operation.

[0115] Although Figure 20 Operations are shown in sequence, such as operations at 2004 before 2008, but operations are not limited to this, and for example, operation 2008 may occur before or at the same time as 2004, or they may overlap in time.

[0116] Figure 21At 2100, an example is shown in its entirety where calls to parameter stack-specific instructions and calls to register stack-specific instructions are temporally independent. At 2102, a representative timeline is shown, with arrows indicating earlier times near the end marked 2102. Arrows indicating later times are closer to the current time. At 2104, four representative calls to parameter stack-specific instructions at 2106-1, 2106-2, 2106-3, and 2106-4 are shown. This technique is not limited to this, and any number of calls to parameter stack-specific instructions is possible. At 2108, three representative calls to register stack-specific instructions at 2110-1, 2110-2, and 2110-3 are shown. This technique is not limited to this, and any number of calls to register stack-specific instructions is possible. As shown at 2112, calls to parameter stack-specific instructions and calls to register stack-specific instructions are temporally independent and may overlap temporally, or may not overlap temporally, but are not limited to this.

[0117] Figure 22 At 2200, an example is shown of multiple calls to parameter stack-specific instructions and multiple calls to register stack-specific instructions, with states independent of the contents of the parameter stack and independent of the contents of the register stack. At 2202, a representative timeline is shown, with arrows indicating earlier times near the end marked 2202. Arrows indicating later times are closer to the current time. At 2204, four representative calls to parameter stack-specific instructions at various times along timeline 2202 are shown. At 2206, four representative calls to register stack-specific instructions at various times along timeline 2202 are shown. At 2208, five representative states of the contents of the parameter stack at various times along timeline 2202 are shown. At 2210, four representative states of the contents of the register stack at various times along timeline 2202 are shown. At 2212, the first plurality of calls to parameter stack-specific instruction 2204 and the second plurality of calls to register stack-specific instruction 2206 are shown, with states independent of the contents of parameter stack 2208 and independent of the contents of register stack 2210.

[0118] Figure 23At 2300, an overall example of simultaneous operations saving or restoring multiple parameter stack contents and simultaneous operations saving or restoring multiple register stack contents without using a valid address generator is shown. At 2302, a representative timeline is shown, with arrows indicating earlier times near the end marked 2302. Arrows indicating later times are closer to the current time. At 2304, four representative calls of parameter stack-specific instructions at various times along timeline 2302 are shown. At 2306, four representative calls of register stack-specific instructions at various times along timeline 2302 are shown. At 2308, six representations of saving or restoring multiple parameter stack contents are shown. At 2310, five representations of saving or restoring multiple register stack contents are shown. At 2312, simultaneous operations saving or restoring multiple parameter stack contents and simultaneous operations saving or restoring multiple register stack contents without using a valid address generator are shown.

[0119] As described in detail above and in the claims, a vector processor device is shown, in one example of which it does not have a valid address generator. The vector processor has a first stack for pushing parameters and a second stack for saving and restoring registers. The first stack and the second stack can operate simultaneously.

[0120] As shown, it can handle call (or subroutine) operations, and can handle multiple deep (nested subroutine) recursive calls using the techniques disclosed in this invention.

[0121] In one example, multiple calls (or subroutines) can be handled without requiring a valid address generator.

[0122] It also demonstrates the ability to handle both clustered and distributed registers.

[0123] Furthermore, the ability of parameter stack-specific instructions and register stack-specific instructions to save and / or restore multiple stack memory contents in a single call is demonstrated. These specific instructions can operate substantially simultaneously in time, or the calls can be different in time. The invocation of these specific instructions is independent of the state of any stack memory contents.

[0124] The special instructions disclosed in this article handle multiple stack operations with a single call. For example: Save rX by pushing r0, r1, ..., rX onto the stack, where X represents an integer greater than 1. and RSTR rX pops r0, r1, ..., rX from the stack, where X represents an integer greater than 1. An example call operation in the pseudocode is as follows:

[0125] For the purposes of discussion and understanding of the embodiments, it should be understood that various terms are used by those skilled in the art to describe the techniques and methods. Furthermore, numerous specific details are set forth in this specification for purposes of explanation in order to provide a thorough understanding of the examples. However, it will be apparent to those skilled in the art that the examples can be practiced without these specific details. In some instances, to avoid obscuring the embodiments, well-known structures and apparatuses are shown in block diagram form rather than in detail. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the embodiments, and it should be understood that other embodiments can be utilized, and logical, mechanical, electrical, and other changes can be made without departing from the scope of the embodiments.

[0126] As used herein, "an example" or "example" or similar phrases mean that the described feature is included in at least one example. References to "an example" in this specification do not necessarily refer to the same example; however, such examples are not mutually exclusive. "An example" also does not imply the existence of only a single example. For example, features, structures, actions, etc., described in "an example" may also be included in other examples. Therefore, the invention may include various combinations and / or integrations of the examples described herein.

[0127] As used in this specification, the terms "substantially" or "substantially equivalent" or similar phrases are used to indicate that these items are very close or similar. Since two physical entities can never be completely identical, phrases such as "substantially equivalent" are used to indicate that they are equivalent for all practical purposes.

[0128] It should be understood that in any one or more examples of alternative methods or techniques discussed, any and all possible combinations of such combinations may be disclosed. For example, if all five techniques in question are possible, each technique is represented as follows: A, B, C, D, E, each of which may or may not be present with each of the other techniques, thus generating 2^5 or 32 combinations, the range of which in binary order is from neither A nor B nor C nor D nor E to A and B and C and D and E. The applicant thereby claims protection for all such possible combinations. The applicant thereby declares that the aforementioned combinations meet the applicable EP (European Patent) standard. No preference is given for any particular combination.

Claims

1. A method for invoking an operation, the method comprising: A call operation is performed in a vector processor that includes a parameter stack and a register stack. The call operation is performed using only stack operations and register-to-register operations. The call operation includes: Push one or more parameters onto the parameter stack; Push the contents of one or more registers of the vector processor onto the register stack; Pop the one or more parameters from the parameter stack into the one or more registers of the vector processor; A register-to-register operation is performed on one or more registers of the vector processor, wherein the result of the register-to-register operation is stored in a result register, which is one of the one or more registers of the vector processor; Push the contents of the result register onto the parameter stack; Pop the contents of one or more registers of the vector processor from the register stack into their respective registers; and Control is returned to the instructions following the invocation operation.

2. The method of claim 1, wherein the invocation operation is performed without using a valid address generator.

3. The method according to claim 1, Pushing one or more parameters onto the parameter stack includes pushing one or more parameters directly onto the parameter stack. Pushing the contents of one or more registers of the vector processor onto the register stack includes directly pushing the contents of one or more registers of the vector processor onto the register stack. Popping one or more parameters from the parameter stack into one or more registers of the vector processor includes directly popping one or more parameters from the parameter stack into one or more registers of the vector processor. Pushing the contents of the result register onto the parameter stack includes directly pushing the contents of the result register onto the parameter stack, and Popping the contents of one or more registers of the vector processor from the register stack into their respective registers includes directly popping the contents of one or more registers of the vector processor from the register stack into their respective registers.

4. The method of claim 1, wherein the register-to-register operation is performed in the form of a set of parallel operations of the vector processor.

5. The method of claim 1, wherein the parameter stack and the register stack operate substantially simultaneously.

6. The method according to claim 1, wherein, The invocation of another invocation operation is performed during the execution of the aforementioned invocation operation.

7. The method according to claim 1, wherein, During the execution of the aforementioned call operation, as long as there is still stack space on both the parameter stack and the register stack, another call operation is executed.

8. A vector processor, the vector processor comprising: A parameter stack, which has a corresponding control instruction set, a stack base address register, a stack limit register, and a stack pointer register, and the parameter stack is connected to memory; A register stack, which has a corresponding control instruction set, a stack base address register, a stack limit register, and a stack pointer register, and the register stack is connected to the memory; and A vector processing unit, which is connected to the memory, is also described. The vector processor is configured to perform a call operation using only stack operations and register-to-register operations, the call operation including: Push one or more parameters onto the parameter stack; Push the contents of one or more registers of the vector processor onto the register stack; Pop the one or more parameters from the parameter stack into the one or more registers of the vector processor; A register-to-register operation is performed on one or more registers of the vector processor, wherein the result of the register-to-register operation is stored in a result register, which is one of the one or more registers of the vector processor; Push the contents of the result register onto the parameter stack; Pop the contents of one or more registers of the vector processor from the register stack into their respective registers; and Control is returned to the instructions following the invocation operation.

9. The vector processor of claim 8, wherein the calling operation is performed without using a valid address generator.

10. A flash memory controller, the flash memory controller having a read module, a write module coupled to the read module, and a control module coupled to the read module, a data storage device, and the write module, the flash memory controller comprising: A neural network engine, coupled to the read module, the data storage device, and the control module, includes a vector processor comprising: Memory; A parameter stack, which has a corresponding control instruction set, a stack base address register, a stack limit register, and a stack pointer register, and the parameter stack is coupled to the memory; A register stack, having a corresponding control instruction set, a stack base address register, a stack limit register, and a stack pointer register, the register stack being coupled to the memory; and A vector processing unit, coupled to the memory, is configured to perform vector operations. The vector processor is configured to perform a call operation using only stack operations and register-to-register operations, the call operation including: Push one or more parameters onto the parameter stack; Push the contents of one or more registers of the vector processor onto the register stack; Pop the one or more parameters from the parameter stack into the one or more registers of the vector processor; A register-to-register operation is performed on one or more registers of the vector processor, wherein the result of the register-to-register operation is stored in a result register, which is one of the one or more registers of the vector processor; Push the contents of the result register onto the parameter stack; Pop the contents of one or more registers of the vector processor from the register stack into their respective registers; and Control is returned to the instructions following the invocation operation.

11. The flash memory controller of claim 10, wherein the calling operation is performed without using a valid address generator.

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