Resonant coupling transmission line

Abstract

An example printed circuit board (PCB) includes a substrate having a dielectric material layer, wherein the dielectric material layer includes a first layer and a second layer; a conductive trace located between the first layer and the second layer and parallel to the first layer and the second layer along at least a portion of a length of the conductive trace; and a conductive via extending at least partially through the dielectric material layer and electrically connected to the conductive trace, wherein the conductive via is further configured to be electrically connected to a signal input to receive or transmit a signal having a center sweep width.

Description

Technical Field

[0001] This specification describes an example of a transmission line that includes a resonantly coupled conductor. Background Technology

[0002] The test system is configured to test the operation of electronic devices (referred to as devices under test, DUTs). The test system may include test instruments to send signals (including digital and analog signals) to the DUT for testing. An exemplary device interface board (DIB) includes structures to route signals to the DUT and back towards the test instruments from the DUT. Summary of the Invention

[0003] An exemplary printed circuit board (PCB) includes: a substrate having a dielectric material layer, wherein the dielectric material layer includes a first layer and a second layer; a conductive trace located between the first layer and the second layer and parallel to the first layer and the second layer for at least a portion of its length; and a conductive via extending at least partially through the dielectric material layer and electrically connected to the conductive trace, wherein the conductive via is further configured to be electrically connected to a signal input to receive a signal having a center frequency span. The exemplary PCB also includes a first ground layer electrically connected to the conductive via, wherein the first ground layer is connected to a reference ground voltage, wherein the first ground layer is adjacent to the second layer, and wherein the first ground layer is positioned at a distance from the conductive trace, the distance being substantially equal to one-quarter (1 / 4) of the wavelength of the center frequency span of the signal. A second ground layer is adjacent to the first layer and is also connected to the reference ground voltage. The conductive trace is located between the first ground layer and the second ground layer. The exemplary PCB may also include one or more of the following features, individually or in combination.

[0004] The first ground layer may reflect at least the center sweep width of the signal along the via, and the resulting reflected signal is transmitted into the conductive trace. The conductive trace, the via, the first ground layer, and the second ground layer may form a first transmission line. The first transmission line may intersect with other transmission lines on different layers of the PCB. The first transmission line may be located in the same layer of the substrate as one or more other transmission lines in the PCB. The conductive trace may be between corresponding dielectric material layers in the substrate and may be at least partially parallel to the corresponding dielectric material layers. The via may extend at least partially through the dielectric material layer and may be electrically connected to the corresponding conductive trace. The via may be configured to be electrically connected to a corresponding signal input to receive a corresponding signal having a center sweep width.

[0005] The signal input may include radio frequency signals, microwave signals, or millimeter-wave signals. The signal input may include sinusoidal signals, modulated signals, or bidirectional signals moving bidirectionally through the conductive track. The bidirectional signals moving through the conductive track may be frequency-differentiated and share a common total bandwidth.

[0006] The third ground layer may be electrically connected to the corresponding via electrically connected to the corresponding signal input. Each third ground layer may be connected to a reference ground voltage. Each third ground layer may be positioned at a distance from the corresponding conductive trace, the distance being approximately equal to one-quarter (1 / 4) of the wavelength of the center sweep width of the signal received at the corresponding signal input. The first, second, and third ground layers may be uninterrupted. The first, second, and third ground layers may be electrically connected to a common reference ground voltage.

[0007] A structure having the conductive traces, vias, first ground layer, and second ground layer configuration can be repeated in the substrate along the same dimension of the PCB. For example, the same dimension can be horizontal in the same layer. A structure having the conductive traces, vias, first ground layer, and second ground layer configuration can be stacked in the substrate along a dimension orthogonal to the dielectric material layer.

[0008] The signal input may include an input transmission line. The signal input may include a coaxial connector configured to connect directly to the via. The signal input may also be configured to supply a signal for output from the DIB. The PCB may be or include a device interface board (DIB) configured to mount a device under test (DUT) for testing. The signal input may be electrically connected to a signal path between the DIB and a test instrument configured to generate or receive the signal.

[0009] The first layer of the substrate may include one or more dielectric layers, and the second layer of the substrate may include one or more dielectric layers. The first and second layers may be asymmetrical because they may have different thicknesses. The thickness of the second layer may be approximately equal to one-quarter (1 / 4) of the wavelength of the center sweep width of the signal.

[0010] The exemplary PCB may include a ground via that is conductive and partially surrounds the conductive via connected to the signal input. The ground via may be electrically connected to the first ground layer. The ground via may not exist at an electrical connection point between the conductive trace and the conductive via. The exemplary PCB may include a conductor configured to establish an electrical connection between the conductive trace and the conductive via. The conductor may be configured to match the impedance of the conductive trace to the impedance of the conductive via. The conductor may be located between the first layer and the second layer, and may be parallel to the first layer and the second layer for at least a portion of its length. The conductive trace may include a strip conductor. The conductor may have a width different from the width of the conductive trace.

[0011] The exemplary PCB may include a conductive via that extends substantially parallel to the conductive trace for at least a portion of its length. The via may be electrically connected to the first ground layer.

[0012] The first and second layers of the PCB may be or include different dielectrics. The different dielectrics may have at least one of different dispersion characteristics or different insertion losses. The different dielectrics may have different chemical properties such that, from a signal perspective, the first and second layers have the same electromagnetic thickness even if they have different physical thicknesses.

[0013] An exemplary system includes: a device interface board (DIB) configured to hold a device under test (DUT) for testing; a test instrument configured to output a signal to test the DUT, wherein the DIB is used to route the signal to the DUT; and a control system configured to control the operation of the test instrument to output the signal to test the DUT. The DIB may include: a substrate having a dielectric material layer, wherein the dielectric material layer includes a first layer and a second layer; a conductive trace located between the first layer and the second layer and parallel to the first layer and the second layer at least partially along the length of the conductive trace; and a via extending at least partially through the dielectric material layer and electrically connected to the conductive trace, wherein the via is further configured to be electrically connected to a signal input to receive a signal having a center sweep width. The exemplary PCB further includes a first ground plane electrically connected to the conductive via, wherein the first ground plane is connected to a reference ground voltage, wherein the first ground plane is adjacent to the second layer, and wherein the first ground plane is positioned at a distance from the conductive trace, the distance being approximately equal to one-quarter (1 / 4) of the wavelength of the center sweep width of the signal. A second ground plane is adjacent to the first layer and is also connected to the reference ground voltage. The conductive trace is located between the first ground plane and the second ground plane. The exemplary system may also include one or more of the following features, individually or in combination.

[0014] The first layer of the substrate may include one or more dielectric layers, and the second layer of the substrate may include one or more dielectric layers. The first and second layers may be asymmetrical because they may have different thicknesses. The thickness of the second layer may be approximately equal to one-quarter (1 / 4) of the wavelength of the center sweep width of the signal.

[0015] The DIB may include a conductive ground via that partially surrounds the conductive via. The ground via may be electrically connected to the first ground layer. The DIB may include a conductor configured to establish an electrical connection between the conductive trace and the conductive via. The conductor may be configured to match the impedance of the conductive trace with the impedance of the conductive via.

[0016] A structure having the configuration of the conductive traces, the conductive vias, the first ground layer, and the second ground layer can be repeated in the substrate. A structure having the configuration of the conductive traces, the conductive vias, the first ground layer, and the second ground layer can be stacked in the substrate along a dimension orthogonal to the dielectric material layer.

[0017] The exemplary DIB is configured as a mechanical and electrical interface between the DUT and the test instruments of the test system. The DIB includes: a substrate having a dielectric material layer, wherein the dielectric material layer includes a first layer and a second layer; a conductive trace located between the first layer and the second layer, and parallel to the first layer and the second layer for at least a portion of its length; and a conductive via extending through the dielectric material layer and electrically connected to the conductive trace, wherein the conductive via is further configured to be electrically connected to a signal input to receive a signal having a center sweep width. The DIB also includes components for reflecting the signal along the conductive via, components for suppressing at least a portion of the signal dissipation into the substrate, and components for suppressing signal reflection along the conductive trace.

[0018] Any two or more features described in this specification, including the summary paragraph, may be combined to form an embodiment not specifically described in this specification.

[0019] At least a portion of the systems and apparatus described herein can be configured or controlled by executing instructions on one or more processing devices, said instructions stored on one or more non-transitory machine-readable storage media. Examples of non-transitory machine-readable storage media include read-only memory, optical disc drives, memory disk drives, and random access memory. At least a portion of the systems and apparatus described herein can be implemented as an apparatus, method, or test system, which may include one or more processing devices and computer memory for storing control of executable instructions to perform said functions. The apparatus, system, and / or components thereof described herein can be configured, for example, by design, construction, arrangement, placement, programming, operation, startup, deactivation, and / or control.

[0020] The accompanying drawings and the following description illustrate details of one or more embodiments. Other features and advantages will become apparent from the description and drawings, and from the claims. Attached Figure Description

[0021] Figure 1 This is a bottom-facing transparent perspective view of an exemplary transmission line assembly formed on a device interface board (DIB).

[0022] Figure 2 yes Figure 1 A front view of the components of an exemplary transmission line.

[0023] Figure 3 yes Figure 1 A transparent perspective view of the top-facing portion of an exemplary transmission line component.

[0024] Figure 4 It shows its energy dissipation. Figure 1A front view of the components of an exemplary transmission line.

[0025] Figure 5 It shows its energy dissipation. Figure 1 A transparent perspective view of the lower portion of an exemplary transmission line component.

[0026] Figure 6 This is a bottom-facing transparent perspective view of an exemplary transmission line component formed on a DIB.

[0027] Figure 7 yes Figure 6 A front view of the components of an exemplary transmission line.

[0028] Figure 8 yes Figure 6 An upward perspective view of the components of an exemplary transmission line.

[0029] Figure 9 It shows the dissipation of energy within it. Figure 6 A front view of the components of an exemplary transmission line.

[0030] Figure 10 It is shown Figure 6 A graph of insertion loss in decibels for an exemplary transmission line of the type shown for a signal with a center frequency of 44 GHz (gigahertz).

[0031] Figure 11 It is shown Figure 6 A graph showing the signal return loss in decibels for an exemplary transmission line of the type shown, for a signal with a center frequency of 44 GHz.

[0032] Figure 12 It is a front view of a matrix of transmission lines that may be included in an exemplary DIB.

[0033] Figure 13 This is a block diagram of components of an exemplary test system, which includes instruments for transmitting digital signals to a device under test (DUT).

[0034] Similar reference numerals in different diagrams indicate similar elements. Detailed Implementation

[0035] This document describes examples of printed circuit boards (PCBs), such as device interface boards (DIBs) having transmission lines formed therein. Exemplary transmission lines include resonant coupled conductors configured to transmit time-varying signals having a center sweep width. Examples of signals that can be transmitted on the transmission lines include, but are not limited to, microwave signals, radio frequency (RF) signals, and millimeter wave (mmwave) signals. The signals can be sinusoidal, modulated, unidirectional, or bidirectional, as described below.

[0036] In some examples, a PCB (e.g., a DIB) is formed by converging a substrate layer and a conductive material layer. The substrate may include, for example, one or more different types of dielectric materials, as described below. The conductive material forms conductive traces and vias through the substrate. Some types of DIBs may exhibit suboptimal performance when transmitting high-frequency signals. For example, Figures 1 to 3 Components of an exemplary transmission line structure formed in DIB 10 are shown. In this respect, Figure 2 It shows the view in the direction of arrow 9. Figure 1 The front view of the component shown, and Figure 3 A bottom perspective view is shown. In DIB 10, a signal is received via a flat-shaped signal input 11. A columnar conductive via 12 carries the signal to a strip conductor 14, which is a type of conductive trace. Figure 2 and 3 As shown, the conductive via 12 includes a protrusion into the underlying substrate 17. Figure 2 The drill-through component 15 (or simply "drill-through") is an artifact of the construction of the DIB 10 and, according to some circuit board manufacturers, cannot be removed from the structure.

[0037] The drill-through element 15 may adversely affect signal transmission, especially at high frequencies, including but not limited to millimeter-wave frequencies. For example, in some cases, a portion of the input signal may not be transmitted into the conductor 14 as intended, but may instead propagate downwards to the via 12 and the drill-through element 15. In this example, as... Figure 4 As shown, the drill bit 15 dissipates the energy 19 from the signal (represented by grayscale shading) to the surrounding substrate and nearby transmission lines. Figure 4 (Not shown) It serves as an antenna. Figure 5 It shows about Figure 4 Another view of the type of energy dissipation described 19 (again shown in grayscale shading). Figure 4 and 5The type of energy dissipation shown can cause signal insertion loss and crosstalk in nearby transmission traces. In some cases, crosstalk can affect transmission lines within 100 mils (2.54 mm) of each other. However, in general, transmission lines are closer together than in a DIB.

[0038] In addition, such as Figure 1 As shown, although the flat input 11, via 12, and strip conductor 14 define the electrical path through which electrical signals can be transmitted and received, the cylindrical shape of the via 12 introduces impedance discontinuities at the contact points with the flat input 11 and strip conductor 14. These impedance discontinuities can cause signal reflections along the strip conductor. Signal reflections can also cause signal insertion losses experienced by the transmission line.

[0039] The PCB implementation scheme described herein addresses (e.g., reduces or eliminates) crosstalk, signal insertion loss, and / or signal reflection of the types previously described. An exemplary PCB (e.g., a DIB with one or more transmission lines) includes a substrate comprising dielectric material layers comprising an asymmetrical first and second layer. Conductive traces (e.g., strip conductors) are located between the first and second layers and are at least partially parallel to the first and second layers along their length. A central conductive via, which may have a columnar shape, extends at least partially through the first and second dielectric layers and is electrically connected to the conductive trace. The via is configured to be electrically connected to a signal input to receive a time-varying signal having a center sweep width, such as a microwave signal, an RF signal, or a millimeter-wave signal. A first ground layer is electrically connected to the via. The first ground layer is connected to and defines a reference ground voltage and is adjacent to the second layer. The first ground layer may be positioned at a distance from the conductive trace, the distance being approximately equal to one-quarter (1 / 4) of the wavelength of the center sweep width of the signal. In this context, the length is generally equal to, but may include, within ±5% or less of, a quarter wavelength of the center sweep width of the signal. This configuration causes the strip conductor to be resonantly coupled. A second ground layer is adjacent to the first layer and connected to the reference ground voltage, such that the conductive trace and the first and second layers of the substrate are between the first and second ground layers. The foregoing configuration is part of a shielded transmission line used for transmitting signals received from external sources on the PCB and for transmitting signals from the PCB to external destinations.

[0040] In this respect, the first ground plane connected to the via is configured to reflect a portion of the RF signal propagating downwards into the via without entering the strip conductor back towards the strip conductor, and then transmit it into the strip conductor. Since the first ground plane is positioned at a distance from the conductive trace that is approximately equal to one-quarter the wavelength of the center sweep width of the signal, the center sweep width (which may include the center frequency of the signal and a frequency band near that center frequency) does not experience significant interference on the strip conductor. In this respect, by short-circuiting the via at one-quarter the wavelength of the desired operating center frequency, the drill-through exhibits infinite impedance at the connection point to the strip conductor, thereby preventing signal energy loss or impedance distortion at the connection point. Furthermore, although the signal continuing into the drill-through is first shifted by 90° during its transmission to the drill-through and then shifted another 90° upon returning to the intersection point of the transmission line, the signal experiences a half-cycle time delay at the operating center frequency. During this time delay, the signal from the input also experiences a half-cycle lead, or a 180° progression. The time for both signals to reach the intersection point (source and reflection) continues. Therefore, when the drill-through reflected signal from the ground plane reaches the intersection point of the conductor and is shifted by 180°, the input signal at the same intersection point is also shifted by 180°, resulting in constructive interference, since the two signals are now in phase and at the same voltage at any given instant.

[0041] The reflection from the ground plane also reduces signal energy dissipation into the surrounding substrate, thereby reducing crosstalk in nearby transmission lines. Signal reflection back into the strip conductor also reduces signal insertion loss and signal reflection along the strip conductor. To further address signal reflection, the conductor is configured to establish an electrical connection between the strip conductor and the via, such that the impedance of the conductive trace matches the impedance of the conductive via. In this regard, in some embodiments, the impedance of the strip conductor (conductive trace) is 50Ω; however, a conductive trace with any suitable impedance can be used.

[0042] Figures 6 to 8 Exemplary components included in a PCB (e.g., DIB 20) are shown, which may be portions of transmission lines through which signals are transmitted via the DIB. In this respect, Figure 7 Shown in the direction of arrow 37 Figure 6 The front view of the component shown, and Figure 8 A bottom perspective view is shown. (See attached image.) Figures 6 to 8As shown, DIB 20 is made of multiple layers 21 and 22, each of which may include multiple layers of a substrate (e.g., a dielectric material) and a conductive material in the substrate to form conductive traces and vias through the substrate. For example, in some cases, hundreds or thousands of such layers may be stacked and fused to form the DIB. Conductive traces may be formed inside the DIB surrounded by the substrate or on the surface of the DIB. In some embodiments, the substrate comprises epoxy resin, resin, polytetrafluoroethylene (PTFE), or a combination thereof; however, any suitable dielectric material may be used as the substrate. In some examples, the dielectric material comprises epoxy resin in which powder is bonded together with glass fibers. In some examples, as described below, the dielectric material comprises materials purchased from... Corporation's Megtron and Megtron Dielectric material.

[0043] like Figures 6 to 8 As shown, DIB 20 includes a center via 25. In this example, the center via 25 is cylindrical, conductive, and can be directly or indirectly connected to a signal input, such as a flat transmission line (not shown) or a coaxial cable connector (not shown). The signal input transmits a signal with a center sweep width to the DIB. The center sweep width can be a major issue in applications such as device testing, as wireless devices may be configured to operate within a frequency band near the center frequency. In the example, an RF device may be configured to operate at a center frequency of 44 GHz and with a 1 dB insertion loss in a 3 GHz band near 44 GHz. As mentioned, in some examples, the signal provided by the signal input includes, but is not limited to, microwave signals, RF signals, and millimeter-wave signals.

[0044] In the exemplary definitions, microwave signals have a frequency range of about 1 GHz to about 30 GHz. In the exemplary definitions, RF signals have a frequency range of about 20 kHz to about 3 GHz. In the exemplary definitions, millimeter wave signals have a frequency range of about 30 GHz to about 300 GHz. However, the definitions of microwave, RF, and millimeter wave can vary over time and in different jurisdictions. Therefore, signals labeled as microwave, RF, or millimeter wave herein are not limited to the previously stated numerical frequency ranges.

[0045] A signal input carrying a signal with a center sweep width can be along a signal path and a portion of the signal path between the DIB and a test instrument configured to generate the signal, a variant of the signal, or a signal based on the signal. A center via 25 is configured to receive this signal and transmit it through the substrate in the DIB 20 to a conductive trace located within a substrate layer included in the DIB 20. For this purpose, the center via 25 extends at least partially (e.g., completely or partially) through layers 21 and 22 of the substrate. In the DIB 20, the center via 25 extends completely through layers 23 and 24. Figure 6 As shown, one end 27 of the center via 25 is exposed to enable direct connection to an input transmission line or to a coaxial cable connector. In some embodiments, the connection to the signal input and the center via may include an intermediate conductive structure.

[0046] like Figure 7 and 8 As shown, the central through-hole 25 also includes a protrusion into the lower substrate 30. Figure 7 The drill bit 29 in the DIB 20. As explained above, the drill bit 29 is an artifact of the construction of the DIB 20. The central through hole 25 and the drill bit 29 can be made of any suitable conductive material (including but not limited to copper).

[0047] like Figure 7 and 8 As shown, DIB 20 includes at least two layers 21 and 22 having dielectric material. In some applications, DIB 20 includes far more than two layers. In this example, the layers include: a first layer 21 containing dielectric material; and a second layer 22 containing dielectric material. The first layer 21 and the second layer 22 may also include conductive material deposited in etched or cut-out portions into the substrate to form the conductive component described herein. The conductive material is a portion of the thickness of the dielectric material and is sandwiched between all or most of the dielectric material in the layers.

[0048] The first layer 21 may include one or more dielectric layers, and the second layer 22 may include one or more dielectric layers. In this case, the first and second layers are asymmetrical because they have different thicknesses. However, in some embodiments, the first and second layers may have the same thickness and are therefore symmetrical. For reasons explained herein, the thickness of the second layer is approximately equal to one-quarter of the wavelength of the center sweep width of the signal passing through the DIB. In this regard, a deviation substantially equal to one-quarter wavelength of the center sweep width of the signal may include, but is not limited to: ±10% deviation from one-quarter wavelength of the center sweep width, ±9% deviation from one-quarter wavelength of the center sweep width, ±8% deviation from one-quarter wavelength of the center sweep width, ±7% deviation from one-quarter wavelength of the center sweep width, ±6% deviation from one-quarter wavelength of the center sweep width, ±5% deviation from one-quarter wavelength of the center sweep width, ±4% deviation from one-quarter wavelength of the center sweep width, ±3% deviation from one-quarter wavelength of the center sweep width, ±2% deviation from one-quarter wavelength of the center sweep width, or ±1% deviation from one-quarter wavelength of the center sweep width. Figure 6 and 7 In the middle, the central through hole 25 extends to the end of the second layer 22, and its drilled part 29 protrudes beyond the second layer 22 into the lower substrate 30. Figure 7 ), such as regarding Figure 2 and 3 The situation.

[0049] As previously explained, the first layer 21 and the second layer 22 of the substrate may comprise the same type of dielectric material or different types of dielectric materials. In the example, different dielectrics may have different chemical properties such that, from an electromagnetic perspective, the first layer 21 and the second layer 22 appear to have the same physical thickness, even though the first layer and the second layer have different physical thicknesses. Different chemical properties can cause different dielectrics to have different signal dispersion characteristics, different signal insertion losses, or both. In the example, the first layer 21 comprises one or more layers containing materials purchased from [source missing]. Corporation's dielectric material: Megtron Dielectric material. In the example, the second layer 22 includes one or more layers containing materials purchased from [source missing]. Corporation's dielectric material: Megtron Dielectric. In other cases, Megtron and Megtron It is rigid enough to withstand the pressure required for connection to a signal input without deforming or significantly deforming. It can replace or be used in addition to Megtron. and Megtron In addition, other types of dielectrics can also be used in DIB 20.

[0050] refer to Figure 6 The DIB 20 also includes one or more conductive traces, such as strip conductors 32. An exemplary strip conductor comprises a flat metal strip, such as copper formed on or within a layer of a substrate. The strip width, the thickness around the substrate, and the relative permittivity of the substrate affect the characteristic impedance of the strip conductor. In this example, the strip conductor 32 is between at least a portion of the first layer 21 and the second layer 22, and is parallel to the first and second layers for at least a portion of its length. The strip conductor is part of a transmission line formed within the DIB 20, configured to transmit signals between a central via 25 and one or more DUTs on the DIB. Therefore, the length of the strip conductor can vary and is based on the distance between the central via 26 and the DUT. As mentioned above, a signal can move through the strip conductor 32 in one or both directions. For example, a signal can move from the central via 25 through the strip conductor 32 to reach the DUT on the DIB. This is referred to as receiving a signal at the DIB. For example, a signal can move from the DUT on the DIB through the strip conductor 32 to reach the central via 25. This is called the sourcing signal for output from the DIB. The signal can move bidirectionally and in parallel through the strip conductor 32, for example, while the signal moves from the DUT to the center via 25, the signal can also move from the center via 25 to the DUT. The bidirectional signals transmitted in parallel may include two signals that are frequency-differentiated (e.g., the signals have different frequencies) and share a common total bandwidth.

[0051] like Figure 7 and 8As shown, DIB 20 includes a first ground layer 34, which may be made of any suitable conductive material (e.g., copper). Ground layer 34 is electrically connected to the central via 25 and defines a reference ground voltage for the DIB. That is, ground layer 34 may be electrically connected to a reference voltage 36, which includes the common ground voltage of all transmission line ground layers in the DIB. In this example, ground layer 34 is adjacent to (e.g., plated to) the bottom of the second layer 22 protruding from the drill-through 29. And, since the thickness of the second layer 22 is approximately equal to one-quarter of the wavelength of the center sweep width of the time-varying signal input to the DIB via the signal input described above, the ground layer is also positioned at a distance from the strip conductor 32, the distance being approximately equal to one-quarter of the wavelength of the center sweep width of the signal. The drill-through 29 of the central via 25 is electrically connected to (in other words, electrically short-circuited to) ground layer 34, as... Figure 8 This is most clearly shown. This relates to the electrical connection between the hole 35, which prevents electrical grounding, and the drilled part 15. Figure 3 The configurations are in contrast. As mentioned above, Figures 6 to 8 The configuration of the DIB 20 shown produces signal reflection along the central via 25, which can reduce or eliminate signal insertion loss through the central via and / or reduce signal reflection along the strip conductor 32.

[0052] Figure 9 The signal reflection along the central through-hole 25 is shown as grayscale shadow 38. Figure 9 This illustrates that reflected energy is confined to the central via 25 and does not leak into the surrounding substrate through the drill-through 29. To explain the reflection through the central via 25 in another way, the ground layer 34 establishes a hard short circuit to the drill-through 29 at a quarter-wavelength distance to form a resonator in the desired center frequency band. The resulting resonator is electrically connected to the strip conductor 32 via an electrical connection between the central via 25 and the strip conductor 32. Due to this configuration, the drill-through 29 becomes merely redundant copper and is no longer connected to any RF energy. However, since the drill-through 29 is now used to establish an electrical ground connection to the central via 25 to form the resonator, the drill-through 29 has been converted from a liability to an asset.

[0053] refer to Figure 6 and 7 The DIB 20 also includes a second ground layer 39, which may be made of any suitable conductive material, such as copper. Ground layer 39 is connected to a reference ground voltage 36, such as... Figure 7 As shown. In this respect, both the first ground layer 34 and the second ground layer 39 are connected to the same reference ground voltage. For this example, the ground layers are also uninterrupted. The ground layer 39 is separated from the live conductor 32 by the base layer 21, as shown. Figure 7 As shown. Figure 6As shown, hole 40 electrically isolates the central through-hole 25 from ground layer 39. Given that the first ground layer 34 provides shielding below the transmission line generated using the wire connector 32 in the substrate, the second ground layer 38 provides shielding above the transmission line generated using the wire connector 32 in the substrate.

[0054] like Figures 6 to 8 As shown, the central through-hole 25 is also partially surrounded by a grounding through-hole 42. The grounding through-hole 42 may be a columnar conductive through-hole electrically connected to the grounding layers 34 and / or 39 and extending along the length of the central through-hole 25; for example, the grounding through-hole may be at least as long as the central through-hole 25. In this respect, the grounding layer 34 is connected to all grounding through-holes and to the drill bit 29. Figure 6 Ten grounding vias 42 are shown; however, any suitable number of grounding vias 42 can be used. Also as shown, the grounding vias 42 partially surround the center via 25. In this configuration, the center via 25 and the grounding vias 42 together approximate the function of a coaxial conductor, where the center via 25 serves as the center conductor and the grounding via 42 serves as a shield or loop. The center via configured for coaxial connection allows the input coaxial transmission line to be mounted directly to the DIB surface, rather than through a short section of the transmission line (e.g., ...). Figure 1 The connection is achieved using a flat input 11). However, in some implementations, for example, a flat input 11) can be used. Figure 1 A short section of the flat input 11 of the transmission line is used to make an electrical connection to the central via 25. Furthermore, compared to a configuration that does not include a radial ground via, the radial ground via 42 improves the impedance matching between the central via 25 and the strip conductor 32. In this respect, the dimensions of the central via 25 and the strip conductor 32, as well as the spacing and location of the ground vias 42, all affect the impedance matching within the transmission line structure.

[0055] As shown, the absence of a grounding via at the electrical connection point 45 between the central via 25 and the conductor 32 renders the previous approximation imperfect. This is because the conductor 32 conducts signals along its length, and directly connecting the grounding via to the conductor would adversely affect signal transmission. Due to the "absence" of the grounding via, energy may leak from the near-coaxial structure, resulting in signal insertion loss.

[0056] To address the issue of the "absence" (or multiple) of grounding vias at the location of the strip conductor 32, an additional conductive trace (or simply "conductor" 46) is connected between the central via 25 and the strip conductor 32. Conductor 46 may be made of copper or any other suitable conductive material. Conductor 46 is configured to establish an electrical connection between the central via 25 and the strip conductor 32. Conductor 46 is configured (e.g., sized, shaped, and / or connected) to establish impedance matching between the strip conductor 32 and the central via 25. This impedance matching resolves the impedance discontinuity explained above and reduces insertion loss and signal reflection along the strip conductor 32. Figure 6 In the example, conductor 46 is a flat conductor with a width greater than that of the strip conductor 32. However, the dimensions of conductor 46 may differ for different strip conductor / center via combinations. For example, conductor 46 may be a flat conductor with a width less than that of the strip conductor 32. The width and length of conductor 46 are at least in part based on the geometry of other transmission lines and DIB components. For example, different diameters of the center via 25 and widths of the strip conductor 32 will require conductor 46 with different geometries to achieve impedance matching. Different types of dielectrics and dielectric thicknesses will also affect the dimensions of conductor 46.

[0057] DIB 20 also includes a ground via 50, which is conductive and extends substantially parallel to and along each side of the strip conductor 32 for at least a portion (e.g., all or less) of its length. The ground via 50 is electrically connected to ground layers 34 and / or 39, and thus electrically connected to a common reference voltage 36. The ground via 50 provides electromagnetic shielding along the sides of the strip conductor 32. As mentioned above, shielding is provided above and below the strip conductor 32 by ground layers 34 and 39. In some embodiments, the ground vias are positioned sufficiently away from the strip conductor 32 to prevent signal short circuits. The number and geometry of the ground vias can be determined by factors such as the frequency of the transmitted signal and the geometry of other components of the transmission line, including conductive and non-conductive parts. In some embodiments, the ground vias 50 overlapping the ground via 42 can be removed.

[0058] because Figures 6 to 8 The configuration ensures that the energy leaking from the drill-through 29 (e.g., all energy) is returned to the transmission line (with conductor 32). Therefore, the energy is not lost through radiation and no crosstalk is generated in the vicinity of the transmission line. Furthermore, in some examples, since the resonator λ / 4 formed by the asymmetric PCB layer perfectly returns all center sweep width energy to the transmission line, no energy is reflected back out of the coaxial connector. Additionally, the impedance matching section implemented by the additional conductor 46 can improve transmission line performance by improving both insertion loss and return loss (in some examples, by a relatively small amount).

[0059] Figure 10 It shows having information about Figures 6 to 8 A graph of the insertion loss 51 in decibels for an exemplary system of the type of DIB described and tuned to a frequency 52 of 44 GHz 55. The target insertion loss in this example is less than 4 dB for at least 3 GHz of frequency band near the 44 GHz center frequency (i.e., the center sweep width in this example). The markers (one of which is labeled 54) correspond to a 1 dB loss at 37 GHz, leaving margin for manufacturing variations and a 3 dB loss at 50 GHz, making this exemplary system usable in multiple Federal Communications Commission (FCC) bands.

[0060] Figure 11 This is a graph showing the return loss 57 at 44 GHz 58 in the aforementioned system. In this example, the desired return loss is -15 dB or less. Generally, the lower the return loss, the better. Marker 59 is at -15 dB, which shows an acceptable performance span of 22 GHz.

[0061] about Figures 6 to 8 The described exemplary transmission line structure can be repeated multiple times on the same substrate, wherein all ground layers are connected to the same common reference voltage. Thus, the exemplary transmission line structure includes multiple conductive traces (e.g., strip conductors 32) located between and at least partially parallel to corresponding dielectric material layers in the substrate. The exemplary transmission line structure also includes multiple conductive vias (e.g., center via 25) extending at least partially through the dielectric material layers and electrically connected to the corresponding conductive traces and corresponding signal inputs to receive or supply corresponding signals having a center sweep width. The exemplary transmission line structure also includes ground layers electrically connected to the corresponding ones in the conductive vias, wherein the ground layers define a reference ground voltage, and wherein each ground layer is positioned at a distance from the corresponding conductive trace, the distance being substantially equal to one-quarter (1 / 4) of the wavelength of the center sweep width of the signal received at the corresponding signal input. In some examples, the ground plane of the lower ground plane forming the first transmission line (which is connected to the drill bit) can be directly connected to the ground plane of the upper ground plane forming the second transmission line, which is below the first transmission line in the substrate.

[0062] In this regard, such as Figure 12 As shown, layers can be stacked in the substrate along dimensions orthogonal to the dielectric material layer. Figures 6 to 8 The described transmission line structure 60, with its dimensions indicated by arrow 62, indicates that multiple transmission lines can be formed along the thickness or depth of the substrate. Similarly, as... Figure 12As shown, the dimensions indicated by arrow 63 (which are orthogonal to the dimensions indicated by arrow 62) can be repeated in the basis regarding... Figures 6 to 8 The transmission line structure 60 is described. Therefore, multiple transmission lines can be located side-by-side on the same or nearly identical horizontal layers in the substrate. Transmission lines can be repeatedly stacked in the substrate to form a transmission line matrix distributed throughout the same PCB, such as... Figure 12 As shown. Although Figure 12 Only four transmission lines are shown, but any suitable number of transmission lines may be included. The transmission lines 60 in the matrix may extend in different directions and cross each other in different layers of the DIB. For example, transmission lines on one layer of the PCB may intersect with other transmission lines on different layers. In this exemplary transmission line matrix of this type, each transmission line has... Figures 6 to 8 The structure is one of its variations. Therefore, for the reasons described herein, interference between signals in a transmission line matrix can be eliminated or reduced relative to transmission lines with different structures. Each such transmission line may also have other advantages, such as reduced signal insertion loss and unwanted reflections.

[0063] In some implementation schemes, such as Figure 12 The transmission line matrix shown may include and have Figures 6 to 8 The configuration shown combines one or more transmission lines with Figures 1 to 3 One or more transmission lines as shown in the configuration. For example, having Figures 1 to 3 One or more transmission lines in the configuration shown can be physically isolated from other transmission lines in the matrix to reduce the possibility of energy dissipation affecting other transmission lines.

[0064] In some examples, the signals transmitted on the exemplary DIBs and transmission lines described herein include, but are not limited to: signals at or above 20 kHz, signals at or above 100 kHz, signals at or above 1 GHz, signals at or above 10 GHz, signals at or above 20 GHz, signals at or above 30 GHz, signals at or above 40 GHz, signals at or above 50 GHz, signals at or above 60 GHz, signals at or above 70 GHz, signals at or above 80 GHz, signals at or above 90 GHz, signals at or above 100 GHz, signals at or above 200 GHz, or signals at or above 300 GHz, signals at or above 500 GHz, signals at or above 1000 GHz, and so on.

[0065] Figure 13 Components of ATE 100, which may include the type of DIB 138 described herein, are shown. ATE 100 may be part of a test system. Figure 13In the diagram, dashed lines conceptually represent potential signal paths between components of a test system.

[0066] ATE 100 includes a test head 135 and a control system 1361. The control system may include a computing system, which includes one or more microprocessors or other suitable processing devices as described herein.

[0067] DIB 138 is or includes a PCB connected to test head 135 and includes mechanical and electrical interfaces for one or more DUTs being tested by or to be tested by ATE. The DIB includes a point 141, which may include pins, ball grid arrays (BGAs), conductive traces, or other electrical and mechanical connection points to which the DUT can be connected. Test signals, response signals, voltage signals, and other signals pass through the test channel via the point between the DUT and the test instrument. DIB 138 may also include connectors, conductive traces, and circuitry, etc., for routing signals between the test instrument, the DUT connected to point 141, and other circuitry. In this example, DIB 138 includes one or more connectors for connecting to signal transmission lines or coaxial cables for transmitting signals between one or more test instruments and one or more DUTs. DIB 138 also includes structures having, for example, those described herein (e.g., Figure 12 One or more transmission lines (of the matrix) are used to transmit signals to and / or from the DUT via internal strip conductors or other conductive traces within the DIB.

[0068] The control system 136 communicates with the components of the test head to control the test. For example, the control system 136 may download test programs to test instruments 140A to 140N in the test head. The test instruments include hardware devices that may include one or more processing units and other circuitry. The test instruments 140A to 140N can execute the test programs to test the DUT communicating with them. The control system 136 may also send instructions, test data, and / or other information usable by the test instruments to the test instruments in the test head to perform appropriate tests on the DUT interfacing with the DIB. In some embodiments, this information may be sent via a computer or other type of network or via a direct electrical path. In some embodiments, this information may be sent via a local area network (LAN) or a wide area network (WAN).

[0069] The test program generates test procedures to provide to the DUT. For example, a test procedure is written to output signals to elicit a response from the DUT. Test procedures can be written to output signals (including RF signals, microwave signals, and / or millimeter-wave signals) to one or more DUTs to receive responses from the DUTs to those signals and analyze the responses to determine whether the device passes or fails the test.

[0070] exist Figure 13 In the example, ATE 100 includes multiple test instruments 140A to 140N, each of which can be configured as needed to perform one or more of the following functions: testing and / or other functions. Although only four test instruments are depicted, the system may include any suitable number of test instruments, including those located outside the test head 135. In some embodiments, one or more test instruments may be configured to output microwave, RF, or millimeter-wave signals to test the DUT based on data provided, for example, by a control system, and to receive response signals from the DUT. Different test instruments may be configured to perform different types of tests and / or be configured to test different DUTs. The received signals may include response signals based on test signals and / or signals originating from the DUT that are not prompted by test signals (e.g., do not respond to test signals). In some embodiments, coaxial cables and / or signal transmission lines may be present between the DUT, DIB, and the test instrument interface through which test and response signals are transmitted.

[0071] Signals can be sent to and received from the DUT via multiple test channels. Each of these test channels may include one or more signal transmission lines, coaxial cables, or other wired or wireless transmission media. In some examples, the test channel may be defined by multiple physical transmission media through which signals are sent from the test instrument to the DUT and received from the DUT. In some examples, the test channel may be defined by a frequency range within which signals are transmitted via one or more physical transmission media. The test channel may include multiple conductive traces on the DIB.

[0072] In some examples, ATE 100 includes a connection interface 144 for connecting test instrument test channel 147 to DIB 138. Connection interface 144 may include connector 146 or other means for routing signals between the test instrument and DIB 138. For example, the connection interface may include one or more circuit boards or other substrates on which such connectors are mounted. Conductors included in the test channel can be routed through the connection interface and the DIB.

[0073] All test systems and programs, or parts thereof, and their various modifications, described in this specification can be configured or controlled, at least in part, by one or more computers (e.g., control system 136) using one or more computer programs tangibly embodied in one or more information carriers (e.g., one or more non-transitory machine-readable storage media). The computer programs can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including as standalone programs or as modules, components, subroutines, or other units suitable for use in a computing environment. The computer programs can be deployed to execute on one or more computers, which may be located in the same field or distributed across multiple fields and interconnected via a network.

[0074] Actions associated with configuring or controlling the voltage source, test system, and program described herein may be performed by one or more programmable processors that execute one or more computer programs to control all or some of the previously described perfecting operations. All or part of the test system and program may be configured or controlled by a dedicated logic circuit system, such as an FPGA (Field-Programmable Gate Array) and / or an ASIC (Application-Specific Integrated Circuit).

[0075] For example, processors suitable for executing computer programs include both general-purpose and special-purpose microprocessors and any one or more processors of any kind of digital computer. Generally, a processor receives instructions and data from read-only memory or random access memory, or both. The components of a computer include one or more processors for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include one or more machine-readable storage media, or media operably coupled to receive data from or transfer data to, or both, such as mass storage devices (e.g., magnetic disks, magneto-optical disks, or optical disks) for storing data. Suitable non-transitory machine-readable storage media for embodying computer program instructions and data include all forms of non-volatile memory, such as: semiconductor memory devices, such as EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM (Optical Disc Read-Only Memory) and DVD-ROM (Digital Multifunction Optical Disc Read-Only Memory).

[0076] The components of the different embodiments described can be combined to form other embodiments not specifically presented above. Components may be omitted from the system described above without adversely affecting its general operation or system operation. Furthermore, various separate components can be combined into one or more individual components to perform the functions described in this specification.

[0077] As used in this article, “conductive” includes electrical conductivity.

[0078] Other embodiments not specifically described in this specification are also included in the following claims.

Claims

1. A printed circuit board (PCB), comprising: A substrate, the substrate comprising a dielectric material layer, the dielectric material layer comprising a first layer and a second layer; A conductive trace, the conductive trace being located between the first layer and the second layer, and being parallel to the first layer and the second layer along at least a portion of the length of the conductive trace; A conductive via, the conductive via extending at least partially through the dielectric material layer and electrically connected to the conductive trace, the conductive via also being configured to be electrically connected to a signal input to receive a signal having a center sweep width; A first ground layer is electrically connected to the conductive via and connected to a reference ground voltage. The first ground layer is adjacent to the second layer and is positioned at a distance from the conductive trace, the distance being approximately equal to one-quarter (¼) of the wavelength of the center sweep width of the signal. as well as A second grounding layer, adjacent to the first layer and also connected to the reference ground voltage, the conductive trace being located between the first grounding layer and the second grounding layer.

2. The printed circuit board according to claim 1, wherein the conductive trace, the conductive via, the first ground layer, and the second ground layer form a first transmission line; and The first transmission line intersects with other transmission lines on different layers of the printed circuit board.

3. The printed circuit board according to claim 1, wherein the conductive trace, the conductive via, the first ground layer, and the second ground layer form a first transmission line; and The first transmission line and one or more other transmission lines in the printed circuit board are located in the same layer of the substrate.

4. The printed circuit board according to claim 1, further comprising: Conductive traces, the conductive traces being located between corresponding dielectric material layers in the substrate and being at least partially parallel to the corresponding dielectric material layers; A conductive via, which at least partially extends through the dielectric material layer and is electrically connected to a corresponding conductive trace, is also configured to be electrically connected to a corresponding signal input to receive a corresponding signal having a center sweep width; as well as A third grounding layer is electrically connected to the conductive via. Each third grounding layer is connected to the reference grounding voltage. Each third grounding layer is positioned at a distance from the corresponding conductive trace, the distance being approximately equal to one-quarter (¼) of the wavelength of the center sweep width of the signal received at the corresponding signal input.

5. The printed circuit board according to claim 4, wherein the first ground layer, the second ground layer and the third ground layer are uninterrupted.

6. The printed circuit board of claim 4, wherein the first ground layer, the second ground layer and the third ground layer are electrically connected to a common reference ground voltage.

7. The printed circuit board of claim 1, wherein the configuration of the conductive traces, the conductive vias, the first ground layer and the second ground layer is repeated in the substrate along the same dimension of the printed circuit board.

8. The printed circuit board of claim 7, wherein the same dimension is horizontal.

9. The printed circuit board of claim 1, wherein a structure having the conductive traces, the conductive vias, the first ground layer and the second ground layer are stacked in the substrate along a dimension orthogonal to the dielectric material layer.

10. The printed circuit board of claim 1, wherein the signal input includes an input transmission line.

11. The printed circuit board of claim 1, wherein the signal input includes a coaxial connector configured to be directly connected to the conductive via.

12. The printed circuit board of claim 1, wherein the signal input is further configured to supply a signal for output from the printed circuit board.

13. The printed circuit board of claim 1, wherein the printed circuit board includes a device interface board (DIB) configured to hold the device under test (DUT) for testing; and The signal input is electrically connected to a signal path between the device interface board and the test instrument, which is configured to generate or receive the signal.

14. The printed circuit board of claim 1, wherein the first layer comprises one or more dielectric layers, and the second layer comprises one or more dielectric layers; The first and second layers are asymmetrical because they have different thicknesses; and The thickness of the second layer is approximately equal to one-quarter (¼) of the wavelength of the center sweep width of the signal.

15. The printed circuit board of claim 1, further comprising: A grounding via, the grounding via being conductive and partially surrounding the conductive via, the grounding via being electrically connected to the first grounding layer.

16. The printed circuit board of claim 15, wherein a ground via is not present at an electrical connection point between the conductive trace and the conductive via.

17. The printed circuit board of claim 1, further comprising: A conductor configured to establish an electrical connection between the conductive trace and the conductive via, the conductor matching the impedance of the conductive trace with the impedance of the conductive via.

18. The printed circuit board of claim 17, wherein the conductor is located between the first layer and the second layer and is parallel to the first layer and the second layer along at least a portion of the length of the conductor.

19. The printed circuit board of claim 18, wherein the conductive trace comprises a wire conductor; and The conductor has a width different from that of the conductive trace.

20. The printed circuit board of claim 1, further comprising: A grounding via, the grounding via being conductive and extending substantially parallel to the conductive trace along at least a portion of the length of the conductive trace, the grounding via being electrically connected to the first grounding layer.

21. The printed circuit board of claim 1, wherein the first ground layer reflects at least the center sweep width of the signal along the conductive via, and the resulting reflected signal is emitted into the conductive trace.

22. The printed circuit board of claim 1, wherein the signal includes a radio frequency signal.

23. The printed circuit board of claim 1, wherein the signal includes a microwave signal.

24. The printed circuit board of claim 1, wherein the signal includes a millimeter-wave signal.

25. The printed circuit board of claim 1, wherein the first layer and the second layer comprise different dielectrics.

26. The printed circuit board of claim 25, wherein the different dielectrics have at least one of different dispersion characteristics or different insertion losses.

27. The printed circuit board of claim 25, wherein the different dielectrics have different chemical properties such that, from the perspective of the signal, the first layer and the second layer have the same electromagnetic thickness even though the first layer and the second layer have different physical thicknesses.

28. The printed circuit board of claim 1, wherein the signal comprises a sine wave signal.

29. The printed circuit board of claim 1, wherein the signal includes a modulated signal.

30. The printed circuit board of claim 1, wherein the signal is one of a plurality of signals that move bidirectionally through the conductive trace.

31. The printed circuit board of claim 30, wherein the plurality of signals comprises two signals that are separated by a frequency difference and share a common total bandwidth.

32. A testing system, comprising: Device interface board (DIB), which is configured to fix the device under test (DUT) for testing; A test instrument configured to output a signal to test the fixed device under test, wherein the device interface board is used to route the signal to the fixed device under test; as well as A control system configured to control the operation of the test instrument to output the signal to test the stationary device under test; The device interface board includes: A substrate, the substrate comprising a dielectric material layer, the dielectric material layer comprising a first layer and a second layer; A conductive trace, the conductive trace being located between the first layer and the second layer, and being parallel to the first layer and the second layer along at least a portion of the length of the conductive trace; A conductive via, the conductive via extending at least partially through the dielectric material layer and electrically connected to the conductive trace, the conductive via also being configured to be electrically connected to a signal input to receive a signal having a center sweep width; A first ground layer, electrically connected to the conductive via, connected to a reference ground voltage, adjacent to the second layer, and positioned at a distance from the conductive trace, the distance being approximately equal to one-quarter (¼) of the wavelength of the center sweep width of the signal; and A second grounding layer is adjacent to the first layer and connected to the reference ground voltage, and the conductive trace is located between the first grounding layer and the second grounding layer.

33. The test system of claim 32, wherein the first layer comprises one or more dielectric layers, and the second layer comprises one or more dielectric layers; The first and second layers are asymmetrical because they have different thicknesses; and The thickness of the second layer is approximately equal to one-quarter (¼) of the wavelength of the center sweep width of the signal.

34. The test system according to claim 32, wherein the device interface board further comprises: A grounding via, the grounding via being conductive and partially surrounding the conductive via, the grounding via being electrically connected to the first grounding layer.

35. The test system according to claim 32, wherein the device interface board further comprises: A conductor configured to establish an electrical connection between the conductive trace and the conductive via, the conductor matching the impedance of the conductive trace with the impedance of the conductive via.

36. The test system of claim 32, wherein the configuration having the conductive trace, the conductive via, the first ground layer and the second ground layer is repeatedly formed in the substrate.

37. The test system of claim 32, wherein a structure having the conductive trace, the conductive via, the first ground layer and the second ground layer are stacked in the substrate along a dimension orthogonal to the dielectric material layer.

38. A device interface board (DIB) configured as a mechanical and electrical interface between a device under test (DUT) and test instruments of a test system, the device interface board comprising: A substrate, the substrate comprising a dielectric material layer, the dielectric material layer comprising a first layer and a second layer; A conductive trace, the conductive trace being located between the first layer and the second layer, and being parallel to the first layer and the second layer along at least a portion of the length of the conductive trace; A conductive via extending through the dielectric material layer and electrically connected to the conductive trace, the conductive via also being configured to be electrically connected to a signal input to receive a signal having a center sweep width; A first ground layer is electrically connected to the conductive via and connected to a reference ground voltage. The first ground layer is adjacent to the second layer and is positioned at a distance from the conductive trace, the distance being approximately equal to one-quarter (¼) of the wavelength of the center sweep width of the signal. as well as A second grounding layer, adjacent to the first layer and also connected to the reference ground voltage, the conductive trace being located between the first grounding layer and the second grounding layer.

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