A method for constructing a semiconductor heterojunction
By using amorphous chalcogenide semiconductor materials as epitaxial layers and combining them with three-temperature zone chemical vapor deposition, the lattice mismatch problem was solved, and the construction of high-quality semiconductor heterojunctions was achieved, thus improving the performance of photodetectors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG UNIV
- Filing Date
- 2023-06-27
- Publication Date
- 2026-07-10
AI Technical Summary
Existing technologies are limited by lattice mismatch when constructing semiconductor heterojunctions, resulting in loss of coherence between the epitaxial layer and the substrate structure and a reduction in the lifetime of photogenerated carriers, which limits the application of semiconductor heterojunctions in high-performance electronic and optoelectronic devices.
Using amorphous chalcogenide semiconductor materials as epitaxial layers, and taking advantage of their random covalent network structure and ease of bonding with semiconductor surfaces, semiconductor heterojunctions are constructed by three-temperature zone chemical vapor deposition, including depositing metal catalysts on the substrate, growing IIIA-VA or IIB-VIA group semiconductor layers and amorphous chalcogenide semiconductor layers.
By overcoming the lattice mismatch limitation, controllable growth of epitaxial layers was achieved, and diverse semiconductor heterostructures were fabricated, improving the performance of photodetectors, especially the photodetector performance of GaSb/GeS and InGaAs/GeS core-shell semiconductor heterojunction nanowires.
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Abstract
Description
Technical Field
[0001] This invention relates to a method for constructing a semiconductor heterojunction, belonging to the field of semiconductor nanomaterials and devices. Background Technology
[0002] Semiconductor heterojunctions combine the advantages of various functional materials and can effectively modulate the electrical and optoelectronic properties of semiconductors through flexible band alignment design. They are widely used in various functional devices, such as photodetectors, light-emitting devices, photovoltaic devices, lasers, and high-speed chips. However, constructing high-quality semiconductor heterojunctions faces the challenge of lattice mismatch. Lattice mismatch introduces mismatch stress during the growth of the epitaxial semiconductor layer, which can lead to mismatch dislocations and a loss of structural coherence between the epitaxial layer and the substrate. Furthermore, mismatch dislocations often act as recombination centers, reducing the lifetime of photogenerated carriers and severely weakening the performance of optoelectronic devices. Therefore, overcoming the limitations of lattice mismatch has become a crucial problem to be solved in constructing semiconductor heterojunctions.
[0003] Currently, there are two main strategies for solving the problem of lattice mismatch: one is to reduce the thickness of the epitaxial layer. For example, Professor Charles M. Lieber of Harvard University used an ultrathin shell (about 2-3 nm) strategy to construct an InP / InAs core-shell heterojunction with a large lattice mismatch in order to ensure the coherence of the structure. The other common strategy is to select semiconductors with similar lattice parameters to construct semiconductor heterojunctions. For example, a typical lattice constant is... Heterojunctions of group III-V semiconductors (InAs / GaSb, InAs / AlSb, and GaSb / AlSb, etc.) have been successfully constructed. However, both of the aforementioned strategies for constructing semiconductor heterojunctions have certain limitations in photodetector applications. The ability of ultrathin shells to modulate photoelectric properties is limited; and the limited variety of semiconductors with similar lattice constants restricts the construction of different heterostructure types. This significantly limits the application of semiconductor heterojunctions in next-generation high-performance electronic and optoelectronic devices.
[0004] To promote the application of semiconductor heterojunctions, there is an urgent need to develop a simple, efficient, and universal method for constructing semiconductor heterojunctions that is not limited by lattice mismatch. This invention is proposed for this purpose. Summary of the Invention
[0005] To address the shortcomings of existing technologies, particularly the limitations imposed by lattice mismatch in constructing semiconductor heterojunctions, this invention provides a method for constructing semiconductor heterojunctions. This invention utilizes amorphous chalcogenide semiconductor materials as epitaxial layers to construct semiconductor heterostructures, overcoming the limitations imposed by lattice mismatch. Simultaneously, it leverages the ease with which chalcogenide elements bond with semiconductor surface atoms, promoting the conformal growth of amorphous chalcogenide semiconductor materials on the surface of crystalline semiconductors. This invention utilizes the lack of long-range order in amorphous semiconductors, resulting in a covalently random network structure without periodic constraints, thus solving the lattice mismatch problem encountered during epitaxial layer growth. The method is simple to operate and low in cost.
[0006] The technical solution of the present invention is as follows:
[0007] A method for constructing a semiconductor heterojunction includes the following steps:
[0008] Provide a substrate, and deposit a metal catalyst on the substrate;
[0009] Metal catalyst-assisted growth of IIIA-VA group semiconductor layers or IIB-VIA group semiconductor layers;
[0010] By growing an amorphous chalcogenide semiconductor layer on the surface of a IIIA-VA group semiconductor layer or an IIB-VIA group semiconductor layer, the construction of a semiconductor heterojunction is completed.
[0011] According to a preferred embodiment of the present invention, the substrate is a SiO2 / Si substrate with a thickness of 100-500 μm.
[0012] According to a preferred embodiment of the present invention, the metal catalyst is Au or Ni, and the thickness is 0.5-5 nm.
[0013] According to a preferred embodiment of the present invention, a metal catalyst is deposited on the substrate using electron beam evaporation or thermal evaporation. The electron beam evaporation or thermal evaporation method is readily available from existing technologies.
[0014] According to a preferred embodiment of the present invention, a core-shell semiconductor nanowire is obtained by growing a group IIIA-VA semiconductor layer or a group IIB-VIA semiconductor layer with the assistance of a metal catalyst; an amorphous chalcogenide semiconductor shell is grown on the surface of the core-shell semiconductor nanowire to construct a core-shell semiconductor heterojunction nanowire.
[0015] Preferably, the diameter of the core semiconductor nanowire is 20-100 nm and the length is 5-30 μm; the thickness of the amorphous chalcogenide semiconductor shell is 2-50 nm, and the amorphous chalcogenide semiconductor shell encapsulates the core semiconductor nanowire.
[0016] According to the present invention, IIIA-VA group semiconductor layer refers to semiconductor material composed of group IIIA elements and group VA elements; IIB-VIA group semiconductor material refers to semiconductor material composed of group IIB elements and group VIA elements.
[0017] According to the present invention, the IIIA-VA group semiconductor layer or the IIB-VIA group semiconductor layer is preferably GaSb, GaAs, InGaAs or CdS.
[0018] According to a preferred embodiment of the present invention, the amorphous chalcogenide semiconductor layer is GeS or GeSe.
[0019] According to a preferred embodiment of the present invention, the method for constructing a semiconductor heterojunction includes the following steps: constructing a semiconductor heterojunction using a three-temperature zone chemical vapor deposition method; wherein the three temperature zones include an upstream temperature zone (an amorphous chalcogenide semiconductor source region), a midstream temperature zone (a IIIA-VA or IIB-VIA semiconductor source region), and a growth region (a downstream temperature zone); an amorphous chalcogenide semiconductor material is placed in the upstream temperature zone, a IIIA-VA semiconductor material or an IIB-VIA semiconductor material is placed in the midstream temperature zone, and a substrate for depositing a metal catalyst is placed in the growth region; then, the IIIA-VA semiconductor material or the IIB-VIA semiconductor material is grown on the substrate for depositing the metal catalyst to obtain a IIIA-VA semiconductor layer or an IIB-VIA semiconductor layer, and the amorphous chalcogenide semiconductor material is grown on the surface of the IIIA-VA semiconductor layer or the IIB-VIA semiconductor layer to complete the construction of the semiconductor heterojunction.
[0020] Preferably, the three-zone chemical vapor deposition method is carried out in a three-zone horizontal tube furnace. Along the direction of the protective gas introduction, an upstream temperature zone, a midstream temperature zone, and a growth zone are sequentially arranged.
[0021] Preferably, the amorphous chalcogenide semiconductor material, IIIA-VA semiconductor material, or IIB-VIA semiconductor material and the substrate for depositing the metal catalyst are located at the center of the upstream temperature zone, the midstream temperature zone, and the growth zone, respectively.
[0022] Preferably, the IIIA-VA group semiconductor material or the IIB-VIA group semiconductor material is in powder form, with a purity of 99.999% and a particle size of less than 100 mesh.
[0023] Preferably, the amorphous chalcogenide semiconductor material is in powder form with a purity of 99.999% and a particle size of less than 100 mesh.
[0024] Preferably, the growth of IIIA-VA group semiconductor layers, IIB-VIA group semiconductor layers, and amorphous chalcogenide semiconductor layers are all carried out in a protective gas atmosphere of H2 or Ar, with the protective gas continuously introduced during the growth process at a rate of 50-200 sccm; the purity of the protective gas is 99.9995%.
[0025] Preferably, the growth of the IIIA-VA group semiconductor layer, the IIB-VIA group semiconductor layer, and the amorphous chalcogenide semiconductor layer is achieved by controlling the heating sequence of three temperature zones; during the growth of the IIIA-VA group semiconductor layer or the IIB-VIA group semiconductor layer, the midstream temperature zone and the growth zone are heated, while the upstream temperature zone is not heated, maintaining a low temperature in the upstream temperature zone; during the growth of the amorphous chalcogenide semiconductor layer, the upstream temperature zone, the midstream temperature zone, and the growth zone are heated simultaneously, and the temperature of the upstream temperature zone and the midstream temperature zone is kept consistent.
[0026] Preferably, during the growth of IIIA-VA group semiconductor layers, IIB-VIA group semiconductor layers, and amorphous chalcogenide semiconductor layers, the heating rate is less than 100°C / minute.
[0027] Preferably, during the growth of the IIIA-VA group semiconductor layer or the IIB-VIA group semiconductor layer, the temperature range of the midstream temperature zone is 750-810℃, and the temperature range of the growth zone is 540-610℃.
[0028] Preferably, during the growth of the amorphous chalcogenide semiconductor layer, the upstream temperature zone is 500-550℃, the midstream temperature zone is 500-550℃, and the growth zone is 320℃.
[0029] Preferably, the growth time of the IIIA-VA group semiconductor layer or the IIB-VIA group semiconductor layer is 20-40 minutes; after the growth of the IIIA-VA group semiconductor layer or the IIB-VIA group semiconductor layer is completed, the midstream temperature zone and the growth zone are naturally cooled to 500-550℃ and 320℃ respectively; then the upstream temperature zone is heated to 500-550℃ within 10 minutes to start the growth of the amorphous chalcogenide semiconductor layer, and the growth time of the amorphous chalcogenide semiconductor layer is 10-60 seconds; finally, the heating of the three temperature zones is stopped at the same time, and they are rapidly cooled to room temperature within 20 minutes.
[0030] According to the present invention, a preferred embodiment of the method for constructing the semiconductor heterojunction includes the following steps:
[0031] (1) A substrate for depositing metal catalyst is obtained by depositing metal catalyst on a substrate using electron beam evaporation or thermal evaporation; the substrate for depositing metal catalyst is placed in the middle of the growth zone of a three-temperature zone horizontal tube furnace, a boron nitride crucible containing IIIA-VA group semiconductor material or IIB-VIA group semiconductor material is placed in the middle of the downstream temperature zone of the three-temperature zone horizontal tube furnace, and a boron nitride crucible containing amorphous chalcogen semiconductor material is placed in the middle of the upstream temperature zone of the three-temperature zone horizontal tube furnace.
[0032] (2) Reduce the pressure of the tubular furnace to 10. -3 Torr and ventilate with protective gas for 30 minutes;
[0033] (3) Keep the protective gas continuously flowing in, heat the midstream temperature zone to 750-810℃, heat the growth zone to 540-610℃, and grow the IIIA-VA group semiconductor material or IIB-VIA group semiconductor material on the substrate of the deposited metal catalyst.
[0034] (4) Keep the protective gas continuously flowing in, and naturally cool the midstream temperature zone and the growth zone to 500-550℃ and 320℃ respectively;
[0035] (5) Keep the protective gas continuously flowing in and heat the upstream temperature zone to 500-550°C within 10 minutes. The amorphous chalcogenide semiconductor material begins to grow an amorphous chalcogenide semiconductor layer on the surface of the IIIA-VA group semiconductor layer or the IIB-VIA group semiconductor layer.
[0036] (6) After growth is completed, the heating process of the three temperature zones is stopped at the same time, and the temperature is rapidly cooled to room temperature within 20 minutes under the protection gas flow, thus completing the construction of the semiconductor heterojunction.
[0037] Unless otherwise described in this invention, all matters are governed by existing techniques in the field.
[0038] The technical features and beneficial effects of this invention are as follows:
[0039] 1. This invention utilizes the characteristic that amorphous semiconductors lack long-range order and are structurally a covalent random network without the constraint of periodic arrangement. By using amorphous chalcogenide semiconductor materials as epitaxial layers, the limitation of constructing semiconductor heterojunctions by lattice mismatch is overcome. At the same time, by utilizing the characteristic that chalcogenide elements can easily bond with semiconductor surface atoms, the amorphous chalcogenide semiconductor materials are conformally grown on the surface of crystalline semiconductors.
[0040] 2. The method of the present invention is universal, simple and convenient, easy to implement, stable in results, low in cost and significant in benefits. It successfully prepares semiconductor heterostructures with controllable epitaxial layer thickness and diverse semiconductor heterostructure types on substrates, which is expected to promote the application of semiconductor heterostructures in next-generation high-performance electronic and optoelectronic devices.
[0041] 3. The semiconductor heterojunction construction method of this invention can obtain core-shell semiconductor heterostructure nanowires. The resulting core-shell semiconductor heterostructure nanowires have smooth surfaces, with the shell layer uniformly grown on the surface of the core nanowire. By changing the growth time of the shell layer, core-shell semiconductor heterostructure nanowires with different shell layer thicknesses can be grown. By rationally selecting the combination of shell semiconductor materials and core semiconductor materials, the construction of various semiconductor heterostructures can be realized. Furthermore, the method of this invention can fabricate high-performance broadband photodetectors. For example, Type I heterostructure GaSb / GeS core-shell semiconductor heterostructure nanowires achieve bidirectional photodetection and visible light-assisted infrared detection performance, while Type II heterostructure InGaAs / GeS core-shell semiconductor heterostructure nanowires achieve broadband photodetector devices with high responsivity and high response speed.
[0042] 4. This invention preferably employs a three-zone chemical vapor deposition method to construct semiconductor heterojunctions. During the growth of the amorphous chalcogenide semiconductor layer, to ensure that the vapor of the amorphous chalcogenide semiconductor material in the upstream zone can be transported to the growth region, the temperature of the mid-zone needs to be consistent with that of the upstream zone. To avoid the influence of the IIIA-VA or IIB-VIA group semiconductor materials placed in the mid-zone during the growth of the amorphous chalcogenide semiconductor material, the evaporation temperature of the IIIA-VA or IIB-VIA group semiconductor materials needs to be higher than that of the amorphous chalcogenide semiconductor material. The growth sequence of the semiconductor heterojunction constructed in this invention is to first grow the IIIA-VA or IIB-VIA group semiconductor layer, and then grow the amorphous chalcogenide semiconductor layer. Therefore, the amorphous chalcogenide semiconductor material needs to be placed in the upstream zone, and the IIIA-VA or IIB-VIA group semiconductor material needs to be placed in the mid-zone; these positions cannot be interchanged. In this invention, the heating sequence of the three temperature zones (upstream temperature zone, midstream temperature zone, and growth zone) is crucial. The growth of IIIA-VA group semiconductor layers or IIB-VIA group semiconductor layers and amorphous chalcogenide semiconductor layers is controlled by the heating sequence of the three temperature zones. Attached Figure Description
[0043] Figure 1 This is a schematic diagram of the three-temperature zone horizontal tube furnace used in this invention.
[0044] Figure 2This is a diagram showing the heating sequence of the three temperature zones for the two-step growth of core-shell semiconductor heterojunction nanowires in Embodiment 1 of the present invention.
[0045] Figure 3 The images show transmission electron microscopy (TEM), scanning transmission electron microscopy (STEM), and elemental mapping (EDS) images of the GaSb / GeS core-shell semiconductor heterojunction nanowires prepared in Example 1 of this invention.
[0046] Figure 4 This is a statistical diagram showing the distribution of diameter and shell thickness of GaSb / GeS core-shell semiconductor heterojunction nanowires obtained at different shell growth times in Example 1 of the present invention.
[0047] Figure 5 The images shown are scanning electron microscope (SEM) images, transmission electron microscope (TEM) images, and elemental distribution maps of the GaAs / GeS, InGaAs / GeS, and GaSb / GeSe core-shell semiconductor heterojunction nanowires prepared in Examples 2-4 of this invention.
[0048] Figure 6 The band structure characterization and band diagrams of the GaSb / GeS, GaAs / GeS, InGaAs / GeS, and GaSb / GeSe core-shell semiconductor heterojunction nanowires prepared in Examples 1-4 of this invention are presented.
[0049] Figure 7 The images show transmission electron microscopy (TEM) images and elemental distribution diagrams of the CdS / GeS core-shell semiconductor heterojunction nanowires prepared in Example 5 of this invention.
[0050] Figure 8 Scanning electron microscope (SEM), transmission electron microscope (TEM), scanning transmission electron microscope (STEM), and elemental mapping (EDS) images of the GaSb / GaAs core-shell semiconductor heterojunction nanowires prepared for Comparative Example 1.
[0051] Figure 9 The graph shows the broadband photoelectric detection performance and visible-assisted infrared detection performance of the GaSb / GaAs core-shell semiconductor heterojunction nanowires prepared in Example 1.
[0052] Figure 10 Broadband photoelectric detection performance of InGaAs core nanowires and InGaAs / GeS core-shell semiconductor heterojunction nanowires prepared in Example 3. Detailed Implementation Plan
[0053] To illustrate the invention more clearly, the invention will be further described below with reference to specific embodiments and accompanying drawings.
[0054] Unless otherwise specified, the experimental methods used in the examples are conventional methods.
[0055] Unless otherwise specified, all materials, reagents, and devices used in the embodiments are commercially available.
[0056] Example 1 uses amorphous chalcogenide semiconductor material GeS as the shell to construct GaSb / GeS core-shell semiconductor heterojunction nanowires.
[0057] A method for constructing a semiconductor heterojunction includes the following steps:
[0058] A 1 nm thick Au catalyst film was deposited on a 300 μm thick SiO2 / Si substrate using electron beam evaporation. The prepared substrate was placed in the middle of the growth zone of a three-zone horizontal tube furnace. Then, a boron nitride crucible containing 0.4 g of GaSb powder (99.999% purity, particle size less than 100 mesh) and a boron nitride crucible containing 0.1 g of GeS powder (99.999% purity, particle size less than 100 mesh) were placed in the middle of the upstream and downstream temperature zones of the three-zone horizontal tube furnace, respectively. The quartz tube was evacuated until the pressure reached 10... -3 The process involves continuously supplying H2 protective gas (99.9995% purity) at a flow rate of 200 sccm for 30 minutes. While maintaining this continuous H2 supply (200 sccm flow rate), the midstream temperature zone and growth zone are heated to 750℃ and 560℃ respectively, at a heating rate of 80℃ / min, for 25 minutes to achieve GaSb core nanowire growth. After growth, the midstream temperature zone and growth zone are naturally cooled to 500℃ and 320℃ respectively and held at these temperatures. Then, while maintaining this continuous H2 supply (200 sccm flow rate), the upstream temperature zone is heated to 500℃ within 10 minutes and grown for 10-60 seconds to achieve GeS shell growth. After growth, the heating process in all three temperature zones is stopped simultaneously, and the zone is rapidly cooled to room temperature within 20 minutes under a protective gas flow (200 sccm flow rate), thus completing the construction of the semiconductor heterojunction and obtaining GaSb / GeS semiconductor heterostructure nanowires with controllable shell thickness.
[0059] Example 2 uses amorphous chalcogenide semiconductor material GeS as the shell to construct GaAs / GeS core-shell semiconductor heterojunction nanowires.
[0060] A method for constructing a semiconductor heterojunction includes the following steps:
[0061] A 1 nm thick Au catalyst film was deposited on a 300 μm thick SiO2 / Si substrate using electron beam evaporation. The prepared substrate was placed in the middle of the growth zone of a three-temperature zone horizontal tube furnace. Then, a boron nitride crucible containing 0.4 g of GaAs powder (99.999% purity, particle size less than 100 mesh) and a boron nitride crucible containing 0.1 g of GeS powder (99.999% purity, particle size less than 100 mesh) were placed in the middle of the upstream and downstream temperature zones of the three-temperature zone horizontal tube furnace, respectively. The quartz tube was evacuated until the pressure reached 10... -3 Torr was then supplied with a protective H2 gas (99.9995% purity) at a flow rate of 200 sccm for 30 minutes. The H2 supply was maintained at 200 sccm, and the midstream and growth regions were heated to 800°C and 600°C respectively at a heating rate of 80°C / min for 25 minutes to achieve GaAs core nanowire growth. After growth, the midstream and growth regions were naturally cooled to 500°C and 320°C respectively and held at these temperatures. The H2 supply was then maintained at 200 sccm, and the upstream region was heated to 500°C within 10 minutes for 10 seconds to achieve GeS shell growth. After growth, the heating programs in all three regions were simultaneously stopped, and the region was rapidly cooled to room temperature within 20 minutes under a protective gas flow (200 sccm), thus completing the construction of the semiconductor heterojunction and obtaining semiconductor heterostructure nanowires.
[0062] Example 3 uses amorphous chalcogenide semiconductor material GeS as the shell to construct InGaAs / GeS core-shell semiconductor heterojunction nanowires.
[0063] A method for constructing a semiconductor heterojunction includes the following steps:
[0064] A 1 nm thick Ni catalyst film was deposited on a 300 μm thick SiO2 / Si substrate using electron beam evaporation. The prepared substrate was placed in the middle of the growth zone of a three-temperature zone horizontal tube furnace. Then, a boron nitride crucible containing 0.4 g of InGaAs powder (InAs:GaAs = 1:1, purity 99.999%, particle size less than 100 mesh) and a boron nitride crucible containing 0.1 g of GeS powder (purity 99.999%, particle size less than 100 mesh) were placed in the middle of the upstream and downstream temperature zones of the three-temperature zone horizontal tube furnace, respectively. The quartz tube was evacuated until the pressure reached 10... -3The InGaAs core nanowire was grown by continuously introducing H2 protective gas (99.9995% purity) at a flow rate of 200 sccm for 30 minutes. The midstream and growth regions were then heated to 810°C and 610°C respectively at a heating rate of 80°C / min for 40 minutes. After growth, the midstream and growth regions were naturally cooled to 500°C and 320°C respectively and held at these temperatures. The upstream region was then heated to 500°C within 10 minutes and grown for 10 seconds to achieve the GeS shell growth. After growth, the heating programs in all three regions were stopped simultaneously, and the nanowire was rapidly cooled to room temperature within 20 minutes under a protective gas flow (200 sccm), thus completing the construction of the semiconductor heterojunction and obtaining the semiconductor heterostructure nanowire.
[0065] Example 4 uses amorphous chalcogenide semiconductor material GeSe as the shell to construct GaSb / GeSe core-shell semiconductor heterojunction nanowires.
[0066] A method for constructing a semiconductor heterojunction includes the following steps:
[0067] A 1 nm thick Au catalyst film was deposited on a 300 μm thick SiO2 / Si substrate using electron beam evaporation. The prepared substrate was placed in the middle of the growth zone of a three-zone horizontal tube furnace. Then, a boron nitride crucible containing 0.4 g of GaSb powder (99.999% purity, particle size less than 100 mesh) and a boron nitride crucible containing 0.1 g of GeSe powder (99.999% purity, particle size less than 100 mesh) were placed in the middle of the upstream and downstream temperature zones of the three-zone horizontal tube furnace, respectively. The quartz tube was evacuated until the pressure reached 10... -3 The Torr was then supplied with a protective H2 gas (99.9995% purity) at a flow rate of 200 sccm for 30 minutes. The H2 supply was maintained at 200 sccm, and the midstream and growth regions were heated to 750°C and 560°C, respectively, at a heating rate of 80°C / min, for 25 minutes to grow the GaSb core nanowires. After growth, the midstream and growth regions were naturally cooled to 550°C and 320°C, respectively, and held at these temperatures. The H2 supply was then maintained at 200 sccm, and the upstream region was heated to 550°C within 10 minutes for 10 seconds to grow the GeSe shell. After growth, the heating programs in all three regions were stopped simultaneously, and the region was rapidly cooled to room temperature within 20 minutes under a protective gas flow (200 sccm), thus completing the construction of the semiconductor heterojunction and obtaining the semiconductor heterostructure nanowires.
[0068] Example 5 uses amorphous chalcogenide semiconductor material GeS as the shell to construct CdS / GeS core-shell semiconductor heterojunction nanowires.
[0069] A method for constructing a semiconductor heterojunction includes the following steps:
[0070] A 1 nm thick Au catalyst film was deposited on a 300 μm thick SiO2 / Si substrate using electron beam evaporation. The prepared substrate was placed in the middle of the growth zone of a three-zone horizontal tube furnace. Then, a boron nitride crucible containing 0.1 g of CdS powder (99.999% purity, particle size less than 100 mesh) and a boron nitride crucible containing 0.1 g of GeS powder (99.999% purity, particle size less than 100 mesh) were placed in the middle of the upstream and downstream temperature zones of the three-zone horizontal tube furnace, respectively. The quartz tube was evacuated until the pressure reached 10... -3 Torr was then supplied with Ar protective gas (99.9995% purity) at a flow rate of 50 sccm for 30 minutes. The Ar supply was maintained at 50 sccm, and the midstream and growth regions were heated to 750°C and 540°C, respectively, at a heating rate of 80°C / min, for 25 minutes to achieve CdS core nanowire growth. After growth, the midstream and growth regions were naturally cooled to 500°C and 320°C, respectively, and held at these temperatures. 200 sccm of H2 was continuously supplied, and the upstream region was heated to 500°C within 10 minutes for 10 seconds to achieve GeS shell growth. After growth, the heating programs in all three regions were simultaneously stopped, and the region was rapidly cooled to room temperature within 20 minutes under a protective gas flow (200 sccm), thus completing the construction of the semiconductor heterojunction and obtaining semiconductor heterostructure nanowires.
[0071] Comparative Example 1 uses GaAs, a crystalline semiconductor material, as the shell to construct GaSb / GaAs core-shell semiconductor heterojunction nanowires.
[0072] A 1 nm thick Au catalyst film was deposited on a 300 μm thick SiO2 / Si substrate using electron beam evaporation. The prepared substrate was placed in the middle of the growth zone of a three-temperature zone horizontal tube furnace. Then, a boron nitride crucible containing 0.4 g of GaSb powder (99.999% purity, particle size less than 100 mesh) and a boron nitride crucible containing 0.4 g of GaAs powder (99.999% purity, particle size less than 100 mesh) were placed in the middle of the upstream and downstream temperature zones of the three-temperature zone horizontal tube furnace, respectively. The quartz tube was evacuated until the pressure reached 10... -3Torr was then supplied with a protective H2 gas (99.9995% purity) at a flow rate of 200 sccm for 30 minutes. The H2 supply was maintained at 200 sccm, and the midstream and growth regions were heated to 750°C and 560°C respectively at a heating rate of 80°C / min for 25 minutes to achieve GaSb core nanowire growth. After growth, the midstream and growth regions were held at 750°C and 560°C respectively. The H2 supply was maintained at 200 sccm, and the upstream region was heated to 750°C within 10 minutes for 60 seconds to achieve GaAs shell growth. After growth, the heating programs in all three regions were simultaneously stopped, and the nanowires were rapidly cooled to room temperature within 20 minutes under a protective gas flow (200 sccm) to obtain the semiconductor heterostructure nanowires.
[0073] Experimental Example 1
[0074] A schematic diagram of the three-temperature zone horizontal tube furnace used in Embodiment 1 of the present invention is shown below. Figure 1 As shown.
[0075] A schematic diagram of the heating sequence of the three temperature zones in the three-zone tubular furnace in Example 1 is shown below. Figure 2 As shown; where source region 1 is the upstream temperature region and source region 2 is the midstream temperature region.
[0076] Transmission electron microscopy image of the GaSb / GeS core-shell semiconductor heterojunction nanowires obtained in Example 1 (GeS shell growth time was 30 seconds), as shown below. Figure 3 As shown in a, there is a clear contrast between the core and the shell, indicating that the core-shell nanowires have been successfully constructed. Figure 3 b and 3c are cross-sectional scanning transmission electron microscope images of the synthesized nanowires. It can be seen that the shell is amorphous, while the core nanowire is crystalline. Figure 3 dg is the elemental distribution diagram of the synthesized nanowires, which shows that the shell is GeS and the core nanowires are GaSb.
[0077] Figure 4 The figures (a) and (b) show the diameters and shell thicknesses of the core-shell semiconductor heterojunction nanowires grown at GeS shell times of 10 seconds, 30 seconds, and 60 seconds in Example 1. It can be seen that using the amorphous semiconductor material GeS as the shell, GaSb / GeS core-shell semiconductor heterojunction nanowires with controllable diameter and thickness can be constructed using a simple chemical vapor deposition method.
[0078] Experimental Example 2
[0079] Scanning electron microscope (SEM) images, transmission electron microscope (TEM) images, and elemental distribution maps of the GaAs / GeS(ac), InGaAs / GeS(df), and GaSb / GeSe(gi) core-shell semiconductor heterojunction nanowires obtained in Examples 2-4 of this invention are shown below. Figure 5 As shown, the method for constructing semiconductor heterojunctions proposed in this invention has universality and is applicable to IIIA-VA group semiconductor materials.
[0080] Experimental Example 3
[0081] The band structure characterization of the GaSb / GeS (GeS shell growth time is 30 seconds), GaAs / GeS, InGaAs / GeS, and GaSb / GeSe core-shell semiconductor heterojunction nanowires obtained in Examples 1-4 of this invention is as follows: Figure 6 As shown. Through ultraviolet photoelectron spectroscopy (UV PES) Figure 6 ae) characterizes the band structure of GeS, GeSe shells and GaSb, GaAs, InGaAs core nanowires, showing that the method for constructing semiconductor heterojunctions proposed in this invention can construct core-shell semiconductor heterojunction nanowires with different heterostructure types. Figure 6 fi).
[0082] Test Example 4
[0083] The transmission electron microscope image (a) and elemental distribution map (b) of the CdS / GeS core-shell semiconductor heterojunction nanowires obtained in Example 5 of this invention are shown below. Figure 7 As shown, the method for constructing semiconductor heterojunctions proposed in this invention has universality and is applicable not only to IIIA-VA group semiconductor materials but also to IIB-VIA group semiconductor materials.
[0084] Experimental Example 5
[0085] The scanning electron microscope (a), transmission electron microscope (bc), and elemental distribution map (d) of the GaSb / GaAs core-shell semiconductor heterojunction nanowires obtained in Comparative Example 1 of this invention are shown below. Figure 8 As shown. Obviously, due to the lattice mismatch between the crystalline GaAs shell and the GaSb core nanowire, the surface of the prepared semiconductor heterojunction nanowire is not smooth, and the GaAs shell is unevenly distributed on the surface of the core GaSb nanowire.
[0086] Experimental Example 6
[0087] The broadband photoelectric detection performance and visible-light-assisted infrared detection performance of the GaSb / GeS core-shell semiconductor heterojunction nanowires obtained in Example 1 of this invention are as follows: Figure 9 As shown. Figure 9a shows a broadband photodetector test pattern of core-shell semiconductor heterojunction nanowires with different shell thicknesses. Figure 9 b is a visible-assisted infrared detection test image of a core-shell semiconductor heterojunction nanowire with moderate shell thickness. Figure 9 c is the transient response test diagram of a core-shell semiconductor heterojunction nanowire with moderate shell thickness. Figure 9 d represents the band structure principle of photodetector in a type I semiconductor heterojunction. Wherein, Figure 9 The growth times for the thin, medium-thickness, and thick shells are 10 seconds, 30 seconds, and 60 seconds, respectively. It can be seen that, thanks to the type-I heterojunction band structure, the fabricated GaSb / GeS core-shell semiconductor heterojunction nanowires exhibit wavelength-dependent bidirectional photodetector performance, displaying a negative response in the visible light band and a positive response in the infrared band. Furthermore, visible-light-assisted infrared detection performance has been achieved, greatly expanding the application of semiconductor heterojunction nanowires in the field of photodetector.
[0088] Experimental Example 7
[0089] The broadband photodetector performance of the pure InGaAs nanowires and InGaAs / GeS core-shell semiconductor heterojunction nanowires obtained in Example 3 of this invention is as follows: Figure 10 As shown. Figure 10 a shows broadband photodetector test results for pure InGaAs nanowires and InGaAs / GeS core-shell semiconductor heterojunction nanowires. Figure 10 b shows a comparison of the detection performance of pure InGaAs nanowires and InGaAs / GeS core-shell semiconductor heterojunction nanowires for 850nm light. Figure 10 c represents a comparison of the response time of pure InGaAs nanowires and InGaAs / GeS core-shell semiconductor heterojunction nanowires to 850nm light. Figure 10 d represents the band structure principle of photodetector in a type II semiconductor heterojunction. It can be seen that, thanks to the type II heterojunction band structure's advantage in separating photogenerated carriers, the prepared InGaAs / GeS core-shell semiconductor heterojunction nanowires exhibit significantly improved photoresponse performance compared to pure InGaAs nanowires. The photocurrent is increased by three orders of magnitude, and the responsivity and detectivity are increased by two orders of magnitude. Simultaneously, the response time is shortened by nearly 1500 times. This demonstrates that the prepared core-shell semiconductor heterojunction nanowires are beneficial for improving the photodetector performance of semiconductor heterojunction nanowires.
[0090] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, thereby achieving controlled growth of semiconductor heterostructures urgently needed in other research fields. These improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A method for constructing a semiconductor heterojunction, comprising the steps of: Provide a substrate, and deposit a metal catalyst on the substrate; Metal catalyst-assisted growth of IIIA-VA group semiconductor layers or IIB-VIA group semiconductor layers; Amorphous chalcogenide semiconductor layers are grown on the surface of IIIA-VA group semiconductor layers or IIB-VIA group semiconductor layers, thus completing the construction of semiconductor heterojunctions. A core-layer semiconductor nanowire is obtained by growing a group IIIA-VA semiconductor layer or a group IIB-VIA semiconductor layer with the assistance of a metal catalyst; an amorphous chalcogenide semiconductor shell is grown on the surface of the core-layer semiconductor nanowire to construct a core-shell semiconductor heterojunction nanowire. The IIA-VA group semiconductor layer or the IIB-VIA group semiconductor layer is GaSb, GaAs, InGaAs or CdS; the amorphous chalcogenide semiconductor layer is GeS or GeSe; The method for constructing a semiconductor heterojunction includes the following steps: constructing a semiconductor heterojunction using a three-temperature zone chemical vapor deposition method; the three temperature zones include an upstream temperature zone, a midstream temperature zone, and a growth zone; placing an amorphous chalcogenide semiconductor material in the upstream temperature zone, placing a IIIA-VA group semiconductor material or a IIB-VIA group semiconductor material in the midstream temperature zone, and placing a substrate with a deposited metal catalyst in the growth zone; then growing a IIIA-VA group semiconductor material or a IIB-VIA group semiconductor material on the substrate with the deposited metal catalyst to obtain a IIIA-VA group semiconductor layer or a IIB-VIA group semiconductor layer, and growing an amorphous chalcogenide semiconductor material on the surface of the IIIA-VA group semiconductor layer or the IIB-VIA group semiconductor layer, thereby completing the construction of the semiconductor heterojunction; The growth of IIIA-VA or IIB-VIA semiconductor layers, as well as amorphous chalcogenide semiconductor layers, is achieved by controlling the heating sequence of three temperature zones. During the growth of IIIA-VA or IIB-VIA semiconductor layers, the midstream temperature zone and the growth zone are heated, while the upstream temperature zone is not heated, maintaining a low temperature. During the growth of amorphous chalcogenide semiconductor layers, the upstream, midstream, and growth zones are heated simultaneously, and the temperature of the upstream and midstream temperature zones is kept consistent. During the growth of IIIA-VA or IIB-VIA semiconductor layers, the temperature range of the midstream temperature zone is 750-810℃, and the temperature range of the growth zone is 540-610℃; during the growth of amorphous chalcogenide semiconductor layers, the temperature range of the upstream temperature zone is 500-550℃, the temperature range of the midstream temperature zone is 500-550℃, and the temperature range of the growth zone is 320℃.
2. The method for constructing a semiconductor heterojunction according to claim 1, characterized in that, Includes one or more of the following conditions: i. The substrate is a SiO2 / Si substrate with a thickness of 100-500μm; ii. The metal catalyst is Au or Ni, with a thickness of 0.5-5 nm; iii. Deposit metal catalysts on the substrate using electron beam evaporation or thermal evaporation methods.
3. The method for constructing a semiconductor heterojunction according to claim 1, characterized in that, The core-layer semiconductor nanowires have a diameter of 20-100 nm and a length of 5-30 μm; the amorphous chalcogenide semiconductor shell has a thickness of 2-50 nm and wraps around the surface of the core-layer semiconductor nanowires.
4. The method for constructing a semiconductor heterojunction according to claim 1, characterized in that, Includes one or more of the following conditions: i. Three-zone chemical vapor deposition is carried out in a three-zone horizontal tube furnace; ii. The amorphous chalcogenide semiconductor material, IIIA-VA group semiconductor material or IIB-VIA group semiconductor material and the substrate of the deposited metal catalyst are respectively located in the upstream temperature region, the midstream temperature region and the center of the growth region; iii. IIIA-VA group semiconductor materials or IIB-VIA group semiconductor materials are in powder form with a purity of 99.999% and a particle size of less than 100 mesh; iv. Amorphous chalcogenide semiconductor materials are in powder form with a purity of 99.999% and a particle size of less than 100 mesh; The growth of group IIIA-VA semiconductor layers, group IIB-VIA semiconductor layers, and amorphous chalcogenide semiconductor layers is carried out in a protective gas atmosphere of H2 or Ar. During the growth, the protective gas is continuously introduced at a rate of 50-200 sccm, and the purity of the protective gas is 99.9995%.
5. The method for constructing a semiconductor heterojunction according to claim 1, characterized in that, Includes one or more of the following conditions: i. During the growth of IIIA-VA group semiconductor layers or IIB-VIA group semiconductor layers and amorphous chalcogen semiconductor layers, the heating rate is less than 100℃ / min. ii. The growth time for the IIIA-VA group semiconductor layer or the IIB-VIA group semiconductor layer is 20-40 minutes. After the growth of the IIIA-VA group semiconductor layer or the IIB-VIA group semiconductor layer is completed, the midstream temperature zone and the growth zone are naturally cooled to 500-550℃ and 320℃, respectively. Then, the upstream temperature zone is heated to 500-550℃ within 10 minutes to start the growth of the amorphous chalcogenide semiconductor layer. The growth time of the amorphous chalcogenide semiconductor layer is 10-60 seconds. Finally, the heating of the three temperature zones is stopped at the same time, and they are rapidly cooled to room temperature within 20 minutes.
6. The method for constructing a semiconductor heterojunction according to claim 1, characterized in that, Including the following steps: (1) A substrate for depositing metal catalyst is obtained by depositing metal catalyst on a substrate using electron beam evaporation or thermal evaporation; the substrate for depositing metal catalyst is placed in the middle of the growth zone of a three-temperature zone horizontal tube furnace, a boron nitride crucible containing IIIA-VA group semiconductor material or IIB-VIA group semiconductor material is placed in the middle of the downstream temperature zone of the three-temperature zone horizontal tube furnace, and a boron nitride crucible containing amorphous chalcogen semiconductor material is placed in the middle of the upstream temperature zone of the three-temperature zone horizontal tube furnace. (2) Reduce the pressure of the tubular furnace to 10. -3 Torr and ventilate with protective gas for 30 minutes; (3) Keep the protective gas continuously flowing in, heat the midstream temperature zone to 750-810℃, heat the growth zone to 540-610℃, and grow the IIIA-VA group semiconductor material or IIB-VIA group semiconductor material on the substrate of the deposited metal catalyst. (4) Keep the protective gas continuously flowing in, and naturally cool the midstream temperature zone and the growth zone to 500-550℃ and 320℃ respectively; (5) Keep the protective gas continuously flowing in and heat the upstream temperature zone to 500-550°C within 10 minutes. The amorphous chalcogenide semiconductor material begins to grow an amorphous chalcogenide semiconductor layer on the surface of the IIIA-VA group semiconductor layer or the IIB-VIA group semiconductor layer. (6) After growth is completed, the heating process of the three temperature zones is stopped at the same time, and the temperature is rapidly cooled to room temperature within 20 minutes under the protective gas flow, thus completing the construction of the semiconductor heterojunction.