An on-chip antenna impedance matching method and radar system

Abstract

The application discloses an on-chip antenna impedance matching method and a radar antenna, and belongs to the technical field of printed circuit manufacturing. The method mainly comprises the following steps: connecting a stake line with a predetermined depth and a predetermined length to a predetermined position of a packaging substrate and / or a core particle of an on-chip antenna; and using the stake line as an impedance matcher to perform impedance matching of the on-chip antenna. The application has the advantages of simple structure, direct integration in the chip, no need of complex external components, flexible design, compatibility with various types of chips, and better realization of impedance matching of the on-chip antenna.

Description

Technical Field

[0001] This application relates to the field of printed circuit manufacturing technology, and in particular to an on-chip antenna impedance matching method and a radar system. Background Technology

[0002] With the increasing application of millimeter-wave radar in industries such as automotive, drones, security, and sports, the demand for miniaturization is becoming increasingly stringent. As millimeter-wave radar is applied across various sectors, both simple printed circuit board antennas and radar products with externally machined metal parts for assembly are constraining the development of application scenarios.

[0003] Currently used printed circuit board (PCB) antennas suffer from limitations in supporting non-surface feeding structures. They are constrained by manufacturing processes such as the number of lamination cycles and aspect ratio. Furthermore, the feed lines and RF circuits of existing PCB antennas cannot be miniaturized. Assembling externally machined metal components is problematic because manufacturing errors amplify and worsen with increasing frequency, leading to quality instability. Moreover, with the application of millimeter-wave radar across various industries, both externally machined metal components and PCB hardware circuit and transmission line designs cannot meet the requirements for miniaturization and lightweighting. Additionally, both existing methods require complex transition structures to connect the die (DIE), but this transition process introduces significant losses, degrading the overall performance of the link. Summary of the Invention

[0004] To address the problem that existing technologies cannot simultaneously achieve miniaturization, lightweight design, and product quality, this application mainly provides an on-chip antenna impedance matching method and a radar system.

[0005] To achieve the above objectives, the first technical solution adopted in this application is: to provide an on-chip antenna impedance matching method, which includes: connecting stakes of predetermined depth and predetermined length at predetermined positions on the packaging substrate and / or core of the on-chip antenna; using the stakes as an impedance matching device to perform impedance matching of the on-chip antenna; wherein, based on the parameters of the on-chip antenna, the values ​​of the predetermined position, predetermined depth and predetermined length are obtained by simulation calculation.

[0006] Optionally, the on-chip antenna impedance matching method also includes: calculating the solder ball size corresponding to the stake line based on the parameters of the on-chip antenna using simulation, or calculating whether solder balls need to be configured; when configuring solder balls, using solder balls and stake lines to perform impedance matching of the on-chip antenna.

[0007] Optionally, the on-chip antenna impedance matching method further includes: using through-silicon via technology to connect stakes of predetermined depth and length at predetermined positions of at least two stacked chips, and using the stakes as impedance matching devices for on-chip antenna impedance matching.

[0008] Optionally, the on-chip antenna impedance matching method further includes: connecting stakes of predetermined depth and length at predetermined positions on the redistribution layer and the chip, and using the stakes as impedance matching devices for impedance matching of the on-chip antenna.

[0009] Optionally, the on-chip antenna impedance matching method further includes: connecting stakes of predetermined depth and predetermined length at predetermined positions of the power supply chip, digital processing chip, and RF front-end chip of the radar system, respectively, and calculating the values ​​of each predetermined position, predetermined position, and predetermined length based on the parameters of the radar system.

[0010] The second technical solution adopted in this application is: providing a radar system, comprising: a radar system clock for providing a clock signal to the radar system; an external device interface for connecting the radar system to external devices; a transmitting antenna and a receiving antenna for transmitting and receiving radar signals; a power supply chip with a first terminal line of a first predetermined depth and a first predetermined length connected at a first predetermined position; a digital processing chip with a second terminal line of a second predetermined depth and a second predetermined length connected at a second predetermined position; and a radio frequency front-end chip with a third terminal line of a third predetermined depth and a third predetermined length connected at a third predetermined position; wherein the radar system utilizes the first terminal line, the second terminal line, and the third terminal line to perform impedance matching of the radar system in coordination.

[0011] Optionally, the radar system also includes a module for calculating the solder ball size corresponding to the stake line based on the parameters of the on-chip antenna using simulation calculations, or calculating whether solder balls need to be configured, and using the solder balls and stake lines to perform impedance matching of the on-chip antenna when configuring solder balls.

[0012] Optionally, the radar system further includes a module for using through-silicon via (TSV) technology to insert stakes of predetermined depth and length at predetermined locations on at least two stacked power chips, digital processing chips, and / or RF front-end chips, and using the stakes as impedance matching devices for on-chip antenna impedance matching.

[0013] The beneficial effects that the technical solution of this application can achieve are: the on-chip radar system designed by on-chip antenna impedance matching can adapt to more customized requirements of application scenarios, the design means are rich and flexible, the antenna design can be made more convenient and efficient through custom adjustable impedance matching, and miniaturization and high integration design are well realized. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of a specific implementation of an on-chip antenna impedance matching method according to this application;

[0016] Figure 2 This is a schematic diagram of a specific embodiment of this application;

[0017] Figure 3 This is a schematic diagram of a specific embodiment of the chip stacking process described in this application;

[0018] Figure 4 This is a schematic diagram of another specific embodiment of this application;

[0019] Figure 5 This is a schematic diagram of a specific embodiment of a radar system according to this application.

[0020] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0021] The preferred embodiments of this application will now be described in detail with reference to the accompanying drawings, so that the advantages and features of this application can be more easily understood by those skilled in the art, thereby providing a clearer and more definite definition of the scope of protection of this application.

[0022] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0023] The technical solutions of this application and how they solve the aforementioned technical problems will be described in detail below with specific embodiments. The specific embodiments described below can be combined with each other to form new embodiments. The same or similar ideas or processes described in one embodiment may not be repeated in other embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0024] Figure 1 This paper illustrates one embodiment of an on-chip antenna impedance matching method according to this application.

[0025] Figure 1 The on-chip antenna impedance matching method shown includes: step S101, connecting stakes of predetermined depth and predetermined length at predetermined positions on the on-chip antenna packaging substrate and / or core chip;

[0026] Step S102 involves using a stake wire as an impedance matching device to perform impedance matching for the on-chip antenna. Specifically, based on the parameters of the on-chip antenna, the values ​​of a predetermined position, predetermined depth, and predetermined length are obtained through simulation calculations. This specific implementation achieves on-chip antenna impedance adjustment by employing an easily adjustable metal hole on the chip. This method has a simple structure, is easy to integrate within the chip, requires no complex external components, offers greater design flexibility, and is compatible with various chip stacking processes.

[0027] In one specific embodiment of this application, the on-chip antenna impedance matching method further includes: calculating the solder ball size corresponding to the stud wire based on the parameters of the on-chip antenna using simulation, or calculating whether solder balls need to be configured; when configuring solder balls, using solder balls and stud wires to perform impedance matching of the on-chip antenna. This specific embodiment, by using solder joints pre-reserved on the top surface of the package corresponding to the metal vias and solder balls of different sizes soldered onto the solder joints, assists the stud wires in adjusting the on-chip antenna impedance, resulting in better adjustment performance.

[0028] Specifically, any antenna or equivalent transmission line design must ensure impedance matching throughout the entire transmission line link; otherwise, reflections will occur, directly affecting the entire transmission system and preventing it from meeting product design specifications. In severe cases of reflection, it can even cause the system to malfunction. As the high-frequency component of a radar system, the antenna has extremely strict impedance matching requirements. Theoretically, the antenna's VSWR (Standing Wave Ratio) should be equal to 1, but due to practical limitations, the design must make the VSWR as close to 1 as possible. When designing antennas, it is desirable for all high-frequency energy to be radiated by the antenna without energy reflection loss; all impedance matching adjustment methods aim to achieve this goal. To ensure that more high-frequency energy is radiated by the antenna and less energy is lost due to reflection, the commonly used method is through a metal waveguide pin matching structure. This method requires the additional assembly of externally machined metal parts to complete the impedance matching of the entire transmission path. This method requires a complex transition structure, which cannot meet the requirements for miniaturization and lightweight antenna systems. Another common approach is to achieve impedance matching of the entire antenna system's transmission path by combining hardware circuitry on the PCB with PCB transmission lines. However, this method has low precision, inflexible design, and cannot effectively support off-plane feeding structures. It is limited by the number of PCB lamination cycles, aspect ratio, and the material of the high-frequency board. Furthermore, it requires additional hardware circuitry to support and adjust the link impedance matching, which means more circuit modules, more components, larger dimensions, and higher BOM (Bill of Materials) costs.

[0029] Based on this, this application proposes an on-chip antenna impedance matching method. This method performs impedance matching of the antenna directly on the dielectric wafer, and then integrates the dielectric wafer into an on-chip radar system to form a radar system that meets the requirements of miniaturization and lightweighting. Furthermore, the method proposed in this application can continuously reduce the error between the actual circuit and the design simulation as the precision of chip integration manufacturing process improves, thus better matching the original design and ensuring antenna performance. When designing the antenna, this method first calculates parameters such as the installation position of the stud wire on the packaging substrate, the chip, or both, the installation depth of the stud wire, and the length of the stud wire in the simulation software according to the designed antenna parameters. This calculation process requires the simulation software to calculate the optimal matching value of position, depth, and height based on the required antenna process parameters and requirements. After obtaining the relevant parameters, the on-chip antenna is manufactured according to these parameters, so that the antenna, based on the insertion depth and position of the stud wire, the corresponding solder ball size and presence, and the impedance of the load itself, matches the characteristic impedance of the antenna with that of the entire transmission line. The studs configured in this on-chip antenna configuration are equivalent to inductors or capacitors, forming reactance. By adjusting the insertion depth and position of the studs, as well as the presence and size of the corresponding solder balls, the reactance can be flexibly adjusted, forming a formal impedance matching device. The presence of solder balls is not mandatory; their necessity is determined based on antenna performance calculations.

[0030] For example, Figure 2 This is a schematic diagram of a specific embodiment of this application. Figure 2 As shown, there are two ways to insert the pins into the metal holes: one is to insert the pins into the package substrate for antenna impedance matching, and the other is to insert the pins into the core chip for antenna impedance matching. These two methods can be used individually or in combination. When using them, simply configure the corresponding position and depth parameters for each method to achieve impedance matching. For example, with a PCB board thickness of 1.6mm and a substrate thickness of 100μm, the pin insertion depth into the package substrate can be 25μm, and the hole diameter can be 120μm; the pin insertion depth into the core chip can be 10μm, and the hole diameter can be 64μm. The solder ball height at the top of the pin can be 10μm; the diameter of the solder ball connecting the core chip and the package substrate can be 10μm, and the DIE thickness between the solder ball and the core chip can be 60μm; the package height of the package substrate, core chip, and corresponding solder ball can be 400μm; and the solder ball height between the package substrate and the PCB board can be 100μm.

[0031] In one specific embodiment of this application, the on-chip antenna impedance matching method further includes: using a through-silicon via process to connect stakes of predetermined depth and predetermined length at predetermined positions of at least two stacked chips, and using the stakes as impedance matching devices to perform impedance matching of the on-chip antenna.

[0032] Specifically, Figure 3 This is a schematic diagram of a specific embodiment of the chip stacking process described in this application. Figure 3 As shown, through-silicon via (TSV) technology is used to penetrate at least two wafers at predetermined locations, and a stake wire is inserted into the through-hole to form the required stake wire. This stake wire is then used as an impedance matching device for on-chip antenna impedance matching. Simultaneously, it can be used in conjunction with a method of inserting the stake wire into the packaging substrate for impedance matching to achieve better matching results.

[0033] In one specific embodiment of this application, the on-chip antenna impedance matching method further includes: connecting stake lines of predetermined depth and predetermined length at predetermined positions on the redistribution layer and the chip, and using the stake lines as impedance matching devices to perform impedance matching of the on-chip antenna.

[0034] Specifically, this application can be flexibly applied to printed circuit boards with various design methods. Figure 4 This is a schematic diagram of another specific embodiment of this application, as shown below. Figure 4 As shown, the redistribution layer enables rewiring during antenna design, allowing for more antenna design possibilities. This application supports inserting staked wires into the redistribution layer for impedance matching. Furthermore, the usage of this application is not limited to... Figures 2-4 The flip-chip packaging shown, including bonding packaging, lead frame packaging, or a combination of these, is applicable to the on-chip antenna impedance matching method provided in this application.

[0035] In one specific embodiment of this application, the on-chip antenna impedance matching method further includes: connecting stakes of predetermined depth and predetermined length at predetermined positions of the power supply chip, digital processing chip and radio frequency front-end chip of the radar system, respectively, and calculating the values ​​of each predetermined position, predetermined position and predetermined length based on the parameters of the radar system.

[0036] Specifically, the values ​​of each predetermined position, predetermined length, and predetermined length are obtained through simulation calculations based on the parameters of the radar system. Based on the calculated values, the corresponding predetermined positions, predetermined lengths, and predetermined lengths on the power supply chip, digital processing chip, and RF front-end chip are coordinated, along with whether solder balls need to be configured and the size of the configured solder balls, so that the radar system can better perform impedance matching. It is not restricted that all three types of chips must be configured with pins; the specific configuration method and number of pins are determined based on the parameter requirements and simulation structure of the radar system.

[0037] Figure 5 An embodiment of a radar system according to this application is shown.

[0038] Figure 5The radar system shown includes: a radar system clock, which is used to provide a clock signal to the radar system;

[0039] External device interface, which is used to connect the radar system to external devices;

[0040] Transmitting and receiving antennas are used for transmitting and receiving radar signals;

[0041] A power chip, wherein a first stake wire of a first predetermined depth and a first predetermined length is connected to a first predetermined position;

[0042] A digital processing core, wherein a second stake line of a second predetermined depth and a second predetermined length is connected at a second predetermined position; and

[0043] The radio frequency front-end chip has a third stake wire with a third predetermined depth and a third predetermined length connected to its third predetermined position; wherein, the radar system uses the first stake wire, the second stake wire and the third stake wire to cooperate in impedance matching of the radar system.

[0044] In one specific embodiment of this application, the radar system further includes: a module for calculating the size of the solder ball corresponding to the stake line based on the parameters of the on-chip antenna using simulation calculation, or calculating whether solder balls need to be configured, and using the solder balls and stake lines to perform impedance matching of the on-chip antenna when configuring solder balls.

[0045] In one specific embodiment of this application, the radar system further includes: a module for using through-silicon via (TSV) technology to connect stakes of predetermined depth and length at predetermined positions on stacked power chips, digital processing chips, and / or radio frequency front-end chips, and using the stakes as impedance matching devices for impedance matching of the on-chip antenna.

[0046] The radar system provided in this application can be used to execute the on-chip antenna impedance matching method described in any of the above embodiments. Its implementation principle and technical effect are similar, and will not be repeated here.

[0047] In the several embodiments provided in this application, it should be understood that the disclosed methods can be implemented in other ways. For example, the method embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0048] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An on-chip antenna impedance matching method, characterized in that, include: Insert stakes of predetermined depth and length at predetermined positions on the packaging substrate and / or core of the on-chip antenna; The pile wire is used as an impedance matching device to perform impedance matching of the on-chip antenna; Specifically, based on the parameters of the on-chip antenna, the values ​​of the predetermined position, the predetermined depth, and the predetermined length are obtained through simulation calculations.

2. The on-chip antenna impedance matching method according to claim 1, characterized in that, Also includes: Based on the parameters of the on-chip antenna, the size of the solder ball corresponding to the stake line is obtained by simulation calculation, or whether solder balls need to be configured is calculated. When configuring the solder balls, impedance matching of the on-chip antenna is performed using the solder balls and the stud wires.

3. The on-chip antenna impedance matching method according to claim 1, characterized in that, Also includes: Using through-silicon via (TSV) technology, stake lines of predetermined depth and length are connected at predetermined positions on at least two stacked wafers, and the stake lines are used as impedance matching devices for impedance matching of the on-chip antenna.

4. The on-chip antenna impedance matching method according to claim 1, characterized in that, Also includes: A stud wire of predetermined depth and predetermined length is inserted at a predetermined position on the redistribution layer and the core, and the stud wire is used as an impedance matching device to perform impedance matching of the on-chip antenna.

5. The on-chip antenna impedance matching method according to claim 1, characterized in that, Also includes: Stakes of predetermined depth and length are installed at predetermined positions in the power supply core, digital processing core, and radio frequency front-end core of the radar system, respectively, and the values ​​of each predetermined position, the predetermined position, and the predetermined length are calculated based on the parameters of the radar system.

6. A radar system, characterized in that, include: The radar system clock is used to provide clock signals to the radar system. External device interface, which is used to connect the radar system to external devices; Transmitting and receiving antennas are used for transmitting and receiving radar signals; A power chip, wherein a first stake wire of a first predetermined depth and a first predetermined length is connected to a first predetermined position; A digital processing core, wherein a second stake line of a second predetermined depth and a second predetermined length is connected at a second predetermined position; as well as The radio frequency front-end chip has a third stake wire with a third predetermined depth and a third predetermined length connected to its third predetermined position; The radar system utilizes the first stake line, the second stake line, and the third stake line to perform impedance matching.

7. The radar system according to claim 6, characterized in that, Also includes: This module is used to calculate the solder ball size corresponding to the stud wire based on the parameters of the on-chip antenna, or to calculate whether solder balls need to be configured, and to perform impedance matching of the on-chip antenna using the solder balls and the stud wire when configuring the solder balls.

8. The radar system according to claim 6, characterized in that, Also includes: A module for using through-silicon via (TSV) technology to insert stakes of predetermined depth and length at predetermined positions on at least two stacked power chips, digital processing chips, and / or RF front-end chips, and to use the stakes as impedance matching devices for on-chip antenna impedance matching.

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