A multi-core SSD non-4k alignment writing method, system, device and storage medium

Abstract

The present application relates to the technical field of data processing, in particular to a method, system and device for optimizing non-4k alignment writing of multi-core SSD and a storage medium. The method comprises receiving host data, locking the received host data according to the minimum 4k granularity, and if the host data is non-4k alignment writing, marking the corresponding memory cache after the locking is successful. After the non-4k alignment writing host data is moved to the 4k memory cache of the SSD, the flash memory position data corresponding to the host data is modified as CACHE_DM. Whether the host data less than 4K has a relationship with other memory spaces is determined according to the flash memory position data, and the host data is processed. The host data is unlocked to release resources. The non-4k alignment writing host data is sequentially subjected to 4k granularity locking, updating of the flash memory position data and unlocking operation. The context of the business application for writing the flash memory is obtained, and the memory cache data is written into the flash memory.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to an optimized method, system, device, and storage medium for non-4k aligned writes of multi-core SSDs. Background Technology

[0002] Currently, SSD firmware write operations are performed by the FTL module mapping LBAs in 4k granularity. When a multi-core SSD is formatted to 512 bytes (i.e., one LBA corresponds to 512 bytes of data), FTL faces two situations:

[0003] (1) The data length written at one time is 4k aligned and the starting LBA is divisible by 8 (e.g., bs = 4096, s_lba = 0).

[0004] (2) The length of the data written at one time is not 4k aligned, or the starting LBA is not divisible by 8 (e.g., bs = 1024, s_lba = 1).

[0005] In case (1), FTL will directly write each piece of data to the flash in 4k granularity.

[0006] In scenario (2), the situation becomes more complex because each newly received write data entry may not fill the entire 4k memory space. Therefore, it is necessary to first determine whether there is valid data in the unfilled position corresponding to the old 4k flash memory or memory space. If so, the data in the unfilled position corresponding to the old 4k flash memory or memory space needs to be read first, and then combined with the data to be written to form a complete 4k block, ready to be written to the new location in the flash. At the same time, if there is valid data in the unfilled position corresponding to the old memory space, the processing method for this memory space is the same as that for ordinary memory space, following the subsequent flash write process. This is because after the operation of writing the newly combined data to the new location in the flash is completed, the PBA value will be updated to the new flash location, and the data from the old memory space written to the flash location will not take effect. However, writing both the old and new memory space data to the flash will result in write amplification and write performance issues. To solve this technical problem, an optimized method, system, device, and storage medium for non-4k aligned writing of multi-core SSDs is proposed. Summary of the Invention

[0007] In order to solve the technical problems existing in the prior art, the present invention provides an optimized method, system, device and storage medium for non-4k aligned write of multi-core SSDs.

[0008] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0009] In a first aspect, in one embodiment of the present invention, an optimized method for non-4k aligned write operations to multi-core SSDs is provided, the method comprising the following steps:

[0010] Receive host data and lock the received host data with a minimum 4k granularity. If the host data is not 4k aligned after successful locking, mark the corresponding memory cache.

[0011] After moving the non-4k aligned host data to the SSD's 4k memory cache, modify the flash memory location data corresponding to the host data to CACHE_DM;

[0012] Based on the flash memory location data, determine whether the less than 4K of host data is related to other memory spaces, and process the host data accordingly;

[0013] Unlock the host data to release resources; for the host data that is not written with 4k alignment, perform 4k-granular locking, update flash memory location data and unlock operations in sequence.

[0014] The application requests a context to write to flash memory and writes the memory cache data to flash memory.

[0015] As a further aspect of the present invention, the step of determining whether the less than 4KB of host data is related to other memory spaces based on flash memory location data, and processing the host data, includes:

[0016] If the flash memory location data is equal to CACHE_DM, then move the valid data in the current memory cache to the corresponding location in other memory spaces;

[0017] If the flash memory location data equals a valid flash memory location, then the data at the corresponding flash memory location is read into the corresponding location in the buffer;

[0018] If the flash location data is not equal to CACHE_WM, the host data write processing context is added to the polling list, waiting for the flash location data to be changed to a valid flash location before processing.

[0019] As a further aspect of the present invention, before sequentially performing 4k-granular locking, flash memory location data update, and unlocking operations on the non-4k aligned host data, the following steps are also included:

[0020] By checking whether the memory cache corresponding to the host data is marked, it can be determined whether the host data is non-4k aligned write data.

[0021] As a further aspect of the present invention, for the host data written without 4k alignment, 4k-granular locking, flash memory location data update, and unlocking operations are performed sequentially, including:

[0022] If the host data is written in 4k alignment, then no 4k-granular locking, flash memory location data update, or unlocking operations will be performed.

[0023] As a further aspect of the present invention, the service request writes the flash memory context and writes memory cache data to the flash memory, and then further includes:

[0024] Update the flash memory location data to a valid flash memory location.

[0025] As a further aspect of the present invention, updating the flash memory location data to a valid flash memory location includes:

[0026] The memory cache data written to flash memory is locked at a 4k granularity. After successful locking, the flash memory location data is updated to the valid flash memory location, and then the memory cache data is unlocked.

[0027] Secondly, in another embodiment provided by the present invention, an optimized multi-core SSD non-4k aligned write system is provided, the system comprising: a data processing module and a write module;

[0028] The data processing module is used to receive host data, lock the received host data in a minimum 4k granularity, and after successful locking, if the host data is not 4k aligned, mark the corresponding memory cache; after moving the non-4k aligned host data to the SSD's 4k memory cache, modify the flash memory location data corresponding to the host data to CACHE_DM; based on the flash memory location data, determine whether the less than 4K host data is related to other memory spaces, process the host data accordingly, and unlock the host data.

[0029] The writing module is used to receive the unlocked host data sent by the data processing module, and for the non-4k aligned host data, perform 4k granular locking, flash memory location data update and unlocking operations in sequence; the service requests the context for writing to the flash memory and writes the memory cache data to the flash memory.

[0030] As a further aspect of the present invention, the data processing module is also used to move the valid data in the current buffer to the corresponding location in other memory spaces if the flash memory location data is equal to CACHE_DM.

[0031] If the flash memory location data is equal to the valid flash memory location, then the data at the corresponding location of the flash memory is read into the corresponding location in the buffer, and the buffer is sent to the write module;

[0032] If the flash location data is not equal to CACHE_WM, the host data write processing context is added to the polling list, waiting for the next flash location data to be written to the module to change to a valid flash location before processing.

[0033] Thirdly, in another embodiment of the present invention, a device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor loads and executes the computer program to implement the steps of optimizing the non-4k aligned write method of a multi-core SSD.

[0034] Fourthly, in another embodiment provided by the present invention, a storage medium is provided storing a computer program, which, when loaded and executed by a processor, implements the steps of the optimized multi-core SSD non-4k aligned write method.

[0035] The technical solution provided by this invention has the following beneficial effects:

[0036] This invention provides an optimized method, system, device, and storage medium for non-4k aligned writes to multi-core SSDs. The method involves receiving host data and locking it at a minimum 4k granularity. Upon successful locking, if the host data is non-4k aligned, the corresponding memory cache is marked. The non-4k aligned host data is moved to the SSD's 4k memory cache, and the corresponding flash memory location data is modified to CACHE_DM. The flash memory location data is used to determine if the less than 4K host data is related to other memory spaces, and the host data is processed accordingly. The host data is then unlocked to release resources. For the non-4k aligned host data, 4k granular locking, updating the flash memory location data, and unlocking operations are performed sequentially. The application requests a context for writing to flash memory and writes the memory cache data to the flash memory. When a non-4k aligned write operation finds that the 4k location to be written already contains valid data in another memory space, the invention directly moves the data to be written to that memory space and terminates the current write operation. This reduces the number of write operations to the current memory space, theoretically reducing write amplification and improving write performance. This invention also utilizes mutexes to resolve timing dependencies in non-4k aligned writes between multiple cores.

[0037] These or other aspects of the invention will become more apparent from the following description of embodiments. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a flowchart illustrating an embodiment of the optimized non-4k aligned write method for multi-core SSDs according to the present invention.

[0040] Figure 2 This is a block diagram of an optimized multi-core SSD non-4k aligned write system according to an embodiment of the present invention.

[0041] Figure 3 This is a structural block diagram of a device according to an embodiment of the present invention.

[0042] In the diagram: Data processing module-100, writing module-200, processor-301, communication interface-302, memory-303, communication bus-304. Detailed Implementation

[0043] Various embodiments and / or forms are described below with reference to the accompanying drawings. In the following description, numerous specific details are disclosed for illustrative purposes to provide a general understanding of more than one form. However, those skilled in the art will understand that these forms can be implemented without specific details. Specific examples of more than one form will be described in detail in the following description and drawings. However, these forms are merely illustrative and may utilize a portion of the principles and methods of various forms; the descriptions are intended to encompass all forms and their equivalents. Specifically, the terms "embodiment," "example," "form," "illustration," etc., as used in this specification can be interpreted as meaning that any form or design described may be better or more advantageous than other forms or designs.

[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0046] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0047] Specifically, the embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0048] Please see Figure 1 , Figure 1 This is a flowchart of an optimized non-4k aligned write method for multi-core SSDs provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the optimized multi-core SSD non-4k aligned write method includes steps S10 to S50.

[0049] S10. Receive host data and lock the received host data with a minimum 4k granularity. If the host data is not 4k aligned after successful locking, mark the corresponding memory cache.

[0050] S20. After moving the non-4k aligned host data to the SSD's 4k memory cache, modify the flash memory location data corresponding to the host data to CACHE_DM, where CACHE_DM is a constant.

[0051] S30. Based on the flash memory location data, determine whether the less than 4K host data is related to other memory spaces, and process the host data.

[0052] In an embodiment of the present invention, the step of determining whether the less than 4KB of host data is related to other memory spaces based on flash memory location data, and processing the host data, includes:

[0053] If the flash memory location data is equal to CACHE_DM, then move the valid data in the current memory cache to the corresponding location in other memory spaces;

[0054] If the flash memory location data equals a valid flash memory location, then the data at the corresponding flash memory location is read into the corresponding location in the buffer;

[0055] If the flash memory location data is not equal to CACHE_WM, the host data write processing context is added to the polling list, waiting for the flash memory location data to be changed to a valid flash memory location before processing. This allows a non-4k aligned write operation to directly move the data to be written to that memory space and end the write operation when a valid 4k location already exists in another memory space.

[0056] S40. Unlock the host data and release resources; for the host data that is not written in 4k alignment, perform 4k-granular locking, flash memory location data update and unlocking operations in sequence.

[0057] Before writing the host data that is not 4k aligned, the following steps are performed sequentially: 4k-granular locking, updating flash memory location data, and unlocking.

[0058] By checking whether the memory cache corresponding to the host data is marked, it can be determined whether the host data is non-4k aligned write data.

[0059] In an embodiment of the present invention, for the host data that is not 4k aligned, 4k-granularity locking, flash memory location data updating, and unlocking operations are performed sequentially, including:

[0060] If the host data is written in 4k alignment, then no 4k-granular locking, flash memory location data update, or unlocking operations will be performed.

[0061] S50: The service requests a context to write to the flash memory and writes the memory cache data to the flash memory.

[0062] The service request writes the flash memory context and writes memory cache data to the flash memory, and then includes:

[0063] Update the flash memory location data to a valid flash memory location.

[0064] In an embodiment of the present invention, updating the flash memory location data to a valid flash memory location includes:

[0065] The memory cache data written to flash memory is locked at a 4k granularity. After successful locking, the flash memory location data is updated to the valid flash memory location, and then the memory cache data is unlocked.

[0066] It should be noted that the following are the definitions of abbreviations and key terms used in this application:

[0067] SSD: Solid State Drive

[0068] FTL: Flash Translation Layer, which maps host logical addresses to flash physical addresses.

[0069] LBA: Logical Host Address

[0070] bs: Block size, the size of the data block corresponding to each read / write operation.

[0071] PBA: Contains detailed flash memory location information, and generally corresponds one-to-one with LBA.

[0072] This invention addresses the issue where, during a non-4k aligned write operation, if valid data already exists at the 4k position of the current write location in another memory space, the data to be written is directly moved to that memory space, and the write operation ends. This reduces the number of write operations to that memory space, theoretically lowering write amplification and improving write performance. Furthermore, this invention utilizes mutexes to resolve timing dependencies in non-4k aligned writes between multiple cores.

[0073] It should be understood that although the above description follows a certain order, these steps are not necessarily executed in that order. Unless otherwise expressly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, some steps in this embodiment may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least a portion of the steps or stages in other steps.

[0074] In one embodiment, see Figure 2 As shown, an optimized multi-core SSD non-4k aligned write system is also provided in an embodiment of the present invention, the system including a data processing module 100 and a write module 200.

[0075] The data processing module 100 is used to receive host data, lock the received host data in a minimum 4k granularity, and after successful locking, if the host data is not 4k aligned, mark the corresponding memory cache; after moving the non-4k aligned host data to the SSD's 4k memory cache, modify the flash memory location data corresponding to the host data to CACHE_DM; based on the flash memory location data, determine whether the less than 4K host data is related to other memory spaces, process the host data accordingly, and unlock the host data.

[0076] In an embodiment of the present invention, the data processing module 100 is further configured to move the valid data in the current buffer to the corresponding location in other memory spaces if the flash memory location data is equal to CACHE_DM.

[0077] If the flash memory location data is equal to the valid flash memory location, then the data at the corresponding location of the flash memory is read into the corresponding location in the buffer, and the buffer is sent to the write module 200;

[0078] If the flash memory location data is not equal to CACHE_WM, the host data write processing context is added to the polling list, waiting for the next flash memory location data to be written to module 200 to be changed to a valid flash memory location before processing.

[0079] The writing module 200 is used to receive the unlocked host data sent by the data processing module 100, and for the non-4k aligned host data, sequentially perform 4k granular locking, flash memory location data update and unlocking operations; the service requests the context for writing to flash memory and writes memory cache data to flash memory; and updates the flash memory location data to a valid flash memory location.

[0080] This invention addresses the issue where, during a non-4k aligned write operation, if valid data already exists at the 4k position of the current write location in another memory space, the data to be written is directly moved to that memory space, and the write operation ends. This reduces the number of write operations to that memory space, theoretically lowering write amplification and improving write performance. Furthermore, this invention utilizes mutexes to resolve timing dependencies in non-4k aligned writes between multiple cores.

[0081] In one embodiment, see Figure 3 As shown, an embodiment of the present invention also provides a device, including a processor 301, a communication interface 302, a memory 303 and a communication bus 304, wherein the processor 301, the communication interface 302 and the memory 303 communicate with each other through the communication bus 304.

[0082] Memory 303 is used to store computer programs;

[0083] When processor 301 executes the computer program stored in memory 303, it executes the optimized multi-core SSD non-4k aligned write method described above. When executing instructions, the processor implements the steps in the above method embodiment:

[0084] S10. Receive host data and lock the received host data with a minimum 4k granularity. If the host data is not 4k aligned after successful locking, mark the corresponding memory cache.

[0085] S20. After moving the non-4k aligned host data to the SSD's 4k memory cache, modify the flash memory location data corresponding to the host data to CACHE_DM, where CACHE_DM is a constant.

[0086] S30. Based on the flash memory location data, determine whether the less than 4K host data is related to other memory spaces, and process the host data.

[0087] In an embodiment of the present invention, the step of determining whether the less than 4KB of host data is related to other memory spaces based on flash memory location data, and processing the host data, includes:

[0088] If the flash memory location data is equal to CACHE_DM, then move the valid data in the current memory cache to the corresponding location in other memory spaces;

[0089] If the flash memory location data equals a valid flash memory location, then the data at the corresponding flash memory location is read into the corresponding location in the buffer;

[0090] If the flash memory location data is not equal to CACHE_WM, the host data write processing context is added to the polling list, waiting for the flash memory location data to be changed to a valid flash memory location before processing. This allows a non-4k aligned write operation to directly move the data to be written to that memory space and end the write operation when a valid 4k location already exists in another memory space.

[0091] S40. Unlock the host data and release resources; for the host data that is not written in 4k alignment, perform 4k-granular locking, flash memory location data update and unlocking operations in sequence.

[0092] Before writing the host data that is not 4k aligned, the following steps are performed sequentially: 4k-granular locking, updating flash memory location data, and unlocking.

[0093] By checking whether the memory cache corresponding to the host data is marked, it can be determined whether the host data is non-4k aligned write data.

[0094] In an embodiment of the present invention, for the host data that is not 4k aligned, 4k-granularity locking, flash memory location data updating, and unlocking operations are performed sequentially, including:

[0095] If the host data is written in 4k alignment, then no 4k-granular locking, flash memory location data update, or unlocking operations will be performed.

[0096] S50: The service requests a context to write to the flash memory and writes the memory cache data to the flash memory.

[0097] The service request writes the flash memory context and writes memory cache data to the flash memory, and then includes:

[0098] Update the flash memory location data to a valid flash memory location.

[0099] In an embodiment of the present invention, updating the flash memory location data to a valid flash memory location includes:

[0100] The memory cache data written to flash memory is locked at a 4k granularity. After successful locking, the flash memory location data is updated to the valid flash memory location, and then the memory cache data is unlocked.

[0101] This invention addresses the issue where, during a non-4k aligned write operation, if valid data already exists at the 4k position of the current write location in another memory space, the data to be written is directly moved to that memory space, and the write operation ends. This reduces the number of write operations to that memory space, theoretically lowering write amplification and improving write performance. Furthermore, this invention utilizes mutexes to resolve timing dependencies in non-4k aligned writes between multiple cores.

[0102] The communication bus mentioned in the above terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0103] The communication interface is used for communication between the aforementioned terminal and other devices.

[0104] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0105] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0106] The device includes user equipment and network equipment. The user equipment includes, but is not limited to, computers, smartphones, and PDAs. The network equipment includes, but is not limited to, a single network server, a server group consisting of multiple network servers, or a cloud based on cloud computing, which is a type of distributed computing consisting of a super virtual computer composed of a group of loosely coupled computers. The device can operate independently to implement the invention, or it can connect to a network and interact with other devices within the network to implement the invention. The network in which the device operates includes, but is not limited to, the Internet, wide area networks (WANs), metropolitan area networks (MANs), local area networks (LANs), and VPN networks.

[0107] It should also be understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0108] In one embodiment of the present invention, a storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the steps in the above method embodiments:

[0109] S10. Receive host data and lock the received host data with a minimum 4k granularity. If the host data is not 4k aligned after successful locking, mark the corresponding memory cache.

[0110] S20. After moving the non-4k aligned host data to the SSD's 4k memory cache, modify the flash memory location data corresponding to the host data to CACHE_DM, where CACHE_DM is a constant.

[0111] S30. Based on the flash memory location data, determine whether the less than 4K host data is related to other memory spaces, and process the host data.

[0112] In an embodiment of the present invention, the step of determining whether the less than 4KB of host data is related to other memory spaces based on flash memory location data, and processing the host data, includes:

[0113] If the flash memory location data is equal to CACHE_DM, then move the valid data in the current memory cache to the corresponding location in other memory spaces;

[0114] If the flash memory location data equals a valid flash memory location, then the data at the corresponding flash memory location is read into the corresponding location in the buffer;

[0115] If the flash memory location data is not equal to CACHE_WM, the host data write processing context is added to the polling list, waiting for the flash memory location data to be changed to a valid flash memory location before processing. This allows a non-4k aligned write operation to directly move the data to be written to that memory space and end the write operation when a valid 4k location already exists in another memory space.

[0116] S40. Unlock the host data and release resources; for the host data that is not written in 4k alignment, perform 4k-granular locking, flash memory location data update and unlocking operations in sequence.

[0117] Before writing the host data that is not 4k aligned, the following steps are performed sequentially: 4k-granular locking, updating flash memory location data, and unlocking.

[0118] By checking whether the memory cache corresponding to the host data is marked, it can be determined whether the host data is non-4k aligned write data.

[0119] In an embodiment of the present invention, for the host data that is not 4k aligned, 4k-granularity locking, flash memory location data updating, and unlocking operations are performed sequentially, including:

[0120] If the host data is written in 4k alignment, then no 4k-granular locking, flash memory location data update, or unlocking operations will be performed.

[0121] S50: The service requests a context to write to the flash memory and writes the memory cache data to the flash memory.

[0122] The service request writes the flash memory context and writes memory cache data to the flash memory, and then includes:

[0123] Update the flash memory location data to a valid flash memory location.

[0124] In an embodiment of the present invention, updating the flash memory location data to a valid flash memory location includes:

[0125] The memory cache data written to flash memory is locked at a 4k granularity. After successful locking, the flash memory location data is updated to the valid flash memory location, and then the memory cache data is unlocked.

[0126] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Furthermore, any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include at least one of non-volatile and volatile memory.

[0127] It should be understood that, as used herein, the singular form "a" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the associatedly listed items. The embodiment numbers disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0128] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A non-4k aligned write method for multi-core SSDs, characterized in that, The method includes: Receive host data and lock the received host data with a minimum 4k granularity. If the host data is not 4k aligned after successful locking, mark the corresponding memory cache. After moving the non-4k aligned host data to the SSD's 4k memory cache, modify the flash memory location data corresponding to the host data to CACHE_DM; Based on the flash memory location data, determine whether the less than 4KB of host data is related to other memory spaces, and process the host data accordingly. This includes: if the flash memory location data is equal to CACHE_DM, move the valid data in the current memory cache to the corresponding location in other memory spaces; if the flash memory location data is equal to a valid flash memory location, read the data at the corresponding location in the flash memory into the corresponding location in the buffer; if the flash memory location data is not equal to CACHE_WM, add the host data to the polling list in the writing context, waiting for the flash memory location data to be changed to a valid flash memory location before processing. Unlock the host data and release resources; For the host data that is not written in 4k alignment, perform 4k-granular locking, flash memory location data update, and unlocking operations in sequence; After the business requests a context to write to the flash memory and writes the memory cache data to the flash memory, it updates the flash memory location data to a valid flash memory location. This includes: locking the memory cache data written to the flash memory at a 4k granularity, and after successful locking, updating the flash memory location data to a valid flash memory location and unlocking the memory cache data.

2. The multi-core SSD non-4k aligned write method as described in claim 1, characterized in that, Before writing the host data that is not 4k aligned, the following steps are performed sequentially: 4k-granular locking, updating flash memory location data, and unlocking. By checking whether the memory cache corresponding to the host data is marked, it can be determined whether the host data is non-4k aligned write data.

3. The multi-core SSD non-4k aligned write method as described in claim 1, characterized in that, For the host data written without 4k alignment, perform 4k-granular locking, flash memory location data update, and unlocking operations sequentially, including: If the host data is written in 4k alignment, then no 4k-granular locking, flash memory location data update, or unlocking operations will be performed.

4. A multi-core SSD non-4k aligned write system, characterized in that, The system includes: a data processing module and a writing module; The data processing module is used to receive host data, lock the received host data in a minimum 4k granularity, and after successful locking, if the host data is not 4k aligned, mark the corresponding memory cache; after moving the non-4k aligned host data to the SSD's 4k memory cache, modify the flash memory location data corresponding to the host data to CACHE_DM; based on the flash memory location data, determine whether the less than 4K host data is related to other memory spaces, process the host data accordingly, and unlock the host data. The writing module is used to receive the unlocked host data sent by the data processing module, and for the non-4k aligned host data, perform 4k-granular locking, flash memory location data update and unlocking operations in sequence; the service requests the context for writing to flash memory and writes the memory cache data to flash memory; The data processing module is further configured to: if the flash memory location data is equal to CACHE_DM, move the valid data in the current buffer to the corresponding location in other memory spaces; if the flash memory location data is equal to a valid flash memory location, read the data at the corresponding location in the flash memory into the corresponding location in the buffer, and send the buffer to the write module; if the flash memory location data is not equal to CACHE_WM, add the host data write processing context to the polling list, and wait for the next flash memory location data to be changed to a valid flash memory location by the write module before processing. The writing module is also used to update the flash memory location data to a valid flash memory location; lock the memory cache data written to the flash memory at a 4k granularity, and after successful locking, update the flash memory location data to a valid flash memory location and unlock the memory cache data.

5. A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor loads and executes the computer program to implement the steps of the multi-core SSD non-4k aligned write method as described in any one of claims 1-3.

6. A storage medium storing a computer program, which, when loaded and executed by a processor, implements the steps of the multi-core SSD non-4k aligned write method as described in any one of claims 1-3.

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