A hardware acceleration system and method applied to trim update processing of an SSD

Abstract

This invention provides a hardware acceleration system and method for Trim update processing in SSDs, belonging to the field of data management and main control chip technology for non-volatile storage media. It includes a controller, a base address register, a storage address calculation unit, an address buffer FIFO, a Trim update unit, a mapping buffer FIFO, and a valid bit update unit. This invention implements Trim update processing in hardware. During the Trim process, the hardware performs processing in real time without foreground or background processes. After the SSD is powered off, only the unprocessed Trim instructions need to be saved, and execution continues after power-on reconstruction. Because the amount of Trim instructions saved is minimal, this improves the speed of saving data after power failure and avoids saving failures due to excessive data volume during power failure. In summary, this invention helps improve the operating efficiency and security of SSDs.

Description

Technical Field

[0001] This invention relates to a hardware acceleration system and method for Trim update processing of SSDs, belonging to the field of data management and controller chip technology for non-volatile storage media. Background Technology

[0002] Solid-state drives (SSDs) are a type of flash memory-based storage technology. SSDs used in computer systems require relatively low latency and high capacity. SSDs utilize multi-channel, parallel methods to read and write data, improving the speed of sequential read and write operations. SSDs use non-volatile memory cells (such as NAND flash cells) to store data. If data has already been written to a non-volatile memory cell, it must be erased before new data can be written; a direct overwrite operation cannot be performed on the original non-volatile cell location. SSD write operations can be implemented according to different mapping granularities, but erase operations are generally performed on a block basis. If an SSD performs an overwrite operation on a page, it needs to read all the data in the block containing that page into a buffer, then erase that data block, write the page to be overwritten into the block in the buffer, and then rewrite the data block in the buffer that has undergone the overwrite operation into the erased data block or other available data blocks. Computer systems need a mechanism to notify SSDs of deletion operations, allowing the SSD to preemptively clear invalid data deleted by the operating system, i.e., clear the mapping relationships of deleted data, ensuring that the SSD's read and write performance does not degrade. This mechanism is usually the Trim or Unmap command. The Trim mechanism informs the SSD of invalid data marked by the operating system. Once the SSD is aware of the invalid data, it can discard invalid data during garbage collection (GC), reducing data movement operations.

[0003] like Figure 1 As shown, the host sends commands to the SSD via a communication interface. Upon receiving the command, the SSD's processor executes the corresponding operation through the flash translation layer. The storage media control unit performs read, write, and erase operations on the non-volatile memory cells through the media interface. Trim is also a command sent by the host, informing the SSD which data needs to be deleted. The flash translation layer invalidates the memory mapping corresponding to the logical address. The Trim hardware acceleration device, based on the received command, internally resolves and invalidates the memory mapping directly corresponding to the logical address.

[0004] When performing Trim processing, if there are too many Trim commands or the space is too large, the SSD will need to spend more time and consume more computing resources to process Trim. This will inevitably lead to a decrease in the read and write performance of the SSD and an increase in latency. At the same time, Trim requires additional space to store the status of marking whether the data is valid. After the SSD is powered off, these statuses and related information need to be saved to non-volatile storage units for rebuilding the mapping table when powered on. If the valid status of Trim is too large, it will take longer to save when the SSD is powered off, increasing the risk of saving failure and affecting the security of the data stored on the SSD. Summary of the Invention

[0005] The purpose of this invention is to provide a hardware acceleration system and method for Trim update processing in SSDs, which improves the impact of Trim update processing on normal read and write operations in SSDs and reduces read and write latency in SSDs.

[0006] To achieve the above objectives, the present invention employs the following technical solution: It includes a controller, a base address register, a storage address calculation unit, an address buffer FIFO, a Trim update unit, a mapping buffer FIFO, and a valid bit update unit.

[0007] The controller is used to control the memory address calculation unit to obtain the Trim instruction, and to control the Trim update unit to start processing and provide feedback on the status of Trim processing.

[0008] The base address register stores the base address of the mapping table, the base address of the block information, and the base address of the block valid bits.

[0009] The storage address calculation unit converts the starting logical address in the Trim instruction into the index address of the physical address of the data block corresponding to the storage logical address in the mapping table.

[0010] One unit in the address cache FIFO contains the context identifier, index address, and number of data blocks for the Trim instruction.

[0011] The Trim update unit reads the physical address of the data block corresponding to the logical address and puts it into the specified cache according to the index address and the number of data blocks. Then, it sets the area specified by the index address as a special or proprietary identifier and pushes the context of the physical address cache area into the mapping cache FIFO.

[0012] The mapping cache FIFO stores the context identifier for cache management at the physical address of the data block corresponding to the management logical address. It contains two FIFOs: one stores the cache context identifier used for Trim updates, and the other stores the cache context identifier that has been released.

[0013] The valid bit update unit updates the number of valid data blocks and the corresponding valid identifier of the data block in the flash memory block according to the physical address of the data block.

[0014] Preferably, the Trim instruction includes a starting logical address and the number of data blocks, wherein the data block size is 512B or 4KiB.

[0015] Preferably, the index address is equal to the logical address multiplied by the index address size of the physical block plus the base address of the mapping table.

[0016] Preferably, the region specified by the index address refers to the region from the starting index address to the last index address of Trim. The physical address of the data block is placed in the specified cache through a mapping cache FIFO.

[0017] Preferably, the Trim update unit includes an update controller, an address register, and direct memory access.

[0018] The update controller controls the acquisition of execution instructions from the address cache FIFO, the acquisition of cache context identifiers from the mapping FIFO and the parsing of cache storage addresses, the initiation of direct storage access for data migration, the pushing of valid cache context identifiers into the mapping cache FIFO, and the updating of the Trim processing status.

[0019] The address register stores the index address of Trim, the number of data blocks, and the source and destination addresses for direct storage access.

[0020] Direct storage access reads data into a specified cache based on the index address and the number of data blocks, and sets a special or proprietary identifier for the area specified by the index address.

[0021] Preferably, the effective bit update controller, address register, physical address resolver, direct memory access, and cache are included.

[0022] The valid bit update controller obtains and parses instructions from the mapping cache FIFO, initiates direct memory access, reads the corresponding physical address according to the cache context identifier and puts it into the cache, controls the physical address resolver to parse the physical address in the cache, and initiates direct memory access to update the valid number and valid position of the flash memory block based on the physical address.

[0023] The address register stores the base address of flash memory block management information, the base address of the valid bits of the flash memory block physical data block, and the address of the mapping cache.

[0024] The physical address resolver mainly resolves the physical addresses of data blocks stored in flash memory. Based on the physical addresses, it updates the management information of the flash memory blocks - the number of valid data blocks and the valid identifier of the data blocks. If multiple physical addresses are on the same flash memory block, they will be accumulated and then updated. If the physical addresses of multiple data blocks are consecutive, they can be aggregated and the valid identifier of the data blocks can be updated.

[0025] Direct storage access reads the required data from the cache address parsed from the above identifier of the mapped cache, places it in the cache, and updates the management information of the flash block and the valid identifier of the data block.

[0026] The cache temporarily stores management information and valid identifiers of flash memory blocks.

[0027] A hardware acceleration method for Trim update processing applied to SSDs includes the following steps: Step 1: Initialize the Trim processing hardware acceleration device, configure the base address register, and set the startup state.

[0028] Step 2: The controller sets the startup status of each internal module's status register bit according to the startup status identifier.

[0029] Step 3: Check whether the status feedback of each module is normal. If it is abnormal, output an error status. If it is normal, output a normal status indicating that the acceleration device is available.

[0030] Step 4: The controller starts the storage address calculation unit, the Trim update unit, and the valid bit update unit.

[0031] Step 5: The storage address calculation unit polls to obtain the Trim instruction, parses the Trim instruction into an index address, and pushes the instruction context, index address, and number of data blocks into the address cache FIFO.

[0032] Step 6: Trim update unit polls the address cache FIFO. First, it obtains the execution instruction, and then obtains the cache context identifier. If there is no cache context identifier, it polls the cache context identifier continuously.

[0033] Step 7: The Trim update unit reads the physical address based on the Trim index address and the number of data blocks and stores it in the designated cache. It sets the area specified by the index address as a special or proprietary identifier and then pushes the context of the physical address cache area into the mapping cache FIFO.

[0034] Step 8: The valid bit update unit polls the mapping cache FIFO to obtain the cache context identifier, and obtains the cache context identifier of the physical address where the data block is stored from the mapping FIFO. Based on the context identifier, it accesses the corresponding cache address to obtain the physical address of the corresponding invalid data block.

[0035] The advantages of this invention are as follows: This invention utilizes hardware to implement Trim update processing, significantly accelerating Trim processing. Moreover, it is handled automatically by hardware, without firmware intervention, greatly reducing the impact on normal SSD read / write operations. During Trim processing, the hardware performs the process in real-time, without foreground or background processes. After the SSD is powered off, only unprocessed Trim commands need to be saved, and execution continues after power-on reconstruction. Since the amount of Trim commands saved is minimal, this improves the speed of saving data after power failure and avoids save failures due to excessive data volume during power-off. In summary, this invention helps improve SSD operating efficiency and enhances SSD security. Attached Figure Description

[0036] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0037] Figure 1 This is a schematic diagram of the solid-state drive (SSD) structure and communication structure.

[0038] Figure 2 This is a schematic diagram of the system structure of the present invention.

[0039] Figure 3 This is a schematic diagram of the Trim update unit structure of the present invention.

[0040] Figure 4 This is a schematic diagram of the effective bit update unit structure of the present invention. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] Example 1 like Figure 1 As shown, a hardware acceleration system and method for Trim update processing applied to SSDs includes a controller, a base address register, a storage address calculation unit, an address buffer FIFO, a Trim update unit, a mapping buffer FIFO, and a valid bit update unit.

[0043] The controller is used to control the memory address calculation unit to obtain the Trim instruction, and to control the Trim update unit to start processing and provide feedback on the status of Trim processing.

[0044] The base address register stores the base address of the mapping table, the base address of the block information, and the base address of the block valid bits.

[0045] The storage address calculation unit converts the starting logical address in the Trim instruction into the index address of the physical address of the data block corresponding to the storage logical address in the mapping table.

[0046] One unit in the address cache FIFO contains the context identifier, index address, and number of data blocks for the Trim instruction.

[0047] The Trim update unit reads the physical address of the data block corresponding to the logical address and puts it into the specified cache according to the index address and the number of data blocks. Then, it sets the area specified by the index address as a special or proprietary identifier and pushes the context of the physical address cache area into the mapping cache FIFO.

[0048] The mapping cache FIFO stores the context identifier for cache management at the physical address of the data block corresponding to the management logical address. It contains two FIFOs: one stores the cache context identifier used for Trim updates, and the other stores the cache context identifier that has been released.

[0049] The valid bit update unit updates the number of valid data blocks and the corresponding valid identifier of the data block in the flash memory block according to the physical address of the data block.

[0050] The Trim instruction includes a starting logical address and the number of data blocks, the size of which is 512B or 4KiB.

[0051] The index address is equal to the logical address multiplied by the physical block index address size plus the base address of the mapping table.

[0052] The region specified by the index address refers to the area from the starting index address to the last index address of Trim. The physical address of the data block is placed in the specified cache through a mapped cache FIFO.

[0053] The Trim update unit includes an update controller, an address register, and direct memory access.

[0054] The update controller controls the acquisition of execution instructions from the address cache FIFO, the acquisition of cache context identifiers from the mapping FIFO and the parsing of cache storage addresses, the initiation of direct storage access for data migration, the pushing of valid cache context identifiers into the mapping cache FIFO, and the updating of the Trim processing status.

[0055] The address register stores the index address of Trim, the number of data blocks, and the source and destination addresses for direct storage access.

[0056] Direct storage access reads data into a specified cache based on the index address and the number of data blocks, and sets a special or proprietary identifier for the area specified by the index address.

[0057] Valid bit update controller, address register, physical address resolver, direct memory access, and cache.

[0058] The valid bit update controller obtains and parses instructions from the mapping cache FIFO, initiates direct memory access, reads the corresponding physical address according to the cache context identifier and puts it into the cache, controls the physical address resolver to parse the physical address in the cache, and initiates direct memory access to update the valid number and valid position of the flash memory block based on the physical address.

[0059] The address register stores the base address of flash memory block management information, the base address of the valid bits of the flash memory block physical data block, and the address of the mapping cache.

[0060] The physical address resolver mainly resolves the physical addresses of data blocks stored in flash memory. Based on the physical addresses, it updates the management information of the flash memory blocks - the number of valid data blocks and the valid identifier of the data blocks. If multiple physical addresses are on the same flash memory block, they will be accumulated and then updated. If the physical addresses of multiple data blocks are consecutive, they can be aggregated and the valid identifier of the data blocks can be updated.

[0061] Direct storage access reads the required data from the cache address parsed from the above identifier of the mapped cache, places it in the cache, and updates the management information of the flash block and the valid identifier of the data block.

[0062] The cache temporarily stores management information and valid identifiers of flash memory blocks.

[0063] Example 2 A hardware acceleration method for Trim update processing in SSDs is proposed, which utilizes hardware to implement Trim processing and update the valid bits of the physical address of the flash memory data block corresponding to Trim.

[0064] The hardware acceleration system processing flow for Trim updates is as follows: (1) Initialize the Trim processing hardware acceleration device, mainly by configuring the base address register and setting the startup state.

[0065] (2) The controller sets the startup status of each internal module status register bit according to the startup status identifier.

[0066] (3) Check whether the status feedback of each module is normal. If it is abnormal, output the error status. If it is normal, output the normal status. This acceleration device is available.

[0067] (4) The controller starts the storage address calculation unit, the Trim update unit and the valid bit update unit.

[0068] (5) The storage address calculation unit polls to obtain the Trim instruction.

[0069] (6) The storage address calculation unit parses the Trim instruction and converts it into an index address, and pushes the instruction context, index address and number of data blocks into the address cache FIFO.

[0070] (7) Trim update unit polls the address cache FIFO first to obtain the execution instruction, and then obtains the cache context identifier. If there is no cache context identifier, it will keep polling the cache context identifier.

[0071] (8) The Trim update unit reads the physical address based on the Trim index address and the number of data blocks and stores it in the specified cache. Then, it sets the area specified by the index address as a special or proprietary identifier and pushes the context of the physical address cache area into the mapping cache FIFO.

[0072] (9) The valid bit update unit polls the mapped cache FIFO to obtain the cache context identifier.

[0073] (10) The valid bit update unit obtains the cache context identifier of the physical address of the data block from the mapped FIFO, and accesses the corresponding cache address to obtain the physical address of the corresponding invalid data block according to the context identifier.

[0074] (11) The controller checks the status register to determine whether to continue running the Trim processing hardware acceleration device. If it is running, it will execute steps (5) to (10). If the status is paused or stopped, it will exit the execution state. If it restarts, it will start from step (2).

[0075] The process for processing Trim update units is as follows: (1) The update controller is started, performs self-inspection and returns the status.

[0076] (2) If the status is abnormal, stop the startup and return to the error status; if it is normal, return to the normal status and run.

[0077] (3) Update the controller to start polling the address cache FIFO to obtain the execution instructions and parse them.

[0078] (4) The update controller obtains the cache context identifier from the mapped FIFO and resolves the cache storage address.

[0079] (5) Update the controller to start DMA, read the data into the specified cache according to the index address and the number of data blocks, and then set a special or proprietary identifier for the area specified by the index address.

[0080] (6) Update the controller to push the valid cache context identifier into the mapped cache FIFO.

[0081] (7) Update the controller to update the Trim processing status.

[0082] (8) Update the controller to check the status register and determine whether to continue running. If running, execute steps (3) to (7). If the status is paused or stopped, exit the execution state. If restarting, start execution from step (2).

[0083] The processing flow of the valid bit update unit is as follows: (1) The valid bit update controller is started, performs self-inspection and returns the status.

[0084] (2) If the status is abnormal, stop the startup and return to the error status; if it is normal, return to the normal status and run.

[0085] (3) The valid bit update controller starts polling the address cache FIFO to obtain the instruction to be executed and parses it.

[0086] (4) The valid bit update controller obtains the cache context identifier from the mapped FIFO and resolves the cache storage address.

[0087] (5) The valid bit update controller starts DMA and reads the data into the cache according to the index address and the number of data blocks.

[0088] (6) The valid bit update controller starts the physical address resolver to resolve the physical address in the cache.

[0089] (7) The physical address resolver updates the management information of the flash memory block based on the physical address - the number of valid data blocks and the valid identifier of the data block. If multiple physical addresses are on the same flash memory block, they will be accumulated and then updated. If the physical addresses of multiple data blocks are consecutive, they can be aggregated and the valid identifier of the data block can be updated.

[0090] (8) The valid bit update controller starts the DMA to update the management information of the flash memory block - the number of valid data blocks and the valid identifier of the data block, and writes it back to the corresponding storage space.

[0091] (9) If all invalid physical addresses in the mapping cache context identifier have been processed, the valid bit update controller will push the corresponding cache context identifier into the mapping cache FIFO.

[0092] (10) The valid bit update controller checks the status register to determine whether to continue running. If running, it will execute steps (3) to (9). If the status is paused or stopped, it will exit the execution state. If restarting, it will start from step (2).

[0093] This disclosure provides a hardware acceleration device for Trim update processing of SSDs, comprising: a product body, wherein a hardware acceleration system for Trim update processing of SSDs is installed on the product body. The installation relationship described herein is not limited to placement within the product, but also includes installation connections with other components of the product, including but not limited to physical connections, electrical connections, or signal transmission connections. Those skilled in the art will understand that the hardware acceleration system for Trim update processing of SSDs can be adapted to feasible product bodies to achieve other feasible embodiments.

[0094] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to perform the method described above for…

[0095] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0096] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0097] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A hardware acceleration system for Trim update processing of SSDs, characterized in that, It includes a controller, a base address register, a storage address calculation unit, an address buffer FIFO, a Trim update unit, a mapping buffer FIFO, and a valid bit update unit; The controller is used to control the memory address calculation unit to obtain the Trim instruction, and to control the Trim update unit to start processing and provide feedback on the status of Trim processing. The base address register stores the base address of the mapping table, the base address of the block information, and the base address of the block valid bits; The storage address calculation unit converts the starting logical address in the Trim instruction into the index address of the physical address of the data block corresponding to the storage logical address in the mapping table; One unit in the address cache FIFO contains the context identifier, index address, and number of data blocks for the Trim instruction; The Trim update unit reads the physical address of the data block corresponding to the logical address and puts it into the specified cache according to the index address and the number of data blocks. Then, it sets the area specified by the index address as a special or proprietary identifier and pushes the context of the physical address cache area into the mapping cache FIFO. The mapping cache FIFO stores the context identifier of cache management at the physical address of the data block corresponding to the management logical address; it includes two FIFOs, one for storing the cache context identifier used for Trim updates, and the other for the cache context identifier that has been released; The valid bit update unit updates the number of valid data blocks and the corresponding valid identifier of the data block in the flash memory block according to the physical address of the data block.

2. The hardware acceleration system for Trim update processing applied to SSDs according to claim 1, characterized in that, The Trim instruction includes a starting logical address and the number of data blocks, the size of which is 512B or 4KiB.

3. The hardware acceleration system for Trim update processing applied to SSDs according to claim 2, characterized in that, The index address is equal to the logical address multiplied by the physical block index address size plus the base address of the mapping table.

4. The hardware acceleration system for Trim update processing applied to SSDs according to claim 1, characterized in that, The region specified by the index address refers to the area from the starting index address to the last index address of Trim; the physical address of the data block is placed in the specified cache by obtaining the mapping cache FIFO.

5. The hardware acceleration system for Trim update processing applied to SSDs according to claim 1, characterized in that, The Trim update unit includes an update controller, an address register, and direct memory access; The update controller controls the acquisition of execution instructions from the address cache FIFO, the acquisition of cache context identifiers from the mapping FIFO and the parsing of cache storage addresses, the initiation of direct storage access for data migration, the pushing of valid cache context identifiers into the mapping cache FIFO, and the update of the Trim processing status. The address register stores the index address of Trim, the number of data blocks, and the source and destination addresses for direct storage access; Direct storage access reads data into a specified cache based on the index address and the number of data blocks, and sets a special or proprietary identifier for the area specified by the index address.

6. The hardware acceleration system for Trim update processing applied to SSDs according to claim 1, characterized in that, Valid bit update controller, address register, physical address resolver, direct memory access, and cache; The valid bit update controller obtains and parses instructions from the mapped cache FIFO, initiates direct memory access, reads the corresponding physical address according to the cache identifier and puts it into the cache, and controls the physical address parser to parse the physical address in the cache. Based on the physical address, it initiates direct memory access to update the valid number and valid position of the data block of the flash memory block. The address register stores the base address of flash memory block management information, the base address of the valid bits of the flash memory block physical data block, and the address of the mapped cache; The physical address resolver mainly resolves the physical addresses of data blocks stored in flash memory. Based on the physical addresses, it updates the management information of the flash memory blocks - the number of valid data blocks and the valid identifier of the data blocks. If multiple physical addresses are on the same flash memory block, they will be accumulated and then updated. If the physical addresses of multiple data blocks are consecutive, they can be aggregated and the valid identifier of the data blocks can be updated. Direct storage access reads the required data from the cache address parsed from the above identifier of the mapped cache, places it in the cache, and updates the management information of the flash block and the valid identifier of the data block; The cache temporarily stores management information and valid identifiers of flash memory blocks.

7. A hardware acceleration method for Trim update processing applied to SSDs using any one of claims 1-6, characterized in that, Includes the following steps: Step 1: Initialize the Trim processing hardware acceleration device, configure the base address register, and set the startup state; Step 2: The controller sets the startup status of each internal module's status register bit according to the startup status identifier. Step 3: Check whether the status feedback of each module is normal. If it is abnormal, output an error status. If it is normal, output a normal status: This acceleration device is available. Step 4: The controller starts the memory address calculation unit, the Trim update unit, and the valid bit update unit; Step 5: The storage address calculation unit polls to obtain the Trim instruction, parses the Trim instruction into an index address, and pushes the instruction context, index address, and number of data blocks into the address cache FIFO; Step 6: Trim update unit polls the address cache FIFO. First, it obtains the execution instruction, and then obtains the cache context identifier. If there is no cache context identifier, it polls the cache context identifier continuously. Step 7: The Trim update unit reads the physical address based on the Trim index address and the number of data blocks and stores it in the designated cache. It sets the area specified by the index address as a special or proprietary identifier and then pushes the context of the physical address cache area into the mapping cache FIFO. Step 8: The valid bit update unit polls the mapping cache FIFO to obtain the cache context identifier, and obtains the cache context identifier of the physical address where the data block is stored from the mapping FIFO. Based on the context identifier, it accesses the corresponding cache address to obtain the physical address of the corresponding invalid data block.

8. A hardware acceleration device for Trim update processing of SSDs, characterized in that, include: Equipment body; The hardware acceleration system for Trim update processing of SSDs as described in any one of claims 1-6 is installed on the product body.

9. A storage medium storing program instructions, characterized in that, When the program instructions are executed, they perform the hardware acceleration method for Trim update processing applied to SSDs as described in claim 6.

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