Clock frequency selection device and method in master device for bus system

Abstract

The present invention provides a clock frequency selection device and method in a master device of a bus system. In order to increase the overall access speed and performance of the bus system, the master device is designed to use clock signals of different clock frequencies to address and read / write data to / from slave devices. In the address phase, the master device uses a first operating frequency at which the master device can successfully address a plurality of slave devices as the clock frequency of the clock signal, and in the read / write phase, the master device uses the lowest one of a plurality of operating frequencies of the plurality of slave devices as the clock frequency of the clock signal, wherein the operating frequency of a slave device refers to the maximum clock frequency supported by the slave device.

Description

Technical Field

[0001] This invention relates to a master device for a bus system, and more particularly to a clock frequency selection device and method for a master device in a bus system, which can effectively improve the overall access speed and performance of the bus system. Background Technology

[0002] Inter-Integrated Circuit (I2C) is a serial communication bus circuit that allows a master device to connect to multiple slave devices via a bus. When using a general-purpose microcontroller (MCU) in I2C-related applications, the MCU sometimes needs to act as the I2C master device, using a set of I2C interfaces to connect multiple slave devices for control and data transmission on the I2C bus.

[0003] Currently, some slave devices can accept data access from the master device at a higher bit rate (i.e., a higher clock frequency), while others can only accept data access from the master device at a lower bit rate (i.e., a lower clock frequency). However, on this I2C bus, if there are slave devices with different acceptable bit rates, the master device can only select the slave device with the lowest acceptable bit rate as the reference and access data or control from each slave device on the I2C bus at this lowest bit rate. Therefore, slave devices that could originally accept higher bit rates will be forced to access data and control data from the master device at a slower speed, resulting in a decrease in the overall performance of this I2C bus.

[0004] For example, multiple slave devices are designated as a first slave device, a second slave device, and a third slave device. The highest bit rates (i.e., the highest acceptable operating clock frequencies, hereinafter referred to as the working clock frequencies) that the first, second, and third slave devices can accept are 400kHz, 100kHz, and 50kHz, respectively. In order to control and access the data of each slave device correctly, the master device sets the bit rate of its I2C clock signal (i.e., the serial clock signal) to 50kHz. Summary of the Invention

[0005] This invention provides a clock frequency selection device for a master device in a bus system. The bus system includes a master device and multiple slave devices, with the master device connected to the slave devices via a bus. The clock frequency selection device includes: an addressing check unit for checking whether the master device successfully addresses the multiple slave devices using a clock signal with a first operating frequency, wherein the first operating frequency is by default the highest among multiple operating clock frequencies of the multiple slave devices, and the operating frequency of a slave device refers to the maximum clock frequency supported by the slave device; a frequency control unit electrically connected to the addressing check unit, which generates a first operating frequency setting signal and a clock frequency selection signal based on the check result indicating whether the master device successfully addresses the multiple slave devices using a clock signal with the first operating frequency; and a clock signal generation unit electrically connected to the frequency control unit. The clock signal is set to a first operating frequency according to the first operating frequency setting signal, and the clock frequency is set to either the first operating frequency or the second operating frequency according to the clock frequency selection signal. If the check result is successful, the frequency control unit controls the clock signal generation unit to allow the master device to address multiple slave devices using a clock signal with the first operating frequency, and the frequency control unit controls the clock signal generation unit to allow the master device to read and write data to multiple slave devices using a clock signal with the second operating frequency, wherein the second operating frequency is the lowest among the multiple operating clock frequencies of the multiple slave devices. If the check result is unsuccessful, the frequency control unit generates a first operating frequency setting signal to reduce the first operating frequency, so that the addressing check unit can check again whether the master device has successfully addressed multiple slave devices using a clock signal with the first operating frequency.

[0006] The present invention also provides a master device that includes the above-described clock frequency selection device.

[0007] The present invention also provides a bus system comprising the aforementioned master device and the aforementioned plurality of slave devices.

[0008] This invention also provides a clock frequency selection method for a master device in a bus system, wherein the bus system includes a master device and multiple slave devices, the master device is connected to the multiple slave devices via a bus, and the clock frequency selection method includes: checking whether the master device successfully addresses the multiple slave devices using a clock signal with a clock frequency of a first operating frequency, wherein the first operating frequency is by default the highest among the multiple working clock frequencies of the multiple slave devices, and the working frequency of the slave device refers to the maximum clock frequency supported by the slave device; if the check result is successful, the master device addresses the multiple slave devices using a clock signal with a clock frequency of the first operating frequency, and the master device performs data read and write operations on the multiple slave devices using a clock signal with a clock frequency of a second operating frequency, wherein the second operating frequency is the lowest among the multiple working clock frequencies of the multiple slave devices; and if the check result is unsuccessful, the first operating frequency is reduced to check again whether the master device successfully addresses the multiple slave devices using a clock signal with a clock frequency of the first operating frequency.

[0009] In summary, the technical solution of the present invention can increase the overall access speed and performance of the bus system.

[0010] To further understand the technology, means, and effects of the present invention, reference can be made to the following detailed description and accompanying drawings, which will provide a thorough and concrete understanding of the purpose, features, and concepts of the present invention. However, the following detailed description and accompanying drawings are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0011] The accompanying drawings are provided to enable those skilled in the art to further understand the invention, and are incorporated in and constitute a part of the specification of the invention. The drawings illustrate exemplary embodiments of the invention and are used together with the specification to explain the principles of the invention.

[0012] Figure 1 This is a schematic diagram of a bus system according to an embodiment of the present invention.

[0013] Figure 2 This is a schematic diagram of the master device writing data to the slave device in an embodiment of the present invention.

[0014] Figure 3 This is a schematic diagram of a data frame transmitted by the master device to the slave device during data reading in an embodiment of the present invention.

[0015] Figure 4 This is a block diagram of the clock frequency selection device in the main device of this invention embodiment.

[0016] Figure 5This is a flowchart of a clock frequency selection method for a master device in a bus system according to an embodiment of the present invention.

[0017] Figure 6 This is a flowchart of the addressing check of the clock frequency selection method according to an embodiment of the present invention.

[0018] The symbols shown in the diagram are explained as follows: 1: Bus system; 11: Master device; 121: First slave device; 122: Second slave device; 123: Third slave device; SCL: Clock signal; SDA: Data; VDD: System voltage; R1, R2: Resistors; 2, 3: Data frames; 21, 31: Address data subframes; 22: Write data subframe; 23, 33: End subframe; 32: Read data subframe; 4: Clock frequency selection device; 41: Addressing check unit; 42: Frequency control unit; 43: Clock signal generation unit; S501~S638: Steps Detailed Implementation

[0019] Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Where possible, the same component reference numerals are used in the drawings and description to refer to the same or similar parts. Furthermore, the exemplary embodiments are merely one way of implementing the design concept of the invention, and the following examples are not intended to limit the invention.

[0020] Generally, slave devices (e.g., but not limited to I2C slave devices) can be divided into two main categories: one is a slave device whose entire circuitry is digital (i.e., a purely digital slave device), and the other is a slave device whose circuitry is partly digital and partly analog (i.e., a hybrid slave device). Digital circuitry can include digital logic circuits, control registers, memory (e.g., electronically erasable programmable read-only memory, EEPROM), or digital signal processing units, but this invention is not limited thereto. Analog circuitry can include analog-to-digital converters, digital-to-analog converters (e.g., audio decoders or audio signal amplifiers), or analog sensing circuitry (e.g., capacitive touch sensors, temperature sensors, humidity sensors, or gravity sensors), but this invention is not limited thereto.

[0021] The complete process of a master device accessing data (i.e., reading and writing) from a slave device involves addressing the slave device's device address and register address, then verifying the slave device after receiving its response, and finally performing data reading and writing. In other words, the complete process of a master device accessing data from a slave device includes both addressing and reading / writing phases. Hybrid circuit slave devices incorporate both digital and analog circuits. The digital circuits (e.g., control registers, logic circuits, etc.) in a hybrid circuit slave device are primarily used in the addressing phase. The analog circuits in a hybrid circuit slave device require more time to process or collect data, such as capacitor charging and discharging and surrounding sensing and detecting. This results in the access speed of these hybrid circuit slave devices not being as fast as that of purely digital circuit slave devices, thus causing the bit rate of data access for hybrid circuit slave devices to typically not be very high.

[0022] In view of this, in order to increase the overall access speed and performance of the bus system, the present invention designs the master device to use clock signals of different clock frequencies to address and read / write data to slave devices. During the addressing phase, the first operating frequency at which the master device can successfully address multiple slave devices is used as the clock frequency of the clock signal. During the read / write phase, the lowest of the multiple operating frequencies of the multiple slave devices (i.e., the second operating frequency) is used as the clock frequency of the clock signal for read / write operations. The master device is connected to multiple slave devices via a bus, and the operating frequency of a slave device refers to the maximum clock frequency supported by that slave device.

[0023] Furthermore, the master device checks whether its addressing of multiple slave devices using a clock signal with a first operating frequency (defaulting to the highest among the multiple operating clock frequencies of the slave devices) was successful. If the check is successful, the master device addresses the multiple slave devices using the clock signal with the first operating frequency and performs data read / write operations on the multiple slave devices using a clock signal with a second operating frequency (the lowest among the multiple operating clock frequencies of the slave devices). If the check fails, the first operating frequency is lowered to re-check whether the master device's addressing of the multiple slave devices using the clock signal with the first operating frequency was successful.

[0024] In simple terms, if the check fails, the first operating frequency is reduced, and the addressing check is performed again. Then, until the check succeeds, the first operating frequency used in that addressing check is used as the clock frequency for subsequent addressing of multiple slave devices, and the second operating frequency is used as the clock frequency for data read / write operations on the multiple slave devices. Therefore, the technical solution of this invention can increase the overall access speed and performance of the bus system.

[0025] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a bus system according to an embodiment of the present invention. The bus system 1 includes a master device 11 and multiple slave devices (a first slave device 121, a second slave device 122, and a third slave device 123). The master device 11 is connected to the first slave device 121, the second slave device 122, and the third slave device 123 via a bus. The bus transmits the serial clock signal SCL and various data SDA. The bus typically includes resistors R1 and R2, and the connection point of resistors R1 and R2 receives the system voltage VDD to avoid interference between the serial clock signal SCL and the data SDA. That is, resistors R1 and R2 act as pull-up resistors to separate the clock signal SCL and the data SDA on the bus. In this embodiment, three slave devices are used as an example, but the present invention is not limited to the number of slave devices.

[0026] Please refer to the following: Figure 2 , Figure 2 This is a schematic diagram of a data frame transmitted from a master device to a slave device during data writing, according to an embodiment of the present invention. The data frame 2 transmitted from the master device to the slave device includes an addressing data subframe 21, a writing data subframe 22, and an ending subframe 23 arranged in sequence. The complete process of the master device accessing data from the slave device includes an addressing phase and a read / write phase. The addressing data subframe 21 contains the data transmitted during the addressing phase, the writing data subframe 22 contains the data transmitted during the read / write phase, and the ending subframe 23 is used to terminate the complete data access process.

[0027] In this invention, when the master device transmits the addressing data subframe 21 (i.e., performs the addressing phase), it uses the first operating frequency when the check result is successful as the clock frequency. When the master device transmits the write data subframe 22 (i.e., performs the read / write phase), it uses the second operating frequency (the smallest of the multiple operating frequencies of multiple slave devices) as the clock frequency. When the master device transmits the end subframe 23, it uses the first operating frequency when the check result is successful as the clock frequency.

[0028] The contents of address data subframe 21, in sequence, are the start bit ST, the slave device's device address signal SLA, the write bit Wr, the slave device's response bit AKS (corresponding to the device address signal SLA), and a combination of multiple consecutive sets of slave device register address signals RegAdd1, RegAdd2, ..., RegAddn and the slave device's response bit AKS (corresponding to the register address signals RegAdd1, RegAdd2, ..., RegAddn), where n is the number of slave device registers. The contents of write data subframe 22, in sequence, are a combination of multiple consecutive sets of write data to be written to the slave device WD1, WD2, ..., WDm and the slave device's response bit AKS (corresponding to the write data WD1, WD2, ..., WDm), where m is the number of data entries to be written to the slave device. End subframe 23 includes the stop bit SP.

[0029] Please refer to the following: Figure 3 , Figure 3 This is a schematic diagram of a data frame transmitted by a master device to a slave device during data reading according to an embodiment of the present invention. The data frame 3 transmitted by the master device to the slave device during data reading includes an addressing data subframe 31, a read data subframe 32, and an end subframe 33 arranged in sequence. The complete process of the master device accessing data from the slave device includes an addressing phase and a read / write phase. The addressing data subframe 31 contains the data transmitted during the addressing phase, the read data subframe 32 contains the data transmitted during the read / write phase, and the end subframe 33 is used to terminate the complete data access process.

[0030] In this invention, when the master device transmits the addressing data subframe 31 (i.e., performs the addressing phase), it uses the first operating frequency when the check result is successful as the clock frequency. When the master device transmits the reading data subframe 32 (i.e., performs the read / write phase), it uses the second operating frequency (the smallest of the multiple operating frequencies of multiple slave devices) as the clock frequency. When the master device transmits the ending subframe 33, it uses the first operating frequency when the check result is successful as the clock frequency.

[0031] The contents of the address data subframe 31, in sequence, are: start bit ST, slave device address signal SLA, write bit Wr, slave device response bit AKS (corresponding to device address signal SLA), a combination of multiple consecutive slave device register address signals RegAdd1, RegAdd2, ..., RegAddn and slave device response bit AKS (corresponding to register address signals RegAdd1, RegAdd2, ..., RegAddn), repeat start bit RS, slave device address signal SLA, read bit Rd and slave device response bit AKS (corresponding to device address signal SLA), where n is the number of slave device registers. The contents of the read data subframe 32, in sequence, are a combination of multiple consecutive read data RD1, RD2, ..., RDm read from the slave device and master device response bit AKM (corresponding to read data RD1, RD2, ..., RDm), where m is the number of data entries to be written to the slave device. The end subframe 33 includes a stop bit SP.

[0032] Please refer to the following: Figure 4 , Figure 4 This is a block diagram of a clock frequency selection device in a master device according to an embodiment of the present invention. The clock frequency selection device 4 in the master device for a bus system includes an address checking unit 41, a frequency control unit 42, and a clock signal generation unit 43, wherein the frequency control unit 42 is electrically connected between the address checking unit 41 and the clock signal generation unit 43. The address checking unit 41 is used to check whether the master device has successfully addressed multiple slave devices using a clock signal SCL with a clock frequency of a first operating frequency (through the transmission and reception of data SDA). One embodiment of its address checking success is as follows: Figure 6 As described in the description, the first operating frequency is the highest among the multiple operating clock frequencies of the multiple slave devices by default, and the operating frequency of the slave device refers to the maximum clock frequency supported by the slave device. For example, if there are three slave devices with operating frequencies of 400KHz, 100KHz and 50KHz respectively, then the first operating frequency is 400KHz by default.

[0033] The frequency control unit 42 generates a first operating frequency setting signal and a clock frequency selection signal based on the check result. The check result is generated by the addressing check unit 41 and is used to indicate whether the master device has successfully addressed multiple slave devices using a clock signal SCL with a clock frequency of the first operating frequency. The clock signal generation unit 43 sets the first operating frequency of the clock signal SCL based on the first operating frequency setting signal and sets the clock frequency to either the first operating frequency or the second operating frequency based on the clock frequency selection signal.

[0034] If the check is successful, the frequency control unit 42 controls the clock signal generation unit 43 to allow the master device to use a clock signal SCL with a clock frequency of the first operating frequency to address multiple slave devices, and the frequency control unit 42 controls the clock signal generation unit 43 to allow the master device to use a clock signal SCL with a clock frequency of the second operating frequency to read and write data to multiple slave devices, wherein the second operating frequency is the lowest among the multiple operating clock frequencies of the multiple slave devices. For example, if there are three slave devices with operating frequencies of 400KHz, 100KHz and 50KHz respectively, then the second operating frequency is 50KHz by default.

[0035] If the check fails, the frequency control unit 42 generates a first operating frequency setting signal to lower the first operating frequency, so that the addressing check unit 41 checks again whether the master device successfully addresses the multiple slave devices using the clock signal SCL with the clock frequency of the first operating frequency. After multiple addressing checks, until the check result is successful, the master device uses the first operating frequency used in that addressing check as the clock frequency used for subsequent addressing of the multiple slave devices, and uses the second operating frequency as the clock frequency for data read and write operations on the multiple slave devices.

[0036] When a check fails, the method of lowering the first operating frequency can be implemented in several ways, and the present invention is not limited thereto. In one embodiment, the highest of the multiple operating clock frequencies is 2n times the lowest of the multiple operating clock frequencies, where n is an integer, and the reduced first operating frequency is (1 / 2)i times the highest of the multiple operating clock frequencies, where i is the number of checks to check whether the addressing is successful, and this method can be implemented using a frequency divider. In another embodiment, the reduced first operating frequency is the (i+1)th of the multiple operating clock frequencies of the multiple slave devices, sorted from high to low, where i is the number of checks to check whether the addressing is successful. In yet another embodiment, the highest of the multiple operating clock frequencies is K times the lowest of the multiple operating clock frequencies, where K is an integer, and the reduced first operating frequency is (Ki) times the lowest of the multiple operating clock frequencies, where i is the number of checks to check whether the addressing is successful.

[0037] Furthermore, the master device performs addressing checks for each slave device as follows: Addressing check unit 41 causes the master device to transmit a start bit, the slave device's device address signal, and a write bit to the slave device, and addresses check unit 41 determines whether the master device receives a response bit transmitted by the slave device based on the start bit, device address signal, and write bit. If addressing check unit 41 determines that no response bit has been received, the check result is deemed a failure; if a response bit has been received, addressing check unit 41 causes the master device to transmit the slave device's identification register address signal to the slave device, and addresses check unit 41 determines whether the master device receives another response bit transmitted by the slave device based on the identification register address signal.

[0038] If the addressing check unit 41 determines that no other response bit has been received, the check result is deemed a failure. If another response bit has been received, the addressing check unit 41 causes the master device to transmit a repeat start bit, the slave device's device address signal, and a read bit to read the slave device's identification and transmit the master device's response bit to the slave device. The addressing check unit 41 then checks whether the slave device's identification is correct. If the slave device's identification is incorrect, the check result is deemed a failure. If the slave device's identification is correct, the addressing check unit causes the master device to transmit a stop bit to end the addressing check for this slave device. The check result is considered successful only when every slave device's addressing check passes successfully; if any slave device's addressing check fails, the check result is deemed a failure.

[0039] Please refer to Figure 5 , Figure 5 This is a flowchart of a clock frequency selection method for a master device in a bus system according to an embodiment of the present invention. In this embodiment, there are three slave devices, and the operating frequencies of the three slave devices are 400KHz, 100KHz and 50KHz, respectively. 400KHz is 8 times 50KHz. The first operating frequency is 400KHz by default, and the second operating frequency is 50KHz. The method of reducing the first operating frequency is to divide the previous first operating frequency by 2.

[0040] First, in step S501, the master device uses a clock signal with a clock frequency of 400kHz to perform addressing checks on the three slave devices and generates corresponding check results. In step S502, the check result is determined to be successful or unsuccessful. If the check result is successful, in step S503, the master device uses a clock frequency of 400kHz during the addressing phase and a clock frequency of 50kHz during the read / write phase; otherwise, the first operating frequency is reduced to 200kHz, and step S504 is executed.

[0041] In step S504, the master device uses a clock signal with a clock frequency of 200kHz to perform addressing checks on the three slave devices and generates corresponding check results. In step S505, the check result is determined to be successful or unsuccessful. If the check result is successful, in step S506, the master device uses a clock frequency of 200kHz during the addressing phase and a clock frequency of 50kHz during the read / write phase; otherwise, the first operating frequency is reduced to 100kHz, and step S507 is executed.

[0042] In step S507, the master device uses a 100kHz clock signal to perform addressing checks on the three slave devices and generates corresponding check results. In step S508, the check result is determined to be successful or unsuccessful. If the check result is successful, in step S509, the master device uses a 100kHz clock frequency during the addressing phase and a 50kHz clock frequency during the read / write phase; otherwise, step S510 is executed, and the master device uses a 50kHz clock frequency during both the addressing and read / write phases.

[0043] Next, please refer to Figure 6 , Figure 6 This is a flowchart of the addressing check of the clock frequency selection method according to an embodiment of the present invention. In this embodiment, there are three slave devices, namely the first slave device, the second slave device, and the third slave device, but the present invention is not limited thereto. First, in step S611, the master device transmits the start bit ST, the device address signal SLA1 of the first slave device, and the write bit Wr to the first slave device. Then, in step S612, it is determined whether the master device has received the response bit ASK1 transmitted by the first slave device based on the start bit ST, the device address signal SLA1, and the write bit Wr. If the addressing check unit 41 determines that no response bit has been received, the check result is set to failure; if a response bit has been received, step S613 is executed. In step S613, the master device transmits the identification register address signal of the first slave device to the first slave device. In step S614, it is determined whether the master device has received another response bit ASK1 transmitted by the first slave device based on the identification register address signal. If the addressing check unit 41 determines that no other response bit ASK1 has been received, the check result is deemed a failure; if another response bit ASK1 has been received, step S615 is executed. In step S615, the master device transmits the repeat start bit RS, the device address signal SLA1 of the first slave device, and the read bit Rd. In step S616, the master device reads the identification of the first slave device and transmits the master device's response bit AKM to the first slave device. In step S617, it is determined whether the identification of the first slave device is correct. If the identification of the first slave device is incorrect, the check result is deemed a failure; if the identification of the slave device is correct, step S618 is executed, and in step S618, the master device transmits the stop bit SP to end the addressing check of the first slave device.

[0044] Steps S621 to S628 and S631 to S638 can be deduced from steps S611 to S618, and therefore will not be elaborated further. If the first slave device, the second slave device, and the third slave device are addressed and successfully pass the check, the check result is considered successful. If the address check of any one of the slave devices fails, the check result is considered unsuccessful.

[0045] In summary, the clock frequency selection device and method for the master device in a bus system provided by the embodiments of the present invention enable an ARM-based microcontroller, when acting as a master device, to use different bit rates for addressing and reading / writing to multiple external I2C slave devices on the same I2C bus. Therefore, it can effectively improve the access speed and performance of the entire I2C bus system.

[0046] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A clock frequency selection device for a master device in a bus system, characterized in that, The bus system includes the master device and multiple slave devices, the master device being connected to the multiple slave devices via a bus, and the clock frequency selection device includes: An addressing check unit is used to check whether the master device successfully addresses the plurality of slave devices using a clock signal with a clock frequency of a first operating frequency, wherein the first operating frequency is by default the highest among the plurality of working clock frequencies of the slave devices, and the working clock frequency of the slave devices refers to a maximum clock frequency supported by the slave devices. A frequency control unit, electrically connected to the addressing check unit, generates a first operating frequency setting signal and a clock frequency selection signal based on a check result indicating whether the master device successfully addresses the plurality of slave devices using the clock signal with the clock frequency being the first operating frequency; and A clock signal generation unit is electrically connected to the frequency control unit, which sets the first operating frequency of the clock signal according to the first operating frequency setting signal, and sets the clock frequency to the first operating frequency or a second operating frequency according to the clock frequency selection signal. If the check result is successful, the frequency control unit controls the clock signal generation unit to allow the master device to use the clock signal with the clock frequency of the first operating frequency to address the plurality of slave devices, and the frequency control unit controls the clock signal generation unit to allow the master device to use the clock signal with the clock frequency of the second operating frequency to read and write data to the plurality of slave devices, wherein the second operating frequency is the lowest among the plurality of operating clock frequencies of the plurality of slave devices; If the check result is a failure, the frequency control unit generates the first operating frequency setting signal to reduce the first operating frequency, so that the addressing check unit can check again whether the master device has successfully addressed the plurality of slave devices using the clock signal with the clock frequency of the first operating frequency.

2. The clock frequency selection device as described in claim 1, characterized in that, The highest of the plurality of operating clock frequencies is 2n times the lowest of the plurality of operating clock frequencies, where n is an integer, and the first operating frequency is reduced by (1 / 2)i times the highest of the plurality of operating clock frequencies, where i is the number of checks to determine whether the addressing is successful.

3. The clock frequency selection device as described in claim 1, characterized in that, The reduced first operating frequency is the (i+1)th of the plurality of operating clock frequencies of the plurality of slave devices, ordered from high to low, where i is the number of checks to determine if the addressing was successful.

4. The clock frequency selection device as described in claim 1, characterized in that, The highest of the plurality of operating clock frequencies is K times the lowest of the plurality of operating clock frequencies, where K is an integer, and the first operating frequency is reduced by (Ki) times the lowest of the plurality of operating clock frequencies, where i is the number of checks to determine if the addressing is successful.

5. The clock frequency selection device as described in claim 1, characterized in that, The addressing check for each of the plurality of slave devices includes: The addressing check unit causes the master device to transmit a start bit, a device address signal of the slave device, and a write bit to the slave device, and the addressing check unit determines whether the master device receives a first response bit transmitted by the slave device based on the start bit, the device address signal of the slave device, and the write bit; The address checking unit causes the master device to transmit an identification register address signal of the slave device to the slave device, and the address checking unit determines whether the master device receives a second response bit transmitted by the slave device based on the identification register address signal; The addressing check unit causes the master device to transmit a repeat start bit, the slave device's device address signal, and a read bit to read an identification of the slave device and transmit a third response bit, and determines whether the slave device's identification is correct; and The addressing check unit causes the master device to transmit a stop bit.

6. A main device, characterized in that, The main device includes: The clock frequency selection device as claimed in any one of claims 1 to 5.

7. The main equipment as described in claim 6, characterized in that, The main device is a microcontroller.

8. A bus system, characterized in that, The bus system includes: The main equipment as described in claim 6; and The plurality of slave devices.

9. The bus system as described in claim 8, characterized in that, The slave device includes a first part of circuitry and a second part of circuitry, wherein the first part of circuitry is a digital circuit and the second part of circuitry is an analog circuit or another digital circuit.

10. A clock frequency selection method for a master device in a bus system, characterized in that, The bus system includes the master device and multiple slave devices, the master device is connected to the multiple slave devices via a bus, and the clock frequency selection method includes: Check whether the master device successfully addresses the plurality of slave devices using a clock signal with a clock frequency of a first operating frequency, wherein the first operating frequency is by default the highest among the plurality of working clock frequencies of the plurality of slave devices, and the working clock frequency of the slave device refers to the maximum clock frequency supported by the slave device. If a check result is successful, the master device uses the clock signal with a clock frequency equal to the first operating frequency to address the plurality of slave devices, and the master device uses the clock signal with a clock frequency equal to a second operating frequency to read and write data to the plurality of slave devices, wherein the second operating frequency is the lowest among the plurality of operating clock frequencies of the plurality of slave devices; and If the check result is a failure, the first operating frequency is reduced to check again whether the master device successfully addresses the plurality of slave devices using the clock signal with the clock frequency being the first operating frequency.

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