A data transmission circuit, method and semiconductor memory

Abstract

This disclosure provides a data transmission circuit, method, and semiconductor memory. The data transmission circuit includes a control module and a processing module. The control module is configured to receive a first enable signal and control the processing module to operate when the first enable signal is valid, and to control the processing module to operate when the first enable signal is invalid. The processing module is configured to receive an initial data signal and perform driving processing on the initial data signal to obtain a target transmission signal when operating.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a data transmission circuit, method, and semiconductor memory. Background Technology

[0002] In semiconductor chips, data transmission circuits (such as data readout driver circuits) can be used to read data from memory. In some scenarios, data stored in memory needs to be transferred to other circuits, such as being read from a memory cell and transferred to other data ports, or further transferred to other chips or memory controllers. Taking a data readout driver circuit as an example, it can acquire data stored in memory, process this data, and further output signals representing this data. Summary of the Invention

[0003] The technical solution disclosed herein is implemented as follows:

[0004] In a first aspect, embodiments of this disclosure provide a data transmission circuit, including a control module and a processing module, wherein,

[0005] The control module is configured to receive a first enable signal, and control the processing module to be in a working state when the first enable signal is in a valid state, and control the processing module to be in a non-working state when the first enable signal is in a invalid state.

[0006] The processing module is used to receive an initial data signal when it is in working state, and to drive the initial data signal to obtain the target transmission signal.

[0007] In some embodiments, the control module includes a first switching unit; wherein,

[0008] The control module is configured to control the first switching unit to conduct when the first enable signal is active, so that the processing module is in a working state; and

[0009] The control module is further configured to control the first switching unit to turn off when the first enable signal is in an invalid state, so that the processing module is in a non-working state.

[0010] In some embodiments, when the first enable signal is in a first level state, it is determined that the first enable signal is in an invalid state;

[0011] When the first enable signal is in the second level state, it is determined that the first enable signal is in a valid state.

[0012] In some embodiments, the first switching unit includes a first transistor; wherein...

[0013] The first transistor includes a first terminal, a second terminal, and a third terminal;

[0014] The first terminal is coupled to the first enable signal, the second terminal is coupled to the power supply terminal or the ground terminal, and the third terminal is coupled to the processing module.

[0015] In some embodiments, the initial data signal includes a first initial data signal and a second initial data signal, and the level states of the first initial data signal and the second initial data signal are opposite; the processing module includes:

[0016] The first processing module is configured to perform driving processing on the first initial data signal to obtain a first driving signal when the processing module is in the working state.

[0017] The second processing module is used to drive the second initial data signal to obtain a second driving signal when the processing module is in the working state.

[0018] The output module is used to obtain the target transmission signal based on the first driving signal and the second driving signal.

[0019] In some embodiments, the first processing module includes N first inverters; wherein, the input terminal of the first first inverter receives the first initial data signal, the output terminal of the i-th first inverter is connected to the input terminal of the (i+1)-th first inverter, the output terminal of the N-th first inverter is used to output the first drive signal, and the enable terminals of all N first inverters are connected to the control module, where i is an integer greater than 0 and less than N, and N is an even number greater than 0;

[0020] The second processing module includes M second inverters; wherein, the input terminal of the first second inverter receives the second initial data signal, the output terminal of the j-th second inverter is connected to the input terminal of the (j+1)-th second inverter, the output terminal of the M-th second inverter is used to output the second drive signal, and the enable terminals of the M second inverters are all connected to the control module, where j is an integer greater than 0 and less than M, and M is an even number greater than 0.

[0021] In some embodiments, the output module includes a second transistor and a third transistor; wherein,

[0022] The gate of the second transistor is connected to the output of the first processing module, the gate of the third transistor is connected to the output of the second processing module, one end of the second transistor is connected to the power supply, and one end of the third transistor is connected to the ground.

[0023] The other end of the second transistor is connected to the other end of the third transistor for outputting the target transmission signal.

[0024] In some embodiments, the initial data signal is generated based on the data signal obtained by the data transmission circuit when the first enable signal is active; wherein...

[0025] When the data signal is a first value, the first initial data signal is determined to be in a first level state, and the second initial data signal is determined to be in a second level state;

[0026] When the data signal is the second value, the first initial data signal is determined to be in the second level state, and the second initial data signal is in the first level state.

[0027] In some embodiments, the output module further includes a second switching unit; wherein,

[0028] The output module is configured to receive a second enable signal and, when the second enable signal is active, turn on the second switching unit; and, if the data signal is a first value, turn on the third transistor according to the second driving signal, so that the target transmission signal is at a first level; or, if the data signal is a second value, turn on the second transistor according to the first driving signal, so that the target transmission signal is at a second level.

[0029] In some embodiments, the first enable signal and the second enable signal include at least one of the following: a read operation signal, a write operation signal, a row address strobe pulse signal, a column address strobe pulse signal, and an activation operation signal.

[0030] In some embodiments, the data transmission circuit further includes a receiving module; wherein,

[0031] The processing module is further configured to send the target transmission signal to the receiving module after obtaining the target transmission signal.

[0032] In some embodiments, when the first enable signal includes a read operation signal, the receiving module includes a data pad;

[0033] When the first enable signal includes a write operation signal, the receiving module includes a storage unit.

[0034] Secondly, embodiments of this disclosure provide a data transmission method, the method comprising:

[0035] Receive the first enable signal;

[0036] When the first enable signal is active, the first switching unit is turned on to receive the initial data signal;

[0037] The initial data signal is driven to obtain the target transmission signal; wherein the initial data signal is generated based on the data signal obtained by the data transmission circuit when the first enable signal is in an active state.

[0038] In some embodiments, the initial data signal includes a first initial data signal and a second initial data signal, and the level states of the first initial data signal and the second initial data signal are opposite.

[0039] Accordingly, the step of driving the initial data signal to obtain the target transmission signal includes:

[0040] The first initial data signal is processed by the first processing module to obtain the first driving signal;

[0041] The second initial data signal is processed by the second processing module to obtain the second driving signal;

[0042] The output module receives the first driving signal and the second driving signal, and outputs the target transmission signal.

[0043] In some embodiments, the method further includes:

[0044] When the data signal is a first value, the first initial data signal is determined to be in a first level state, and the second initial data signal is determined to be in a second level state;

[0045] When the data signal is the second value, the first initial data signal is determined to be in the second level state, and the second initial data signal is in the first level state.

[0046] In some embodiments, the method further includes:

[0047] When the second enable signal is active, the second switching unit is turned on;

[0048] Accordingly, when the second switching unit is turned on, the method further includes:

[0049] If the data signal is a first value, then the third transistor is turned on according to the second driving signal, so that the target transmission signal is in a first level state;

[0050] If the data signal is the second value, then the second transistor is turned on according to the first driving signal, so that the target transmission signal is in the second level state.

[0051] In some embodiments, the first enable signal and the second enable signal include at least one of the following: a read operation signal, a write operation signal, a row address strobe pulse signal, a column address strobe pulse signal, and an activation operation signal.

[0052] Thirdly, embodiments of this disclosure provide a semiconductor memory including a data transmission circuit as described in any of the first aspects.

[0053] This disclosure provides a data transmission circuit, method, and semiconductor memory. The data transmission circuit includes a control module and a processing module. The control module receives a first enable signal and controls the processing module to operate when the first enable signal is active, and controls the processing module to operate in a non-active state when the first enable signal is inactive. The processing module, when operating, receives an initial data signal and performs driving processing on the initial data signal to obtain a target transmission signal. By controlling the operating state of the processing module through the first enable signal and the control module, the processing module operates only when the first enable signal is active, thereby reducing leakage current in the data transmission circuit, saving power consumption, and preventing excessive leakage current from damaging the circuit. Attached Figure Description

[0054] Figure 1 A schematic diagram of the composition structure of a data transmission circuit provided in an embodiment of this disclosure. Figure 1 ;

[0055] Figure 2 A schematic diagram of the composition structure of a data transmission circuit provided in an embodiment of this disclosure. Figure 2 ;

[0056] Figure 3 A schematic diagram of the circuit structure of a data transmission circuit provided in this embodiment of the present disclosure. Figure 1 ;

[0057] Figure 4 A partial circuit structure diagram of a data transmission circuit provided in this embodiment of the present disclosure. Figure 1 ;

[0058] Figure 5 A schematic diagram of the circuit structure of a data transmission circuit provided in this embodiment of the present disclosure. Figure 2 ;

[0059] Figure 6 A signal timing diagram provided for an embodiment of this disclosure Figure 1;

[0060] Figure 7 A schematic diagram of the circuit structure of a data transmission circuit provided in this embodiment of the present disclosure. Figure 3 ;

[0061] Figure 8 A partial circuit structure diagram of a data transmission circuit provided in this embodiment of the present disclosure. Figure 2 ;

[0062] Figure 9 A schematic diagram of the circuit structure of a data transmission circuit provided in this embodiment of the present disclosure. Figure 4 ;

[0063] Figure 10 A signal timing diagram provided for an embodiment of this disclosure Figure 2 ;

[0064] Figure 11 A schematic flowchart illustrating a data transmission method provided in an embodiment of this disclosure;

[0065] Figure 12 This is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of this disclosure. Detailed Implementation

[0066] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the relevant disclosure and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0067] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure.

[0068] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0069] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0070] Taking a data readout driver circuit as an example, the data readout driver circuit can acquire data stored in the memory, process this data, and further output signals representing this data. However, leakage current is usually generated inside the circuit, which leads to a relatively large static power consumption when the circuit is not working, and may even damage the circuit, causing problems when the circuit is working.

[0071] Based on this, embodiments of this disclosure provide a data transmission circuit, including a control module and a processing module. The control module receives a first enable signal and controls the processing module to operate when the first enable signal is active, and controls the processing module to operate in a non-active state when the first enable signal is inactive. The processing module, when operating, receives an initial data signal and performs driving processing on the initial data signal to obtain a target transmission signal. Thus, by controlling the operating state of the processing module through the first enable signal and the control module, the processing module operates only when the first enable signal is active. Since there is no leakage path in the circuit when the processing module is inactive, leakage current generated by the data transmission circuit can be reduced, power consumption can be saved, and excessive leakage current can be avoided from damaging the circuit.

[0072] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0073] In one embodiment of this disclosure, see [link to embodiment]. Figure 1 It illustrates a schematic diagram of the composition structure of a data transmission circuit 10 provided in an embodiment of this disclosure. Figure 1 .like Figure 1 As shown, the data transmission circuit 10 may include a control module 11 and a processing module 12, wherein,

[0074] The control module 11 is used to receive a first enable signal, and when the first enable signal is in an active state, the control processing module 12 is in an active state, and when the first enable signal is in an inactive state, the control processing module 12 is in an inactive state.

[0075] The processing module 12 is used to receive the initial data signal and perform driving processing on the initial data signal to obtain the target transmission signal when it is in the working state.

[0076] It should be noted that the first enable signal can be a signal related to the operation performed by the processing module 12. For example, the first enable signal can include at least one of the following: a read operation signal, a write operation signal, a row address strobe pulse signal, a column address strobe pulse signal, and an activation operation signal. In addition, the first enable signal can also be other types of signals, and this embodiment does not specifically limit them.

[0077] After receiving the first enable signal, the control module 11 controls the operating state of the processing module 12 based on the state of the first enable signal. When the first enable signal is valid, the control module 12 is in the working state, enabling it to operate normally and perform corresponding operations; when the first enable signal is invalid, the control module 12 is in the non-working state, preventing it from working. Thus, when the first enable signal is invalid, the processing module 12 does not work, and therefore no power is consumed. Compared to circuits that remain in the conducting state in standby mode, this reduces leakage current and saves power.

[0078] The valid and invalid states can be determined based on the level of the first enable signal. In some embodiments, when the first enable signal is at a first level, it is determined that the first enable signal is in an invalid state; when the first enable signal is at a second level, it is determined that the first enable signal is in a valid state. The first level can be low, and the second level can be high.

[0079] It should be noted that the first enable signal can be a periodically or non-periodically changing waveform or pulse, and its level state can vary between a first level state and a second level state. When the first enable signal is in the low-level first level state, it is determined that the first enable signal is in an inactive state; when the first enable signal is in the high-level second level state, it is determined that the first enable signal is in an active state. In some cases, the first enable signal may also be active when it is low and inactive when it is high, which is related to the specific signal type and application scenario, and this disclosure does not specifically limit it. This disclosure defines the first level state as low and the second level state as high for ease of description.

[0080] In addition, the first enable signal can also be a digital control code, with different numbers representing different states. For example, the first enable signal can be composed of the numerical control code "0" and / or "1" (or other numbers). When the first enable signal is "1", it indicates that the first enable signal is in an active state, and when the first enable signal is "0", it indicates that the first enable signal is in an inactive state, thereby realizing the control of the processing module 12.

[0081] When the processing module 12 is in operation, it receives the initial data signal and performs driving processing on the initial data signal to obtain the target transmission signal. After obtaining the target transmission signal, the target transmission signal can be output, for example, transmitted to other data ports in the circuit or other chips, memory controllers, etc.; or, the target transmission signal can be written, for example, in Dynamic Random Access Memory (DRAM), the target transmission signal can be written into its storage cell 1 transistor 1 capacitor (1T1C).

[0082] In this embodiment of the disclosure, the initial data signal can be generated by the data signal obtained by the data transmission circuit 10 performing related operations when the first enable signal is in an active state. For example, the data transmission circuit 10 is a circuit with a read function. When the first enable signal is a read operation signal and is in an active state, the data transmission circuit 10 performs a read operation to obtain a read data signal and processes the obtained read data signal to obtain the initial data signal; or, the obtained read data signal can be directly used as the initial data signal. This embodiment of the disclosure does not specifically limit this. When the first enable signal is a write operation signal and is in an active state, the data transmission circuit 10 performs a write operation to obtain a write data signal and processes the obtained write data signal to obtain the initial data signal.

[0083] Regarding control module 11, in some embodiments, see [link to relevant documentation]. Figure 2 It illustrates a schematic diagram of the composition structure of a data transmission circuit 10 provided in an embodiment of this disclosure. Figure 2 .like Figure 2 As shown, the control module 11 may include a switching unit 111; wherein,

[0084] Control module 11 is configured to control switch unit 111 to conduct when the first enable signal is active, thereby enabling processing module 12 to operate; and

[0085] The control module 11 is also used to control the switch unit 111 to turn off when the first enable signal is in an invalid state, so that the processing module 12 is in a non-working state.

[0086] It should be noted that, in this embodiment, the processing module 12 can be controlled via the switching unit 111. When the first enable signal is active, the switching unit 111 is turned on, thereby turning on the processing module 12 and putting it into operation. When the first enable signal is inactive, the switching unit 111 is turned off, thereby turning off the processing module 12 and putting it into a non-operational state. By controlling the switching unit 111 to be on or off according to the state of the first enable signal, the processing module 12 is controlled to operate or not operate, thus avoiding power consumption caused by the processing module 12 still operating when it is not needed.

[0087] The switching unit 111 can be a diode, transistor, field-effect transistor, thyristor, or other components with switching control functions. This embodiment does not specifically limit the specific components in this embodiment.

[0088] Taking the switching unit 111 as a field-effect transistor as an example, when the switching unit 111 includes a first transistor, the first transistor may include a first terminal, a second terminal, and a third terminal; wherein,

[0089] The first terminal is coupled to the first enable signal, the second terminal is coupled to the power supply terminal or the ground terminal, and the third terminal is coupled to the processing module 12.

[0090] It should be noted that the first terminal of the first transistor is a control terminal, coupled to the first enable signal, used to receive the first enable signal. The voltage change at the first terminal can turn the first transistor on or off. The second terminal is coupled to the power supply terminal or the ground terminal; the third terminal is coupled to the processing module 12 to realize the state control of the processing module 12, so that the processing module 12 is in a working state or a non-working state.

[0091] The connection and operation of the first transistor will be explained in detail below, taking an N-channel metal-oxide-semiconductor (NMOS) and a P-channel metal-oxide-semiconductor (PMOS) as examples.

[0092] When the first transistor is an NMOS transistor, see Figure 3 It shows a schematic diagram of the circuit structure of a data transmission circuit 10 provided in an embodiment of this disclosure. Figure 1 .like Figure 3As shown, when the first transistor T1 is an NMOS transistor, the first terminal of the first transistor T1 is the gate terminal, which is directly connected to the first enable signal and used to receive the first enable signal; the second terminal of the first transistor T1 is the source terminal, which is connected to the ground terminal; and the third terminal of the first transistor T1 is the drain terminal, which is connected to the processing module 12.

[0093] like Figure 3 As shown, the processing module 12 may include a first processing module 121 and a second processing module 122. The first processing module 121 includes an even number of first inverters 1211, and the second processing module 122 includes an even number of second inverters 1221. The ground port (Vss_Footer) of each first inverter 1211 and each second inverter 1221 in the processing module 12 is connected to the drain terminal of the first transistor T1. Figure 3 Only the connection between the first transistor T1 and each of the second inverters 1221 is shown. It can be understood that the drain terminal of the first transistor T1 is also connected to each of the first inverters 1211 in the first processing module 121, only in... Figure 3 Not shown in the diagram. In addition, each first inverter 1211 and each second inverter 1221 also includes a power supply port (Vdd_Footer) not shown, and the power supply port is connected to a power supply.

[0094] In a specific example, see Figure 4 It shows a partial circuit structure diagram of a data transmission circuit 10 provided in an embodiment of this disclosure. Figure 1 Its corresponding Figure 3 The circuit structure and connection method of the second processing module 122. For example... Figure 4 As shown, for any one of the second inverters 1221, the second inverter 1221 is composed of a PMOS transistor P1 and an NMOS transistor N1; wherein, the gate terminals of P1 and N1 are both connected to the initial data signal, the drain terminal of P1 and the drain terminal of N1 are connected, the source terminal of P1 is the power supply port (Vdd_Footer) of the second inverter 1221, and is connected to the power supply terminal; the source terminal of N1 is the ground port (Vss_Footer) of the second inverter 1221, and is connected to the drain terminal of the first transistor T1.

[0095] In addition, although Figure 4 The first processing module 121 is not shown, but the composition and connection method of the first processing module 121 and the second processing module 122 are basically the same (the difference is that the number of the second inverter 1221 and the first inverter 1211 may be different). Each first inverter 1211 in the first processing module 121 is also connected to the first transistor T1 and the power supply terminal respectively, which will not be described in detail here.

[0096] In other words, the drain terminal of the first transistor T1 is connected to the source terminal of N1 in each first inverter 1211 and each second inverter 1221, thereby realizing the state control of the processing module 12.

[0097] It should be noted that the control of the first processing module 121 and the second processing module 122 by the first transistor T1 is synchronized. Therefore, the following text combines... Figure 3 and Figure 4 Taking the second processing module 122 as an example, the control process will be described in detail.

[0098] An NMOS transistor is turned off when the gate is low and turned on when the gate is high. Figure 3 or Figure 4 In this circuit, the gate of the first transistor T1 directly receives the first enable signal, or the first enable signal can be transmitted through a series of devices (such as inverters, D flip-flops, etc.) before reaching the gate of the first transistor T1. When the first enable signal is high, the first transistor T1 is turned on, and the drain of the first transistor T1 is clamped to the ground voltage (VSS), so that the source terminal (i.e., Vss_Footer) of N1 connected to the first transistor T1 is clamped to the ground voltage (VSS), thereby turning on both the second inverter 1221 and the first inverter 1211, and the processing module 12 is in the working state. When the first enable signal is low, the first transistor T1 is turned off, and the voltage at the drain of the first transistor T1 is in a floating state between the ground voltage (VSS) and the internal voltage (VCC), and neither the second inverter 1221 nor the first inverter 1211 is turned on, and the processing module 12 is in the non-working state.

[0099] In other words, for a first enable signal that is active at a high level, the first transistor T1 will only be turned on while the first enable signal is at a high level, thus putting the processing module 12 into operation. For example, this signal can be a read operation signal (RdEn).

[0100] Furthermore, for certain types of first enable signals, their effective state is low, meaning that the processing module 12 operates when the first enable signal is low. In this case, an inverter can be added before the first transistor T1 to invert the first enable signal. The inverted first enable signal controls the first transistor T1 to turn on or off as needed.

[0101] See Figure 5 It shows a schematic diagram of the circuit structure of a data transmission circuit 10 provided in an embodiment of this disclosure. Figure 2 .like Figure 5As shown, the first transistor T1 is an NMOS transistor. The control module 11 also includes an inverter 112. The first terminal of the first transistor T1 is the gate terminal, which is connected to the output terminal of the inverter 112. The input terminal of the inverter 112 receives the first enable signal. The inverter 112 inverts the first enable signal to obtain the inverted first enable signal. The second terminal of the first transistor T1 is the source terminal, which is connected to the ground terminal. The third terminal of the first transistor T1 is the drain terminal, which is connected to the processing module 12.

[0102] In this way, the first enable signal is inverted by the inverter 112 to obtain the inverted first enable signal, so that the gate terminal of the first transistor T1 receives the inverted first enable signal, thereby realizing the correct control of the circuit.

[0103] For example, see Figure 6 It illustrates a signal timing diagram provided in an embodiment of this disclosure. Figure 1 It shows a timing diagram of the control of the data transmission circuit 10 when the processing module 12 performs a read operation. In this diagram, (a) indicates that the read operation signal is used as the first enable signal for... Figure 3 When the circuit shown is controlled, the signal timing of the read operation signal and the voltage change at the ground port are observed; (b) indicates that the following electrical signal (Pdn) is the first enable signal. Figure 4 When the circuit shown is controlled, the signal timing of the power-down signal, the signal timing of the inverted power-down signal, and the voltage change at the grounding port are recorded.

[0104] like Figure 6 As shown in (a), when the read operation signal is low, it indicates that no read operation is required during this period. The first transistor T1 is not turned on, and the voltage at the ground port is between the ground voltage (VSS) and the internal voltage (VCC). The ground port is not connected to the ground terminal, making the processing module 12 non-operating. When the read operation signal is high, it indicates that the circuit needs to perform a read operation during this period. The first transistor T1 is turned on, and the voltage at the ground port is clamped to the ground voltage (VSS). The ground port is connected to the ground terminal, making the processing module 12 operational.

[0105] like Figure 6As shown in (b), when the power-down signal is at a high level, it indicates that the circuit needs to be in a power-down state (or standby state), and the processing module 12 needs to be in a non-working state. At this time, the inverted power-down signal is at a low level, the first transistor T1 is not turned on, and the processing module 12 is in a non-working state. When the power-down signal is at a low level, it indicates that the circuit needs to exit the power-down state and start working, and the processing module 12 needs to be in a working state. At this time, the inverted power-down signal is at a high level, the first transistor T1 is turned on, the voltage of the ground port is clamped to the ground voltage (VSS), the ground port is connected to the ground terminal, and the processing module 12 is in a working state.

[0106] As can be seen, by controlling the on and off of the first transistor T1 through the first enable signal, the processing module 12 is controlled to operate only during the period when the first enable signal is valid, thereby reducing the leakage current generated by the processing module 12 and reducing power consumption. Specifically, this mainly involves controlling the first inverter 1211 and the second inverter 1221 in the processing module 12 to operate or not operate, thereby reducing the leakage current generated by the first inverter 1211 and the second inverter 1221.

[0107] When the first transistor T1 is a PMOS transistor, see [link to relevant documentation]. Figure 7 It shows a schematic diagram of the circuit structure of a data transmission circuit 10 provided in an embodiment of this disclosure. Figure 3 .like Figure 7 As shown, when the first transistor T1 is a PMOS transistor, the control module 11 also includes an inverter 113. The first terminal of the first transistor T1 is the gate terminal, which is connected to the output terminal of the inverter 113. The input terminal of the inverter 113 is connected to a first enable signal. The inverter 113 inverts the first enable signal to obtain an inverted first enable signal. The inverted first enable signal is used to control the first transistor T1 to be turned on or off. The second terminal of the first transistor T1 is the source terminal, which is connected to the power supply terminal. The third terminal of the first transistor T1 is the drain terminal, which is connected to the processing module 12.

[0108] Figure 7 The processing module 12 and Figure 3 The processing module 12 in the same way has the same structure, except that the connection method of the inverter and the first transistor T1 is different. For example Figure 7 As shown, the power supply port (Vdd_Footer) of each first inverter 1211 and each second inverter 1221 is connected to the drain terminal of the first transistor T1. Figure 7 Only the connection between the first transistor T1 and each of the first inverters 1211 is shown. It can be understood that the drain terminal of the first transistor T1 is also connected to each of the second inverters 1221 in the second processing module 122, only in... Figure 7 Not shown in the diagram. In addition, each first inverter 1211 and each second inverter 1221 also includes a ground port (Vss_Footer) not shown, and the ground port is connected to the ground terminal.

[0109] In a specific example, see Figure 8 It shows a partial circuit structure diagram of a data transmission circuit 10 provided in an embodiment of this disclosure. Figure 2 ,correspond Figure 7 The circuit structure and connection method of the first processing module 121. For example... Figure 8 As shown, for each first inverter 1211, the first inverter 1211 consists of a PMOS transistor P1 and an NMOS transistor N1; wherein, the gate terminals of P1 and N1 are both connected to the initial data signal, the drain terminal of P1 and the drain terminal of N1 are connected, the source terminal of P1 is the power supply port (Vdd_Footer) of the first inverter 1211, and is connected to the drain terminal of the first transistor T1, and the source terminal of N1 is the ground port (Vss_Footer) of the first inverter 1211, and is connected to the ground terminal.

[0110] In addition, although Figure 8 The second processing module 122 is not shown, but the composition and connection method of the first processing module 121 and the second processing module 122 are basically the same (the difference is that the number of the second inverter 1221 and the first inverter 1211 may be different). Each second inverter 1221 in the second processing module 122 is also connected to the first transistor T1 and the ground terminal respectively, which will not be described in detail here.

[0111] In other words, the drain terminal of the first transistor T1 is connected to the source terminal of P1 in each first inverter 1211 and each second inverter 1221, thereby realizing the state control of the processing module 12.

[0112] It should be noted that the control of the first processing module 121 and the second processing module 122 by the first transistor T1 is synchronized. Therefore, the following text combines... Figure 7 and Figure 8 Taking the first processing module 121 as an example, the control process will be described in detail.

[0113] The PMOS transistor turns on when the gate is low and turns off when the gate is high. Figure 7 or Figure 8In the first transistor T1, the gate terminal receives the inverted first enable signal. When the first enable signal is high, the inverted first enable signal is low, causing the first transistor T1 to turn on. The drain terminal of the first transistor T1 is clamped to the power supply voltage (VDD), causing the source terminal (Vdd_Footer) of P1 connected to the first transistor T1 to be clamped to the power supply voltage. Thus, both the first inverter 1211 and the second inverter 1221 are turned on, and the processing module 12 is in the working state. When the first enable signal is low, the inverted first enable signal is high, causing the first transistor T1 to turn off. The voltage at the drain terminal of the first transistor T1 is in a floating state between the power supply voltage (VDD) and the internal voltage (VCC). Both the first inverter 1211 and the second inverter 1221 are not turned on, and the processing module 12 is in the non-working state.

[0114] In other words, for a first enable signal that is active at a high level, the first transistor T1 will only be turned on while the first enable signal is at a high level, thus enabling the processing module 12 to operate. For example, this signal can be a read operation signal.

[0115] Furthermore, for certain types of first enable signals, their effective state is low, meaning that processing module 12 operates when the first enable signal is low. In this case, inverter 113 can be removed from control module 11, allowing the first transistor T1 to be turned on or off as needed.

[0116] See Figure 9 It shows a schematic diagram of the circuit structure of a data transmission circuit 10 provided in an embodiment of this disclosure. Figure 4 .like Figure 9 As shown, the first transistor is a PMOS transistor. The first terminal of the first transistor T1 is the gate terminal, which directly receives the first enable signal. Alternatively, the first enable signal can be transmitted through a series of devices (such as inverters, D flip-flops, etc.) before reaching the gate of the first transistor T1. The second terminal of the first transistor T1 is the source terminal, which is connected to the power supply terminal. The third terminal of the first transistor T1 is the drain terminal, which is connected to the processing module 12.

[0117] In this way, the gate terminal of the first transistor T1 can directly receive the first enable signal, thereby achieving correct control of the circuit.

[0118] For example, see Figure 10 It illustrates a signal timing diagram provided in an embodiment of this disclosure. Figure 2 It shows a timing diagram of the control of the data transmission circuit 10 when the processing module 12 performs a read operation. In this diagram, (a) indicates that the read operation signal is used as the first enable signal for... Figure 7When the circuit shown is controlled, the signal timing of the read operation signal, the signal timing of the inverted read operation signal, and the voltage change at the power supply port are shown; (b) indicates that the following electrical signal is the first enable signal. Figure 7 The circuit shown illustrates the signal timing of the power-down signal and the voltage changes at the grounding port when the circuit is controlled.

[0119] like Figure 10 As shown in (a), when the read operation signal is low, the inverted read operation signal is high, the first transistor T1 is not turned on, the ground port is between the power supply voltage (VDD) and the internal voltage (VCC), and the ground port is not connected to the power supply terminal, making the processing module 12 non-operating. When the read operation signal is high, it indicates that the circuit needs to perform a read operation during this period. The inverted read operation signal is low, the first transistor T1 is turned on, the ground port is clamped to the power supply voltage (VDD), and the ground port is connected to the power supply terminal, making the processing module 12 operational.

[0120] like Figure 10 As shown in (b), when the current electrical signal is at a high level, it indicates that the processing module 12 needs to be in a non-working state. At this time, the first transistor T1 is not turned on, and the processing module 12 is in a non-working state. When the current electrical signal is at a low level, it indicates that the processing module 12 needs to be in a working state. At this time, the first transistor T1 is turned on, and the processing module 12 is in a working state.

[0121] Furthermore, combined Figure 6 and Figure 10 It can also be seen that, compared with using the write operation signal as the first enable signal, using the write operation signal as the first enable signal to control the first transistor T1 (whether it is an NMOS or PMOS transistor) can more accurately control the processing module 12 to be in the working state only during the read operation period, and in the non-working state at other times. This can save more leakage current and reduce circuit power consumption better. Therefore, in practical applications, a suitable first enable signal can be set by combining the characteristics of different signals and the specific requirements of the circuit to achieve accurate control of the processing module 12.

[0122] For processing module 12, in one specific implementation, the initial data signal includes a first initial data signal and a second initial data signal, and the level states of the first initial data signal and the second initial data signal are opposite; for example... Figure 3 (or Figure 7 As shown in the figure, the processing module 12 may include:

[0123] The first processing module 121 is used to drive the first initial data signal to obtain the first driving signal when the processing module 12 is in the working state.

[0124] The second processing module 122 is used to drive the second initial data signal to obtain the second driving signal when the processing module 12 is in the working state.

[0125] The output module 123 is used to obtain the target transmission signal based on the first driving signal and the second driving signal.

[0126] It should be noted that, with Figure 3 For example, processing module 12 can be a data readout driving circuit, consisting of a first processing module 121, a second processing module 122, and an output module 123. This circuit can be used to perform a read operation, read out the data, and then transmit it. The initial data signal can include a first initial data signal and a second initial data signal, which are generated based on the data signal read by the data transmission circuit 10 when the read operation signal is active.

[0127] The data transmission circuit 10 may further include a readout module (not shown in the figure) for reading data signals from a storage module (e.g., a storage cell, not shown in the figure) and performing related processing on the data signals to obtain a first initial data signal and a second initial data signal.

[0128] For example, the readout module may include two parts. After reading the data signal, the first part directly transmits the data signal as the first initial data signal to the first processing module 121. Alternatively, the first part may include an even number of inverters to perform an even number of inversions on the data signal to obtain a first initial data signal with the same logical state as the read data signal. The second part may include one inverter to perform an inversion on the read data signal after reading it, and transmit the inverted data signal as the second initial data signal to the second processing module 122. Alternatively, the second part may include an odd number of inverters to perform an odd number of inversions on the data signal to obtain a second initial data signal with the opposite logical state to the read data signal.

[0129] In other words, the level states of the first initial data signal and the second initial data signal are opposite.

[0130] Therefore, in some embodiments, when the data signal is a first value, the first initial data signal is determined to be a first level state, and the second initial data signal is determined to be a second level state;

[0131] When the data signal is the second value, the first initial data signal is determined to be in the second level state, and the second initial data signal is determined to be in the first level state.

[0132] It should be noted that data signals can be stored in the memory unit in the form of logic "1" or logic "0". Here, the first value can represent logic "0" and the second value can represent logic "1". Logic "1" corresponds to a high level and logic "0" corresponds to a low level. When the data signal is the first value, the first initial data signal is determined to be in the first level state, that is, a low level, and the second initial data signal is determined to be in the second level state, that is, a high level. When the data signal is the second value, the first initial data signal is determined to be in the second level state, and the second initial data signal is determined to be in the first level state.

[0133] When the processing module 12 is in operation, the first processing module 121 receives the first initial data signal and performs driving processing on the first initial data signal to obtain the first driving signal; the second processing module 122 receives the second initial data signal and performs driving processing on the second initial data signal to obtain the second driving signal; the output module 123 obtains the target transmission signal based on the first driving signal and the second driving signal, and outputs the target transmission signal or transmits it to other ports, modules, etc. in the circuit.

[0134] See Figure 3 or Figure 7 The data transmission circuit 10 may further include a receiving module 14, wherein,

[0135] The processing module 12 is also used to send the target transmission signal to the receiving module 14 after obtaining the target transmission signal.

[0136] It should be noted that the receiving module 14 can be used to receive the target transmission signal obtained after processing by the processing module 12.

[0137] In some embodiments, when the first enable signal includes a read operation signal, the receiving module 14 may include a data pad; when the first enable signal includes a write operation signal, the receiving module 14 may include a storage unit.

[0138] It should be noted that the data transmission circuit 10 can be a circuit with a read function. In this case, the first enable signal can be a read operation signal, and the corresponding receiving module 14 can be a data pad (DQPAD). The processing module 12 sends the target transmission signal obtained after reading and processing to the data pad to realize the reading and transmission of data.

[0139] The data transmission circuit 10 can also be a circuit with a write function. In this case, the first enable signal can be a write operation signal, and the corresponding receiving module 14 can be a storage unit. For example, for DRAM, the storage unit can be a 1T1C unit. After the processing module 12 obtains the target transmission signal, it can perform write processing on the target transmission data to realize the writing of data into the storage unit.

[0140] For example, the first processing module 121 can be a pull-up circuit, and the first initial data signal can be a pull-up signal (DataPU); the second processing module 122 can be a pull-down circuit, and the second initial data signal can be a pull-down signal (DataPD).

[0141] For processing module 12, refer to Figure 3 (or Figure 7 In a specific example, such as Figure 3 As shown, the first processing module 121 may include N first inverters 1211; wherein, the input terminal of the first first inverter 1211 receives the first initial data signal, the output terminal of the i-th first inverter 1211 is connected to the input terminal of the (i+1)-th first inverter 1211, the output terminal of the N-th first inverter 1211 is used to output the first drive signal, and the enable terminals of the N first inverters 1211 are all connected to the control module 11, where i is an integer greater than 0 and less than N, and N is an even number greater than 0;

[0142] The second processing module 122 includes M second inverters 1221; wherein, the input terminal of the first second inverter 1221 receives the second initial data signal, the output terminal of the j-th second inverter 1221 is connected to the input terminal of the (j+1)-th second inverter 1221, the output terminal of the M-th second inverter 1221 is used to output the second drive signal, and the enable terminals of the M second inverters 1221 are all connected to the control module 11, where j is an integer greater than 0 and less than M, and M is an even number greater than 0.

[0143] It should be noted that, as Figure 3 (or Figure 7 As shown in the diagram, the first processing module 121 may include four first inverters 1211, and the second processing module 122 may include four second inverters 1221. The number of first inverters 1211 and second inverters 1221 may also be 2, 6, or 8, etc. The number of first inverters 1211 and second inverters 1221 may be the same or different, and this embodiment does not specifically limit this.

[0144] It should also be noted that, in this embodiment of the present disclosure, both the first processing module 121 and the second processing module 122 include an even number of inverters. For example, as Figure 3As shown, the first processing module 121 includes four first inverters 1211. These four first inverters 1211 drive and enhance the first initial data signal, so that the final first driving signal is an enhanced signal. The signal strength will not be too weak due to loss during transmission, thus avoiding misreading or signal loss. The same applies to the second processing module 122, which will not be described in detail here.

[0145] In addition, for Figure 3 The data transmission circuit 10 shown is in conjunction with the reference. Figure 4 The enable terminals of the first inverter 1211 and the second inverter 1221 are the sources of N1, which are also the ground ports (Vss_Footer). For Figure 7 The data transmission circuit 10 shown is in conjunction with the reference. Figure 9 The enable terminals of the first inverter 1211 and the second inverter 1221 are the source terminals of P1, which are the power supply ports (Vdd_Footer).

[0146] The circuit structures of the first processing module 121 and the second processing module 122 can be referred to Figure 4 and Figure 8 This is based on the relevant descriptions and will not be elaborated upon here.

[0147] In this way, by controlling the on and off states of the first transistor T1 through the first enable signal, the voltage state of the enable terminals of the first inverter 1211 and the second inverter 1221 can be controlled, thereby causing the first inverter 1211 and the second inverter 1221 to be turned on or off, thereby controlling the first processing module 121 and the second processing module 122 to work normally only when the first enable signal is in an active state, reducing the generation of leakage current.

[0148] Regarding the output module 123 in the processing module 12, in some embodiments, such as Figure 3 (or Figure 7 As shown in the figure, the output module 123 may include a second transistor T2 and a third transistor T3; wherein,

[0149] The gate of the second transistor T2 is connected to the output of the first processing module 121, the gate of the third transistor T3 is connected to the output of the second processing module 122, one end of the second transistor T2 is connected to the power supply terminal, and one end of the third transistor T3 is connected to the ground terminal.

[0150] The other end of the second transistor T2 is connected to the other end of the third transistor T3, and is used to output the target transmission signal.

[0151] It should be noted that, in this embodiment, the output module 123 may include a second transistor T2 and a third transistor T3. The gate of the second transistor T2 is connected to the output of the first processing module 121 to receive a first driving signal, and the gate of the third transistor T3 is connected to the output of the second processing module 122 to receive a second driving signal. Each of the second transistor T2 and the third transistor T3 also has one end connected to a power supply terminal and a ground terminal, respectively, and another end of each transistor is connected together to output a target transmission signal. The second transistor T2 and the third transistor T3 can be NMOS transistors or PMOS transistors, and their types can be the same or different.

[0152] For example, such as Figure 3 As shown, the second transistor T2 and the third transistor T3 can both be NMOS transistors; wherein, the gate terminal of the second transistor T2 is connected to the output terminal of the first processing module 121, that is, connected to the output terminal of the Nth first inverter 1211, for receiving the first drive signal, and the source terminal of the second transistor T2 is connected to the power supply terminal; the gate terminal of the third transistor T3 is connected to the output terminal of the second processing module 122, that is, connected to the output terminal of the Mth second inverter 1221, for receiving the second drive signal, and the source terminal of the third transistor T3 is connected to the ground terminal; the drain terminal of the second transistor T2 is connected to the drain terminal of the third transistor T3 for outputting the target transmission signal.

[0153] For example, if the data signal is the second value logic "1", then the first initial data signal is also logic "1" and the second initial data signal is logic "0". After the first processing module 121 performs driving processing on the first initial data signal, the resulting first driving signal is also logic "1". After the second processing module 122 performs driving processing on the second initial data signal, the resulting second driving signal is also logic "0". Then the gate of the second transistor T2 receives a high level, and the second transistor T2 is turned on. The gate of the third transistor T3 receives a low level, and the third transistor T3 is turned off. The turned-on second transistor T2 clamps its source to the power supply voltage and outputs a high-level signal, that is, the target transmission signal is logic "1", thereby realizing the correct reading of data.

[0154] For example, if the data signal is a first value logic "0", then the first initial data signal is also logic "0", and the second initial data signal is logic "1". After the first processing module 121 performs driving processing on the first initial data signal, the resulting first driving signal is also logic "0". After the second processing module 122 performs driving processing on the second initial data signal, the resulting second driving signal is also logic "1". Then the gate of the second transistor T2 receives a low level, the second transistor T2 is turned off, the gate of the third transistor T3 receives a high level, and the third transistor T3 is turned on. The turned-on third transistor T3 clamps its drain to the ground voltage and outputs a low-level signal, that is, the target transmission signal is logic "0", thereby realizing the correct reading of data.

[0155] In some embodiments, the output module further includes a second switching unit 15; wherein,

[0156] The output module 123 is used to receive a second enable signal and, when the second enable signal is in an active state, to turn on the second switch unit 15; and if the data signal is a first value, to turn on the third transistor T3 according to the second drive signal so that the target transmission signal is in a first level state; or, if the data signal is a second value, to turn on the second transistor T2 according to the first drive signal so that the target transmission signal is in a second level state.

[0157] It should be noted that, in this embodiment, a second switching unit 15 can be added to the data transmission circuit 10. The second switching unit 15 can be a diode, transistor, field-effect transistor, thyristor, or other component with switching control function; this embodiment does not specifically limit its application. By controlling the conduction or disconnection of the second switching unit 15 to determine whether the second transistor T2 and the third transistor T3 enter the working state, leakage current can be avoided in the standby state of the second transistor T2 and the third transistor T3, thereby saving power consumption.

[0158] For example, such as Figure 3 or Figure 7 As shown, the second switching unit 15 may include a fourth transistor T4. Specifically, the fourth transistor T4 may be an NMOS transistor. The gate of the fourth transistor T4 receives a second enable signal, its source is connected to the power supply terminal, and its drain is connected to the source of the second transistor T2. That is, one end of the second transistor T2 is connected to the power supply terminal through the second switching unit 15. When the second enable signal is active, the fourth transistor T4 is turned on, and when the second enable signal is inactive, the fourth transistor T4 is turned off.

[0159] When the fourth transistor T4 is turned on, if the data signal is the first value and is in a low-level state, then the logic state of the first drive signal is the same as that of the data signal, which is also a low-level state, so the second transistor T2 will not be turned on. At the same time, the logic state of the second drive signal is opposite to that of the data signal, which is a high-level state, so the third transistor T3 is turned on. At this time, the drain terminal of the third transistor T3 is pulled to the ground voltage VSS, so the output target transmission signal is in a low-level state, i.e., the first level state.

[0160] When the fourth transistor T4 is turned on, if the data signal is the second value and is in a high-level state, then the logic state of the first drive signal is the same as that of the data signal, which is also a high-level state, thus turning on the second transistor T2. At the same time, the logic state of the second drive signal is opposite to that of the data signal, which is a low-level state, thus preventing the third transistor T3 from turning on. At this time, the drain terminal of the second transistor T2 is pulled to the power supply voltage VDD, so the output target transmission signal is in a high-level state, i.e., the second-level state.

[0161] In other words, in this embodiment of the disclosure, the first processing module 121 mainly outputs the second value, and the second processing module 122 mainly outputs the first value.

[0162] Alternatively, an inverter can be added before the fourth transistor T4 in conjunction with the actual second enable signal to control the second transistor T2 and the third transistor T3 to work as needed. For details, please refer to the settings of the first enable signal mentioned above, which will not be repeated here.

[0163] The fourth transistor T4 can also be a PMOS transistor. In this case, the fourth transistor T4 is connected to the ground terminal and the third transistor T3 respectively. That is, one end of the third transistor T3 is connected to the ground terminal through the second switching unit 15, and the second transistor T2 is connected to the power supply terminal.

[0164] It should also be noted that the first enable signal used to control the first transistor T1 and the second enable signal used to control the fourth transistor T4 can be the same signal or different signals. That is, the first enable signal and the second enable signal can be the same signal or two different signals. The specific settings can be combined with the actual usage requirements, and this disclosure does not impose specific limitations on this.

[0165] This disclosure provides a data transmission circuit including a control module and a processing module. The control module receives a first enable signal and controls the processing module to operate when the first enable signal is active, and controls the processing module to operate in a non-active state when the first enable signal is inactive. The processing module, when operating, receives an initial data signal and performs driving processing on the initial data signal to obtain a target transmission signal. Thus, by controlling the operating state of the processing module through the first enable signal and the control module, the processing module operates only when the first enable signal is active. Since there is no leakage path in the circuit when the processing module is inactive, leakage current generated by the data transmission circuit can be reduced, power consumption can be saved, and excessive leakage current can be avoided from damaging the circuit.

[0166] In another embodiment of this disclosure, see Figure 11 This illustration shows a flowchart of a data transmission method provided in an embodiment of this disclosure. Figure 11 As shown, the method may include:

[0167] S101, Receive the first enable signal.

[0168] S102. When the first enable signal is in an active state, the first switching unit is turned on to receive the initial data signal.

[0169] S103. Drive the initial data signal to obtain the target transmission signal.

[0170] It should be noted that the data transmission method provided in this disclosure can be applied to the data transmission circuit 10 described in the foregoing embodiments.

[0171] Specifically, the control module 11 receives the first enable signal, and the control processing module 12 is in a working state when the first enable signal is in a valid state, and in a non-working state when the first enable signal is in a invalid state.

[0172] When the first enable signal is in an active state, the first switch unit 111 is turned on, and the processing module 12 is in a working state. The processing module 12 receives the initial data signal and performs driving processing on the initial data signal to obtain the target transmission signal. The initial data signal is generated based on the data signal obtained by the data transmission circuit 10 when the first enable signal is in an active state.

[0173] In this way, the initial data signal is only driven when the first enable signal is active, which can reduce leakage current and save power consumption.

[0174] In some embodiments, the method may further include:

[0175] When the first enable signal is active, the first switching unit is turned on.

[0176] When the first enable signal is in an invalid state, the first switch unit is turned off.

[0177] It should be noted that, through the control module 11, when the first enable signal is in an effective state, the first switch unit 111 is controlled to be turned on; and when the first enable signal is in an ineffective state, the first switch unit 111 is controlled to be turned off.

[0178] In some embodiments, the method may further include:

[0179] When the first enable signal is in the first level state, it is determined that the first enable signal is in an invalid state;

[0180] When the first enable signal is in the second level state, it is determined that the first enable signal is in an effective state.

[0181] In some embodiments, the first level state is low level and the second level state is high level.

[0182] It should be noted that when the first enable signal is in a first-level state, it can be determined that the first enable signal is inactive; when the first enable signal is in a second-level state, it can be determined that the first enable signal is active. The first level state is low, and the second level state is high. However, for certain types of signals, a low level can be active and a high level can be inactive. This allows for flexible control based on the specific signal type.

[0183] In some embodiments, the initial data signal includes a first initial data signal and a second initial data signal, and the level states of the first initial data signal and the second initial data signal are opposite.

[0184] Accordingly, driving the initial data signal to obtain the target transmission signal may include:

[0185] The first initial data signal is processed by the first processing module to obtain the first driving signal;

[0186] The second initial data signal is processed by the second processing module to obtain the second driving signal;

[0187] The output module receives the first driving signal and the second driving signal, and outputs the target transmission signal.

[0188] It should be noted that the initial data signal may include a first initial data signal and a second initial data signal with opposite level states. When processing the initial data signal, the first processing module drives the first initial data signal to obtain a first driving signal, and then transmits the first driving signal to the output module; the second processing module drives the second initial data signal to obtain a second driving signal, and then transmits the second driving signal to the output module; after receiving the first driving signal and the second driving signal, the output module outputs the target transmission signal according to the first driving signal and the second driving signal.

[0189] In some embodiments, the method may further include:

[0190] When the data signal is the first value, the first initial data signal is determined to be in the first level state, and the second initial data signal is determined to be in the second level state;

[0191] When the data signal is the second value, the first initial data signal is determined to be in the second level state, and the second initial data signal is determined to be in the first level state.

[0192] In some embodiments, the method may further include:

[0193] When the second enable signal is active, the second switching unit 15 is turned on.

[0194] Accordingly, when the second switching unit 15 is turned on, the method may further include:

[0195] If the data signal is the first value, the third transistor is turned on according to the second driving signal, so that the target transmission signal is in the first level state;

[0196] If the data signal is the second value, the second transistor is turned on according to the first drive signal, so that the target transmission signal is in the second level state.

[0197] It should be noted that the second enable signal can also be used to control the conduction or disconnection of the second switching unit 15, thereby controlling whether the second transistor T2 and the third transistor T3 work and obtaining the target output signal.

[0198] When the second switch unit 15 is turned on and the output module 123 is in working state, the output module 123 determines the target transmission signal after receiving the first drive signal and the second drive signal in the following way: if the data signal is the first value, the third transistor is turned on based on the second drive signal to obtain the target transmission signal in the first level state; if the data signal is the second value, the second transistor is turned on based on the first drive signal to obtain the target transmission signal in the second level state.

[0199] In some embodiments, the method may further include:

[0200] After receiving the target transmission signal, the processing module 12 sends the target transmission signal to the receiving module 14.

[0201] It should be noted that after receiving the target transmission signal, the processing module 12 also sends the target transmission signal to the receiving module 14; wherein the receiving module 14 can be a data pad or a storage unit.

[0202] In some embodiments, the first enable signal and the second enable signal include at least one of the following: a read operation signal, a write operation signal, a row address strobe pulse signal, a column address strobe pulse signal, and an activation operation signal.

[0203] It should be noted that the first enable signal and the second enable signal can be the same signal or different signals, depending on the actual circuit requirements.

[0204] For details not disclosed in the embodiments of this disclosure, please refer to the description of the foregoing embodiments for understanding.

[0205] This disclosure provides a data transmission method, which includes: receiving a first enable signal; when the first enable signal is active, turning on a first switching unit to receive an initial data signal; and performing driving processing on the initial data signal to obtain a target transmission signal. In this way, the initial data signal is received and processed to obtain the target transmission signal only when the first enable signal is active, thereby reducing leakage current in the data transmission circuit and saving power consumption.

[0206] In another embodiment of this disclosure, see [reference needed]. Figure 12 This illustrates a schematic diagram of the structural composition of a semiconductor memory 20 provided in an embodiment of this disclosure. For example... Figure 12 As shown, the semiconductor memory 20 may include a data transmission circuit 10 as described in any of the foregoing embodiments.

[0207] In some embodiments, the semiconductor memory may be dynamic random access memory (DRAM).

[0208] For the semiconductor memory 20, since it includes the data transmission circuit 10 described in the foregoing embodiments, the control module only controls the processing module to work when the first enable signal is in a valid state. That is, the processing module only works normally when the first enable signal is in a valid state, and does not work at other times. This helps the semiconductor memory 20 (e.g., DRAM) save more leakage current in standby mode and also avoids excessive leakage current from damaging the circuit.

[0209] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure.

[0210] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0211] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0212] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0213] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0214] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0215] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A data transmission circuit, characterized by It includes a control module and a processing module, wherein, The control module is configured to receive a first enable signal, and control the processing module to be in a working state when the first enable signal is in a valid state, and control the processing module to be in a non-working state when the first enable signal is in a invalid state. The processing module is used to receive an initial data signal when it is in working state, and to perform driving processing on the initial data signal to obtain a target transmission signal; The initial data signal includes a first initial data signal and a second initial data signal, and the level states of the first initial data signal and the second initial data signal are opposite; the processing module includes: The first processing module is configured to perform driving processing on the first initial data signal to obtain a first driving signal when the processing module is in the working state. The second processing module is used to drive the second initial data signal to obtain a second driving signal when the processing module is in the working state. An output module is used to obtain the target transmission signal based on the first driving signal and the second driving signal; The first processing module includes N first inverters; wherein, the input terminal of the first first inverter receives the first initial data signal, the output terminal of the i-th first inverter is connected to the input terminal of the (i+1)-th first inverter, the output terminal of the N-th first inverter is used to output the first drive signal, and the enable terminals of all N first inverters are connected to the control module, where i is an integer greater than 0 and less than N, and N is an even number greater than 0; The second processing module includes M second inverters; wherein, the input terminal of the first second inverter receives the second initial data signal, the output terminal of the j-th second inverter is connected to the input terminal of the (j+1)-th second inverter, the output terminal of the M-th second inverter is used to output the second drive signal, and the enable terminals of the M second inverters are all connected to the control module, where j is an integer greater than 0 and less than M, and M is an even number greater than 0.

2. The data transmission circuit of claim 1, wherein, The control module includes a first switching unit; wherein... The control module is configured to control the first switching unit to conduct when the first enable signal is active, thereby enabling the processing module to operate; and The control module is further configured to control the first switching unit to turn off when the first enable signal is in an invalid state, so that the processing module is in a non-working state.

3. The data transmission circuit according to claim 1, characterized in that, When the first enable signal is in the first level state, it is determined that the first enable signal is in an invalid state; When the first enable signal is in the second level state, it is determined that the first enable signal is in a valid state.

4. The data transmission circuit of claim 2, wherein, The first switching unit includes a first transistor; wherein, The first transistor includes a first terminal, a second terminal, and a third terminal; The first terminal is coupled to the first enable signal, the second terminal is coupled to the power supply terminal or the ground terminal, and the third terminal is coupled to the processing module.

5. A data transmission circuit, characterized by It includes a control module and a processing module, wherein, The control module is configured to receive a first enable signal, and control the processing module to be in a working state when the first enable signal is in a valid state, and control the processing module to be in a non-working state when the first enable signal is in a invalid state. The processing module is used to receive an initial data signal when it is in working state, and to perform driving processing on the initial data signal to obtain a target transmission signal; The initial data signal includes a first initial data signal and a second initial data signal, and the level states of the first initial data signal and the second initial data signal are opposite; the processing module includes: The first processing module is configured to perform driving processing on the first initial data signal to obtain a first driving signal when the processing module is in the working state. The second processing module is used to drive the second initial data signal to obtain a second driving signal when the processing module is in the working state. An output module is used to obtain the target transmission signal based on the first driving signal and the second driving signal; The output module includes a second transistor and a third transistor; wherein, The gate of the second transistor is connected to the output of the first processing module, the gate of the third transistor is connected to the output of the second processing module, one end of the second transistor is connected to the power supply, and one end of the third transistor is connected to the ground. The other end of the second transistor is connected to the other end of the third transistor for outputting the target transmission signal.

6. The data transmission circuit of claim 5, wherein, The initial data signal is generated based on the data signal obtained by the data transmission circuit when the first enable signal is in an active state; wherein... When the data signal is a first value, the first initial data signal is determined to be in a first level state, and the second initial data signal is determined to be in a second level state; When the data signal is the second value, the first initial data signal is determined to be in the second level state, and the second initial data signal is in the first level state.

7. The data transmission circuit of claim 6, wherein, The output module further includes a second switching unit; wherein... The output module is configured to receive a second enable signal and, when the second enable signal is active, turn on the second switching unit; and, if the data signal is a first value, turn on the third transistor according to the second driving signal, so that the target transmission signal is at a first level; or, if the data signal is a second value, turn on the second transistor according to the first driving signal, so that the target transmission signal is at a second level.

8. The data transmission circuit according to any one of claims 1 to 7, characterized in that, The first enable signal and the second enable signal include at least one of the following: a read operation signal, a write operation signal, a row address strobe pulse signal, a column address strobe pulse signal, and an activation operation signal.

9. The data transmission circuit of claim 8, wherein, The data transmission circuit further includes a receiving module; wherein... The processing module is further configured to send the target transmission signal to the receiving module after obtaining the target transmission signal.

10. The data transmission circuit according to claim 9, characterized in that, When the first enable signal includes a read operation signal, the receiving module includes a data pad; When the first enable signal includes a write operation signal, the receiving module includes a storage unit.

11. A data transmission method, characterized by, The method includes: Receive the first enable signal; When the first enable signal is active, the first switching unit is turned on to receive the initial data signal; The initial data signal is processed to obtain the target transmission signal; The initial data signal includes a first initial data signal and a second initial data signal, and the level states of the first initial data signal and the second initial data signal are opposite. Accordingly, the step of driving the initial data signal to obtain the target transmission signal includes: The first initial data signal is processed by the first processing module to obtain the first driving signal; The second initial data signal is processed by the second processing module to obtain the second driving signal; The output module receives the first driving signal and the second driving signal, and outputs the target transmission signal. The initial data signal is generated based on the data signal obtained by the data transmission circuit when the first enable signal is in an active state, and the method further includes: When the data signal is a first value, the first initial data signal is determined to be in a first level state, and the second initial data signal is determined to be in a second level state; When the data signal is the second value, the first initial data signal is determined to be in the second level state, and the second initial data signal is in the first level state.

12. The method of claim 11, wherein, The method further includes: When the second enable signal is active, the second switching unit is turned on; Accordingly, when the second switching unit is turned on, the method further includes: If the data signal is a first value, then the third transistor is turned on according to the second driving signal, so that the target transmission signal is in a first level state; If the data signal is the second value, then the second transistor is turned on according to the first driving signal, so that the target transmission signal is in the second level state.

13. The method of claim 12, wherein, The first enable signal and the second enable signal include at least one of the following: a read operation signal, a write operation signal, a row address strobe pulse signal, a column address strobe pulse signal, and an activation operation signal.

14. A semiconductor memory, characterized by comprising: Includes the data transmission circuit as described in any one of claims 1 to 10.

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