A signal quality testing method and device for a nonlinear macrocell mode flash memory

Abstract

The application discloses a kind of nonlinear macrocell mode flash's signal quality test method, device, equipment and system, it is related to electronic information technical field, to solve the problem that NAND Flash signal is difficult to read-write separation, the method comprises: in the process of reading and writing data transmission in nonlinear macrocell mode flash, the test signal of nonlinear macrocell mode flash is collected;According to read-write detection signal in test signal, the working condition of nonlinear macrocell mode flash is determined;Wherein, working condition includes write state and read state;From test signal, the target signal corresponding to each working condition is separated respectively;Wherein, target signal includes the test signal in corresponding working condition;The present application reasonably selects four kinds of test signals, three kinds of test signals are used as trigger signal, and read-write separation of the four kinds of test signals is conveniently and accurately completed, so that tester can check the signal quality of NAND Flash.

Description

Technical Field

[0001] This invention relates to the field of electronic information technology, and in particular to a signal quality testing method, apparatus, device, and system for nonlinear macrocell mode flash memory. Background Technology

[0002] With the continuous development of electronic information technology, there is a great demand for high-density memories such as NAND Flash (Non-linear Macrocell Flash Memory). NAND Flash has many excellent characteristics, such as large storage capacity, high density, fast random access, high reliability, and low cost, and is widely used in SSDs (Solid State Disks) for data storage. Currently, mainstream SSDs use NAND Flash as their storage chip. To ensure the stable operation of NAND Flash chips on SSDs and to guarantee data security and reliability, measuring the signal integrity of the NAND Flash chips on the SSD to ensure compliance with standards has become an essential and crucial process in SSD development. This has a vital impact on SSD storage performance and evaluation.

[0003] In existing technologies, testing the signals of NAND Flash chips on SSDs cannot separate read and write operations during normal operation. Instead, a host computer must initiate read and write commands to the SSD, causing the controller chip to perform read and write transfers to the NAND Flash. Finally, the corresponding read or write test is performed. However, simple read and write commands make it difficult to separate the read and write signals, making it hard for testers to obtain signal waveforms under pure write and pure read states. This results in inaccurate eye diagrams, leading to biases in signal quality assessment. This poses a significant risk to the signal integrity testing of NAND Flash chips and seriously affects the evaluation of SSD storage performance by development and testing personnel.

[0004] Therefore, how to conveniently and accurately separate NAND Flash signals for reading and writing, and improve the accuracy of NAND Flash signal quality testing, is an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a signal quality testing method, apparatus, device, and system for nonlinear macrocell mode flash memory, so as to conveniently and accurately separate NAND Flash signals for reading and writing, thereby improving the accuracy of NAND Flash signal quality testing.

[0006] To address the aforementioned technical problems, this invention provides a signal quality testing method for nonlinear macrocell mode flash memory, comprising:

[0007] During the read and write data transmission process of the nonlinear macrocell mode flash memory, test signals of the nonlinear macrocell mode flash memory are collected; wherein, the test signals include chip enable signal, read enable signal, data strobe signal and data transmission signal;

[0008] The operating status of the nonlinear macrocell mode flash memory is determined based on the read / write detection signal in the test signal; wherein, the read / write detection signal includes the chip enable signal, the read enable signal, and the data strobe signal, and the operating status includes write state and read state;

[0009] The target signal corresponding to each of the operating conditions is separated from the test signal; wherein the target signal includes the test signal under the corresponding operating condition.

[0010] In some embodiments, the nonlinear macrocell mode flash memory is any nonlinear macrocell mode flash memory chip on a solid-state drive in a server.

[0011] In some embodiments, determining the operating status of the nonlinear macrocell mode flash memory based on the read / write detection signal in the test signal includes:

[0012] If the frequency of the read enable signal is at a preset frequency, the chip enable signal is at a preset chip enable, and the data strobe signal is at a rising edge or a falling edge, then the working condition is determined to be the read state.

[0013] If the frequency of the read enable signal is not at the preset frequency, the chip enable signal is at the preset chip enable, and the data strobe signal is at the rising or falling edge, then the working state is determined to be the write state.

[0014] In some embodiments, the preset frequency is the clock frequency of the nonlinear macrocell mode input / output of the solid-state drive where the nonlinear macrocell mode flash memory is located.

[0015] In some embodiments, before determining the operating condition as the read state, the method further includes:

[0016] Determine whether the chip enable signal is in the preset chip enable state;

[0017] If the preset chip is enabled, then determine whether the data strobe signal is at a rising edge or a falling edge;

[0018] If it is at the rising edge or falling edge, then determine whether the pulse width of the read enable signal is within the pulse width range corresponding to the preset frequency;

[0019] If the pulse width is within the preset frequency range, then the operating state is determined to be the read state;

[0020] If the pulse width is not within the preset frequency range, then the working state is determined to be the write state.

[0021] In some embodiments, the method further includes:

[0022] The data gating signal and the data transmission signal are respectively subjected to anti-skew calibration to obtain the calibration data gating signal and the calibration data transmission signal;

[0023] Correspondingly, the read / write detection signal includes the chip enable signal, the read enable signal, and the calibration data strobe signal; the target signal includes the chip enable signal, the read enable signal, the calibration data strobe signal, and the calibration data transmission signal under the corresponding operating conditions.

[0024] In some embodiments, after separating the target signal corresponding to each of the operating conditions from the test signal, the method further includes:

[0025] Based on the target signal, generate signal eye diagrams corresponding to each of the aforementioned operating conditions.

[0026] The present invention also provides a signal quality testing device for nonlinear macrocell mode flash memory, comprising:

[0027] The acquisition module is used to acquire test signals of the nonlinear macrocell mode flash memory during read and write data transmission; wherein, the test signals include chip enable signal, read enable signal, data strobe signal and data transmission signal;

[0028] The determination module is used to determine the operating status of the nonlinear macrocell mode flash memory based on the read / write detection signal in the test signal; wherein the read / write detection signal includes the chip enable signal, the read enable signal, and the data strobe signal, and the operating status includes write state and read state;

[0029] A separation module is used to separate the target signal corresponding to each of the operating conditions from the test signal; wherein the target signal includes the test signal under the corresponding operating condition.

[0030] The present invention also provides a signal quality testing device for nonlinear macrocell mode flash memory, comprising:

[0031] Memory, used to store computer programs;

[0032] A processor, used to execute the computer program, implements the steps of the signal quality testing method for nonlinear macrocell mode flash memory as described above.

[0033] In addition, the present invention also provides a signal quality testing system for nonlinear macrocell mode flash memory, including: a server, a computer and an oscilloscope;

[0034] The server has a non-linear macro cell mode flash memory on its solid-state drive, and the server is used to control the non-linear macro cell mode flash memory to perform read and write data transmission.

[0035] The computer is connected to the solid-state drive and is used to adjust the clock frequency of the non-linear macrocell mode input / output of the solid-state drive;

[0036] The oscilloscope is connected to the test signal pins of the nonlinear macrocell flash memory, and is used to acquire the test signals of the nonlinear macrocell flash memory during read and write data transmission. Based on the read / write detection signals in the test signals, the operating status of the nonlinear macrocell flash memory is determined. Target signals corresponding to each operating status are separated from the test signals. The test signals include a chip enable signal, a read enable signal, a data strobe signal, and a data transmission signal; the read / write detection signals include the chip enable signal, the read enable signal, and the data strobe signal; the operating status includes a write state and a read state; and the target signals include the test signals corresponding to the operating status.

[0037] The present invention provides a signal quality testing method for nonlinear macrocell mode flash memory, comprising: acquiring test signals of the nonlinear macrocell mode flash memory during read and write data transmission; wherein the test signals include a chip enable signal, a read enable signal, a data strobe signal, and a data transmission signal; determining the operating state of the nonlinear macrocell mode flash memory based on the read and write detection signals in the test signals; wherein the read and write detection signals include the chip enable signal, the read enable signal, and the data strobe signal, and the operating state includes a write state and a read state; separating the target signal corresponding to each operating state from the test signals; wherein the target signal includes the test signal under the corresponding operating state;

[0038] As can be seen, this invention rationally selects four test signals in NAND Flash, determines the operating status of the nonlinear macrocell mode flash memory based on the read / write detection signals in the test signals, and separates the target signals corresponding to each operating status from the test signals. It can use three test signals as trigger signals to conveniently and accurately complete the read / write separation of these four test signals, allowing testers to check the signal quality of NAND Flash and improving the accuracy of NAND Flash signal quality testing. Furthermore, this invention also provides a signal quality testing device, equipment, and system for nonlinear macrocell mode flash memory, which also has the above-mentioned beneficial effects. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0040] Figure 1 A flowchart illustrating a signal quality testing method for a nonlinear macrocell-mode flash memory provided in an embodiment of the present invention;

[0041] Figure 2 This is a schematic diagram of a signal quality testing system for a nonlinear macrocell mode flash memory provided in an embodiment of the present invention;

[0042] Figure 3 A truth table diagram illustrating the data input and output process of a nonlinear macrocell mode flash memory provided in an embodiment of the present invention;

[0043] Figure 4 A flowchart of another signal quality testing method for nonlinear macrocell mode flash memory provided in an embodiment of the present invention;

[0044] Figure 5 This is a structural block diagram of a signal quality testing device for a nonlinear macrocell mode flash memory provided in an embodiment of the present invention;

[0045] Figure 6 This is a schematic diagram of the structure of a signal quality testing device for a nonlinear macrocell mode flash memory provided in an embodiment of the present invention;

[0046] Figure 7 This is a schematic diagram of the signal quality testing system for a nonlinear macrocell mode flash memory provided in an embodiment of the present invention. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] Please refer to Figure 1 , Figure 1A flowchart illustrating a signal quality testing method for a nonlinear macrocell-mode flash memory provided in an embodiment of the present invention. The method may include:

[0049] Step 101: During the read and write data transmission process of the nonlinear macrocell mode flash memory, acquire the test signals of the nonlinear macrocell mode flash memory; wherein, the test signals include chip enable signal, read enable signal, data strobe signal and data transmission signal.

[0050] It should be noted that the nonlinear macrocell mode flash memory (NAND Flash) in this embodiment can be a NAND Flash chip that requires signal quality testing, that is, a NAND Flash chip that needs to separate the waveforms in the read and write states during the read and write data transmission process, so that testers can obtain the waveforms in the pure write and pure read states and complete an accurate signal quality assessment.

[0051] Correspondingly, the specific location and type of the nonlinear macrocell mode flash memory in this embodiment can be set by the designer according to the practical scenario and user needs. For example, the nonlinear macrocell mode flash memory can be any nonlinear macrocell mode flash memory chip (NAND Flash chip) in a solid-state drive (SSD); for instance, the nonlinear macrocell mode flash memory can be any nonlinear macrocell mode flash memory chip on a solid-state drive in a server, to achieve signal quality testing of NAND Flash chips in actual server scenarios. For example, in this embodiment, a server can be used as the power supply and service system, connected to the SSD board containing the NAND Flash chip via a PCIe (PCI-Express, a bus and interface standard) slot.

[0052] It is understood that the test signals in this embodiment can be the pin signals of the nonlinear macrocell mode flash memory to be acquired, i.e., the signal quality testing equipment (such as an oscilloscope) of the NAND Flash is connected to the pins of the test signals in the NAND Flash for acquisition. The specific number and type of test signals in this embodiment can be set by the designer according to the practical scenario and user requirements. For example, the test signals may include chip enable (CE) signals, read enable (RE) signals, data strobe signals (DQS), and data inputs / outputs (DQ) signals; Figure 2As shown, the oscilloscope's four probes can be connected to the CE, RE, DQS, and DQ pins on the NAND Flash chip on the SSD board of the server, respectively, to acquire the four signals DQS, DQ, RE, and CE (i.e., test signals). The test signals can also include other signals from the non-linear macrocell mode flash memory, such as the write-enable (WE) signal, to provide more information for the subsequent target signal, facilitating the tester's assessment of the NAND Flash signal quality. This embodiment does not impose any limitations on this.

[0053] Correspondingly, the specific method by which the processor in the quality testing equipment (such as an oscilloscope or computer) acquires the test signals of the nonlinear macrocell mode flash memory during read and write data transmission can be set by the designer. For example, the processor can acquire the test signals of the nonlinear macrocell mode flash memory during stress testing. For instance, the server can issue service commands to the nonlinear macrocell mode flash memory to control its read and write data transmission. For example, the server can use FIO (a storage input / output testing tool) commands to stress test the SSD, causing the NAND Flash chips on the SSD to perform read and write data transmission; that is, the processor can acquire the test signals of the NAND Flash during the stress test controlled by the server. Correspondingly, in this embodiment, a computer (i.e., a host computer, such as a personal computer PC) can also be used as the power supply and service system; that is, the computer can issue service commands to the nonlinear macrocell mode flash memory to control its read and write data transmission. This embodiment does not impose any limitations on this.

[0054] Step 102: Determine the operating status of the nonlinear macrocell mode flash memory based on the read / write detection signals in the test signals; wherein, the read / write detection signals include the chip enable signal, the read enable signal, and the data strobe signal, and the operating status includes the write state and the read state.

[0055] It is understood that the read / write detection signal in this embodiment can be a signal among the test signals that can be used to detect the read / write state of the nonlinear macrocell mode flash memory, such as the chip enable signal, read enable signal, and data strobe signal. The operating state of the nonlinear macrocell mode flash memory in this embodiment can be the read / write operating state of the nonlinear macrocell mode flash memory, that is, whether the nonlinear macrocell mode flash memory is operating in a read state for data reading or a write state for data writing.

[0056] Correspondingly, the specific method by which the processor determines the operating status of the nonlinear macrocell mode flash memory based on the read / write detection signal in the test signal in this embodiment can be set by the designer according to the practical scenario and user needs, such as... Figure 3 The truth table shown illustrates the data input and output process of the NAND Flash. When the chip enable signal (CE) is pulled low, the current NAND Flash chip is selected; when the read enable signal (RE) is pulled high, it is in read mode; the data transfer signal (DQ) is acquired on the rising and falling edges of the data strobe signal (DQS), with edge alignment indicating data reading and center alignment indicating data writing. In other words, a low CE signal enables the NAND Flash chip, and the RE signal acts as the read enable. When the RE signal is active, serial data is transmitted from the NAND Flash chip to the bus, which is received by the controller. DQS and DQ serve as input and output ports, used to input or output addresses, commands, or data to the storage device. Data is transmitted on both the rising and falling edges of DQS. As can be seen from the truth table, the only difference in data input is whether the RE signal toggles; therefore, in this embodiment, RE can be used as a trigger signal. For example, in this embodiment, the processor can determine the working state as read state when the frequency of the read enable signal is at a preset frequency, the chip enable signal is at a preset chip enable, and the data strobe signal is at a rising edge or falling edge; and determine the working state as write state when the frequency of the read enable signal is not at a preset frequency, the chip enable signal is at a preset chip enable, and the data strobe signal is at a rising edge or falling edge.

[0057] For example, in this embodiment, RE can be used as a pulse width trigger signal. That is, in this step, the processor can determine whether the chip enable signal is in the preset chip enable state; if it is in the preset chip enable state, it determines whether the data strobe signal is at the rising edge or falling edge; if it is at the rising edge or falling edge, it determines whether the pulse width of the read enable signal is within the pulse width range corresponding to the preset frequency; if it is within the pulse width range corresponding to the preset frequency, it determines that the working state is read; if it is not within the pulse width range corresponding to the preset frequency, it determines that the working state is write.

[0058] In other words, in this embodiment, RE can be used as the first trigger signal to set pulse width triggering. The pulse width range corresponding to the preset frequency can be the pulse width range corresponding to one-hundredth of the preset frequency. The preset frequency can be the clock frequency of the non-linear macrocell mode input / output (NAND IO) of the solid-state drive where the non-linear macrocell mode flash memory is located. The preset frequency can be 333, 400, 533 and / or 600MHz. For example, the tester can control and adjust the NAND IO clock frequency of the SSD where the NAND Flash chip is located through a computer (or server) to achieve the setting of the preset frequency. For example, the preset frequencies of 333, 400, 533 and 600MHz can be switched to achieve signal quality testing involving these four frequencies. Figure 2 As shown, a computer (PC) connected to the SSD via a serial port can send firmware commands to the SSD to change the NAND IO clock frequency of the SSD and complete the preset frequency setting adjustment.

[0059] Accordingly, in this embodiment, CE can be set as the second trigger signal. Since CE is usually pulled low to be active in NAND Flash chips, a low level can be selected as the trigger region (i.e., preset chip enable) to ensure that the chip enable of the NAND Flash chip under test is achieved. In this embodiment, DQS can be set as the third trigger signal. The rising and falling edges of DQS simultaneously acquire the test signal (i.e., the target signal).

[0060] In other words, in this embodiment, based on the settings of the three trigger signals mentioned above, the first trigger signal RE is simultaneously set as a separation signal, and the frequency of the RE signal is set as the separation frequency, which is the clock frequency of the NAND Flash. If the actual frequency of the RE signal meets the separation frequency, the RE signal is separated, and this state is the read state. At the same time, the other three signals are separated synchronously with RE, so that the reading and writing of data can be completely separated.

[0061] Furthermore, in this embodiment, the processor can also perform anti-skew calibration on the acquired data gating signal and data transmission signal respectively to obtain a calibration data gating signal and a calibration data transmission signal, so that the calibration data gating signal and calibration data transmission signal obtained after calibration can be used for subsequent determination of working status and signal separation; correspondingly, the read / write detection signal may include a chip enable signal, a read enable signal and a calibration data gating signal; the target signal may include the chip enable signal, the read enable signal, the calibration data gating signal and the calibration data transmission signal under the corresponding working condition.

[0062] Step 103: Separate the target signals corresponding to each working condition from the test signals; wherein, the target signals include the test signals under the corresponding working conditions.

[0063] It is understood that in this embodiment, the processor can separate the test signals (i.e., target signals) corresponding to the write state and read state from the collected test signals according to the determined write state and read state, so as to realize the read and write separation of the test signals, so that the testers can check the signal quality of NAND Flash and improve the accuracy of NAND Flash signal quality testing.

[0064] It should be noted that this embodiment demonstrates the separation of all test signals corresponding to the read and write states of NAND Flash as an example, so as to more comprehensively and specifically demonstrate the signal quality of NAND Flash by separating all test signals corresponding to the read and write states. For schemes that separate partial test signals corresponding to the read and write states of NAND Flash, i.e., where the target signal includes partial test signals under the corresponding operating conditions, the same or similar methods can be used. For example, the target signal may include the DQ signal under the corresponding operating conditions, and this embodiment does not impose any restrictions on this.

[0065] Furthermore, in this embodiment, the signal quality testing equipment (such as an oscilloscope) can also generate signal eye diagrams corresponding to each operating condition based on the target signal, so that users can intuitively measure the signal quality of NAND Flash by viewing the signal eye diagrams.

[0066] In this embodiment, the present invention reasonably selects four test signals in NAND Flash. By determining the working status of the nonlinear macrocell mode flash memory based on the read and write detection signals in the test signals, and separating the target signals corresponding to each working status from the test signals, the three test signals can be used as trigger signals to conveniently and accurately complete the read and write separation of these four test signals, so that testers can check the signal quality of NAND Flash and improve the accuracy of NAND Flash signal quality testing.

[0067] Based on the above embodiments, this invention also provides another method for testing the signal quality of nonlinear macrocell-mode flash memory. Accordingly, please refer to... Figure 4 , Figure 4 A flowchart illustrating another signal quality testing method for nonlinear macrocell mode flash memory provided in an embodiment of the present invention. The method may include:

[0068] Step 201: During the read and write data transmission process of the nonlinear macrocell mode flash memory, the oscilloscope acquires the test signals of the nonlinear macrocell mode flash memory; wherein, the test signals include chip enable signal, read enable signal, data strobe signal and data transmission signal, and the nonlinear macrocell mode flash memory is any nonlinear macrocell mode flash memory chip on the solid-state drive in the server.

[0069] Understandably, in this embodiment, the four probes of the oscilloscope can be connected to the CE, RE, DQS, and DQ pins on the NAND Flash chip on the SSD board of the server, respectively, to acquire the four signals (i.e., test signals) of DQS, DQ, RE, and CE. Correspondingly, the server can use the FIO command to perform stress testing on the SSD, enabling the NAND Flash chip on the SSD to perform read and write data transmission.

[0070] Step 202: Perform anti-skew calibration on the data gating signal and the data transmission signal respectively to obtain the calibration data gating signal and the calibration data transmission signal.

[0071] In this step, the oscilloscope can perform deskew calibration on the acquired DQS and DQ signals. The calibration data gating signal and calibration data transmission signal obtained after calibration are used to determine the working status and separate the signals, thereby further improving the accuracy of signal quality testing.

[0072] Step 203: Determine whether the chip enable signal is in the preset chip enable state; if so, proceed to step 204.

[0073] It is understood that the preset chip enable in this step can be the enable signal that is enabled when the chip enable signal is valid. For example, since the CE signal is usually pulled low to be valid in a NAND Flash chip, the preset chip enable in this embodiment can be a preset low level. In this step, the oscilloscope can determine whether the current NAND Flash chip is selected for testing by judging whether the chip enable signal is in the preset chip enable state.

[0074] Correspondingly, if the chip enable signal in this embodiment is not in the preset chip enable state, that is, the current NAND Flash chip is not selected, this process can be ended directly or returned to step 201.

[0075] Step 204: Determine whether the calibration data strobe signal is at the rising edge or falling edge; if so, proceed to step 205.

[0076] In this embodiment, the processor can determine whether the NAND Flash chip is in a data writing or reading state by judging whether the calibrated DQS is at a rising edge or a falling edge. If the calibration data strobe signal in this embodiment is not at a rising edge or a falling edge, that is, the NAND Flash chip is not performing data writing or reading, the process can be terminated directly or the process can be returned to step 201.

[0077] Step 205: Determine whether the pulse width of the read enable signal is within the pulse width range corresponding to the preset frequency; if yes, proceed to step 206; if no, proceed to step 207.

[0078] It is understood that the preset frequency in this embodiment can be the clock frequency of the nonlinear macrocell mode flash memory, such as the clock frequency of the nonlinear macrocell mode input / output (NAND IO) of the solid-state drive where the nonlinear macrocell mode flash memory is located.

[0079] Correspondingly, the method provided in this embodiment may also include a preset frequency configuration adjustment process, such as... Figure 2 As shown, a computer (PC) connected to the SSD via a serial port can send firmware commands to the SSD to change the SSD's NAND IO clock frequency. This allows the oscilloscope to generate eye diagrams for both read and write states corresponding to the preset frequency. The preset frequency can be 333MHz, 400MHz, 533MHz, or 600MHz to obtain eye diagrams for read and write states at various frequencies.

[0080] Step 206: Determine the operating status of the nonlinear macrocell mode flash memory as read mode.

[0081] Step 207: Determine the working status of the nonlinear macrocell mode flash memory as write mode.

[0082] Step 208: Separate the target signals corresponding to each working condition; wherein, the target signals include the chip enable signal, read enable signal, calibration data strobe signal and calibration data transmission signal for the corresponding working condition.

[0083] Understandably, in this step, the oscilloscope can separate the chip enable signal, read enable signal, calibration data strobe signal, and calibration data transmission signal in the read and write states corresponding to the preset frequency.

[0084] Step 209: Generate the signal eye diagram corresponding to each working condition based on the target signal.

[0085] It should be noted that in this step, the oscilloscope can generate signal eye diagrams for the read and write states corresponding to the preset frequencies, based on the target signals for the read and write states obtained from the separation. For example, the oscilloscope can fold the waveforms of the four signals in the read state a preset number of times (e.g., 10,000 times) to form the signal eye diagram for the read state; and fold the waveforms of the four signals in the write state a preset number of times to form the signal eye diagram for the write state.

[0086] Correspondingly, the oscilloscope can also display the signal eye diagrams corresponding to each of the generated operating conditions for the user's convenience.

[0087] In this embodiment, the present invention generates signal eye diagrams corresponding to each working condition based on the target signal, thereby generating eye diagrams corresponding to the signal waveforms of NAND Flash in read and write states, enabling testers to intuitively measure the signal quality of NAND Flash.

[0088] Corresponding to the above method embodiments, this invention also provides a signal quality testing device for nonlinear macrocell mode flash memory. The signal quality testing device for nonlinear macrocell mode flash memory described below and the signal quality testing method for nonlinear macrocell mode flash memory described above can be referred to in correspondence with each other.

[0089] Please refer to Figure 5 , Figure 5 This is a structural block diagram of a signal quality testing device for a nonlinear macrocell-mode flash memory provided in an embodiment of the present invention. The device may include:

[0090] The acquisition module 10 is used to acquire test signals of the nonlinear macrocell mode flash memory during the read and write data transmission process; wherein, the test signals include chip enable signal, read enable signal, data strobe signal and data transmission signal;

[0091] The determination module 20 is used to determine the operating status of the nonlinear macrocell mode flash memory based on the read / write detection signals in the test signals; wherein, the read / write detection signals include a chip enable signal, a read enable signal, and a data strobe signal, and the operating status includes a write state and a read state;

[0092] Separation module 30 is used to separate the target signal corresponding to each operating condition from the test signal; wherein the target signal includes the test signal under the corresponding operating condition.

[0093] In some embodiments, the nonlinear macrocell mode flash memory is any nonlinear macrocell mode flash memory chip on a solid-state drive in a server.

[0094] In some embodiments, the determining module 20 may include:

[0095] The first determining submodule is used to determine the working state as read state if the frequency of the read enable signal is at a preset frequency, the chip enable signal is at a preset chip enable, and the data strobe signal is at a rising edge or a falling edge.

[0096] The second determination submodule is used to determine the working state as write state if the frequency of the read enable signal is not at the preset frequency, the chip enable signal is at the preset chip enable, and the data strobe signal is at the rising edge or falling edge.

[0097] In some embodiments, the preset frequency is the clock frequency of the non-linear macrocell mode input / output of the solid-state drive where the non-linear macrocell mode flash memory is located.

[0098] In some embodiments, the determining module 20 may further include:

[0099] The first judgment submodule is used to determine whether the chip enable signal is in the preset chip enable state.

[0100] The second judgment submodule is used to determine whether the data strobe signal is at the rising edge or falling edge if the preset chip is enabled.

[0101] The third determination submodule is used to determine whether the pulse width of the read enable signal is within the pulse width range corresponding to the preset frequency if it is at the rising edge or falling edge; if it is within the pulse width range corresponding to the preset frequency, a start signal is sent to the first determination submodule; if it is not within the pulse width range corresponding to the preset frequency, a start signal is sent to the second determination submodule.

[0102] In some embodiments, the device may further include:

[0103] The calibration module is used to perform anti-skew calibration on the data gating signal and the data transmission signal respectively, to obtain the calibration data gating signal and the calibration data transmission signal;

[0104] Correspondingly, the read / write detection signals include the chip enable signal, the read enable signal, and the calibration data strobe signal; the target signals include the chip enable signal, the read enable signal, the calibration data strobe signal, and the calibration data transmission signal under the corresponding operating conditions.

[0105] In some embodiments, the device may further include:

[0106] The eye diagram generation module is used to generate signal eye diagrams corresponding to each working condition based on the target signal.

[0107] In this embodiment, the present invention rationally selects four test signals in NAND Flash. The determination module 20 determines the working status of the nonlinear macrocell mode flash memory based on the read / write detection signals in the test signals, and the separation module 30 separates the target signals corresponding to each working status from the test signals. The three test signals can be used as trigger signals to conveniently and accurately complete the read / write separation of these four test signals, so that testers can check the signal quality of NAND Flash and improve the accuracy of NAND Flash signal quality testing.

[0108] Corresponding to the above method embodiments, this invention also provides a signal quality testing device for nonlinear macrocell mode flash memory. The signal quality testing device for nonlinear macrocell mode flash memory described below and the signal quality testing method for nonlinear macrocell mode flash memory described above can be referred to in correspondence with each other.

[0109] Please refer to Figure 6 , Figure 6 This is a schematic diagram of a signal quality testing device for a nonlinear macrocell-mode flash memory provided in an embodiment of the present invention. The signal quality testing device may include:

[0110] Memory D1 is used to store computer programs;

[0111] Processor D2 is used to implement the steps of the signal quality testing method for nonlinear macrocell mode flash memory provided in the above method embodiments when executing a computer program.

[0112] In this embodiment, the signal quality testing device for the nonlinear macrocell mode flash memory can be an oscilloscope; it can also be a computer or server connected to the nonlinear macrocell mode flash memory, such as a computer or server connected to the solid-state drive where the nonlinear macrocell mode flash memory is located.

[0113] Corresponding to the above method embodiments, this invention also provides a signal quality testing system for nonlinear macrocell mode flash memory. The signal quality testing system for nonlinear macrocell mode flash memory described below and the signal quality testing method for nonlinear macrocell mode flash memory described above can be referred to in correspondence.

[0114] Please refer to Figure 7 , Figure 7 This is a schematic diagram of a signal quality testing system for a nonlinear macrocell-mode flash memory provided in an embodiment of the present invention. The system may include: a server 100, a computer 200, and an oscilloscope 300;

[0115] In the server 100, a non-linear macro cell mode flash memory 111 is set on the solid-state drive 110, and the server is used to control the non-linear macro cell mode flash memory 111 to perform read and write data transmission.

[0116] Computer 200 is connected to solid-state drive 110 and is used to adjust the clock frequency of non-linear macrocell mode input / output of solid-state drive 110;

[0117] The oscilloscope 300 is connected to the test signal pins of the nonlinear macrocell flash memory 111, and is used to acquire the test signals of the nonlinear macrocell flash memory 111 during read and write data transmission. Based on the read and write detection signals in the test signals, the operating status of the nonlinear macrocell flash memory 111 is determined. The target signals corresponding to each operating status are separated from the test signals. The test signals include chip enable signals, read enable signals, data strobe signals, and data transmission signals. The read and write detection signals include chip enable signals, read enable signals, and data strobe signals. The operating status includes write status and read status. The target signals include the test signals under the corresponding operating status.

[0118] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatuses, devices, and systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to in the method section.

[0119] The signal quality testing method, apparatus, device, and system for nonlinear macrocell mode flash memory provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A method for testing the signal quality of nonlinear macrocell-mode flash memory, characterized in that, include: During the read and write data transmission process of the nonlinear macrocell mode flash memory, test signals of the nonlinear macrocell mode flash memory are collected; wherein, the test signals include chip enable signal, read enable signal, data strobe signal and data transmission signal; The operating status of the nonlinear macrocell mode flash memory is determined based on the read / write detection signal in the test signal; wherein, the read / write detection signal includes the chip enable signal, the read enable signal, and the data strobe signal, and the operating status includes write state and read state; The target signal corresponding to each of the operating conditions is separated from the test signal; wherein, the target signal includes the test signal under the corresponding operating condition; The step of determining the operating status of the nonlinear macrocell mode flash memory based on the read / write detection signal in the test signal includes: If the frequency of the read enable signal is at a preset frequency, the chip enable signal is at a preset chip enable, and the data strobe signal is at a rising edge or a falling edge, then the working condition is determined to be the read state; the preset frequency is the clock frequency of the nonlinear macrocell mode input / output of the solid-state drive where the nonlinear macrocell mode flash memory is located. If the frequency of the read enable signal is not at the preset frequency, the chip enable signal is at the preset chip enable, and the data strobe signal is at the rising or falling edge, then the working state is determined to be the write state.

2. The signal quality testing method for nonlinear macrocell mode flash memory according to claim 1, characterized in that, The nonlinear macrocell mode flash memory is any nonlinear macrocell mode flash memory chip on the solid-state drive in the server.

3. The signal quality testing method for nonlinear macrocell mode flash memory according to claim 1, characterized in that, Before determining the working state as the read state, the method further includes: Determine whether the chip enable signal is in the preset chip enable state; If the preset chip is enabled, then determine whether the data strobe signal is at a rising edge or a falling edge; If it is at the rising edge or falling edge, then determine whether the pulse width of the read enable signal is within the pulse width range corresponding to the preset frequency; If the pulse width is within the preset frequency range, then the operating state is determined to be the read state; If the pulse width is not within the preset frequency range, then the working state is determined to be the write state.

4. The signal quality testing method for nonlinear macrocell mode flash memory according to claim 1, characterized in that, Also includes: The data gating signal and the data transmission signal are respectively subjected to anti-skew calibration to obtain the calibration data gating signal and the calibration data transmission signal; Correspondingly, the read / write detection signal includes the chip enable signal, the read enable signal, and the calibration data strobe signal; the target signal includes the chip enable signal, the read enable signal, the calibration data strobe signal, and the calibration data transmission signal under the corresponding operating conditions.

5. The signal quality testing method for nonlinear macrocell mode flash memory according to claim 1, characterized in that, After separating the target signal corresponding to each of the operating conditions from the test signal, the method further includes: Based on the target signal, generate signal eye diagrams corresponding to each of the aforementioned operating conditions.

6. A signal quality testing device for nonlinear macrocell mode flash memory, characterized in that, include: The acquisition module is used to acquire test signals of the nonlinear macrocell mode flash memory during read and write data transmission; wherein, the test signals include chip enable signal, read enable signal, data strobe signal and data transmission signal; The determination module is used to determine the operating status of the nonlinear macrocell mode flash memory based on the read / write detection signal in the test signal; wherein the read / write detection signal includes the chip enable signal, the read enable signal, and the data strobe signal, and the operating status includes write state and read state; A separation module is used to separate target signals corresponding to each of the operating conditions from the test signals; wherein the target signals include the test signals under the corresponding operating conditions; The determining module includes: The first determining submodule is used to determine the working state as the read state if the frequency of the read enable signal is at a preset frequency, the chip enable signal is at a preset chip enable, and the data strobe signal is at a rising edge or a falling edge; the preset frequency is the clock frequency of the nonlinear macrocell mode input / output of the solid-state drive where the nonlinear macrocell mode flash memory is located. The second determining submodule determines the working state as the write state if the frequency of the read enable signal is not at the preset frequency, the chip enable signal is at the preset chip enable, and the data strobe signal is at the rising edge or falling edge.

7. A signal quality testing device for nonlinear macrocell mode flash memory, characterized in that, include: Memory, used to store computer programs; A processor, configured to execute the computer program, implement the steps of the signal quality testing method for nonlinear macrocell mode flash memory as described in any one of claims 1 to 5.

8. A signal quality testing system for nonlinear macrocell mode flash memory, characterized in that, include: Servers, computers, and oscilloscopes; The server has a non-linear macro cell mode flash memory on its solid-state drive, and the server is used to control the non-linear macro cell mode flash memory to perform read and write data transmission. The computer is connected to the solid-state drive and is used to adjust the clock frequency of the non-linear macrocell mode input / output of the solid-state drive; The oscilloscope is connected to the test signal pins of the nonlinear macrocell flash memory, and is used to acquire the test signals of the nonlinear macrocell flash memory during read and write data transmission. Based on the read / write detection signals in the test signals, the operating status of the nonlinear macrocell flash memory is determined. Target signals corresponding to each operating status are separated from the test signals. The test signals include a chip enable signal, a read enable signal, a data strobe signal, and a data transmission signal; the read / write detection signals include the chip enable signal, the read enable signal, and the data strobe signal; the operating status includes a write state and a read state; and the target signals include the test signals corresponding to the operating status. The step of determining the operating status of the nonlinear macrocell mode flash memory based on the read / write detection signal in the test signal includes: If the frequency of the read enable signal is at a preset frequency, the chip enable signal is at a preset chip enable, and the data strobe signal is at a rising edge or a falling edge, then the working condition is determined to be the read state; the preset frequency is the clock frequency of the nonlinear macrocell mode input / output of the solid-state drive where the nonlinear macrocell mode flash memory is located. If the frequency of the read enable signal is not at the preset frequency, the chip enable signal is at the preset chip enable, and the data strobe signal is at the rising or falling edge, then the working state is determined to be the write state.

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