Test circuit and method for reading memory device data in a memory dump operation

Abstract

A test circuit is provided for coupling to a memory device for reading data stored by the memory device in a memory dump operation. The test circuit includes a dump controller and a pattern generation circuit. The dump controller is configured to trigger the pattern generation circuit to initiate a pattern generation operation in response to a processor setting a memory dump mode. The pattern generation circuit is configured to generate a plurality of control signals during the pattern generation operation and provide the control signals to the memory device. The control signals include at least an address signal, a memory enable signal and a read enable signal. The address signal includes a plurality of memory addresses arranged in a plurality of consecutive clock cycles of the processor for reading data stored at the plurality of memory addresses during the plurality of consecutive clock cycles.

Description

Technical Field

[0001] This invention relates to a circuit and a corresponding method for performing a memory dump. Background Technology

[0002] Scan dump and memory dump operations are two common operations required when performing diagnostics on a fabricated chip on a development board. These operations are used during the debugging phase to determine the cause of errors or unexpected exceptions. A scan dump involves reading the contents of all registers on the chip, while a memory dump involves reading the contents of all memory on the chip. When an error or unexpected exception occurs, the system stops the chip's clock and starts a lower-frequency scan clock, followed by both scan and memory dumps.

[0003] In a scan-based dump operation, the contents of each register are transferred to the output scan pin in a concatenated order. Similarly, a memory dump operation reads all or part of the contents of the on-chip memory and outputs it. By analyzing these contents, for example, comparing them with a golden pattern generated by a host simulator under the same conditions, the cause of the error or exception can be determined.

[0004] Since memory dumping typically requires reading all the contents stored in memory, and the execution of dump instructions by external devices takes a long time, the time required for memory dumping operations increases significantly as the number of memories configured within the chip increases, resulting in the problem of excessively time-consuming memory dumping operations.

[0005] To solve this problem, a circuit and corresponding method are needed that can efficiently perform memory dumps. Summary of the Invention

[0006] The purpose of this invention is to provide a circuit and corresponding method that can effectively perform memory dumps, so as to solve the problem that traditional memory dump operations take too long.

[0007] According to one embodiment of the present invention, a test circuit coupled to a memory device is used to read data stored in the memory device during a memory dump operation. The circuit includes a dump controller and a pattern generation circuit. The dump controller is used to trigger the pattern generation circuit to start a pattern generation operation in response to a processor setting a memory dump mode. The pattern generation circuit is used to generate a plurality of control signals during the pattern generation operation and provide the control signals to the memory device. Each control signal includes at least an address signal, a memory enable signal, and a read enable signal. The address signal includes a plurality of memory addresses arranged in a plurality of consecutive clock cycles of the processor, for reading data stored at the plurality of memory addresses during the plurality of consecutive clock cycles.

[0008] According to another embodiment of the present invention, a method for reading data from a memory device during a memory dump operation includes: generating a plurality of control signals in response to a processor setting a memory dump mode, wherein the control signals include at least an address signal, a memory enable signal, and a read enable signal, and the address signal includes a plurality of memory addresses arranged in a plurality of consecutive clock cycles of the processor for reading data stored at the plurality of memory addresses in the plurality of consecutive clock cycles; providing the control signals to the memory device; and sequentially reading data stored at the memory addresses in the consecutive clock cycles in response to the control signals. Attached Figure Description

[0009] Figure 1 This is a debugging process illustrated in an embodiment of the present invention.

[0010] Figure 2 This is a system module diagram illustrating an embodiment of the present invention.

[0011] Figure 3 This is a test circuit module diagram shown according to an embodiment of the present invention.

[0012] Figure 4 This is an example waveform diagram of a control signal according to an embodiment of the present invention.

[0013] Figure 5 This is a flowchart illustrating a method for reading data stored in a memory device during a memory dump operation, according to an embodiment of the present invention.

[0014] Figure 6 This is a test circuit module diagram shown according to another embodiment of the present invention.

[0015] Figure 7 This is a signal waveform diagram illustrating the sequential output of data from a memory device under the control of a test circuit, according to an embodiment of the present invention.

[0016] Figure 8This is a signal waveform diagram illustrating the parallel output of multiple data entries from a memory device under the control of a test circuit, according to another embodiment of the present invention.

[0017] Explanation of reference numerals in the attached figures:

[0018] 200: Development board; 210: Chip; 220, 320, 620: Memory device

[0019] 250: Host device; 255: Circuit simulator; 240, 340, 640: Register modules

[0020] 260: Test interface; 310, 610 control modules; 230, 300, 600: Test circuits

[0021] 642: Scheduler 311, 611: Pattern Generation Circuit 330, 630: Multiplexer

[0022] CMD: Instructions 312, 612: Dump Controller; CLK: Clock Signal

[0023] D: Data signal; ADDR: Address signal; ME: Memory enable signal

[0024] OP: Operation; Q: Output communication port; Read: Read operation

[0025] Next: Notification signal Start: Start signal WE: Read enable signal

[0026] BIST_Mode, Memory_Dump_Mode: Set the signal OUT: Signals transmitted on the bus.

[0027] Value_From_Memory: The value read from memory. Value: The signal output from the communication port.

[0028] REG_0, REG_1, REG_2: Registers; Function_Input: Function input signals

[0029] D0, D1, D2, D3, D4, D5, D6, D7, D8: Data REG*: Data signals written to the register

[0030] A_0, A_1, A_2, A_3, A_4, A_5, A_6, A_7, A_8: memory address

[0031] R_0(D0), R_1(D1), R_2(D2), R_0(D3), R_1(D4), R_2(D5), R_0(D6), R_1(D7), R_2(D8): Data written to the registers Detailed Implementation

[0032] Figure 1 This is a debugging process illustrated according to an embodiment of the present invention. Generally, during chip testing, when an error or unexpected exception occurs during the operation of the processor (e.g., a central processing unit) configured within the chip, the debugging process may include the following steps:

[0033] Step S100: An error or unexpected exception event is detected. For example, the processor or the chip under test itself, or another host device coupled to the chip under test or a development board on which the chip under test is mounted, may perform the detection by monitoring one or more debug ports.

[0034] Step S102: Stop the processor clock and switch to Scan Dump mode. At this time, another scan clock with a lower frequency will be turned on to assist in the subsequent dump operation.

[0035] Step S104: Read all register contents (or status) of the chip and provide them to the host device.

[0036] Step S106: Switch to Memory Dump mode.

[0037] Step S108: Read all memory contents of the chip and provide them to the host device.

[0038] Step S110: On the host device, compare the dumped contents with the software simulation results (e.g., the golden pattern generated by the simulator under the same conditions) to determine the cause of the error or exception.

[0039] In the memory read operation similar to that involved in step S108, the processor of the prior art (e.g., the processor configured in the chip) must sequentially issue read instructions for each memory address, and then provide the read data of each memory address to the host device in sequence through a test interface, such as IEEE1149.1 JTAG (Joint Test Action Group).

[0040] However, for each read instruction issued by the processor, each read operation typically requires several (e.g., 3 to 5) processor clock cycles to complete. This is because the instruction issued by the processor must undergo decoding and numerous corresponding processing steps. As the amount of memory configured on the chip increases, the time required for memory dump operations will increase significantly, thus causing the problem of excessively time-consuming memory dump operations.

[0041] To address this problem, the present invention proposes a circuit and corresponding method for efficiently performing memory dumping. In one embodiment of the present invention, a test circuit is used to perform the relevant operations of memory dumping (e.g., the operation in step S108 above). This test circuit can be a Memory Built-in Self Test (MBIST) circuit. In the embodiments of the present invention, the test circuit or MBIST circuit can be configured with a corresponding test algorithm to complete the required memory read operations in memory dumping mode. Unlike the prior art, in the embodiments of the present invention, the read operation of a memory address only requires one processor clock cycle. That is, in the embodiments of the present invention, it is not necessary for the processor to sequentially issue read instructions for each memory address; instead, the test circuit or MBIST circuit automatically completes the read operations of all memory addresses, and the read operation of a memory address of the memory device can be completed within one processor clock cycle. In this way, compared with the prior art which requires multiple clock cycles to complete the read operation of a memory address, the execution time of memory dumping can be significantly shortened by applying the circuit and corresponding method proposed in the present invention.

[0042] Figure 2 This is a system block diagram illustrating an embodiment of the present invention. The system may include a development board 200 and a host device 250, wherein the development board 200 may also be a system-on-a-chip (SoC) platform. The processor (not shown in the figure) of the host device 250 can implement a circuit simulator 255 by executing corresponding software. The development board 200 is equipped with a chip under test 210, which may include a memory device 220, a test circuit 230, and a register module 240. The processor of the host device 250 can transmit CMD instructions to a test interface 260, such as the aforementioned JTEG, via a corresponding bus, and receive read data through the test interface 260 and the corresponding bus, such as the value Value_From_Memory read from memory as shown in the figure. It is worth noting that... Figure 2 This is a simplified schematic diagram, showing only elements relevant to the present invention. It will be understood by those skilled in the art that the host device and chip may include many components not shown in the diagram. Figure 2 The components shown are used to implement the corresponding signal processing functions. Furthermore, in one embodiment of the invention, the test circuit 230 may be an MBIST circuit specifically configured for the memory device 220.

[0043] In an embodiment of the present invention, when the processor of the host device 250 issues an instruction to switch to memory dump mode to perform memory dump, the chip under test 210 will sequentially perform value reading operations on different memory addresses through the test circuit 230, and store the values ​​read from the memory in the register module 240. When the storage in the register module 240 reaches a predetermined level, the data stored in the register module 240 can be read and output to the bus connected between the development board 200 and the host device 250 for transmission to the host device 250. It should be noted that the embodiments of the present invention are not limited to placing the register module 240 outside the test circuit 230. In some embodiments of the present invention, the register module 240 may also be placed inside the test circuit 230.

[0044] Figure 3 This is a test circuit module diagram according to an embodiment of the present invention. The test circuit 300 is coupled to the memory device 320 and is used to read data stored in the memory device 320 during a memory dump operation. It should be noted that, for the purpose of illustrating the operation of the test circuit 300, Figure 3 The memory device 320 is also shown. However, the test circuit 300 may not actually include the memory device 320.

[0045] The test circuit 300 may include a control module 310, a multiplexer 330, and a register module 340. The control module 310 may include a pattern generation circuit 311 and a dump controller 312. The dump controller 312 may trigger the pattern generation circuit 311 to begin a corresponding pattern generation operation in response to a processor (e.g., a processor configured in the chip including the test circuit 300) setting a memory dump mode. The multiplexer 330 may receive signals from multiple input sources and a selection signal, and select one of the multiple input sources to output according to the setting of the selection signal. The multiple input sources may include patterns generated by the pattern generation circuit 311 and a function input signal (Function_Input) generated by a processor (e.g., the aforementioned processor configured in the chip, or a memory controller corresponding to the memory device 320).

[0046] In one embodiment of the present invention, the test circuit 300 may be an MBIST circuit specifically configured for the memory device 320. The selection signal received by the multiplexer 330 may be a BIST_Mode setting signal for a built-in self-test mode or a Memory_Dump_Mode setting signal for a memory dump mode. For example, in addition to the communication port configured to receive the BIST_Mode setting signal, the test circuit 300 may have an additional communication port for receiving the Memory_Dump_Mode setting signal.

[0047] When the test circuit 300 performs a built-in self-test on the memory device 320, the chip's processor can programmably set the register value corresponding to the BIST_Mode signal (e.g., set it to 1) to control the multiplexer 330 to select the pattern generated by the pattern generation circuit 311 for output. This pattern is generated specifically for the built-in self-test. Similarly, when the test circuit 300 performs a memory dump operation on the memory device 320, the processor can programmably set the register value corresponding to the Memory_Dump_Mode signal (e.g., set it to 1) to control the multiplexer 330 to select the pattern generated by the pattern generation circuit 311 for output. This pattern is generated specifically for the memory dump. When the test circuit 300 is not performing a built-in self-test or memory dump operation on the memory device 320, the processor can set the register value corresponding to the BIST_Mode signal to another value (e.g., set it to 0) to control the multiplexer 330 to select the Function_Input signal for output.

[0048] According to one embodiment of the present invention, in response to a host device issuing an instruction requesting the chip to switch to memory dump mode, the chip's processor can notify the test circuit 300 to switch to memory dump mode by setting the register value corresponding to the setting signal Memory_Dump_Mode to a predetermined value, for example, the aforementioned setting to 1. The control module 310 can also receive this setting signal Memory_Dump_Mode, and the dump controller 312 can trigger the pattern generation circuit 311 to start generating the control signal pattern required for the memory dump mode in response to the setting of the memory dump mode (e.g., the aforementioned predetermined value), and provide the control signal to the memory device 320.

[0049] In embodiments of the present invention, in memory dump mode, the control signal generated by pattern generation circuit 311 may include at least an address signal ADDR, a memory enable signal ME, and a read enable signal WE, wherein the read enable signal WE may also be regarded as a write enable signal. For example, one signal level of the read enable signal WE may be defined as the level for enabling a write operation of the memory device, and another signal level of the read enable signal WE may be defined as the level for enabling a read operation of the memory device. In built-in self-test mode, the control signal generated by pattern generation circuit 311 may also include a data signal D. In memory dump mode, pattern generation circuit 311 provides control signals to memory device 320 to control memory device 320 to sequentially read data stored at the corresponding memory address according to the content indicated by address signal ADDR, and sequentially provide the read data to register module 340 through output communication port Q, wherein register module 340 may include one or more registers for sequentially receiving and storing data. In one embodiment of the present invention, the control signal pattern generated by pattern generation circuit 311 may be a sequence pattern that only includes memory read operations.

[0050] Figure 4 This is an example waveform diagram of control signals according to an embodiment of the present invention. In response to the setting of the memory dump mode, the pattern generation circuit 311 can set the level of the memory enable signal ME to 1 (high level) to enable the memory device 320, and set the level of the read enable signal WE to 0 (low level) to enable the read operation of the memory device 320. Furthermore, Figure 4 The waveform of the processor's clock signal CLK is also displayed, and the address signal ADDR generated by the pattern generation circuit 311 in the memory dump mode may include multiple memory addresses arranged in multiple consecutive clock cycles of the processor, such as memory addresses A_0 to A_5 shown in the figure.

[0051] In an embodiment of the present invention, the pattern generation circuit 311 arranges a read operation of a memory address within one clock cycle of the processor by setting the pattern of the address signal ADDR. Furthermore, in the pattern of the address signal ADDR, the pattern generation circuit 311 can arrange multiple memory addresses within multiple consecutive clock cycles, for example, multiple consecutive memory addresses, for sequentially reading the data stored at these memory addresses one after another in consecutive clock cycles. Figure 4The OP waveform shown indicates that multiple read operations will be executed consecutively over multiple clock cycles. Through the arrangement of the memory addresses and the setting of other corresponding control signal patterns, the test circuit 300 can complete this predetermined number of data read operations on the memory device 320 within a predetermined number of clock cycles of the processor. For example, assuming that a memory space addressed by a memory address of the memory device 320 can store 128 bits of data, the test circuits 230 / 300 can complete a 128-bit data read operation within one clock cycle of the processor, and can complete the same number (i.e., the predetermined number) of read operations on memory addresses in response to the aforementioned control signals within a predetermined number of clock cycles of the processor, wherein the amount of data read each time is 128 bits, but the present invention is not limited thereto.

[0052] The following is an example script for automatically performing a memory dump using a test circuit or MBIST circuit. In this example, the memory dump script includes P steps to read N memory addresses, and their corresponding descriptions are as follows:

[0053] Step 0: The host device transmits the memory dump command.

[0054] Step 1: The chip performs a memory dump.

[0055] Step 2: (Internal operation of the test circuit) The test circuit reads the address of the first memory and stores the data in the register.

[0056] Step 3: Perform a register read operation.

[0057] Step 4: Transmit the read data to the host device.

[0058] (...omitted)

[0059] Step (P-3): (Internal operation of the test circuit) The test circuit reads the (N-1)th memory address and stores the data in the register.

[0060] Step (P-2): Perform a register read operation.

[0061] Step (P-1): Transmit the read data to the host device.

[0062] Because this invention does not sequentially read instructions from each memory address using the processor, but instead triggers the test circuit to enter memory dump mode by setting the Memory_Dump_Mode signal, and generates corresponding control signal patterns to execute the corresponding read operation, this invention can complete the operation of reading N memory addresses in a shorter time compared to existing technologies. For example, steps 1, 2, and 3 in the above example do not involve processor operations.

[0063] Figure 5 This is a flowchart illustrating a method for reading data stored in a memory device during a memory dump operation, according to an embodiment of the present invention, comprising the following steps:

[0064] Step S502: In response to a setting of the memory dump mode by the processor, a plurality of control signals are generated.

[0065] Step S504: Provide control signals to the memory device.

[0066] Step S506: In response to the control signal, read the data stored at multiple memory addresses sequentially in consecutive clock cycles.

[0067] In step S506, within a predetermined number of clock cycles of the processor, the memory device will sequentially output the data stored at the same number of memory addresses.

[0068] According to another embodiment of the present invention, in addition to one or more registers, the register module may also include a scheduler for scheduling the reception of data, and the scheduler may handshake with the control module to complete the sequential output of data or the parallel output of multiple data.

[0069] Figure 6 This is a test circuit module diagram according to another embodiment of the present invention. The test circuit 600 is coupled to the memory device 620 and is used to read data stored in the memory device 620 during a memory dump operation. It should be noted that, for the purpose of illustrating the operation of the test circuit 600, Figure 6 Memory device 620 is also shown. However, test circuit 600 may not actually include memory device 620.

[0070] The test circuit 600 may include a control module 610, a multiplexer 630, and a register module 640. The control module 610 may include a pattern generation circuit 611 and a dump controller 612. The dump controller 612 may generate a start signal (e.g., generate a corresponding pulse) in response to a processor (e.g., a processor configured in the chip including the test circuit 600) setting a memory dump mode, and trigger the pattern generation circuit 611 to start the corresponding pattern generation operation.

[0071] In one embodiment of the present invention, the test circuit 600 can also be an MBIST circuit specifically configured for the memory device 620, wherein the basic operations of the control module 610, the memory device 620, the multiplexer 630, the pattern generation circuit 611, and the dump controller 612 are respectively related to... Figure 3 The control module 310, memory device 320, multiplexer 330, pattern generation circuit 311 and dump controller 312 are the same, so please refer to the above paragraphs for details, and will not be repeated here.

[0072] According to one embodiment of the present invention, the register module 640 may include multiple registers, such as register REG_0, register REG_1, and register REG_2, and a scheduler 642 for scheduling data reception. It should be noted that the present invention is not limited to... Figure 6 The number of registers in the system.

[0073] The control module 610 receives a setting signal Memory_Dump_Mode, and the dump controller 612, in response to the setting of the memory dump mode (e.g., the aforementioned predetermined value), generates a start signal Start and triggers the pattern generation circuit 611 to begin generating the control signal pattern required for the memory dump mode. The start signal Start is provided to the scheduler 642 to notify the start of the read operation, and control signals are provided to the memory device 620 to control the read operation of the memory device 620. The memory device 620, in response to the control signals, sequentially reads the data stored at the corresponding memory addresses according to the contents indicated by the address signal ADDR, and sequentially provides the read data to the register module 640 through the output communication port Q. The register module 640 may include one or more registers for sequentially receiving and storing data. The scheduler 642, in response to the start signal Start, sequentially arranges one register to store the data received from the memory device 620.

[0074] When the register module 640 has reached a predetermined storage level, the scheduler 642 can read the data stored in the register module 640 in a sequential or parallel manner and output it to the bus connected to the host device to transmit the data to the host device. In addition, the scheduler 642 can send a notification signal Next (e.g., generate a corresponding pulse) to the dump controller 612 to notify the dump controller 612 that the next round of reading operations can continue.

[0075] The dump controller 612 may generate a start signal Start again (e.g., generate a corresponding pulse) in response to the receipt of the notification signal Next, and trigger the pattern generation circuit 611 to continue arranging multiple unread memory addresses in the address signal ADDR in response to the start signal Start (which is equivalent to responding to the notification signal Next), and generate the corresponding address signal ADDR, memory enable signal ME and read enable signal WE.

[0076] According to one embodiment of the present invention, the scheduler 642 may also count a predetermined time, for example, a specific number of clock cycles, and when the predetermined time expires, the scheduler 642 may read the data stored in the register module 640 in a sequential or parallel manner and output it to the bus connected to the host device to transmit the data to the host device. The scheduler 642 may also send a notification signal Next (for example, generate a corresponding pulse) to the dump controller 612 when the predetermined time expires to notify the dump controller 612 that the next round of reading operation can continue.

[0077] According to one embodiment of the present invention, the predetermined time or specific quantity may be related to the number of registers configured in the register module 640. For example, if the register module 640 includes 3 registers, then in response to the reception of the start signal Start, the scheduler 642 may repeatedly count 3 clock cycles, and after each 3 clock cycles, the scheduler 642 may read the data stored in the 3 registers and generate a corresponding notification signal Next pulse to notify the dump controller 612 to continue the next round of reading operations.

[0078] It should be noted that register module 640 can also be implemented by a first-in-first-out (FIFO) circuit. In such an implementation, the start signal Start and the notification signal Next can be provided as indicators to indicate the operation of writing data to or outputting data from the FIFO circuit.

[0079] Figure 7 This is a signal waveform diagram illustrating the sequential output of data from a memory device under the control of a test circuit, according to an embodiment of the present invention. Figure 7In addition to showing the waveforms of the processor's clock signal CLK, address signal ADDR, memory enable signal ME, read enable signal WE, start signal Start, and notification signal Next, the waveforms of the signal Value at the memory device's output communication port Q, the data signal REG* written to the register, and the signal OUT transmitted on the bus connecting the register module and the host device are also shown.

[0080] As shown in the figure, in response to the pulse of the start signal Start, the pattern generation circuit generates a corresponding control signal, and the memory device outputs the data D0 to D8 of memory addresses A_0 to A_8 sequentially in each cycle of the clock signal CLK according to the setting of the control signal. Assuming that the register module in this embodiment includes three registers, numbered REG_0 to REG_2, the waveform of the register data signal REG* uses simplified register numbers R_0 to R_2 and the data D0 to D8 marked in parentheses to represent the data written to each register in different clock cycles. In this embodiment, the register module sequentially outputs the received data to the bus; therefore, the signal OUT transmitted on the bus has valid data in the corresponding clock cycle. The portion filled with diagonal lines in the figure represents the valid data on the bus. In this embodiment, the data D0 to D8 corresponding to memory addresses A_0 to A_8 are sequentially read over nine consecutive clock cycles and sequentially output to the bus over nine consecutive clock cycles. The scheduler generates a corresponding Next signal pulse after each clock cycle to notify the dump controller to continue the next round of reading operations. Therefore, in the sequential output embodiment, since the test circuit can complete the reading operation of one piece of data within one clock cycle of the processor, N pieces of data can be continuously output over N adjacent clock cycles, where N is a positive integer.

[0081] Figure 8This is a signal waveform diagram illustrating the parallel output of multiple data entries from a memory device controlled by a test circuit according to another embodiment of the present invention. In this embodiment, data R_0(D0), R_1(D1) and R_2(D2), R_0(D3), R_1(D4) and R_2(D5), and R_0(D6), R_1(D7) and R_2(D8), etc., written to registers REG_0 to REG_2 in different clock cycles, are simultaneously output to the bus in parallel. Therefore, the signal OUT transmitted on the bus only has valid data within the clock cycle in which the data is output. In this embodiment, in response to the pulse of the start signal Start, the pattern generation circuit generates a corresponding control signal, and the scheduler can generate a corresponding notification signal Next pulse after the data in the register is read, or after counting at least 3 clock cycles, to notify the dump controller that the next round of read operation can continue. In the parallel output embodiment, since the test circuit can complete a data reading operation within one clock cycle of the processor, the memory device can continuously output M data in adjacent M clock cycles, where M is a positive integer, and the scheduler can output the data in parallel to the bus after the M data are written to the register, for example, after counting M clock cycles, so the M data can be output in parallel to the bus at the same time.

[0082] In summary, in the embodiments of the present invention, the host device only needs to issue a mode switching signal, and when switching to memory dump mode to perform memory dump, the test circuit inside the chip under test will sequentially perform value reading operations on different memory addresses, without needing the processor to issue corresponding read instructions for each memory address separately. That is, when the mode switching signal is received, the processor inside the chip under test only needs to execute the value setting operation of the setting signal Memory_Dump_Mode, without participating in the memory read operation. In response to the setting of the memory dump mode (for example, the value of the setting signal Memory_Dump_Mode is set to a predetermined value), the test circuit can automatically generate corresponding control signals, including arranging address signals ADDR for multiple memory addresses in multiple consecutive clock cycles, and controlling the memory device to only perform the corresponding read operation in memory dump mode. In this way, the embodiments of the present invention can significantly shorten the execution time of memory dump compared with the prior art. Furthermore, the test circuit of the present invention can directly utilize the MBIST circuit, which is typically configured specifically for memory devices, without the need for additional memory dump circuitry. Therefore, although the present invention uses hardware circuitry to perform memory dump operations, it does not actually increase the additional circuit area, making it a low-area-cost solution.

[0083] The above description is only a preferred embodiment of the present invention. Any equivalent changes and modifications made in accordance with the scope of the present invention should fall within the protection scope claimed by the present invention.

Claims

1. A test circuit coupled to a memory device for reading data stored in the memory device during a memory dump operation, comprising: A dump controller is used to trigger a pattern generation circuit to start a pattern generation operation in response to a processor setting a memory dump mode. as well as The pattern generation circuit is configured to generate multiple control signals during the pattern generation operation and provide the multiple control signals to the memory device. The multiple control signals include at least an address signal, a memory enable signal, and a read enable signal. The address signal includes multiple memory addresses arranged in multiple consecutive clock cycles of the processor, and is configured to read data stored at the multiple memory addresses in the multiple consecutive clock cycles.

2. The test circuit according to claim 1, characterized in that, The test circuit completes the predetermined number of data read operations within a predetermined number of clock cycles of the processor.

3. The test circuit according to claim 1, characterized in that, The dump controller also generates a start signal in response to the setting of the memory dump mode, and the test circuit further includes: A register module, coupled to the memory device, includes: Multiple registers for sequentially receiving and storing the data; and A scheduler for scheduling the reception of the data, wherein the scheduler, in response to the start signal, sequentially arranges one of the plurality of registers to store the data received from the memory device.

4. The test circuit according to claim 3, characterized in that, The scheduler also counts a predetermined time, which is related to a number of the plurality of registers. When the predetermined time expires, the scheduler also reads the data stored in the plurality of registers and sends a notification signal.

5. The test circuit according to claim 4, characterized in that, The pattern generation circuit responds to the notification signal by arranging multiple unread memory addresses within the address signal, and generates the corresponding address signal, the memory enable signal, and the read enable signal.

6. A method for reading data from a memory device during a memory dump operation, comprising: In response to a processor setting a memory dump mode, a plurality of control signals are generated, wherein the plurality of control signals include at least an address signal, a memory enable signal and a read enable signal, and the address signal includes a plurality of memory addresses arranged in a plurality of consecutive clock cycles of the processor for reading data stored at the plurality of memory addresses in the plurality of consecutive clock cycles. The plurality of control signals are provided to the memory device; as well as In response to the plurality of control signals, the data stored at the plurality of memory addresses are read sequentially in the plurality of consecutive clock cycles.

7. The method according to claim 6, characterized in that, Within a predetermined number of clock cycles of the processor, the memory device outputs the data stored at the predetermined number of memory addresses.

8. The method according to claim 6, characterized in that, Also includes: A start signal is generated in response to the setting of the memory dump mode; as well as In response to the start signal, one of a plurality of registers is sequentially arranged to receive the data from the memory device.

9. The method according to claim 8, characterized in that, Also includes: Count a predetermined time, wherein the predetermined time is related to a number of the plurality of registers; as well as When the predetermined time expires, the data stored in the plurality of registers is read out and a notification signal is issued.

10. The method according to claim 9, characterized in that, Also includes: The plurality of control signals are generated in response to the notification signal. Multiple unread memory addresses are sequentially arranged within the address signal.

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