Test circuit, test method and memory
By designing a test circuit that includes integration, comparison, and equalization circuits, the accuracy problem of high-speed clock signal duty cycle testing is solved, the testing process is simplified, power consumption is reduced, and it is suitable for different types of memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-04-26
- Publication Date
- 2026-07-31
AI Technical Summary
How to test whether the duty cycle of a high-speed clock signal meets the requirements, how to ensure the accuracy of high-speed clock signal testing, and how to generate equidistant parallel clock signals based on a high-speed clock signal.
A test circuit is provided, including first and second integrating circuits, a comparator circuit, an equalization circuit, and a pre-storage circuit. It accurately judges the signal by integrating and comparing the duty cycles of the signals and using test signals that are inversely related to each other. The equalization circuit reduces power consumption and is suitable for different types of memory.
It enables accurate testing of signal duty cycle, simplifies the testing process, and ensures the applicability and low power consumption of the test circuit.
Smart Images
Figure CN116994639B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to a test circuit, a test method, and a memory. Background Technology
[0002] With the advancement of technology, high-tech products are constantly being updated and upgraded, and their performance is continuously improving. The operation of high-tech products is inseparable from the storage of data by memory. Therefore, improving the data access speed and data access stability of memory is an urgent issue.
[0003] Memory uses clock signals to process data, and the transmission frequency of the clock signal determines the number of operations that the memory can perform in the same amount of time, which determines how fast the memory processes data. Therefore, memory processing based on high-speed clock signals is of great significance to improving memory performance.
[0004] How to test whether the duty cycle of a high-speed clock signal meets the requirements, how to ensure the accuracy of high-speed clock signal testing, and how to generate equidistant parallel clock signals based on high-speed clock signals are urgent problems to be solved. Summary of the Invention
[0005] This disclosure provides a test circuit, test method, and memory to accurately test the duty cycle of an input signal.
[0006] This disclosure provides a test circuit for detecting the duty cycle of a signal, comprising: a first integrating circuit for receiving a first test signal and configured to integrate the first test signal to output a first integrated signal; a second integrating circuit for receiving a second test signal and configured to integrate the second test signal to output a second integrated signal; wherein the first test signal and the second test signal are inverse signals, the voltage value of the first integrated signal is the product of the duty cycle of the first test signal and the power supply amplitude, and the voltage value of the second integrated signal is the product of the duty cycle of the second test signal and the power supply amplitude; a comparison circuit, one input terminal connected to the first integrating circuit and the other input terminal connected to the second integrating circuit; the comparison circuit is configured to compare the magnitudes of the first integrated signal and the second integrated signal, and output a high-level signal when the first integrated signal is greater than the second integrated signal, and output a low-level signal when the second integrated signal is greater than the first integrated signal.
[0007] The first test signal is integrated by the first integrating circuit, and the value of the first integrated signal is proportional to the duty cycle of the first test signal. The second test signal is integrated by the second integrating circuit, and the value of the second integrated signal is proportional to the duty cycle of the second test signal. By converting the determination of the signal duty cycle into a comparison of the magnitude of the signal integral value, the test process of the signal duty cycle is simplified. Since the first test signal and the second test signal are opposite signals, the comparison of the opposite signals is used to accurately determine whether the signal duty cycle is greater than 50%.
[0008] Additionally, the first integrating circuit includes: a first filtering unit, a first preprocessing unit, and a second preprocessing unit; the first filtering unit is used to integrate the received signal; the first preprocessing unit includes: a first conducting transistor, a first pre-charge P-transistor, and a first pre-charge N-transistor; the drain of the first conducting transistor is used to receive a first test signal, the source is connected to the input terminal of the first filtering unit, and the gate is used to receive a first switching signal; the source of the first pre-charge P-transistor is used to receive a high level, the drain is connected to the input terminal of the first filtering unit, and the gate is used to receive an integrating charging signal; the source of the first pre-charge N-transistor is used to receive a low level. The drain of the first filter unit is connected to the input terminal of the second filter unit, and the gate is used to receive the first integral discharge signal. The second preprocessing unit includes a second turn-on transistor, a second pre-charge P-transistor, and a second pre-charge N-transistor. The drain of the second turn-on transistor is connected to the output terminal of the filter unit, the source is used to output the first integral signal, and the gate is used to receive the second switching signal. The source of the second pre-charge P-transistor is used to receive a high level, the drain of which is connected to the output terminal of the filter unit, and the gate is used to receive the integral charging signal. The source of the second pre-charge N-transistor is used to receive a low level, the drain of which is connected to the input terminal of the filter unit, and the gate is used to receive the first integral discharge signal.
[0009] Additionally, the second integrating circuit includes: a second filtering unit, a third preprocessing unit, and a fourth preprocessing unit; the second filtering unit is used to integrate the received signal; the third preprocessing unit includes: a third on-transistor, a third pre-charged P-transistor, and a third pre-charged N-transistor; the drain of the third on-transistor is used to receive the second test signal, the source is connected to the input terminal of the second filtering unit, and the gate is used to receive the first switching signal; the source and gate of the third pre-charged P-transistor are connected and used to receive a high level, the drain is connected to the input terminal of the second filtering unit, and the source of the third pre-charged N-transistor is used to receive a low level. The drain of the fourth preprocessing unit is connected to the input of the filter unit, and the gate is used to receive the second integral discharge signal. The fourth preprocessing unit includes a fourth turn-on transistor, a fourth pre-charge P-transistor, and a fourth pre-charge N-transistor. The drain of the fourth turn-on transistor is connected to the output of the second filter unit, the source is used to output the second integral signal, and the gate is used to receive the second switching signal. The source and gate of the fourth pre-charge P-transistor are connected and used to receive a high level. The drain of the fourth pre-charge N-transistor is connected to the output of the filter unit. The source of the fourth pre-charge N-transistor is used to receive a low level. The drain of the fourth pre-charge N-transistor is connected to the output of the second filter unit, and the gate is used to receive the second integral discharge signal.
[0010] In addition, the first filtering unit is configured with a second-order RC filter.
[0011] In addition, the test circuit also includes: a first equalization circuit and a second equalization circuit; one end of the first equalization circuit is connected to the input terminal of the first integrator circuit, and the other end is connected to the input terminal of the second integrator circuit; the first equalization circuit is configured to make the voltages at the input terminals of the first integrator circuit and the second integrator circuit the same based on the first equalization signal; one end of the second equalization circuit is connected to the output terminal of the first integrator circuit, and the other end is connected to the acceleration segment of the second integrator circuit; the second equalization circuit is configured to make the initial voltages of the first integrator signal and the second integrator signal the same based on the second equalization signal. By equalizing the output voltages of the first integrator circuit and the second integrator circuit before integration, the accuracy of the difference between the integral values of the first integrator circuit and the second integrator circuit is ensured, further ensuring the accuracy of the duty cycle of the subsequently acquired signal; furthermore, by activating the first equalization circuit and the second equalization circuit during the subsequent output of the first integrator signal and the second integrator signal, the power consumption of the test circuit can be further reduced.
[0012] Additionally, the first equalization circuit includes a first equalization P-transistor and a first equalization N-transistor; wherein the source of the first equalization P-transistor and the drain of the first equalization N-transistor are coupled to the input terminal of the first integrating circuit, the drain of the first equalization P-transistor and the source of the first equalization N-transistor are coupled to the input terminal of the second integrating circuit, and the gates of the first equalization P-transistor and the first equalization N-transistor are used to receive the first equalization signal; the second equalization circuit includes a second equalization P-transistor and a second equalization N-transistor; wherein the source of the second equalization P-transistor and the drain of the second equalization N-transistor are coupled to the output terminal of the first integrating circuit, the drain of the second equalization P-transistor and the source of the second equalization N-transistor are coupled to the output terminal of the second integrating circuit, and the gates of the second equalization P-transistor and the second equalization N-transistor are used to receive the second equalization signal.
[0013] Additionally, the comparator circuit includes: a first input P-transistor, whose gate receives a first integration signal, and whose source is connected to the drain of a third input P-transistor, and whose drain is connected to the source of a first comparator P-transistor; a second input P-transistor, whose gate receives a second integration signal, and whose source is connected to the drain of the third input P-transistor, and whose drain is connected to the source of a second comparator P-transistor; the gate of the third input P-transistor receives a comparator enable signal, and its source receives a high-level signal; a first input N-transistor, whose gate receives a comparator enable signal, and its source receives a low-level signal, and whose drain is connected to the source of the first comparator P-transistor; a second input N-transistor, whose gate receives a comparator enable signal, and its source receives a low-level signal, and whose drain is connected to the source of the second comparator P-transistor; and a third input N-transistor, whose gate receives a comparator enable signal, and its source receives a low-level signal, and whose drain is connected to the first comparator P-transistor. The first input N-transistor has its drain connected to the drain of the second comparator N-transistor; the second input N-transistor has its gate connected to the drain of the first comparator N-transistor and its gate connected to the drain of the second comparator N-transistor; the third input N-transistor has its drain connected to the drain of the second comparator N-transistor and its gate connected to the drain of the first comparator N-transistor; the fourth input N-transistor has its gate connected to the drain of the second comparator N-transistor and its gate connected to the drain of the first comparator N-transistor; the fifth input N-transistor has its source connected to the drain of the first comparator N-transistor and its drain connected to the drain of the second comparator N-transistor; the sixth input N-transistor has its source connected to the drain of the second comparator N-transistor and its drain connected to the drain of the first comparator N-transistor; the seventh input N-transistor has its source connected to the drain of the first comparator N-transistor and its drain connected to the drain of the second comparator N-transistor; the eighth input N-transistor has its gate connected to the drain of the first comparator N-transistor and its drain connected to the drain of the second comparator N-transistor; the ninth input N-transistor has its gate connected to the drain of the first comparator N-transistor and its drain connected to the drain of the second comparator N-transistor; the eleventh input N-transistor has its gate connected to the drain of the second comparator N-transistor and its drain connected to the drain of the first ...
[0014] In addition, the test circuit also includes a pre-storage circuit, connected to the output of the comparator circuit, and receiving a first clock signal and a second clock signal. The pre-storage circuit is configured to pre-storage the level signal output by the comparator circuit based on the first clock signal, or to output the pre-storage level signal based on the second clock signal. The pre-storage circuit ensures that the signal output timing of the test circuit is consistent with the signal output timing of the memory to which the test circuit belongs, thus ensuring that the test circuit is applicable to different types of memory.
[0015] Additionally, the pre-store circuit includes: a latch, one input of which is connected to the output of the comparator circuit, and the other input of which is used to receive a first clock signal; the latch is configured to generate an indication signal based on the output level of the comparator circuit when the first clock signal is valid; and a register, one input of which is connected to the output of the latch, the clock input of which is used to receive a second clock signal, and the enable input of which is used to receive an output enable signal; the register is configured to output an indication signal when the second clock signal and the output enable signal are valid.
[0016] In addition, the test circuit also includes a control module configured to provide control signals required for duty cycle detection of the first integrator circuit, the second integrator circuit, and the comparator circuit based on a control enable signal.
[0017] Additionally, the control module includes: a clock unit configured to generate a control clock signal based on a control enable signal; a timing unit connected to the output of the clock unit, storing signal count values, configured to increment the control signal count value by one when both the control enable signal and the control clock signal are valid; and a logic unit connected to the output of the timing unit, storing control signals corresponding to each signal count value, configured to provide control signals corresponding to the signal count values based on the signal count values.
[0018] In addition, the timing unit is also used to receive test control signals. When the test control signal is valid, at least one bit of new data is added to the signal count value B. The new data bit is used to indicate whether the memory to which the test circuit belongs is in test mode.
[0019] This disclosure also provides a testing method applied to the testing circuit provided in the above embodiments, comprising: acquiring a first test signal and a second test signal, wherein the first test signal and the second test signal are inverse signals; integrating the first test signal based on a first integrating circuit to obtain a first integrated signal, and integrating the second test signal based on a second integrating circuit to obtain a second integrated signal; wherein the value of the first integrated signal is the product of the duty cycle of the first test signal and the power supply amplitude, and the value of the second integrated signal is the product of the duty cycle of the second test signal and the power supply amplitude; comparing the voltage value of the first integrated signal with the voltage value of the second integrated signal based on a comparison circuit, and determining the duty cycle of the first test signal based on an indication signal generated by the comparison circuit; wherein if the indication signal is high, the duty cycle of the first test signal is greater than 50%, and if the indication signal is low, the duty cycle of the first test signal is not greater than 50%.
[0020] Additionally, integrating the first test signal using the first integrating circuit to obtain the first integrated signal, and integrating the second test signal using the second integrating circuit to obtain the second integrated signal, includes: coupling the first integrating circuit to a power supply node and coupling the second integrating circuit to a ground node; disconnecting the coupling between the first integrating circuit and the power supply node, and disconnecting the coupling between the second integrating circuit and the ground node, and connecting the first integrating circuit and the second integrating circuit for potential equalization; disconnecting the connection between the first integrating circuit and the second integrating circuit, and providing the first test signal to the first integrating circuit and the second test signal to the second integrating circuit; and obtaining the first integrated signal and the second integrated signal.
[0021] Additionally, integrating the first test signal using the first integrating circuit to obtain a first integrated signal, and integrating the second test signal using the second integrating circuit to obtain a second integrated signal, includes: coupling the first integrating circuit and the second integrating circuit to a ground node; disconnecting the coupling between the first integrating circuit and the second integrating circuit and the ground node, and connecting the first integrating circuit and the second integrating circuit to perform potential equalization; disconnecting the connection between the first integrating circuit and the second integrating circuit, and providing the first test signal to the first integrating circuit and the second test signal to the second integrating circuit; and obtaining the first integrated signal and the second integrated signal.
[0022] Furthermore, after comparing the voltage values of the first and second integral signals using a comparator circuit, the first and second integral circuits are connected to balance their input voltages.
[0023] This disclosure also provides a memory that, based on the test circuit provided in the above embodiments, detects the duty cycle of a signal to accurately test the duty cycle of the input signal. Attached Figure Description
[0024] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0025] Figure 1 This is a schematic diagram of the structure of a test circuit provided in an embodiment of the present disclosure;
[0026] Figure 2 A schematic diagram of the structure of a first integrating circuit and a second integrating circuit provided in an embodiment of the present disclosure;
[0027] Figure 3 This is a schematic diagram of the structure of a comparison circuit provided in an embodiment of the present disclosure;
[0028] Figure 4 This is a schematic diagram of the pre-storage circuit provided in an embodiment of the present disclosure;
[0029] Figure 5 This is a schematic diagram of the control logic of a control module provided in an embodiment of the present disclosure;
[0030] Figure 6 This is a schematic diagram of the structure of a control module provided in an embodiment of the present disclosure;
[0031] Figure 7 A flowchart illustrating a testing method provided in another embodiment of this disclosure;
[0032] Figure 8 A test timing diagram illustrating a test method provided in another embodiment of this disclosure;
[0033] Figure 9 This is a test timing diagram of another test method provided in another embodiment of the present disclosure. Detailed Implementation
[0034] How to test whether the duty cycle of a high-speed clock signal meets the requirements, how to ensure the accuracy of high-speed clock signal testing, and how to generate equidistant parallel clock signals based on high-speed clock signals are urgent problems to be solved.
[0035] One embodiment of this disclosure provides a test circuit for accurately testing the duty cycle of an input signal.
[0036] It will be understood by those skilled in the art that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.
[0037] Figure 1 This is a schematic diagram of the test circuit provided in this embodiment. Figure 2 This is a schematic diagram of the first and second integrating circuits provided in this embodiment. Figure 3 This is a schematic diagram of the comparator circuit provided in this embodiment. Figure 4 This is a schematic diagram of the pre-storage circuit provided in this embodiment. Figure 5 This is a schematic diagram of the control logic of the control module provided in this embodiment. Figure 6 This is a schematic diagram of the control module provided in this embodiment. The test circuit provided in this embodiment will be further described in detail below with reference to the accompanying drawings:
[0038] refer to Figure 1 The test circuit 400 is used to detect the duty cycle of the signal, including:
[0039] The first integrating circuit 401 is used to receive the first test signal Test1 and is configured to integrate the first test signal Test1 to output the first integrated signal FltNdT.
[0040] The second integrating circuit 402 is used to receive the second test signal Test2 and is configured to integrate the second test signal Test2 to output the second integrated signal FltNdC.
[0041] In this system, the first test signal Test1 and the second test signal Test2 are inverse signals. The voltage value of the first integral signal FltNdT is the product of the duty cycle of the first test signal Test1 and the power supply amplitude. The voltage value of the second integral signal FltNdC is the product of the duty cycle of the second test signal Test2 and the power supply amplitude.
[0042] The comparator circuit 403 has one input terminal connected to the first integrating circuit 401 and the other input terminal connected to the second integrating circuit 402. The comparator circuit 403 is configured to compare the magnitudes of the first integrating signal FltNdT and the second integrating signal FltNdC. When the first integrating signal FltNdT is greater than the second integrating signal FltNdC, a high-level signal is output; when the second integrating signal FltNdC is greater than the first integrating signal FltNdT, a low-level signal is output.
[0043] The first test signal Test1 is integrated by the first integrating circuit 401, and the value of the first integrated signal FltNdT is proportional to the duty cycle of the first test signal Test1. The second test signal Test2 is integrated by the second integrating circuit 402, and the value of the second integrated signal FltNdC is proportional to the duty cycle of the second test signal Test2. By converting the determination of the signal duty cycle into a comparison of the magnitude of the signal integral value, the test process of the signal duty cycle is simplified. Since the first test signal Test1 and the second test signal Test2 are inverse signals, the signal duty cycle can be accurately determined by comparing the differential signals.
[0044] Specifically, refer to Figure 2 The first integrating circuit 401 includes: a first filtering unit 501, a first preprocessing unit 510, and a second preprocessing unit 520.
[0045] The first filtering unit 501 is used to integrate the received signal, that is, the first filtering unit 501 is used to integrate the first test signal Test1.
[0046] The first preprocessing unit 510 includes: a first conducting transistor. <dt1>First pre-charged P tube <yp1>and the first pre-charged N tube <yn1>.
[0047] First conducting transistor <dt1>The drain of the transistor is used to receive the first test signal Test1, the source is connected to the input terminal of the first filter unit 501, and the gate is used to receive the first switch signal PassA; the first precharge P-tube... <yp1>The source is used to receive a high level, the drain is connected to the input terminal of the first filter unit 501, and the gate is used to receive the integration charging signal ClampF; the first pre-charge N-transistor <yn1>The source is used to receive a low level, the drain is connected to the input terminal of the first filter unit 501, and the gate is used to receive the first integrated discharge signal ClpGnd.
[0048] Specifically, the first switch signal PassA is used to activate the first preprocessing unit 510. When the first switch signal PassA turns on the first turn-on transistor... <dt1>The first filter unit 501 receives the first test signal Test1 and begins to integrate the first test signal Test1; the first pre-charged P-tube... <yp1>Based on the conduction of the integral charging signal ClampF, the input terminal of the first filter unit 501 is indirectly connected to a high level, thereby pulling up the potential of the input terminal of the first filter unit 501; the first pre-charge N-transistor <yn1>Based on the conduction of the first integral discharge signal ClpGnd, the input terminal of the first filter unit 501 is indirectly connected to a low level, thereby pulling down the potential of the input terminal of the first filter unit 501.
[0049] The second preprocessing unit 520 includes: a second on-transistor <dt2>Second pre-charged P tube <yp2>Second pre-charged N tube <yn2>.
[0050] Second conducting transistor <dt2>The drain of the second precharge P-tube is connected to the output of the first filter unit 501, the source is used to output the first integration signal FltNdT, and the gate is used to receive the second switching signal PassB. <yp2>The source of the second precharge N-transistor is used to receive a high level signal, the drain is connected to the output of the first filter unit 501, and the gate is used to receive the integration charging signal ClampF. <yn2>The drain is used to receive a low level and is connected to the input terminal of the first filter unit 501. The gate is used to receive the first integrated discharge signal ClpGnd.
[0051] Specifically, the second switch signal PassB is used to activate the second preprocessing unit 520. When the second switch signal PassB turns on the second turn-on transistor... <dt2>The first integrated signal FltNdT obtained by the first filter unit 501 can be output to the comparator circuit 403; the second pre-charged P-tube <yp2>Based on the conduction of the integral charging signal ClampF, the output terminal of the first filter unit 501 is indirectly connected to a high level, thereby raising the potential of the output terminal of the first filter unit 501; the second pre-charge N-transistor <yn2>Based on the conduction of the first integral discharge signal ClpGnd, the output terminal of the first filter unit 501 is indirectly connected to a low level, thereby pulling down the potential of the output terminal of the first filter unit 501.
[0052] Continue to refer to Figure 2 The second integrating circuit 402 includes: a second filtering unit 502, a third preprocessing unit 530, and a fourth preprocessing unit 540.
[0053] The second filtering unit 502 is used to integrate the received signal, that is, the second filtering unit 502 is used to integrate the second test signal Test2.
[0054] The third preprocessing unit 530 includes: a third on-transistor <dt3>Third pre-charged P tube <yp3>and the third pre-charged N tube <yn3>.
[0055] Third conducting transistor <dt3>The drain of the transistor is used to receive the second test signal Test2, the source is connected to the input of the second filter unit 502, and the gate is used to receive the first switch signal PassA; the third pre-charge P-tube... <yp3>The source and gate are connected and used to receive high levels; the drain is connected to the input of the second filter unit 502; the third pre-charged N-transistor <yn3>The source is used to receive a low level, the drain is connected to the input terminal of the second filter unit 502, and the gate is used to receive the second integral discharge signal Clamp.
[0056] Specifically, the first switch signal PassA is used to activate the third preprocessing unit 530. When the first switch signal PassA turns on the third turn-on transistor... <dt3>The second filter unit 502 receives the second test signal Test2 and begins to integrate the second test signal Test2; the third pre-charged P-tube... <yp3>When both the gate and source receive a high level, the third precharged P-transistor... <yp3>The transistor is in the off state to prevent a high level from pulling up the input of the second filter unit 502; the third pre-charged N-transistor... <yn3>Based on the conduction of the second integral discharge signal Clamp, the input terminal of the second filter unit 502 is indirectly connected to a low level, thereby pulling down the potential of the output terminal of the second filter unit 502.
[0057] The fourth preprocessing unit 540 includes: a fourth on-transistor <dt3>Fourth pre-charged P tube <yp4>and the fourth pre-charged N tube <yn4>.
[0058] Fourth conducting transistor <dt3>The drain is connected to the output of the second filter unit 502, the source is used to output the second integration signal FltNdC, and the gate is used to receive the second switching signal PassB. The fourth precharge P-tube... <yp4>The source and gate are connected and used to receive high levels; the drain is connected to the output of the second filter unit 502; the fourth precharged N-transistor <yn4>The source is used to receive a low level, the drain is connected to the output of the second filter unit 502, and the gate is used to receive the second integral discharge signal Clamp.
[0059] Specifically, the second switch signal PassB is used to activate the fourth preprocessing unit 540. When the second switch signal PassB turns on the fourth turn-on transistor... <dt3>The second integrated signal FltNdC obtained by the second filter unit 502 can be output to the comparator circuit 403; the fourth pre-charged P-tube <yp4>When both the gate and source receive a high level, the fourth precharged P-transistor... <yp4>The transistor is in the off state to prevent a high level from pulling up the output of the second filter unit 502; the fourth pre-charged N-transistor... <yn4>Based on the conduction of the second integral discharge signal Clamp, the output terminal of the second filter unit 502 is indirectly connected to a low level, thereby pulling down the potential of the output terminal of the second filter unit 502.
[0060] Continue to refer to Figure 2 In this embodiment, the first filtering unit 501 is configured as a second-order RC filter; correspondingly, the second filtering unit 502 is also configured as a second-order RC filter.
[0061] It should be noted that in other embodiments, the first filtering unit and the second filtering unit may be configured to use first-order or higher-order RC filters simultaneously; correspondingly, in some embodiments, the order of the RC filters of the first filtering unit and the second filtering unit may also be set to different orders, and the first filtering unit and the second filtering unit may use other types of filters.
[0062] In some embodiments, the test circuit 400 further includes a first equalization circuit 521 and a second equalization circuit 522.
[0063] In this circuit, one end of the first equalization circuit 521 is connected to the input terminal of the first integrator circuit 401, and the other end is connected to the input terminal of the second integrator circuit 402. The first equalization circuit 521 is configured to make the voltages at the input terminals of the first integrator circuit 401 and the second integrator circuit 402 the same based on the first equalization signal EqA. One end of the second equalization circuit 522 is connected to the output terminal of the first integrator circuit 401, and the other end is connected to the output terminal of the second integrator circuit 402. The second equalization circuit 522 is configured to make the initial voltages of the first integrator signal FltNdT and the second integrator signal FltNdC the same based on the second equalization signal EqB.
[0064] Specifically, in this embodiment, the first equalization circuit 521 includes: a first equalization P-transistor. <ep1>and the first equalization N-tube <en1>Among them, the first equalization P-tube <ep1>The source and the first equalizing N-tube <en1>The drain of the first equalizing P-tube is coupled to the input terminal of the first integrating circuit 401. <ep1>The drain and the first equalizing N-tube <en1>The source of the first equalizing P-tube is coupled to the input of the second integrator circuit 402. <ep1>The gate and the first equalized N-transistor <en1>The gate of the equalization circuit 522 is used to receive the first equalization signal EqA. The second equalization circuit 522 includes: a second equalization P-transistor. <ep2>Second Equalization N-tube <en2>Among them, the second equalization P-tube <ep2>The source and the second equalization N-tube <en2>The drain of the second equalizing P-tube is coupled to the output of the first integrating circuit 401. <ep2>Drain and second equalization N-tube <en2>The source is coupled to the output of the second integrator circuit 402, and the second equalizing P-tube... <ep2>The gate and the second equalized N-transistor <en2>The gate is used to receive the second equalization signal EqB.
[0065] In this embodiment, reference continues to be made to Figure 2 One end of the first equalization circuit 521 is connected to the input terminal of the first filter unit 501, and the other end is connected to the input terminal of the second filter unit 502. The first equalization circuit 521 is configured to make the voltages at the input terminals of the first filter unit 501 and the second filter unit 502 the same based on the first equalization signal EqA. One end of the second equalization circuit 522 is connected to the second turn-on transistor. <dt2>The drain of one end is connected to the fourth conducting transistor at the other end. <dt4>The drain of the first integral signal FltNdT and the second integral signal FltNdC are configured to have the same initial voltage based on the second equalization signal EqB.
[0066] It should be noted that for the first equalization circuit 521 and the second equalization circuit 522, the equalization transistors that need to be turned on can be set according to the actual needs of the test circuit after equalization. For example, if the input terminals of the first filter unit 501 and the second filter unit 502 need to be at an intermediate level after equalization by the first equalization circuit 521, then the first equalization P transistor should be used. <ep1>The input potentials of the first filter unit 501 and the second filter unit 502 are balanced; if it is required that the inputs of the first filter unit 501 and the second filter unit 502 be at a low level after being balanced by the first equalization circuit 521, then the first equalization N-transistor is used. <en1>The input potentials of the first filter unit 501 and the second filter unit 502 are balanced; if the initial voltages of the first integral signal FltNdT and the second integral signal FltNdC are required to be at an intermediate level after being balanced by the second equalization circuit 522, then the second equalization P-tube is used. <ep2>The initial voltages of the first integral signal FltNdT and the second integral signal FltNdC are equalized. If the initial voltages of the first integral signal FltNdT and the second integral signal FltNdC are required to be low after being equalized by the second equalization circuit 522, then the second equalization N-transistor is used. <en2>The initial voltages of the first integral signal FltNdT and the second integral signal FltNdC are equalized.
[0067] Before integration by the first integrating circuit 401 and the second integrating circuit 402, the input and output voltages of the first integrating circuit 401 and the second integrating circuit 402 are balanced to ensure the accuracy of the difference between the integrated values of the first integrating circuit 401 and the second integrating circuit 402, thereby further ensuring the accuracy of the duty cycle of the subsequently acquired signal. In addition, during the subsequent output of the first integrated signal FltNdT and the second integrated signal FltNdC, the power consumption of the test circuit can be further reduced by activating the first equalizing circuit 521 and the second equalizing circuit 522.
[0068] refer to Figure 3 In this embodiment, the comparator circuit 403 includes:
[0069] First input P-tube <sp1>The gate is used to receive the first integration signal FltNdT, and the source is connected to the third input P-channel transistor. <sp3>The drain is connected to the first comparator P-channel. <bp1>The source pole.
[0070] Second input P-tube <sp2>The gate is used to receive the second integration signal FltNdC, and the source is connected to the third input P-channel transistor. <sp3>The drain is connected to the second comparator P-channel. <bp2>The source pole.
[0071] The third input P-tube <sp3>The gate of the transistor is used to receive the comparator enable signal CkN, and the source is used to receive the high-level signal, i.e., the third input P-transistor. <sp3>As a high-level protection transistor of the comparator circuit 403, the high level required for the operation of the comparator circuit 403 is provided by the comparator enable signal CkN.
[0072] First input N-channel transistor <sn1>The gate is used to receive the comparator enable signal CkN, the source is used to receive a low-level signal, and the drain is connected to the first comparator P-transistor. <bp1>The source pole.
[0073] Second input N-channel transistor <sn2>The gate is used to receive the comparator enable signal CkN, the source is used to receive a low-level signal, and the drain is connected to the second comparator P-transistor. <bp2>The source pole.
[0074] Third input N-transistor <sn3>The gate is used to receive the comparator enable signal CkN, the source is used to receive a low-level signal, and the drain is connected to the first comparator N-transistor. <bn1>The drain electrode.
[0075] Fourth input N-tube <sn4>The gate is used to receive the comparator enable signal CkN, and the source is used to receive a low-level signal. The source is connected to the second comparator N-transistor. <bn2>The drain electrode.
[0076] First comparison P-tube <bp1>The drain connection of the first comparator N-channel transistor <bn1>The drain and gate of the second comparator N-channel transistor are connected. <bn2>The drain of the second comparison P-tube <bp2>The drain of the second comparator N-channel MOSFET is connected. <bn2>The drain and gate are connected to the first comparator N-channel transistor. <bn1>The drain of the first N-type transistor is compared. <bn1>The source is used to receive low-level signals, the drain is used to output the first comparator output signal OutP, and the gate is connected to the second comparator N-transistor. <bn2>The drain of the second N-type transistor. <bn2>The source is used to receive a low-level signal, the drain is used to output the second comparison output signal OutN, and the gate is connected to the drain of the first comparison N-transistor; wherein, one of the first comparison output signal OutP and the second comparison output signal OutN is used as the output signal of the comparison circuit 403, and the other is used as the inverted signal of the output signal.
[0077] Specifically, such as Figure 3 As shown, the first input P-tube <sp1>The gate is used to receive the first integration signal FltNdT, and the second input P-tube <sp2>The gate is used to receive the second integration signal FltNdC. At this time, the comparator circuit 403 compares and amplifies the first integration signal FltNdT and the second integration signal FltNdC to generate a first comparison output signal OutP and a second comparison output signal OutN. One of the first comparison output signal OutP or the second comparison output signal OutN is used to characterize the comparison result of the first integration signal FltNdT and the second integration signal FltNdC, and the other is used as the inverted signal of the signal characterizing the comparison result.
[0078] It should be noted that in this embodiment, the first comparison output signal OutP is used to characterize the comparison result of the first integral signal FltNdT and the second integral signal FltNdC, and the second comparison output signal OutN is used as the inverted signal of the first comparison output signal OutP for detailed explanation. This does not constitute a limitation of this embodiment. In other embodiments, the second comparison output signal can also be used to characterize the comparison result of the first integral signal and the second integral signal. More specifically, for the first integral signal FltNdT, if the integral value is greater than 1 / 2*Vcc (Vcc is the power supply amplitude), the corresponding first comparison output signal OutP is high; if the integral value is less than 1 / 2*Vcc, the corresponding first comparison output signal OutP is low.
[0079] In some embodiments, reference Figure 4 The test circuit 400 further includes a pre-storage circuit 600, which is connected to the output of the comparator circuit 400 and receives a first clock signal Clk and a second clock signal Clklat. The pre-storage circuit 600 is configured to pre-storage the level signal output by the comparator circuit 403 based on the first clock signal Clk, or to output the pre-storage level signal based on the second clock signal Clklat.
[0080] The pre-stored circuit 600 ensures that the signal output timing of the test circuit 400 is consistent with the signal output timing of the memory to which the test circuit 400 belongs, so as to ensure that the test circuit 400 can be applied to different types of memory.
[0081] In this embodiment, reference Figure 4 The pre-stored circuit 600 includes:
[0082] Latch 601 is connected at one end to the output of comparator circuit 601 and at the other end to receive the first clock signal Clk. Latch 601 is configured to generate an indication signal Result based on the output level of the comparator circuit when the first clock signal Clk is a valid signal.
[0083] Specifically, latch 601 includes: a first latch NAND gate, one input for receiving a first comparison output signal OutP, and another input for receiving a first clock signal Clk; a second latch NAND gate, one input for receiving a second comparison output signal OutN, and another input for receiving the first clock signal Clk; a third latch NAND gate, one input connected to the output of the first latch NAND gate, and another input connected to the output of the fourth latch NAND gate; and a fourth latch NAND gate, one input connected to the output of the second latch NAND gate, and another input connected to the output of the third latch NAND gate, with the output being used to output an indicator signal Result.
[0084] Register 602 has its input terminal D connected to the output terminal of latch 601, its clock terminal C used to receive the second clock signal Clklat, and its enable terminal RN used to receive the output enable signal ComEn. Register 602 is configured to output an indicator signal Result when the second clock signal Clklat and the output enable signal ComEn are valid.
[0085] It should be noted that in some embodiments, register 603 can be set using the FF register.
[0086] In some embodiments, the test circuit 400 further includes a control module 700, referenced Figure 5 The control module 700 is configured to provide the control signals required for duty cycle detection of the first integrator circuit 401, the second integrator circuit 402, and the comparator circuit 403 based on the control enable signal ControlEn.
[0087] Specifically, the control signals required for duty cycle detection by the first integrating circuit 401, the second integrating circuit 402, and the comparator circuit 403 include: a first equalization signal EqA and a second equalization signal EqB, an integrating charging signal ClampF, a first integrating discharging signal ClpGnd and a second integrating discharging signal Clamp, a first switching signal PassA and a second switching signal PassB, a comparator enable signal CkN, a first clock signal Clk, a second clock signal Clklat, and an output enable signal ComEn.
[0088] In this embodiment, reference Figure 5 The control module 700 includes:
[0089] Clock unit 710 is configured to generate a control clock signal ControlClk based on the control enable signal ControlEn.
[0090] The timing unit 720 is connected to the output terminal of the clock unit 710 and stores the signal count value B. The timing unit 720 is configured to increment the control signal count value B by one when the control enable signal ControlEn and the control clock signal ControlClk are valid signals.
[0091] The logic unit 730, connected to the output of the timing unit 720, stores the control signal corresponding to the signal count value B and is configured to provide the control signal corresponding to the signal count value B based on the signal count value B.
[0092] Specifically, the clock unit 710 is configured with a ring oscillator, and the control enable signal ControlEn is used as the enable signal for the ring oscillator. The signal count value B is illustrated by taking a 7-bit signal composed of 7 bits as an example, which does not constitute a limitation on this embodiment. In actual configuration, the number of bits of the signal count value can be configured according to actual needs.
[0093] In this embodiment, reference continues to be made to Figure 6 The timing unit 720 is also used to receive the test control signal ProbeMode. When the test control signal ProbeMode is valid, at least one bit of new data Bmax is added to the signal count value B. The new data bit Bmax increases the change period of the control clock signal ControlClk by increasing the number of bits in the signal count value B, providing a redundant time period for testing the test circuit, so as to effectively detect whether there is a fault in the test circuit and ensure the effective operation of the test circuit.
[0094] In this embodiment, the first test signal Test1 is integrated by the first integrating circuit 401, and the value of the first integrated signal FltNdT is proportional to the duty cycle of the first test signal Test1. The second test signal Test2 is integrated by the second integrating circuit 402, and the value of the second integrated signal FltNdC is proportional to the duty cycle of the second test signal Test2. By converting the determination of the signal duty cycle into a comparison of the magnitude of the signal integral value, the test process of the signal duty cycle is simplified. Since the first test signal Test1 and the second test signal Test2 are opposite signals, the comparison of the opposite signals is used to accurately determine whether the signal duty cycle is greater than 50%.
[0095] All units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this disclosure, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this disclosure; however, this does not mean that other units are absent from this embodiment.
[0096] It should be noted that the features disclosed in the test circuits provided in the above embodiments can be arbitrarily combined without conflict to obtain new test circuit embodiments.
[0097] Another embodiment of this disclosure provides a testing method that uses the testing circuit provided in the above embodiments to accurately test the duty cycle of the input signal.
[0098] Figure 7 This is a flowchart illustrating the testing method provided in this embodiment. Figure 8 This is a test timing diagram of a test method provided in this embodiment. Figure 9 This is a test timing diagram of another test method provided in this embodiment. The test method provided in this embodiment will be further described in detail below with reference to the accompanying drawings:
[0099] refer to Figure 7 Test methods include:
[0100] Step 701: Obtain the first test signal and the second test signal; wherein the first test signal and the second test signal are inverse signals.
[0101] Step 702: Integrate to obtain the first integral signal and the second integral signal.
[0102] Specifically, the first test signal is integrated based on the first integrating circuit to obtain the first integrated signal; the second test signal is integrated based on the second integrating circuit to obtain the second integrated signal; wherein, the value of the first integrated signal is the product of the duty cycle of the first test signal and the power supply amplitude, and the value of the second integrated signal is the product of the duty cycle of the second test signal and the power supply amplitude.
[0103] In a specific example, refer to Figure 8 Step 702 includes: coupling the first integrating circuit to the power supply node and coupling the second integrating circuit to the ground node; disconnecting the coupling between the first integrating circuit and the power supply node, and disconnecting the coupling between the second integrating circuit and the ground node, and connecting the first integrating circuit and the second integrating circuit to perform potential equalization; disconnecting the connection between the first integrating circuit and the second integrating circuit, and providing a first test signal to the first integrating circuit and a second test signal to the second integrating circuit, and acquiring the first integrating signal and the second integrating signal.
[0104] Specifically, in stage t1, the pre-charging stage, the first integrating circuit is coupled to the power supply node, and the second integrating circuit is coupled to the ground node. In this embodiment, the first integrating circuit is pre-charged to a high level and the second integrating circuit is pre-charged to a low level using the Cl signal (the Cl signal includes: the integrating charging signal ClampF, the first integrating discharging signal ClpGnd, and the second integrating discharging signal Clamp). The dashed line Tk in stage t1 represents the time node at which the test circuit starts. In stage t2, the equalization stage, the coupling between the first integrating circuit and the power supply node is disconnected, and the coupling between the second integrating circuit and the ground node is also disconnected. The first and second integrating circuits are then connected for potential equalization. In this embodiment, the first and second integrating circuits are connected using the first equalization signal EqA and the second equalization signal EqB. At this time, the potential of the first and second integrating circuits after equalization is Vcc / 2 (Vcc is the voltage provided by the high level). In stage t3, the integration and sampling stage, a first switch signal PassA and a second switch signal PassB are provided, along with a first test signal and a second test signal. The first integrator integrates the first test signal to obtain the first integrated signal, and the second integrator integrates the second test signal to obtain the second integrated signal. In stage t4, the comparison stage, the second switch signal PassB is disconnected. Since the first switch signal PassA is not disconnected, the first and second integrators continue to integrate, but their integrated values no longer affect the input of the comparison circuit. The comparison circuit compares and amplifies the values of the first and second integrated signals when the second equalization signal PassB is disconnected, and obtains the comparison result. In this embodiment, the output comparison result is sent to the pre-store circuit to ensure that the signal output timing of the test circuit is consistent with the signal output timing of the memory to which the test circuit belongs, thus ensuring that the test circuit is applicable to different types of memory. In stage t5, the signal output stage, the pre-store circuit outputs the test result. In stage t6, the recovery stage, the test circuit performs the next signal test. The dashed line Tg in stage t6 represents the time node when the test circuit is turned off.
[0105] In a specific example, refer to Figure 9 Step 702 includes: coupling the first integrating circuit and the second integrating circuit to the ground node, disconnecting the coupling of the first integrating circuit and the second integrating circuit to the ground node, and connecting the first integrating circuit and the second integrating circuit to perform potential equalization; disconnecting the connection of the first integrating circuit and the second integrating circuit, providing a first test signal to the first integrating circuit, providing a second test signal to the second integrating circuit, and acquiring the first integrating signal and the second integrating signal.
[0106] Specifically, in stage t1, the pre-charging stage, the first and second integrating circuits are coupled to the ground node, i.e., pre-charged to a low level by the Cl signal (the Cl signal includes: the integrating charging signal ClampF, the first integrating discharging signal ClpGnd, and the second integrating discharging signal Clamp); where the dashed line Tk in stage t1 represents the time node when the test circuit starts. In stage t2, the equalization stage, the coupling between the first and second integrating circuits and the ground node is disconnected, and the first and second integrating circuits are connected to perform potential equalization; in this embodiment, the first and second integrating circuits are connected by the first equalization signal EqA and the second equalization signal EqB, at which point the potential of the first and second integrating circuits after equalization is Vss (Vss is the voltage provided by the low level). In stage t3, the integration sampling stage, the first switch signal PassA and the second switch signal PassB are provided, along with the first test signal and the second test signal. The first integrating circuit integrates the first test signal to obtain the first integrating signal, and the second integrating circuit integrates the second test signal to obtain the second integrating signal. In stage t4, the comparison stage, the second switch signal PassB is disconnected. Since the first switch signal PassA is not disconnected, the first and second integrator circuits are still integrating. However, the integrated values of the first and second integrator circuits no longer affect the input of the comparison circuit. The comparison circuit compares and amplifies the values of the first and second integrated signals when the second equalization signal PassB is disconnected, and obtains the comparison result. In this embodiment, the output comparison result is sent to the pre-store circuit to ensure that the signal output timing of the test circuit is consistent with the signal output timing of the memory to which the test circuit belongs, thus ensuring that the test circuit is applicable to different types of memory. In stage t5, the signal output stage, the pre-store circuit outputs the test result. In stage t6, the recovery stage, the test circuit performs the next signal test. The dashed line Tg in stage t6 represents the time node when the test circuit is turned off and stops working.
[0107] It should be noted that this embodiment provides two specific comparison methods, the core difference of which lies in:
[0108] One method uses a first equalization signal EqA and a second equalization signal EqB to equalize the potentials of the first and second integrating circuits to Vcc / 2 (Vcc is the voltage provided by the high level). The potentials of the first and second integrating circuits are Vcc / 2, and the integral value is the same as the integral value obtained with a 50% duty cycle, which helps to improve the detection accuracy and is suitable for duty cycle detection of full swing test signals.
[0109] Another method uses a first equalization signal EqA and a second equalization signal EqB to equalize the potentials of the first and second integrating circuits to a low level. When the potentials of the first and second integrating circuits are 0, the corresponding integral value is also 0, which helps to reduce the power consumption of the integrating circuit and is suitable for duty cycle detection of low swing test signals.
[0110] Continue to refer to Figure 7 Step 703: Determine whether the duty cycle of the first integral signal exceeds 50%.
[0111] Specifically, the voltage value of the first integrated signal is compared with the voltage value of the second integrated signal based on the comparison circuit, and the duty cycle of the first test signal is determined based on the indication signal generated by the comparison circuit.
[0112] Wherein, if the indicator signal is high, the duty cycle of the first test signal is greater than 50%; if the indicator signal is low, the duty cycle of the first test signal is not greater than 50%.
[0113] In some embodiments, reference Figure 8 and Figure 9 In the corresponding t5 part, the test method further includes: after comparing the voltage value of the first integral signal with the voltage value of the second integral signal based on the comparison circuit, connecting the first integral circuit and the second integral circuit.
[0114] Specifically, after the comparison circuit compares the magnitudes of the first and second integral signals, that is, during the process of outputting the comparison result, the first and second integral circuits are connected to balance the input voltages of the first and second integral circuits.
[0115] It should be noted that the features disclosed in the test methods provided in the above embodiments can be arbitrarily combined without conflict to obtain new test method embodiments.
[0116] Another embodiment of this disclosure provides a memory that, based on the test circuit provided in the above embodiments, detects the duty cycle of a signal to accurately test the duty cycle of the input signal.
[0117] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the DRAM chip conforms to the DDR2 memory specification.
[0118] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the DRAM chip conforms to the DDR3 memory specification.
[0119] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the DRAM chip conforms to the DDR4 memory specification.
[0120] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the DRAM chip conforms to the DDR5 memory specification.
[0121] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.
Claims
1. A test circuit for detecting a duty cycle of a signal, characterized by include: A first integrating circuit is configured to receive a first test signal and integrate the first test signal to output a first integrated signal. The second integrating circuit is used to receive the second test signal and is configured to integrate the second test signal to output a second integrated signal. Wherein, the first test signal and the second test signal are inverse signals, the voltage value of the first integrated signal is the product of the duty cycle of the first test signal and the power supply amplitude, and the voltage value of the second integrated signal is the product of the duty cycle of the second test signal and the power supply amplitude. The comparator circuit has one input terminal connected to the first integrator circuit and the other input terminal connected to the second integrator circuit. The comparison circuit is configured to compare the magnitudes of the first integral signal and the second integral signal, and output a high-level signal when the first integral signal is greater than the second integral signal, and output a low-level signal when the second integral signal is greater than the first integral signal. A pre-storage circuit is connected to the output of the comparator circuit and receives a first clock signal and a second clock signal; the pre-storage circuit is configured to pre-storage the level signal output by the comparator circuit based on the first clock signal, or to output the pre-storage level signal based on the second clock signal.
2. The test circuit of claim 1, wherein, The first integrating circuit includes: a first filtering unit, a first preprocessing unit, and a second preprocessing unit; The first filtering unit is used to integrate the received signal; The first preprocessing unit includes: The first conducting transistor, the first pre-charged P-transistor, and the first pre-charged N-transistor; The drain of the first conducting transistor is used to receive the first test signal, the source is connected to the input terminal of the first filtering unit, and the gate is used to receive the first switching signal. The source of the first pre-charge P transistor is used to receive a high level, the drain is connected to the input terminal of the first filtering unit, and the gate is used to receive an integral charging signal. The source of the first pre-charge N transistor is used to receive a low level, the drain is connected to the input terminal of the first filtering unit, and the gate is used to receive the first integral discharging signal. The second preprocessing unit includes: The second conducting transistor, the second pre-charged P-transistor, and the second pre-charged N-transistor; The drain of the second turn-on transistor is connected to the output terminal of the first filter unit, the source is used to output the first integration signal, and the gate is used to receive the second switching signal. The source of the second pre-charge P transistor is used to receive a high level, the drain is connected to the output terminal of the first filter unit, and the gate is used to receive the integration charging signal. The source of the second pre-charge N transistor is used to receive a low level, the drain is connected to the input terminal of the first filter unit, and the gate is used to receive the first integration discharging signal.
3. The test circuit of claim 1, wherein, The second integrating circuit includes: a second filtering unit, a third preprocessing unit, and a fourth preprocessing unit; The second filtering unit is used to integrate the received signal; The third preprocessing unit includes: The third conducting transistor, the third pre-charged P-transistor, and the third pre-charged N-transistor; The drain of the third conducting transistor is used to receive the second test signal, the source is connected to the input terminal of the second filtering unit, and the gate is used to receive the first switching signal. The source and gate of the third pre-charge P transistor are connected and used to receive a high level, and the drain is connected to the input terminal of the second filtering unit. The source of the third pre-charge N transistor is used to receive a low level, the drain is connected to the input terminal of the filtering unit, and the gate is used to receive the second integral discharge signal. The fourth preprocessing unit includes: The fourth conducting transistor, the fourth precharged P-transistor, and the fourth precharged N-transistor; The drain of the fourth conducting transistor is connected to the output terminal of the second filtering unit, the source is used to output the second integration signal, and the gate is used to receive the second switching signal. The source and gate of the fourth pre-charge P transistor are connected and used to receive a high level, and the drain is connected to the output terminal of the filtering unit. The source of the fourth pre-charge N transistor is used to receive a low level, the drain is connected to the output terminal of the second filtering unit, and the gate is used to receive the second integration discharge signal.
4. The test circuit of claim 2, wherein, The first filtering unit is configured with a second-order RC filter.
5. The test circuit of claim 2 or 3, characterized in that, Also includes: First equalization circuit and second equalization circuit; One end of the first equalization circuit is connected to the input terminal of the first integrator circuit, and the other end is connected to the input terminal of the second integrator circuit. The first equalization circuit is configured to make the voltages at the input terminals of the first integrator circuit and the second integrator circuit the same based on the first equalization signal. One end of the second equalization circuit is connected to the output terminal of the first integrator circuit, and the other end is connected to the output terminal of the second integrator circuit. The second equalization circuit is configured to make the initial voltages of the first integral signal and the second integral signal the same based on the second equalization signal.
6. The test circuit of claim 5, wherein, include: The first equalization circuit includes: a first equalization P-transistor and a first equalization N-transistor; The source of the first equalizing P transistor and the drain of the first equalizing N transistor are coupled to the input terminal of the first integrating circuit, the drain of the first equalizing P transistor and the source of the first equalizing N transistor are coupled to the input terminal of the second integrating circuit, and the gate of the first equalizing P transistor and the gate of the first equalizing N transistor are used to receive the first equalizing signal. The second equalization circuit includes: a second equalization P-transistor and a second equalization N-transistor; The source of the second equalizing P-transistor and the drain of the second equalizing N-transistor are coupled to the output of the first integrating circuit, the drain of the second equalizing P-transistor and the source of the second equalizing N-transistor are coupled to the output of the second integrating circuit, and the gates of the second equalizing P-transistor and the second equalizing N-transistor are used to receive the second equalizing signal.
7. The test circuit of claim 1, wherein, The comparison circuit includes: The first input P-transistor has its gate used to receive the first integration signal, its source connected to the drain of the third input P-transistor, and its drain connected to the source of the first comparator P-transistor; the second input P-transistor has its gate used to receive the second integration signal, its source connected to the drain of the third input P-transistor, and its drain connected to the source of the second comparator P-transistor; the gate of the third input P-transistor is used to receive a comparator enable signal, and its source is used to receive a high-level signal. The first input N-channel transistor has its gate used to receive the comparison enable signal, its source used to receive a low-level signal, and its drain connected to the source of the first comparison P-channel transistor; the second input N-channel transistor has its gate used to receive the comparison enable signal, its source used to receive a low-level signal, and its drain connected to the source of the second comparison P-channel transistor. The third input N-transistor has a gate for receiving the comparison enable signal, a source for receiving a low-level signal, and a drain connected to the drain of the first comparison N-transistor; the fourth input N-transistor has a gate for receiving the comparison enable signal, a source for receiving a low-level signal, and a drain connected to the drain of the second comparison N-transistor. The drain of the first comparator P-transistor is connected to the drain of the first comparator N-transistor, and its gate is connected to the drain of the second comparator N-transistor; the drain of the second comparator P-transistor is connected to the drain of the second comparator N-transistor, and its gate is connected to the drain of the first comparator N-transistor; the source of the first comparator N-transistor is used to receive a low-level signal, its drain is used to output a first comparator output signal, and its gate is connected to the drain of the second comparator N-transistor; the source of the second comparator N-transistor is used to receive a low-level signal, its drain is used to output a second comparator output signal, and its gate is connected to the drain of the first comparator N-transistor. Wherein, one of the first comparison output signal and the second comparison output signal is used as the output signal of the comparison circuit, and the other is used as the inverted signal of the output signal.
8. The test circuit of claim 1, wherein, The pre-stored circuit includes: The latch has one input terminal connected to the output terminal of the comparator circuit, and the other input terminal used to receive the first clock signal. The latch is configured to generate an indication signal based on the output level of the comparator circuit when the first clock signal is a valid signal. The register has an input terminal connected to the latch, a clock terminal for receiving the second clock signal, and an enable terminal for receiving the output enable signal. The register is configured to output the indication signal when the second clock signal and the output enable signal are both valid.
9. The test circuit of claim 1, wherein, Also includes: The control module is configured to provide control signals required for the first integrator circuit, the second integrator circuit, and the comparison circuit to perform duty cycle detection based on a control enable signal.
10. The test circuit of claim 9, wherein, The control module includes: A clock unit is configured to generate a control clock signal based on the control enable signal; A timing unit, connected to the output of the clock unit, stores a signal count value. The timing unit is configured to control the signal count value to increment by one when the control enable signal and the control clock signal are valid signals. A logic unit, connected to the output of the timing unit, stores the control signals corresponding to each of the signal count values, and is configured to provide the control signals corresponding to the signal count values based on the signal count values.
11. The test circuit of claim 10, wherein, The timing unit is also used to receive a test control signal. When the test control signal is valid, at least one bit of new data is added to the signal count value. The new data bit is used to characterize whether the memory to which the test circuit belongs is in test mode.
12. A test method applied to the test circuit according to any one of claims 1 to 10, characterized in that, include: Acquire a first test signal and a second test signal, wherein the first test signal and the second test signal are inverse signals of each other; The first test signal is integrated using the first integrating circuit to obtain the first integrated signal, and the second test signal is integrated using the second integrating circuit to obtain the second integrated signal. Wherein, the value of the first integral signal is the product of the duty cycle of the first test signal and the power supply amplitude, and the value of the second integral signal is the product of the duty cycle of the second test signal and the power supply amplitude. The voltage value of the first integrated signal is compared with the voltage value of the second integrated signal based on the comparison circuit, and the duty cycle of the first test signal is determined based on the indication signal generated by the comparison circuit. Wherein, if the indication signal is high, the duty cycle of the first test signal is greater than 50%; if the indication signal is low, the duty cycle of the first test signal is not greater than 50%.
13. The test method of claim 12, wherein, The step of integrating the first test signal based on the first integrating circuit to obtain a first integrated signal, and integrating the second test signal based on the second integrating circuit to obtain a second integrated signal, includes: The first integrating circuit is coupled to the power supply node, and the second integrating circuit is coupled to the ground node; Disconnect the coupling between the first integrating circuit and the power supply node, and disconnect the coupling between the second integrating circuit and the ground node, and connect the first integrating circuit and the second integrating circuit to perform potential equalization. Disconnect the first integrating circuit and the second integrating circuit, and provide the first test signal to the first integrating circuit and the second test signal to the second integrating circuit; Obtain the first integral signal and the second integral signal.
14. The test method of claim 12, wherein, The step of integrating the first test signal based on the first integrating circuit to obtain a first integrated signal, and integrating the second test signal based on the second integrating circuit to obtain a second integrated signal, includes: Couple the first integrator circuit and the second integrator circuit to the ground node; Disconnect the coupling between the first integrating circuit and the second integrating circuit and the ground node, and connect the first integrating circuit and the second integrating circuit to perform potential equalization; Disconnect the first integrating circuit and the second integrating circuit, and provide the first test signal to the first integrating circuit and the second test signal to the second integrating circuit; Obtain the first integral signal and the second integral signal.
15. The test method of claim 12 or 13, wherein, After the process of comparing the voltage value of the first integral signal with the voltage value of the second integral signal based on the comparison circuit, the first integral circuit and the second integral circuit are connected to balance the input voltage of the first integral circuit and the second integral circuit.
16. A memory, comprising: The duty cycle of a signal is detected using the test circuit based on any one of claims 1 to 10.