Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure comprises: providing a substrate, including a substrate and a first channel material layer formed on the substrate, the substrate including a first region for forming a first device and a second region for forming a second device, the first channel material layer for forming a channel of the first device; sequentially forming a stack of a planarization stop layer, a protection layer and a hard mask layer on the first channel material layer; in the second region, forming an opening in the planarization stop layer, the protection layer, the hard mask layer and the first channel material layer; filling a second channel material layer in the opening, the second channel material layer for forming a channel of the second device; removing the hard mask layer; after removing the hard mask layer, performing a deoxidation treatment on a surface of the second channel material layer; after the deoxidation treatment, performing a planarization treatment on the planarization stop layer, the protection layer and the second channel material layer which are higher than a top surface of the first channel material layer. The embodiments of the present application are beneficial to improve the performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] Semiconductor integrated circuits (ICs) are manufactured using a series of processes such as photolithography, etching, implantation, and deposition to form a large number of complex devices of various types on the same substrate and interconnect them to achieve complete electronic functions. With the rapid development of very large-scale integrated circuits, the integration density of chips is becoming higher and higher, and the size of components is becoming smaller and smaller. The various effects caused by the high density and small size of components have an increasingly prominent impact on the manufacturing results of semiconductor processes.

[0003] The flatness of a wafer plays a crucial role in the quality of semiconductor devices. Poor wafer flatness can negatively impact device manufacturing processes. For example, during epitaxial growth, uneven contact between an uneven wafer and the substrate can cause uneven thermal field distribution on the wafer surface, leading to uneven stress distribution within the wafer.

[0004] Currently, the performance of semiconductor devices needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, thereby improving the performance of semiconductor devices.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a first channel material layer formed on the substrate, the substrate including a first region for forming a first device and a second region for forming a second device, the first channel material layer in the first region being used to form a channel of the first device; sequentially forming a planarization stop layer, a protective layer and a hard mask layer stacked on the first channel material layer; forming an opening in the second region located in the hard mask layer, the protective layer, the planarization stop layer and the first channel material layer; filling the opening with a second channel material layer, the second channel material layer being used to form a channel of the second device; removing the hard mask layer; after removing the hard mask layer, performing an oxidation removal treatment on the surface of the second channel material layer; after the oxidation removal treatment, performing a planarization treatment on the planarization stop layer, the protective layer and the second channel material layer above the top surface of the first channel material layer.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the semiconductor structure formation method provided by this invention, a protective layer is added between the planarization stop layer and the hard mask layer. This protective layer protects the planarization stop layer during the deoxidation process on the surface of the second channel material layer, increasing the process window for deoxidation and reducing the probability that oxides remain on the surface of the second channel material layer. This is beneficial for subsequent planarization of the planarization stop layer, the protective layer, and the second channel material layer above the top surface of the first channel material layer. It avoids the problem of inconsistent removal rates of the second channel material layer in different regions due to excessive differences in the removal rates of oxides and the second channel material layer, thus improving the consistency of the removal rate of the second channel material layer in different regions. This, in turn, improves the flatness of the second channel material layer after planarization, and consequently, improves the performance of the semiconductor device. Attached Figure Description

[0009] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0010] Figures 7 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0011] As the background technology shows, the performance of current semiconductor devices needs improvement. This paper analyzes the reasons why the performance of semiconductor devices needs improvement, using a semiconductor structure formation method as an example.

[0012] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0013] refer to Figure 1 A substrate 100 is provided, including a substrate 1001 and a first channel material layer 1002 formed on the substrate 1001. The substrate 100 includes a first region I for forming a first device and a second region II for forming a second device. The first channel material layer in the first region I is used to form a channel for the first device.

[0014] refer to Figure 2 A mask stack 180 is formed on the substrate 100, the mask stack including a planarization stop layer 101 and a hard mask layer 103 stacked from bottom to top.

[0015] refer to Figure 3 In the second region II, an opening 110 is formed in the hard mask layer 103 and the first channel material layer 1002.

[0016] refer to Figure 4A second channel material layer 111 is filled into the opening 110, and the second channel material layer 111 is used to form the channel of the second device.

[0017] refer to Figure 5 Remove the hard mask layer 103.

[0018] refer to Figure 6 The second channel material layer 111 is planarized.

[0019] When the hard mask layer 103 is removed, the surface of the second channel material layer 111 is easily oxidized, resulting in the formation of oxides (not shown) on the surface of the second channel material layer 111. During planarization of the second channel material layer 111, the removal rate of the oxides is lower than the removal rate of the second channel material 111 itself, and the thickness of the oxides in different regions may be inconsistent. This leads to inconsistent removal rates of the second channel material layer 111 in different regions, resulting in low flatness of the second channel material layer 111 after planarization, which can easily lead to a degradation in the performance of the semiconductor device.

[0020] To address the technical problem, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising a substrate, including a base and a first channel material layer formed on the substrate, the substrate including a first region for forming a first device and a second region for forming a second device, the first channel material layer in the first region being used to form a channel of the first device; a planarization stop layer, a protective layer and a hard mask layer are sequentially formed on the first channel material layer; an opening is formed in the second region located in the hard mask layer, the protective layer, the planarization stop layer and the first channel material layer; a second channel material layer is filled in the opening, the second channel material layer being used to form a channel of the second device; the hard mask layer is removed; after removing the hard mask layer, the surface of the second channel material layer is subjected to a deoxidation treatment; after the deoxidation treatment, the planarization stop layer, the protective layer and the second channel material layer above the top surface of the first channel material layer are planarized.

[0021] In the semiconductor structure formation method provided by this invention, a protective layer is added between the planarization stop layer and the hard mask layer. This protective layer protects the planarization stop layer during the deoxidation process on the surface of the second channel material layer, increasing the process window for deoxidation and reducing the probability that oxides remain on the surface of the second channel material layer. This is beneficial for subsequent planarization of the planarization stop layer, the protective layer, and the second channel material layer above the top surface of the first channel material layer. It avoids the problem of inconsistent removal rates of the second channel material layer in different regions due to excessive differences in the removal rates of oxides and the second channel material layer, thus improving the consistency of the removal rate of the second channel material layer in different regions. This, in turn, improves the flatness of the second channel material layer after planarization, and consequently, improves the performance of the semiconductor device.

[0022] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] Figures 7 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0024] refer to Figure 7 A substrate 200 is provided, including a substrate 2001 and a first channel material layer 2002 formed on the substrate 2001. The substrate 200 includes a first region I for forming a first device and a second region II for forming a second device. The first channel material layer in the first region I is used to form a channel for the first device.

[0025] The substrate 200 is used to provide a process platform for forming semiconductor structures.

[0026] In this embodiment, the substrate 200 is a silicon substrate, that is, the material of the substrate 200 is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride, and the substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate.

[0027] The substrate 2001 is used to provide support for the subsequently formed fins and to provide a process platform for subsequent processes after the fins are formed.

[0028] Subsequently, the first channel material layer 2002 is graphically visualized to form the channel of the first device.

[0029] In this embodiment, the material of the first channel material layer is silicon. In other embodiments, the material of the first channel material layer may also be silicon germanide.

[0030] In this embodiment, the first device is an NMOS device and the second device is a PMOS device.

[0031] The first channel material layer 2002 is used to form the channel of the first device, and the substrate 200 is a silicon substrate, so that the substrate 200 can meet the requirements of NMOS devices for channel materials.

[0032] In other embodiments, the first device may be a PMOS device and the second device may be an NMOS device.

[0033] In other embodiments, the first device and the second device may also be devices with the same channel conductivity type (e.g., both are NMOS devices or both are PMOS devices) but different channel materials.

[0034] It should be noted that, in this embodiment, the substrate 200 includes a substrate 2001 and a first channel material layer 2002 formed on the substrate 2001, and the substrate 2001 and the first channel material layer 2002 are an integral structure.

[0035] In other embodiments, depending on actual process requirements, the first channel material layer may also be a film layer of other materials formed on the substrate by an epitaxial process.

[0036] It should be noted that, in this embodiment, the substrate 200 includes a sparse region (not shown) and a dense region (not shown), the pattern density of the sparse region is lower than the pattern density of the dense region, and both the dense region and the sparse region include the first region and the second region.

[0037] Specifically, the sparse pattern region is the region with a smaller opening size subsequently formed in the first channel material layer 2002; the dense pattern region is the region with a larger opening size subsequently formed in the first channel material layer 2002.

[0038] refer to Figure 8 A planarization stop layer 201, a protective layer 202, and a hard mask layer 203 are sequentially formed on the first channel material layer 2002.

[0039] The top surface of the planarization stop layer 201 is used to protect the substrate 200 and the second channel material layer 211 when the protective layer 202 is removed through planarization treatment, thereby reducing damage to the substrate 200 and the second channel material layer 211.

[0040] Furthermore, when the hard mask layer 203 and the protective layer 202 are subsequently patterned, the top surface of the planarization stop layer 201 can define a stop position, thereby reducing the probability of damage to the substrate 200 and the second channel material layer 211.

[0041] As an example, the planarization stop layer 201 is made of silicon oxide. In other embodiments, the material of the planarization stop layer 201 may also include one or more of silicon nitride, a low-k dielectric layer, a metal oxide, and a metal nitride. Here, low-k dielectric means a dielectric constant k less than 3.9.

[0042] The protective layer 202 is used to protect the planarization stop layer 201 and the substrate 200.

[0043] Specifically, when the surface of the second channel material layer 211 is subsequently deoxidized, the protective layer 202 can protect the planarization stop layer 201, reducing the probability of the planarization stop layer 201 being accidentally etched during the deoxidation process when the material of the planarization stop layer 201 is silicon oxide. This reduces the probability of further damage to the exposed substrate 200 due to the removal of the planarization stop layer 201, and also helps to expand the process window for subsequent deoxidation and planarization of the second channel material layer 211.

[0044] In this embodiment, the material of the protective layer 202 satisfies the following condition: the subsequent deoxidation process has a high etching selectivity ratio for the oxide and the protective layer 202, which is beneficial to reduce the etching loss of the protective layer 202 during the subsequent deoxidation process, thereby ensuring that the protective layer 202 can protect the planarization stop layer 201 and the substrate 200. Furthermore, when the planarization stop layer 201, the protective layer 202, and the second channel material layer 211 (which are above the top surface of the first channel material layer 2002) are subsequently planarized, the removal rates of the protective layer 202 and the second channel material layer are similar, which is beneficial to remove the protective layer 202 simultaneously with the removal of the second channel material layer during the subsequent planarization process. Therefore, the material of the protective layer 202 includes one or more of monocrystalline silicon, polycrystalline silicon, and amorphous silicon. As an example, the material of the protective layer 202 is monocrystalline silicon.

[0045] It should be noted that the thickness of the protective layer 202 should not be too small or too large. If the thickness of the protective layer 202 is too small, it may lead to accidental etching of the planarization stop layer 201 and the substrate 200 located below the protective layer 202 during subsequent deoxidation processing, which is not conducive to ensuring that the protective layer 202 can protect the planarization stop layer 201 and the substrate 200. If the thickness of the protective layer 202 is too large, it increases the time required for subsequent removal of the protective layer 202, which is not conducive to saving process costs. Therefore, in this embodiment, the thickness of the protective layer 202 is 30 angstroms. Up to 200 angstroms.

[0046] The hard mask layer 203 is used as an etching mask for subsequent formation of openings.

[0047] In this embodiment, the material of the hard mask layer 203 is silicon nitride.

[0048] In this embodiment, the process for forming the planarization stop layer 201, the protective layer 202, and the hard mask layer 203 is a chemical vapor deposition process, which is beneficial for forming a dense and uniform planarization stop layer 201, protective layer 202, and hard mask layer 203. Furthermore, the processes for forming the planarization stop layer 201, protective layer 202, and hard mask layer 203 are the same, which is beneficial for improving process compatibility.

[0049] In other embodiments, the process of forming any one of the planarization stop layer 201, the protective layer 202, and the hard mask layer 203 may also include a furnace tube process or an epitaxial process.

[0050] refer to Figure 9 In the second region, an opening 210 is formed in the hard mask layer 203, the protective layer 202, the planarization stop layer 201 and the first channel material layer 2002.

[0051] The opening 210 is used to provide space for the subsequent formation of the second channel material layer.

[0052] Specifically, before forming the opening 210 located in the planarization stop layer 201, the protective layer 202, the hard mask layer 203 and the first channel material layer 2002, a photoresist layer (not shown) is formed on the hard mask layer 203.

[0053] The photoresist layer is patterned by exposure and development to form a patterned layer. Specifically, the photoresist layer can be formed by coating.

[0054] The photoresist layer is transformed into a pattern layer (not shown) by exposure and development, thereby defining the position of the opening 210.

[0055] In this embodiment, the pattern layer is used as a mask to etch the hard mask layer 203; correspondingly, the remaining hard mask layer 203 after etching is used as a mask to continue etching the protective layer 202, the planarization stop layer 201 and the first channel material layer 2002, forming an opening 210 in the hard mask layer 203, the protective layer 202, the planarization stop layer 201 and the first channel material layer 2002.

[0056] It should be noted that, in other embodiments, in the second region, after etching the first channel material layer, a portion of the substrate thickness can also be etched, such that the bottom of the opening is located in the substrate of a portion thickness.

[0057] refer to Figure 10 A second channel material layer 211 is filled into the opening 210, and the second channel material layer 211 is used to form the channel of the second device.

[0058] Subsequently, the second channel material layer 211 is patterned to form the channel of the second device.

[0059] In this embodiment, the second channel material layer 211 is formed by an epitaxial process. In other embodiments, the process for forming the second channel material layer 211 may also include chemical vapor deposition, furnace tube process or atomic layer deposition process.

[0060] In this embodiment, the top surface of the second channel material layer 211 is higher than the top surface of the first channel material layer 2002, which helps to provide a sufficient process window for the subsequent planarization process of the second channel material layer 211, thereby improving the flatness of the top surfaces of the second channel material layer 211 and the first channel material layer 2002 after the planarization process.

[0061] The material of the second channel material layer 211 is determined according to the performance requirements of the second device. In this embodiment, the second device is a PMOS device; therefore, the material of the second channel material layer 211 is silicon germanide. In other embodiments, the second channel material layer 211 may also be made of silicon.

[0062] refer to Figure 11 Remove the hard mask layer 203.

[0063] The hard mask layer 203 is removed, thereby providing a process basis for the subsequent planarization of the second channel material layer 211.

[0064] In this embodiment, after the second channel material layer 211 is filled into the opening 210, the hard mask layer 203 is removed. During the epitaxial process in the opening 210 to form the second channel material layer 211, the probability of the second channel material layer 211 being epitaxially grown on the surface of the hard mask layer 203 is low, which helps to limit the formation position of the second channel material layer 211 to the opening 210.

[0065] refer to Figure 12 After removing the hard mask layer 203, the planarization stop layer 201, the protective layer 202 and the second channel material layer 211, which are above the top surface of the first channel material layer 2002, are planarized.

[0066] When planarizing the planarization stop layer 201, protective layer 202, and second channel material layer 211 above the top surface of the first channel material layer 2002, the protective layer 202 can protect the planarization stop layer 201, increasing the process window for deoxidation treatment. This reduces the probability that oxides remain on the surface of the second channel material layer 211, which helps to avoid inconsistent removal rates of the second channel material layer 211 in different regions due to excessive differences in the removal rates of oxides 204 and the second channel material layer 211 during subsequent planarization treatment. In other words, it helps to improve the consistency of the removal rate of the second channel material layer 211 in different regions, thereby improving the flatness of the second channel material layer 211 after planarization treatment, which in turn helps to improve the performance of the semiconductor device.

[0067] Specifically, in this embodiment, during the removal of the hard mask layer 203, oxidation is easily generated on the surface of the second channel material layer 211. Therefore, after removing the hard mask layer 203, the deoxidation treatment is performed to remove the oxide 204 formed on the surface of the second channel material layer 211 due to oxidation during the removal of the hard mask layer 203.

[0068] In this embodiment, the pattern density of the sparse pattern region is lower than that of the dense pattern region. The sparser the pattern density, the easier it is for oxide 204 to form in the region. This can lead to more oxide 204 forming in the sparse pattern region than in the dense pattern region. Consequently, during the subsequent planarization process of the second channel material layer 211, the difference in the removal rate of oxide 204 and the second channel material layer 211 has a significant impact on the sparse pattern region. Therefore, in this embodiment, by performing an oxidation removal process on the surface of the second channel material layer 211 before planarization, even if there are sparse and dense pattern regions, it is beneficial to improve the flatness and height uniformity of the top surface of the second channel material layer in the sparse and dense pattern regions after planarization.

[0069] In this embodiment, the method for removing oxidation from the surface of the second channel material layer 211 includes etching.

[0070] In this embodiment, the etching process is a wet etching process, which uniformly etches the oxide 204 and minimizes damage to the second channel material layer 211. Specifically, the etching solution used in the wet etching process includes hydrofluoric acid solution.

[0071] In other embodiments, the etching process can also be a dry etching process. The etching gases used in the dry etching process include: hydrogen fluoride (HF), carbon tetrafluoride (CF4), octafluoropropane (CF8), or trifluoromethane (CHF3).

[0072] refer to Figure 13 After the deoxidation treatment, the planarization stop layer 201, the protective layer 202 and the second channel material layer 211, which are above the top surface of the first channel material layer 2002, are planarized.

[0073] The planarization stop layer 201, the protective layer 202, and the second channel material layer 211 above the top surface of the first channel material layer 2002 are planarized to provide a process basis for the formation of subsequent film layers (e.g., the second channel material layer 211 and the substrate 200 are patterned to form fins protruding from the remaining thickness of the substrate (not shown).

[0074] In this embodiment, the planarization process is a chemical mechanical polishing process. In other embodiments, other types of processes may be used for planarization.

[0075] In this embodiment, the material of the protective layer 202 includes one or more of monocrystalline silicon, polycrystalline silicon, and amorphous silicon, and the material of the first channel material layer 2002 is silicon. The planarization stop layer 201 is used to isolate the protective layer 202 and the first channel material layer 2002 and to protect the first channel material layer 2002, thereby enabling the distinction between the protective layer 202 and the first channel material layer 2002, and thus facilitating the removal of the protective layer 202 while reducing the probability of damage to the first channel material layer 2002.

[0076] In this embodiment, the planarization process for the second channel material layer 211 includes: using the top surface of the planarization stop layer 201 as the stop position, performing a first planarization process on the protective layer 202 and the second channel material layer 211; and after the first planarization process, performing a second planarization process on the planarization stop layer 201 and the second channel material layer 211.

[0077] Specifically, when the height difference between the second channel material layer 211 and the top surface of the substrate 200 is large, a first planarization process is performed first. The first planarization process has a large removal rate for the second channel material layer 211, which is conducive to the rapid removal of the second channel material layer 211, reducing the height difference between the second channel material layer 211 and the top surface of the substrate 200, and also helps to improve the flatness of the top surface of the second channel material layer 211 in each region after the first planarization process. This, in turn, helps to improve the efficiency of the planarization process of the second channel material layer 211, and improves the flatness of the top surface of the second channel material layer 211 and the substrate 200 after the second planarization process.

[0078] In this embodiment, during the first planarization process, the ratio of the removal rates of the second channel material layer 211 and the protective layer 202 should not be too small or too large. If the ratio of the removal rates of the second channel material layer 211 and the protective layer 202 is too small, the removal rate of the second channel material layer 211 will be low, and since the surface height of the second channel material layer 211 is higher than the top surface height of the protective layer 202, it will be difficult to quickly remove the second channel material layer 211, which is higher than the top surface of the planarization stop layer 201. This is not conducive to planarizing the second channel material layer 211. If the ratio of the removal rate of the second channel material layer 211 to the removal rate of the protective layer 202 is too large, it is easy to result in a low removal rate of the protective layer 202. In order to remove the protective layer 202 and the second channel material layer 211 that are higher than the top surface of the planarization stop layer 201, the process time of the first planarization process is easy to be too long, thereby increasing the impact of the first planarization process on the second channel material layer 211, and consequently resulting in an insufficient thickness of the second channel material layer 211. Therefore, in this embodiment, in the first planarization process, the ratio of the removal rate of the second channel material layer 211 to the removal rate of the protective layer 202 is 0.8 to 1.2.

[0079] In this embodiment, during the first planarization process, the ratio of the removal rates of the second channel material layer 211 and the planarization stop layer 201 should not be too small. If the ratio is too small, the planarization stop layer 201 is easily damaged during the removal of the second channel material layer 211, making it difficult to define the stop position of the first planarization process using the top surface of the planarization stop layer 201. Therefore, in this embodiment, the ratio of the removal rates of the second channel material layer 211 and the planarization stop layer 201 during the first planarization process is greater than 5.

[0080] After the first planarization process, a second planarization process is performed on the planarization stop layer 201 and the second channel material layer 211, so that when the height difference between the second channel material layer 211 and the top surface of the substrate 200 is small, the second planarization stop layer 201 and the second channel material layer 211 are subjected to a second planarization process.

[0081] Specifically, the second planarization process has a smaller difference in the removal rate of the second channel material layer 211 and the planarization stop layer 201, which is beneficial to planarize the second channel material layer 211 and the planarization stop layer 201 at a smaller rate. This, in turn, helps to improve the consistency of the time required to remove the second channel material layer 211 and the planarization stop layer 201, and to more accurately control the stop time of the planarization process.

[0082] In this embodiment, during the second planarization process, the ratio of the removal rates of the second channel material layer 211 and the planarization stop layer 201 should not be too small or too large. If the ratio is too small, the removal rate of the second channel material layer 211 will be too low, and the planarization stop layer 201 will be removed first, thereby increasing the probability of damage to the first channel material layer 2002. If the ratio is too large, the removal rate of the second channel material layer 211 will be too high, requiring more time to remove the planarization stop layer 201. This process can easily lead to excessive removal of the second channel material layer 211, which is detrimental to improving the surface flatness of the second channel material layer 211. Therefore, in this embodiment, the ratio of the removal rates of the second channel material layer 211 and the planarization stop layer 201 is between 0.8 and 1.2.

[0083] In other embodiments, when the surface height of the second channel material layer is similar to the top surface height of the protective layer, a third planarization process can also be performed on the planarization stop layer, the protective layer, and the second channel material layer in the same planarization step.

[0084] Specifically, the third planarization process has a smaller difference in the removal rate of the second channel material layer and the protective layer, which is conducive to planarizing the second channel material layer and the protective layer at similar removal rates. This, in turn, helps to improve the consistency of the time required to remove the protective layer and the second channel material layer above the top surface of the planarization stop layer, and to more accurately control the stop time of the planarization process.

[0085] It should be noted that, in this embodiment, after planarizing the second channel material layer 211, the method further includes: patterning the second channel material layer 211 and the substrate 200 to form fins (not shown) protruding from the remaining thickness of the substrate, wherein the fins are respectively located on the remaining thickness of the substrate in the first region I and the second region II.

[0086] As an example, the first channel material layer 2002, the second channel material layer 211, and a portion of the substrate are graphically represented to form fins protruding from the remaining thickness of the substrate.

[0087] Accordingly, the first channel material layer 2002 is used to form the fin located in the first region I, and the second channel material layer 211 is used to form the fin located in the second region II, so that the first device formed in the first region I and the second device formed in the second region II have channels of different materials.

[0088] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a substrate and a first channel material layer formed on the substrate, the substrate including a first region for forming a first device and a second region for forming a second device, the first channel material layer in the first region being used to form a channel of the first device; A planarization stop layer, a protective layer, and a hard mask layer are sequentially formed on the first channel material layer, such that the hard mask layer covers the top surface of the protective layer, and the protective layer covers the top surface of the planarization stop layer. In the second region, an opening is formed in the hard mask layer, the protective layer, the planarization stop layer, and the first channel material layer; A second channel material layer is filled into the opening, the second channel material layer being used to form a channel for the second device; Remove the hard mask layer; After removing the hard mask layer, the surface of the second channel material layer is subjected to deoxidation treatment; After the deoxidation treatment, the planarization stop layer, protective layer, and second channel material layer above the top surface of the first channel material layer are planarized; wherein, the step of planarizing the planarization stop layer, protective layer, and second channel material layer above the top surface of the first channel material layer includes: using the top surface of the planarization stop layer as the stop position, performing a first planarization treatment on the protective layer and the second channel material layer; and after the first planarization treatment, performing a second planarization treatment on the planarization stop layer and the second channel material layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method of deoxidizing the surface of the second channel material layer includes etching.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for forming the protective layer includes: chemical vapor deposition, furnace tube process, or epitaxial process.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the protective layer includes one or more of monocrystalline silicon, polycrystalline silicon, and amorphous silicon.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the protective layer, the thickness of the protective layer is 30 angstroms to 200 angstroms.

6. The method for forming a semiconductor structure as described in claim 2, characterized in that, The etching process is a wet etching process, and the etching solution used in the wet etching process includes: hydrofluoric acid solution; Alternatively, the etching process is a dry etching process, and the etching gas used in the dry etching process includes: hydrogen fluoride, carbon tetrafluoride, octafluoropropane or trifluoromethane.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the first planarization process, the ratio of the removal rate of the second channel material layer to the protective layer is 0.8 to 1.2, and the ratio of the removal rate of the second channel material layer to the planarization stop layer is greater than 5. In the second planarization process, the ratio of the removal rate of the second channel material layer to the planarization stop layer is 0.8 to 1.

2.

8. The method for forming a semiconductor structure according to any one of claims 1 to 7, characterized in that, In the step of filling the opening with a second channel material layer, the top surface of the second channel material layer is higher than the top surface of the first channel material layer.

9. The method for forming a semiconductor structure according to any one of claims 1 to 7, characterized in that, After filling the opening with a second channel material layer, the hard mask layer is removed.

10. The method for forming a semiconductor structure according to any one of claims 1 to 7, characterized in that, The material of the first channel material layer includes silicon or silicon germanide, and the material of the second channel material layer includes silicon germanide or silicon.

11. The method for forming a semiconductor structure according to any one of claims 1 to 7, characterized in that, The substrate includes a sparse region and a dense region, wherein the graphic density of the sparse region is lower than that of the dense region, and both the dense region and the sparse region include the first region and the second region.

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