LED chip and preparation method thereof

Abstract

The application provides an LED chip and a preparation method thereof. A sidewall protection layer is deposited on the surface of an N-type GaN layer, an active layer and a P-type GaN layer, so as to block the lateral movement of a lively metal in a reflection layer and reduce the possibility of electric leakage. In addition, a Bragg reflection mirror layer is deposited on the sidewall protection layer, a current spreading layer, a first insulation protection layer and an exposed part of the P-type GaN layer. Specifically, the cooperation of the Bragg reflection mirror layer and the sidewall protection layer can make the light loss at the junction of the N-type GaN layer and the P-type GaN layer be reflected by the Bragg reflection mirror layer, so that the originally lost light is reflected back and emitted from an emitting surface, thereby improving the light emitting efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an LED chip and its fabrication method. Background Technology

[0002] LED (Light Emitting Diode) is a solid-state lighting source that converts electrical energy into light energy. LEDs have advantages such as long lifespan, easy control, and high efficiency, and are a typical example of green energy.

[0003] Silver, being the metal with the highest reflectivity and excellent current diffusion properties, is commonly used as a current spreading layer and reflective layer in LED chips. However, when silver is used as a current spreading layer and reflective layer, its reactivity increases significantly when the LED is powered on, leading to a decrease in the reliability of the LED chip. This is mainly because silver's high reactivity causes it to spread to the surrounding area, which can easily cause a short circuit in the chip. In addition, currently, reflection is only achieved by plating silver on the P-type GaN layer. Light emitted from the sidewalls etched at the junction of the N-type GaN layer and the P-type GaN layer, as well as from the edge of the P-type GaN layer, cannot be reflected and emitted from the light-emitting surface, resulting in some light loss. Summary of the Invention

[0004] Based on this, the purpose of this invention is to provide an LED chip and its fabrication method, which aims to solve the problem in the prior art that only silver is plated on the P-type GaN layer for reflection. Due to the high reactivity of silver, there is a risk of short circuit in the chip. At the same time, the light emitted from the sidewalls etched at the junction of the N-type GaN layer and the P-type GaN layer, as well as the edge of the P-type GaN layer, cannot be reflected, resulting in light loss.

[0005] An LED chip according to an embodiment of the present invention includes a substrate and an N-type GaN layer, an active layer, and a P-type GaN layer sequentially deposited on the substrate. The chip includes a sidewall protection layer, comprising a first sidewall protection portion deposited on the surface of the N-type GaN layer, a second sidewall protection portion deposited on the surface of the active layer, and a third sidewall protection portion deposited on the surface of the P-type GaN layer. The first sidewall protection portion and the third sidewall protection portion are each provided with a first slot, the first slot being used to partially expose the N-type GaN layer and the P-type GaN layer.

[0006] In this process, a current spreading layer, a reflective layer, and a first insulating protective layer are sequentially deposited on the exposed portion of the P-type GaN layer, and a Bragg reflector layer is deposited on the sidewall protective layer, the current spreading layer, the first insulating protective layer, and the exposed portion of the P-type GaN layer.

[0007] Furthermore, the material of the sidewall protective layer is SiO2.

[0008] Furthermore, the Bragg reflector layer is a stacked structure consisting of alternating SiO2 and TiO2 layers, with the thickness of a single SiO2 layer being greater than the thickness of a single TiO2 layer.

[0009] Furthermore, when the end of the Bragg reflector layer furthest from the substrate is a TiO2 layer, the thickness of a single SiO2 layer in the Bragg reflector layer is... The thickness of a single TiO2 layer in the Bragg reflector layer is:

[0010] Furthermore, when the end of the Bragg reflector layer furthest from the substrate is a SiO2 layer, the thickness of a single SiO2 layer in the Bragg reflector layer is... The thickness of a single TiO2 layer in the Bragg reflector layer is:

[0011] Furthermore, the angle between the inclined surface of the reflective layer and the current spreading layer is 20° to 50°.

[0012] Furthermore, the material of the first insulating protective layer is any one of SiN, SiO2, and Al2O3.

[0013] Furthermore, the thickness of the sidewall protective layer is

[0014] Furthermore, the first insulating protective layer has corresponding second slots at the first slot, and the opening angles of the first slot and the second slot are the same.

[0015] According to an embodiment of the present invention, a method for preparing an LED chip is used to prepare the aforementioned LED chip, the method comprising:

[0016] An epitaxial wafer is provided, the epitaxial wafer comprising a substrate and an N-type GaN layer, an active layer and a P-type GaN layer sequentially deposited on the substrate, and the P-type GaN layer is etched until a portion of the N-type GaN layer is exposed;

[0017] Deposit a current-spreading layer on a P-type GaN layer;

[0018] A sidewall protection layer is deposited, the sidewall protection layer including a first sidewall protection portion deposited on the surface of the N-type GaN layer, a second sidewall protection portion deposited on the surface of the active layer, and a third sidewall protection portion deposited on the surface of the P-type GaN layer. The first sidewall protection portion and the third sidewall protection portion are respectively provided with a first slot, the first slot being used to expose the N-type GaN layer and the P-type GaN layer.

[0019] A reflective layer is deposited on the current spreading layer;

[0020] A first insulating protective layer is deposited on the reflective layer;

[0021] A Bragg reflector layer is deposited on the sidewall protective layer, the current spreading layer, the first insulating protective layer, and the exposed portion of the P-type GaN layer.

[0022] Compared with existing technologies, by depositing sidewall protective layers on the surfaces of the N-type GaN layer, the active layer, and the P-type GaN layer, the lateral movement of active metals in the reflective layer can be blocked, reducing the possibility of leakage. In addition, Bragg mirror layers are deposited on the sidewall protective layer, the current spreading layer, the first insulating protective layer, and the exposed portion of the P-type GaN layer. Specifically, the combination of the Bragg mirror layer and the sidewall protective layer can reflect the light that was originally lost at the junction of the N-type GaN layer and the P-type GaN layer back through the reflection of the Bragg mirror layer, and then emit light from the light-emitting surface, thereby improving the luminous efficiency. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of an LED chip from a certain angle, provided in an embodiment of the present invention;

[0024] Figure 2 This is a flowchart illustrating a method for fabricating an LED chip according to an embodiment of the present invention. Detailed Implementation

[0025] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0026] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0028] refer to Figure 1 This is a schematic diagram of the structure of an LED chip from a certain perspective according to an embodiment of the present invention. The LED chip includes a substrate 1 and an N-type GaN layer 2, an active layer 3, and a P-type GaN layer 4 sequentially deposited on the substrate 1. Specifically, the LED chip also includes a sidewall protection layer 8. The sidewall protection layer 8 includes a first sidewall protection portion deposited on the surface of the N-type GaN layer 2, a second sidewall protection portion deposited on the surface of the active layer 3, and a third sidewall protection portion deposited on the surface of the P-type GaN layer 4. The first sidewall protection portion and the third sidewall protection portion are respectively provided with a first slot, which is used to expose the N-type GaN layer 2 and the P-type GaN layer 4.

[0029] In the exposed portion of the P-type GaN layer 4, i.e., at the first slot of the third sidewall protection portion, a current spreading layer 5, a reflective layer 6, and a first insulating protective layer 7 are sequentially deposited. Furthermore, a Bragg reflector layer 9 is deposited in the sidewall protection layer 8, the current spreading layer 5, the first insulating protective layer 7, and the exposed portion of the P-type GaN layer 4. It should be noted that there is a gap between the current spreading layer 5 and the third sidewall protection portion, and the Bragg reflector layer 9 is filled into this gap and contacts the exposed portion of the P-type GaN layer 4.

[0030] Specifically, the material of the sidewall protective layer 8 is SiO2, and the thickness of the sidewall protective layer 8 is... For example, the thickness of the sidewall protective layer 8 is or And so on, but not limited to these; the current spreading layer 5, also known as the ITO thin film layer, is patterned after photolithography. The reflective layer 6 is a silver reflective layer, prepared by metal evaporation; the material of the first insulating protective layer 7 is any one of SiN, SiO2, and Al2O3. In this embodiment, the first insulating protective layer 7 is a SiN layer, and the thickness of the SiN layer is... For example, the thickness of the first insulating protective layer 7 is or And so on, but not limited to; the angle formed between the inclined surface of the reflective layer 6 and the current spreading layer 5 is 20° to 50°. For example, the angle formed between the inclined surface of the reflective layer 6 and the current spreading layer 5 is 20°, 30°, 40° or 50°, etc., but not limited to.

[0031] In addition, the first insulating protective layer 7 has a corresponding second slot at the first slot, and the opening angles of the first slot and the second slot are the same.

[0032] It should be noted that the Bragg reflector layer 9 is a stacked structure composed of alternating SiO2 and TiO2 layers, with a stacking number greater than 2, and the thickness of a single SiO2 layer is greater than the thickness of a single TiO2 layer. Specifically, when the end of the Bragg reflector layer 9 furthest from the substrate 1 is a TiO2 layer, the thickness of a single SiO2 layer in the Bragg reflector layer 9 is... For example, the thickness of a single SiO2 layer is or And so on, but not limited to this; the thickness of a single TiO2 layer in Bragg mirror layer 9 is... For example, the thickness of a single TiO2 layer is or However, this is not the only limitation. In this embodiment, the reflectivity of the Bragg reflector layer 6 can reach over 99.5%, which is higher and can improve LED brightness. When the Bragg reflector layer 6 consists of six sub-layers, namely, sequentially deposited SiO2 and TiO2 layers, specifically, the thickness of the first SiO2 layer is... The thickness of the first TiO2 layer is The thickness of the second SiO2 layer is The thickness of the second TiO2 layer is The thickness of the third SiO2 layer is The thickness of the third TiO2 layer is The etching time is 140 seconds. When the Bragg reflector layer 6 consists of 10 sublayers, that is, the sequentially deposited SiO2 and TiO2 layers, the thickness of the first SiO2 layer is... The thickness of the first TiO2 layer is The thickness of the second SiO2 layer is The thickness of the second TiO2 layer is The thickness of the third SiO2 layer is The thickness of the third TiO2 layer is The thickness of the fourth SiO2 layer is The thickness of the fourth TiO2 layer is The thickness of the fifth SiO2 layer is The thickness of the fifth TiO2 layer is The etching time is 230 seconds.

[0033] When the end of the Bragg reflector layer 9 furthest from the substrate 1 is a SiO2 layer, the thickness of a single SiO2 layer in the Bragg reflector layer 9 is... For example, the thickness of a single TiO2 layer is or However, this is not the only limitation; the thickness of a single TiO2 layer in Bragg mirror layer 9 is... For example, the thickness of a single TiO2 layer is or And so on, but not limited to this. For example, when the Bragg reflector layer 6 consists of 55 sublayers, and the last layer is a SiO2 layer, the wavelength range of the reflected light is 400nm to 800nm, and the total thickness is approximately... The etching time was 1460s.

[0034] The thickness of the film is mainly set according to the Bragg mirror principle. The refractive index of SiO2 is 1.47 and the refractive index of TiO2 is 2.53. The Bragg mirror principle is that it is composed of alternating high and low refractive index materials with a thickness of 1 / (4×N) wavelength. When passing through a thin film, it will be reflected twice on the upper and lower surfaces. The thickness of the film will affect the optical path difference between the two reflections. If the film thickness is controlled to be wavelength λ / (4×N), the optical path difference between the two reflections corresponds to a 180° phase transition. One of the reflections will also undergo a 180° phase transition, so the two reflected lights will eventually be in phase, which can achieve total internal reflection. N represents the refractive index.

[0035] Furthermore, after the Bragg reflector layer 9 is deposited, a first N-type electrode 11 and a first P-type electrode 12 are deposited at the corresponding positions of the N-type GaN layer 2 and the P-type GaN layer 4, respectively. The first N-type electrode 11 and the first P-type electrode 12 are not connected. Subsequently, a second insulating protective layer 10 is deposited on the first N-type electrode 11 and the first P-type electrode 12. The material of the second insulating protective layer 10 is any one of SiN, SiO2, and Al2O3. Finally, a corresponding second N-type electrode 13 and a second P-type electrode 14 are deposited on the first N-type electrode 11 and the first P-type electrode 12, respectively. Tin is brushed onto the second N-type electrode 13 and the second P-type electrode 14 to form tin pads, namely N-type electrode tin pad 15 and P-type electrode tin pad 16, respectively.

[0036] Accordingly, refer to Figure 2 This invention also provides a method for preparing an LED chip, which specifically includes the following steps:

[0037] S1. Provide an epitaxial wafer, the epitaxial wafer including a substrate and an N-type GaN layer, an active layer and a P-type GaN layer sequentially deposited on the substrate, and etch the P-type GaN layer until a portion of the N-type GaN layer is exposed.

[0038] Specifically, the epitaxial wafer is organically cleaned to remove organic impurities generated during epitaxial growth and transportation. After organic cleaning, a 3μm thick photoresist layer is coated on the P-type GaN. The coating process includes two steps: homogenization and soft baking. The soft baking conditions are: baking temperature of 120℃ and baking time of 60s. After coating, exposure is performed at an exposure energy of 200mJ. After exposure, development is performed for 85s. After development, hard baking is performed to harden the photoresist. Coating, exposure, and development together are called one photolithography step, forming a special mask pattern for the MSA. Then, ICP etching is performed for 900s to etch away the exposed P-type GaN layer with a thickness of about 1μm until the N-type GaN layer is formed, forming the MSA step. Then, the photoresist is removed. In this embodiment, the ICP etching conditions are: cavity temperature set to 0℃~5℃, corresponding etching gases such as Cl2, BCl3, and CF4, and etching time of 100s~2000s.

[0039] S2. Deposit a current spreading layer on the P-type GaN layer;

[0040] After resist removal, the epitaxial wafer undergoes SPM cleaning for 30 seconds followed by two water rinses to make the surface of the epitaxial wafer more suitable for ITO growth. A layer with a thickness of [thickness missing] is then deposited on the epitaxial wafer using magnetron sputtering. After the ITO thin film is deposited, the epitaxial wafer is annealed. The annealing conditions are: annealing temperature of 550℃ and annealing time of 3min. Annealing can help the ITO and the P-type GaN layer form a better ohmic contact.

[0041] After annealing, a photolithography step is performed to form a mask with a special TCL pattern on the ITO surface. After photolithography, ITO etching is performed for 180 seconds. After etching, the resist is removed, and a special TCL mask pattern, namely the current spreading layer, can be formed on the epitaxial wafer.

[0042] In some other embodiments, the formation of the mesa step and the formation of the special mask pattern of the TCL can be completed in one photolithography step, and the ITO thin film layer can be eliminated, and the reflective layer can be used directly as the current spreading layer.

[0043] S3. Deposit a sidewall protection layer, the sidewall protection layer including a first sidewall protection portion deposited on the surface of the N-type GaN layer, a second sidewall protection portion deposited on the surface of the active layer, and a third sidewall protection portion deposited on the surface of the P-type GaN layer. The first sidewall protection portion and the third sidewall protection portion are respectively provided with a first slot, the first slot being used to expose the N-type GaN layer and the P-type GaN layer.

[0044] It should be noted that after the current-spreading layer was prepared, a layer with a thickness of [thickness missing] was deposited using chemical vapor deposition at a temperature of 300℃. After the SiO2 sidewall protective layer is deposited, a sidewall protective layer SPL photolithography is performed. After photolithography, BOE etching is performed for 200 seconds. After etching, the resist is removed, forming the first groove in the first and third sidewall protective portions. The groove walls will surround the subsequently formed silver reflective layer, which can better improve the reliability of the chip and reduce the risk of leakage and subsequent Ag migration causing positive and negative electrode conduction. In addition, the preparation order of the sidewall protective layer and the current spreading layer can be adjusted according to product requirements.

[0045] S4. Deposit a reflective layer on the current spreading layer;

[0046] Specifically, a photolithography process is performed to form a special mask for a silver reflective layer above the current spreading layer. Then, the silver reflective layer is deposited onto the partially exposed P-type GaN layer using metal evaporation. Finally, the resist is removed by stripping. In this embodiment, the metal evaporation is first performed under vacuum, achieving a vacuum level of 1×10⁻⁶. -2 After torr, the metal is deposited onto the chip surface by evaporating the corresponding metal target material, with a deposition rate of [missing information].

[0047] S5. Deposit a first insulating protective layer on the reflective layer;

[0048] Among them, a layer with a thickness of [thickness missing] was deposited by chemical vapor deposition at an environment of 230℃. The first insulating protective layer is above the silver reflective layer. In this embodiment, the first insulating protective layer is a SiN layer.

[0049] S6. A Bragg reflector layer is deposited on the sidewall protective layer, the current spreading layer, the first insulating protective layer, and the exposed portion of the P-type GaN layer.

[0050] Specifically, after the first insulating protective layer is deposited, a stack of SiO2 and TiO2 is deposited on top of the first insulating protective layer by vacuum evaporation. Specifically, the epitaxial wafer is first placed in the cavity, and then a vacuum is drawn, achieving a vacuum level of 5 × 10⁻⁶. -5 At time 1, TiO2 and SiO2 targets are evaporated sequentially to form Bragg mirror layers. The number of stacking operations is greater than 2, and the thickness of a single SiO2 layer is greater than the thickness of a single TiO2 layer. Specifically, when the end of the Bragg mirror layer furthest from the substrate is a TiO2 layer, the thickness of a single SiO2 layer in the Bragg mirror layer is [missing information]. When the end of the Bragg reflector layer furthest from the substrate is a SiO2 layer, the thickness of a single SiO2 layer in the Bragg reflector layer is...

[0051] Furthermore, after photolithography to form a special pattern on the Bragg reflector layer through photoresist coating, exposure, and development, plasma etching is performed on the Bragg reflector layer and the first insulating protective layer. The etching gases are Ar, CF4, and BCl3. The etching is carried out under the following conditions: upper power of 1000W, lower power of 500W, and cavity temperature of 0℃, so as to expose the N-type GaN layer and the P-type GaN layer.

[0052] After the resist is removed, a photolithography process is performed to form a special pattern mask for the first N-type electrode and the first P-type electrode. Then, the first N-type electrode and the first P-type electrode are deposited on the exposed silver reflective layer and the N-type GaN layer by metal evaporation. The first P-type electrode is directly connected to the silver reflective layer for normal electrical conduction, and the first N-type electrode forms an ohmic contact with the N-type GaN layer to form normal exciton recombination luminescence. After the evaporation is completed, the first N-type electrode and the first P-type electrode with a specific pattern are stripped.

[0053] After stripping, a layer with a thickness of [thickness missing] is formed over the first N-type electrode and the first P-type electrode by vapor phase chemical deposition or magnetron sputtering. SiO2 is used as the second insulating protective layer. Then, photoresist is applied, exposed and developed. After one photolithography step, ICP etching is performed to expose part of the first N-type electrode and the first P-type electrode. Then, the photoresist is removed.

[0054] After the resist is removed, a photolithography process is performed to form a special pattern mask for the second N-type electrode and the second P-type electrode. Then, the second N-type electrode and the second P-type electrode are deposited on the exposed first N-type electrode and the first P-type electrode by metal evaporation. The second N-type electrode and the second P-type electrode are directly connected to the first N-type electrode and the first P-type electrode respectively and conduct electricity normally. After the evaporation is completed, the first N-type electrode and the first P-type electrode with a specific pattern are stripped.

[0055] After stripping, a tin-brushing process is performed to form tin pads above the first N-type electrode and the first P-type electrode.

[0056] The thickness of the photoresist corresponding to each of the above photolithography steps ranges from 2.5μm to 10μm, the corresponding exposure amount is from 150mj to 1000mj, and the development time is from 50s to 250s.

[0057] In summary, the LED chip and its fabrication method in the embodiments of the present invention, by depositing sidewall protective layers on the surfaces of the N-type GaN layer, the active layer, and the P-type GaN layer, can block the lateral movement of active metals in the reflective layer and reduce the possibility of leakage. In addition, Bragg reflector layers are deposited on the sidewall protective layer, the current spreading layer, the first insulating protective layer, and the exposed portion of the P-type GaN layer. Specifically, the combination of the Bragg reflector layer and the sidewall protective layer can reflect the light that was originally lost at the junction of the N-type GaN layer and the P-type GaN layer back through the reflection of the Bragg reflector layer, and then emit light from the light-emitting surface, thereby improving the luminous efficiency.

[0058] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. An LED chip, comprising a substrate and an N-type GaN layer, an active layer, and a P-type GaN layer sequentially deposited on the substrate, characterized in that, The system includes a sidewall protection layer, which comprises a first sidewall protection portion deposited on the surface of the N-type GaN layer, a second sidewall protection portion deposited on the surface of the active layer, and a third sidewall protection portion deposited on the surface of the P-type GaN layer. The first sidewall protection portion and the third sidewall protection portion are respectively provided with a first slot, which is used to expose the N-type GaN layer and the P-type GaN layer. In this process, a current spreading layer, a reflective layer, and a first insulating protective layer are sequentially deposited on the exposed portion of the P-type GaN layer, and a Bragg reflector layer is deposited on the sidewall protective layer, the current spreading layer, the first insulating protective layer, and the exposed portion of the P-type GaN layer.

2. The LED chip according to claim 1, characterized in that, The material of the sidewall protective layer is SiO2.

3. The LED chip according to claim 1, characterized in that, The Bragg reflector layer is a stacked structure consisting of alternating SiO2 and TiO2 layers, with the thickness of a single SiO2 layer being greater than that of a single TiO2 layer.

4. The LED chip according to claim 3, characterized in that, When the end of the Bragg reflector layer furthest from the substrate is a TiO2 layer, the thickness of a single SiO2 layer in the Bragg reflector layer is: The thickness of a single TiO2 layer in the Bragg reflector layer is:

5. The LED chip according to claim 3, characterized in that, When the end of the Bragg reflector layer furthest from the substrate is a SiO2 layer, the thickness of a single SiO2 layer in the Bragg reflector layer is: The thickness of a single TiO2 layer in the Bragg reflector layer is:

6. The LED chip according to claim 1, characterized in that, The angle between the inclined surface of the reflective layer and the current spreading layer is 20° to 50°.

7. The LED chip according to claim 1, characterized in that, The material of the first insulating protective layer is any one of SiN, SiO2, and Al2O3.

8. The LED chip according to claim 1, characterized in that, The thickness of the sidewall protective layer is 9. The LED chip according to claim 1, characterized in that, The first insulating protective layer has a corresponding second slot at the first slot, and the opening angles of the first slot and the second slot are the same.

10. A method for fabricating an LED chip, characterized in that, The method for preparing the LED chip according to any one of claims 1-9 comprises: An epitaxial wafer is provided, the epitaxial wafer comprising a substrate and an N-type GaN layer, an active layer and a P-type GaN layer sequentially deposited on the substrate, and the P-type GaN layer is etched until a portion of the N-type GaN layer is exposed; Deposit a current-spreading layer on a P-type GaN layer; A sidewall protection layer is deposited, the sidewall protection layer including a first sidewall protection portion deposited on the surface of the N-type GaN layer, a second sidewall protection portion deposited on the surface of the active layer, and a third sidewall protection portion deposited on the surface of the P-type GaN layer. The first sidewall protection portion and the third sidewall protection portion are respectively provided with a first slot, the first slot being used to expose the N-type GaN layer and the P-type GaN layer. A reflective layer is deposited on the current spreading layer; A first insulating protective layer is deposited on the reflective layer; A Bragg reflector layer is deposited on the sidewall protective layer, the current spreading layer, the first insulating protective layer, and the exposed portion of the P-type GaN layer.

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