Switching converter and control circuit and control method thereof

Abstract

The application discloses a switching converter, a control circuit and a control method thereof. The control circuit comprises an error signal generation module for generating an error signal; a PFM control module for generating a first control signal according to the size relationship between a first feedback voltage of an output voltage and a first reference voltage, the size relationship between the first feedback voltage and a third reference voltage, and the error signal, generating a second control signal according to the size relationship between the first feedback voltage and a second reference voltage and the first control signal, and generating a first setting signal according to the second control signal and a clock signal; a reset signal generation module for generating a slope voltage and generating a first reset signal by using the slope voltage and the error signal; and a logic and drive module for controlling the conduction and turn-off of a high-side switch according to the first setting signal and the first reset signal. The second control signal is related to the load degree of the switching converter, so that the timing of entering the PFM mode can be accurately set.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a switching converter and its control circuit and control method. Background Technology

[0002] Switching converters have been widely used in various fields and have become an indispensable part of people's lives.

[0003] In traditional voltage-mode controlled switching converters, the converter operates in continuous current mode (CCM) under heavy load, but switches to discontinuous current mode (DCM) when the load decreases. In DCM, the switching converter typically employs pulse frequency modulation (PFM) technology. However, due to the lack of inductor current sampling information in the circuit and the slow loop response caused by the inherent structure of the voltage-mode circuit, the load level entering PFM mode is difficult to control. Furthermore, PFM mode exhibits slow response and uneven waveform during load transitions, resulting in significant ripple and overshoot voltage at the output, which imposes significant limitations in practical applications.

[0004] Therefore, a new switching converter and its control circuit are needed to solve the above problems. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide a switching converter and its control circuit and control method, which is beneficial to accurately set the timing of entering PFM mode.

[0006] According to one aspect of the present invention, a control circuit for a switching converter is provided, the switching converter including a high-side switch and an inductor, the control circuit controlling the power transfer from input voltage to output voltage by controlling the on and off of the high-side switch, the control circuit including: an error signal generation module, configured to generate an error signal whose voltage magnitude is negatively correlated with the difference between a first feedback voltage and a first reference voltage of the output voltage of the switching converter when a first control signal is in an invalid state, and to set the voltage magnitude of the error signal to a first preset value when the first control signal is in an valid state; and a PFM control module, configured to control the power transfer from input voltage to output voltage based on the relationship between the first feedback voltage and the first reference voltage, the first feedback voltage, and the first reference voltage, the first feedback voltage, the first reference voltage, and the first reference voltage, ... The system generates a first control signal based on the magnitude relationship between the voltage and the third reference voltage and the error signal, generates a second control signal based on the magnitude relationship between the first feedback voltage and the second reference voltage and the first control signal, and generates a first set signal based on the second control signal and a first clock signal, wherein the second reference voltage is greater than the first reference voltage and less than the third reference voltage; a reset signal generation module is used to generate a ramp voltage and generate a first reset signal using the ramp voltage and the error signal; a logic and drive module is used to control the on and off of the high-side switch transistor based on the first set signal and the first reset signal, wherein the second control signal is related to the load level of the switching converter.

[0007] Optionally, the PFM control module is configured to: when the first control signal is in an invalid state, if the voltage magnitude of the error signal meets a preset condition, control the first control signal to become valid; when the first control signal is in an invalid state, if the first feedback voltage is greater than the third reference voltage, control the first control signal to become valid; when the first control signal is valid, if the first feedback voltage is less than the first reference voltage, control the first control signal to become invalid.

[0008] Optionally, the preset condition includes the sum of the voltage magnitude of the error signal and the second feedback voltage of the output voltage being less than a second preset value; wherein, when the sum of the voltage magnitude of the error signal and the second feedback voltage of the output voltage is the second preset value, if the switching converter is in DCM mode, then the equivalent duty cycle of the high-side switching transistor of the switching converter at this time reaches a preset ratio with the equivalent duty cycle of the high-side switching transistor of the switching converter in CCM mode, and the preset ratio is less than 1.

[0009] Optionally, the PFM control module includes: a first comparator, with its positive input receiving the first reference voltage, its negative input receiving the first feedback voltage, and its output providing a first comparison signal; a first buffer, with its positive input receiving the second feedback voltage of the output voltage, its negative input grounded, its first output receiving the error signal, and its second output providing a duty cycle signal, the duty cycle signal being obtained by superimposing the second feedback voltage of the output voltage and the error signal, wherein the second feedback voltage of the output voltage is greater than the first feedback voltage of the output voltage; a second comparator, with its positive input receiving a second preset value, its negative input receiving the duty cycle signal, and its output providing a second comparison signal; a third comparator, with its positive input receiving the first feedback voltage, its negative input receiving the third reference voltage, and its output providing a third comparison signal; and an OR gate, with its first input receiving the first reference voltage, its negative input receiving the first reference voltage, and its output providing a third comparison signal; and an OR gate, with its first input receiving the second feedback voltage, its negative input receiving the first reference voltage, and its negative input receiving the first feedback voltage, the first comparison signal being provided by the third comparison signal. The system comprises: a first AND gate, a first input terminal receiving the second comparison signal, a second input terminal receiving the clock signal, and an output terminal providing the first logic signal; a first flip-flop, a reset terminal receiving the first comparison signal, a set terminal receiving the second set signal, and an output terminal providing the first control signal; a fourth comparator, a positive input terminal receiving the first feedback voltage, a negative input terminal receiving the second reference voltage, and an output terminal providing the fourth comparison signal; a second AND gate, a first input terminal receiving the fourth comparison signal, a second input terminal receiving the first control signal, and an output terminal providing the second control signal; and a NOR gate, a first input terminal receiving the clock signal, a second input terminal receiving the second control signal, and an output terminal providing the first set signal.

[0010] Optionally, the error signal generation module includes: a first transconductance amplifier, whose positive input terminal receives a first feedback voltage of the output voltage and whose negative input terminal receives a first reference voltage, the first transconductance amplifier being used to differentially amplify the first feedback voltage of the output voltage and the first reference voltage; an amplification module being used to amplify the output of the first transconductance amplifier; a compensation module being used to compensate the output of the amplification module; and an output module including: a second transconductance amplifier, whose positive input terminal receives a fourth reference voltage and whose negative input terminal is connected to the compensation module; a first switch being connected between the positive and negative input terminals of the second transconductance amplifier; and a first reference voltage source and a second switch being sequentially connected between the output terminal of the second transconductance amplifier and ground, the first reference voltage source being used to provide the first preset value.

[0011] Optionally, the reset signal generation module is configured to: generate a ramp voltage with a first slope according to a second clock signal when the first control signal is in an invalid state; and generate a ramp voltage with a second slope according to the second clock signal when the first control signal is in an active state, wherein the first slope is less than the second slope.

[0012] Optionally, the reset signal generation module includes: a third switch, with its first terminal receiving a first feedback voltage of the input voltage, its second terminal connected to a first node, and its control terminal receiving the first control signal; a fourth switch, with its first terminal receiving a second feedback voltage of the input voltage, and its second terminal connected to the first node, wherein the second feedback voltage of the input voltage is greater than the first feedback voltage of the input voltage; an inverter connected between the first control signal and the control terminal of the fourth switch; a third transconductance amplifier, with its positive input terminal connected to the first node and its negative input terminal grounded, used to differentially amplify the voltage of the first node and the ground voltage to obtain a differential signal; a first capacitor, with its first terminal connected to the output terminal of the third transconductance amplifier and its second terminal grounded; and a fifth switch, with its first terminal connected to the first terminal of the first capacitor, its second terminal grounded, and its control terminal connected to the second... A clock signal is provided by a common node between the first terminal of the fifth switch and the first terminal of the first capacitor, which is used to provide the ramp voltage. A second buffer has a positive input terminal receiving the first terminal of the fifth switch, a negative input terminal grounded, a first output terminal grounded through a second reference voltage source, and a second output terminal used to superimpose the voltage at the first terminal of the fifth switch with the voltage provided by the second reference voltage source to output the second superimposed signal. A third buffer has a positive input terminal connected to the output voltage, a negative input terminal grounded, a first output terminal receiving the error signal, and a second output terminal used to superimpose the output voltage with the error signal to output the first superimposed signal. A fifth comparator has a positive input terminal receiving the second output terminal of the second buffer, a negative input terminal connected to the second output terminal of the third buffer, and its output terminal used to provide the first reset signal.

[0013] Optionally, the logic and driving module includes: a second flip-flop, with a set terminal receiving the first set signal, a reset terminal receiving the first reset signal, and an output terminal for providing a pulse width modulation signal; and a driving circuit for providing the driving signal according to the pulse width modulation signal to control the on and off of the high-side switching transistor.

[0014] According to a second aspect of the present invention, a switching converter is provided, including the control circuit as described above; and a power stage circuit, including a high-side switch and an inductor, wherein the power stage circuit controls the power transfer from input voltage to output voltage by turning on and off the high-side switch.

[0015] According to a third aspect of the present invention, a control method for a switching converter is provided, the switching converter including a high-side switch and an inductor, the control circuit controlling the power transfer from input voltage to output voltage by controlling the on and off of the high-side switch, the control method comprising: when a first control signal is in an invalid state, generating an error signal whose voltage magnitude is negatively correlated with the difference between a first feedback voltage and a first reference voltage of the output voltage of the switching converter; when the first control signal is in an valid state, setting the voltage magnitude of the error signal to a first preset value; and, based on the magnitude relationship between the first feedback voltage and the first reference voltage, the first feedback... The first control signal is generated based on the magnitude relationship between the voltage and the third reference voltage and the error signal. A second control signal is generated based on the magnitude relationship between the first feedback voltage and the second reference voltage and the first control signal. A first set signal is generated based on the second control signal and the first clock signal. The second reference voltage is greater than the first reference voltage and less than the third reference voltage. A ramp voltage is generated, and a first reset signal is generated using the ramp voltage and the error signal. The high-side switch is turned on and off based on the first set signal and the first reset signal. The second control signal is related to the load level of the switching converter.

[0016] The switching converter and its control circuit and method provided by this invention can determine the timing of entering PFM mode based on the speed of load change after the load changes from heavy to light and the inductor current switches from CCM mode to DCM mode. When the load changes slowly, the change of error signal can be used to enter PFM mode. When the load changes abruptly, the relationship between the first feedback voltage and the third reference voltage can be used to enter PFM mode. This is beneficial for setting the load level for entering PFM more accurately, ensuring that the switching converter has a fast response when the load changes quickly or slowly. Moreover, when entering PFM mode, the first control signal and the first clock signal change synchronously, which is beneficial for uniform output voltage waveform.

[0017] In a preferred embodiment, the switching converter and its control circuit further set the operating voltage of the error signal according to the level state of the first control signal, so as to make the output voltage have less ripple in PFM mode and have a faster response speed when exiting PFM mode. Attached Figure Description

[0018] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0019] Figure 1 A schematic diagram of a switching converter according to an embodiment of the present invention is shown;

[0020] Figure 2 A schematic diagram of the control circuit of a switching converter according to an embodiment of the present invention is shown;

[0021] Figure 3 A circuit diagram of an error signal generation module according to an embodiment of the present invention is shown;

[0022] Figure 4 A circuit diagram of a PFM control module according to an embodiment of the present invention is shown;

[0023] Figure 5 A circuit diagram of a reset signal generation module according to an embodiment of the present invention is shown;

[0024] Figure 6 A circuit diagram of the logic and driving module according to an embodiment of the present invention is shown;

[0025] Figure 7 A timing diagram of a switching converter according to an embodiment of the present invention is shown;

[0026] Figure 8 A flowchart of a control method for a switching converter according to an embodiment of the present invention is shown. Detailed Implementation

[0027] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0028] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0029] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0030] In this application, the term "semiconductor structure" refers to the collective term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. Many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the device, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without adhering to these specific details.

[0031] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0032] Figure 1 A circuit diagram of a switching converter according to an embodiment of the present invention is shown, such as... Figure 1 As shown, the switching converter includes a power stage circuit 100 and a control circuit 200.

[0033] The power stage circuit 100 includes a high-side switch MH and a low-side switch ML connected sequentially between the input voltage VIN and ground, an inductor L connected between the common node of the high-side switch MH and the low-side switch ML and the output voltage VOUT, an equivalent series resistor Reser and a load capacitor Cload connected sequentially between the output voltage VOUT and ground, and a current source Iload connected between the output voltage VOUT and ground. The power stage circuit 100 is used to control the power transfer from the input voltage VIN to the output voltage VOUT by alternately conducting the high-side switch MH and the low-side switch ML. Furthermore, this invention does not specifically limit the structure of the power stage circuit 100; the low-side switch ML of the power stage circuit 100 can also be replaced by a rectifier diode.

[0034] Figure 2 A schematic diagram of the control circuit of a switching converter according to an embodiment of the present invention is shown, as follows: Figure 2 As shown, the control circuit 200 includes an error signal generation module 210, a PFM control module (pulse frequency modulation control module) 220, a reset signal generation module 230, and a logic and drive module 240.

[0035] The error signal generation module 210 is used to generate an error signal eao whose voltage magnitude is negatively correlated with the difference between the first feedback voltage VOUT*0.125 of the output voltage VOUT of the switching converter and the reference voltage Vref1 when the control signal PFM is in an invalid state; and to set the voltage magnitude of the error signal eao to a first preset value when the control signal PFM is in an invalid state. The error signal eao, when the control signal PFM is in an invalid state, can reflect the equivalent duty cycle of the high-side switching transistor MH. For example, the control signal PFM is, for instance, in an valid state when its level is 1 and in an invalid state when its level is 0, and the first preset value is, for example, 1.1V.

[0036] The PFM control module 220 is used to generate a control signal PFM based on the relationship between the first feedback voltage VOUT*0.125 and the reference voltage Vref1, the relationship between the first feedback voltage VOUT*0.125 and the reference voltage Vref4 (e.g., Vref1+30mV), and the error signal eao. It also generates a control signal PFM_OSC_D based on the relationship between the first feedback voltage VOUT*0.125 and the reference voltage Vref3 (e.g., Vref1+10mV) and the control signal PFM. Finally, it generates a set signal V1 based on the control signal PFM_OSC_D and a clock signal clk1.

[0037] When the control signal PFM is in an invalid state, the PFM control module 220 is configured to make the control signal PFM become valid if the voltage magnitude of the error signal eao meets the preset conditions, that is, to control the switching converter to enter the PFM mode.

[0038] The preset conditions include that the sum of the voltage magnitude of the error signal eao and the second feedback voltage VOUT*0.5 of the output voltage VOUT is less than a second preset value (e.g., 1.1V). When the sum of the voltage magnitude of the error signal eao and the second feedback voltage VOUT*0.5 of the output voltage VOUT equals the second preset value, if the switching converter is in DCM mode (discontinuous inductor current mode), then the equivalent duty cycle of the high-side switching transistor MH of the switching converter reaches a preset ratio with the equivalent duty cycle of the high-side switching transistor MH in CCM mode (continuous inductor current mode). The preset ratio is less than 1. In this embodiment, since the second feedback voltage of the output voltage VOUT is VOUT*0.5, the preset ratio is 1:2. However, in practical applications, the preset ratio can be set to any value between 40% and 60%, and can be adjusted by adjusting the second feedback voltage of the output voltage VOUT.

[0039] When the control signal PFM is in an invalid state, the PFM control module 220 is also configured to make the control signal PFM become valid if the first feedback voltage VOUT*0.125 of the output voltage VOUT is greater than the reference voltage Vref4, that is, to control the switching converter to enter the PFM mode.

[0040] When the control signal PFM is active, the PFM control module 220 is configured to make the control signal PFM inactive if the first feedback voltage VOUT*0.125 of the output voltage VOUT is less than the reference voltage Vref1, that is, to control the switching converter to exit the PFM mode.

[0041] The reset signal generation module 230 is used to generate a ramp voltage RAMP_BK, and uses the ramp voltage RAMP_BK and the error signal eao to generate a reset signal BK_c.

[0042] Furthermore, the reset signal generation module 230 can be regarded as generating a reset signal BK_c by comparing the equivalent ramp RAMP and the error signal eao. The equivalent ramp RAMP is related to the input voltage VIN and the output voltage VOUT. The initial value of the equivalent ramp RAMP is 1.1Vk*VOUT / fsw (k is the coefficient of VOUT after passing through the buffer 2213, and fsw is the switching frequency of the high-side switch MH).

[0043] The logic and drive module 240 is used to control the turn-on and turn-off of the high-side switch MH and the low-side switch ML according to the set signal V1 and the reset signal BK_c.

[0044] After entering PFM mode, the PFM control module 220 controls the conduction of the high-side switch MH according to the load level control logic of the switching converter and the drive module 240.

[0045] Specifically, when the first feedback voltage VOUT*0.125 of the output voltage VOUT is lower than the reference voltage Vref3 (i.e., the switching converter is relatively heavily loaded), the control signal PFM_OSC_D is equal to zero, the set signal V1 changes with the clock signal clk1, and immediately resets the clock signal clk, turning on the high-side switch MH. When the first feedback voltage VOUT*0.125 of the output voltage VOUT is higher than the reference voltage Vref3 (i.e., the switching converter is relatively lightly loaded), the control signal PFM_OSC_D is the control signal PFM (i.e., 1), the clock signal clk1 is shielded, and the set signal V1 is zero. When the clock signal clk1 is shielded, the output voltage VOUT does not ripple. When the set signal V1 changes with the clock signal clk1, when the clock signal clk1 has a falling edge, the set signal V1 becomes 1 to control the high-side switch MH to turn on; when the clock signal clk1 has a rising edge, the set signal V1 becomes 0. The clock signals clk1 and clk1 are out of phase.

[0046] Furthermore, when the control signal PFM is in an invalid state, the reset signal generation module 230 generates a ramp voltage RAMP_BK with a first slope according to the clock signal clk; when the first control signal PFM is in an valid state, the reset signal generation module 230 generates a ramp voltage RAMP_BK with a second slope according to the clock signal clk, wherein the first slope is less than the second slope.

[0047] Figure 3 A circuit diagram of an error signal generation module according to an embodiment of the present invention is shown, as follows: Figure 3 As shown, the error signal generation module 210 includes a transconductance amplifier gm1, an amplification module 211, a compensation module 212, an output module 213, a resistor R5, and a capacitor C4.

[0048] The positive input terminal of the transconductance amplifier gm1 is connected to the first feedback voltage VOUT*0.125 of the output voltage VOUT, and the negative input terminal is connected to the reference voltage Vref1. It is used to differentially amplify the reference voltage Vref1 and the first feedback voltage VOUT*0.125 of the output voltage VOUT.

[0049] The amplification module 211 includes a bias current source IB1, a resistor R1, and a transistor Q1 connected in sequence between the power supply voltage VDD and ground, and a transistor Q2 and a bias current source IB2 connected in sequence between the power supply voltage VDD and ground. The first terminal and the control terminal of the transistor Q1 are interconnected, and the control terminal of the transistor Q2 is connected to the output terminal of the transconductance amplifier gm1. The amplification module 211 is used to amplify the output signal of the transconductance amplifier gm1.

[0050] The compensation module 212 includes a resistor R2, a capacitor C1, and a capacitor C2 connected in series between the second terminal of transistor Q2 and the output terminal of transconductance amplifier gm2, and a resistor R3, a resistor R4, and a capacitor C3 connected in series between the second terminal of transistor Q2 and the output terminal of transconductance amplifier gm2. The compensation module 212 is used to compensate the output signal of amplification module 211.

[0051] Resistor R5 and capacitor C4 are connected in parallel between the output terminal of transconductance amplifier gm2 and ground.

[0052] Output module 213 includes transconductance amplifier gm2, switch S1, switch S2, and reference voltage source 2131. The positive input terminal of transconductance amplifier gm2 receives reference voltage Vref2, and the negative input terminal is connected to the common node of capacitors C1 and C2 and the common node of resistors R3 and R4. Switch S1 is connected between the positive and negative input terminals of transconductance amplifier gm2. Switch S2 and reference voltage source 2131 are connected sequentially between the output terminal of transconductance amplifier gm2 and ground. The on and off states of switches S1 and S2 are controlled by control signal PFM.

[0053] The output module 213 is used to set the working voltage of the error signal eao according to the level state of the control signal PFM. Its working principle is as follows: when PFM=1, both switches S1 and S2 are turned on, and the working voltage of the error signal eao is set to a first preset value (e.g., 1.1V) through the reference voltage source 2131 so that the output voltage VOUT has a small ripple in DCM mode; when PFM=0, both switches S1 and S2 are turned off, and the working voltage of the error signal eao is set to the static working voltage of CCM mode through the reference voltage Vref2.

[0054] Figure 4 A circuit diagram of a PFM control module according to an embodiment of the present invention is shown, as follows: Figure 4 As shown, the PFM control module 220 includes comparator 2211, comparator 2212, buffer 2213, comparator 2214, OR gate 2215, AND gate 2216, RS flip-flop 2217, comparator 2221, AND gate 2222, and NOR gate 2223.

[0055] The positive input of comparator 2211 receives the reference voltage Vref1, and the negative input receives the first feedback voltage VOUT*0.125 of the output voltage VOUT. It is used to output a comparison signal VC1 based on the comparison result between the reference voltage Vref1 and the first feedback voltage VOUT*0.125 of the output voltage VOUT to determine the operating mode of the inductor current IL. When the comparison signal VC1 = 1, it indicates that the load is heavy and the inductor current IL operates in CCM mode. When the comparison signal VC1 = 0, it indicates that the load is light and the inductor current IL operates in DCM mode.

[0056] The positive input terminal of comparator 2212 receives the first feedback voltage VOUT*0.125 of the output voltage VOUT, and the negative input terminal receives the reference voltage Vref4. It is used to output a comparison signal VC2 based on the comparison result between the reference voltage Vref4 and the first feedback voltage VOUT*0.125 of the output voltage VOUT.

[0057] The positive input terminal of buffer 2213 receives the second feedback voltage VOUT*0.5 of the output voltage VOUT, the negative input terminal is grounded, the first output terminal receives the error signal eao, and the second output terminal is used to superimpose the second feedback voltage VOUT*0.5 of the output voltage VOUT with the error signal eao to generate the duty cycle signal duty.

[0058] The positive input of comparator 2214 receives a second preset value V11 (e.g., 1.1V), and the negative input receives a duty cycle signal duty. It is used to output a comparison signal VC3 based on the comparison result between the first reference voltage V11 and the duty cycle signal duty.

[0059] The first input of OR gate 2215 receives comparison signal VC2, and the second input receives comparison signal VC3, which is used to output a first logic signal based on comparison signal VC2 and comparison signal VC3.

[0060] The first input of AND gate 2216 is connected to a first logic signal, and the second input is connected to a clock signal clk1. It is used to output a second set signal according to the first logic signal and the clock signal clk1.

[0061] The RS flip-flop 2217 has its reset terminal R connected to the comparison signal VC1, its set terminal S connected to the second set signal, and its output terminal Q providing the control signal PFM. When R = 1, PFM = 0. When R = 0, if S = 1, PFM = 1. Then, when S switches from 1 to 0, the level of PFM remains unchanged.

[0062] The positive input terminal of comparator 2221 receives the first feedback voltage VOUT*0.125 of the output voltage VOUT, and the negative input terminal receives the reference voltage Vref3. It is used to output a comparison signal VC4 based on the comparison result between the reference voltage Vref3 and the first feedback voltage VOUT*0.125 of the output voltage VOUT.

[0063] The first input of AND gate 2222 receives the comparison signal VC4, and the second input receives the control signal PFM. It is used to output the control signal PFM_OSC_D based on the comparison signal VC4 and the control signal PFM.

[0064] The first input of NOR gate 2223 receives the clock signal clk1, and the second input receives the control signal PFM_OSC_D. The output of NOR gate 243 provides the set signal V1.

[0065] Among them, comparator 2212 is used to determine when the switching converter enters PFM mode when the switching converter rapidly changes from heavy load to light load, and buffer 2213 and comparator 2214 are used to determine when the switching converter enters PFM mode when the switching converter slowly changes from heavy load to light load.

[0066] Furthermore, when the switching converter enters PFM mode, it is synchronized with the clock signal clk1, which is beneficial for the uniform waveform of the output voltage VOUT.

[0067] Figure 5 A circuit diagram of a reset signal generation module according to an embodiment of the present invention is shown, as follows: Figure 5 As shown, the reset signal generation module 230 includes a switch S3, a switch S4, an inverter 231, a transconductance amplifier gm3, a capacitor C5, a switch S5, a buffer 232, a reference voltage source 233, a buffer 234, and a comparator 235. The reference voltage source 232 provides a reference voltage, for example, 1.1V.

[0068] Switch S3 has its first terminal connected to the feedback voltage VIN*0.8 of the input voltage VIN, and its second terminal connected to node A. Its control terminal receives the control signal PFM. Switch S4 has its first terminal connected to the feedback voltage VIN*0.5 of the input voltage VIN, and its second terminal connected to node A. Its control terminal receives the control signal PFM after passing through inverter 231. Switches S3 and S4, along with inverter 231, are used to switch the feedback voltage of the input signal VIN to the transconductance amplifier gm3 to either feedback voltage VIN*0.5 or feedback voltage VIN*0.8, based on the control signal PFM.

[0069] The positive input of transconductance amplifier gm3 is connected to node A, and the negative input is grounded. It is used to differentially amplify the voltage VA at node A (i.e., the feedback voltage of the input signal VIN) and the ground voltage to obtain a differential signal. The first end of capacitor C5 is connected to the output of transconductance amplifier gm3, and the second end is grounded. The first end of switch S5 is connected to the output of transconductance amplifier gm3, and the second end is grounded. Switch S5 is controlled to be turned on or off by clock signal clk. The positive input of buffer 232 is connected to the first end of switch S5, and the negative input is grounded. The first output is grounded through reference voltage source 233, and the second output is used to superimpose the voltage at the first end of switch S5 with the reference voltage. The positive input of buffer 234 receives the output signal VOUT, and the negative input is grounded. The first output receives the error signal eao, and the second output is used to superimpose the output voltage with the error signal eao. The positive input terminal of comparator 235 is connected to the second output terminal of buffer 232, and the negative input terminal of comparator 235 is connected to the second output terminal of buffer 234. Comparator 235 is used to output a reset signal BK_c based on the comparison result between the output signal of buffer 232 and the output signal of buffer 234.

[0070] The ramp voltage RAMP_BK is related to the output voltage provided by buffer 232. When the clock signal clk switches to a logic low level, switch S5 is turned off, and transconductance amplifier gm3 charges capacitor C5 according to the voltage VA of node A, causing the ramp voltage RAMP_BK to rise. When the clock signal clk switches to a logic high level, switch S5 is turned on, and transconductance amplifier gm3 discharges capacitor C5 according to the voltage VA of node A, causing the ramp voltage RAMP_BK to drop rapidly to a preset value, such as zero.

[0071] Figure 6 A circuit diagram of the logic and driving module according to an embodiment of the present invention is shown, such as... Figure 6 As shown, the logic and drive module 240 includes a D flip-flop 241 and a drive circuit 242.

[0072] In this D flip-flop 241, the set terminal Clk receives the set signal V1, the input terminal D is connected to the power supply voltage VDD, the reset terminal reset receives the reset signal BK_c, and the output terminal Q provides the pulse width modulation signal PWM.

[0073] The drive circuit 242 is used to provide drive signals hdr and ldr according to the pulse width modulation signal PWM.

[0074] Among them, when the rising edge of the set terminal Clk occurs, the D flip-flop 241 synchronizes the data of the input terminal D to the output terminal Q. When the reset signal BK_c is equal to 1, the output terminal Q is 0. The clock signal clk is synchronized with the timing change of the set terminal Clk.

[0075] Figure 7 A timing diagram of a switching converter according to an embodiment of the present invention is shown below, in conjunction with... Figure 7 This invention will explain the working principle of the control circuit of the switching converter provided by the present invention.

[0076] When the load gradually changes from heavy load to light load, the first feedback voltage VOUT*0.125 of the output voltage VOUT is higher than the reference voltage Vref1. The inductor current IL changes from CCM mode to DCM mode (i.e., VC1 changes from 1 to 0). The equivalent duty cycle of the drive signal hdr decreases, making the error signal eao smaller. When the equivalent duty cycle of the drive signal hdr in DCM mode is equal to half of the equivalent duty cycle of the drive signal hdr in CCM mode, the error signal eao1 = 1.1Vk*VOUT / 2fsw. Then VC3 = 1, and the RS flip-flop 227 outputs a control signal PFM with a logic level of 1, causing the switching converter to enter PFM mode. At this time, the voltage input to the transconductance amplifier gm3 is switched from the feedback voltage VIN*0.5 of the input voltage VIN to the feedback voltage VIN*0.8 of the input voltage VIN. At the same time, switches S1 and S2 are turned on, setting the operating point of the error signal eao to the first preset value (i.e., 1.1V) to reduce the loop recovery time when exiting PFM mode, thereby reducing the ripple amplitude of the output voltage VOUT. When the load rapidly changes from heavy load to light load, the first feedback voltage VOUT*0.125 of the output voltage VOUT is higher than the reference voltage Vref1, and the inductor current IL changes from CCM mode to DCM mode (i.e., VC1 changes from 1 to 0). At this time, although the error signal eao changes slowly, the first feedback voltage VOUT*0.125 of the output voltage VOUT is higher than the reference voltage Vref4 (i.e., VC2 = 1), and the RS flip-flop 227 will also output a control signal PFM with a logic level of 1, causing the switching converter to enter PFM mode. Therefore, the control circuit of the switching converter provided by this invention can accurately set the load level for entering PFM when the load slowly changes from heavy load to light load, and has a fast transient response when the load rapidly changes from heavy load to light load.

[0077] Furthermore, when the load changes from light to heavy, the first feedback voltage VOUT*0.125 of the output voltage VOUT will be lower than the reference voltage Vref1. At this time, the PFM control circuit will output a control signal PFM with a logic level of 0, causing the switching converter to exit PFM mode. Switches S1 and S2 are then turned off, and the error signal eao operates at approximately 1.1V through loop control. The ramp voltage RAMP_BK ratio will also return to normal, allowing direct energy transfer to the output, which is beneficial for the switching converter's fast response and further reduces the voltage ripple of the output voltage VOUT.

[0078] Accordingly, the present invention also provides a control method for a switching converter.

[0079] Figure 8 A flowchart of a control method for a switching converter according to an embodiment of the present invention is shown. The control method is applied to the switching converter described above and includes:

[0080] Step S1: When the first control signal PFM is in an invalid state, an error signal eao is generated based on the difference between the first feedback voltage VOUT*0.125 of the output voltage VOUT of the switching converter and the reference voltage Vref1. When the control signal PFM is in an valid state, the voltage magnitude of the error signal eao is set to a first preset value.

[0081] Step S2: Generate a control signal PFM based on the relationship between the first feedback voltage VOUT*0.125 and the reference voltage Vref1, the relationship between the first feedback voltage VOUT*0.125 and the reference voltage Vref4 (e.g., Vref1+30mV), and the error signal eao. Generate a control signal PFM_OSC_D based on the relationship between the first feedback voltage VOUT*0.125 and the reference voltage Vref3 (e.g., Vref1+10mV) and the control signal PFM. Generate a set signal V1 based on the control signal PFM_OSC_D and a clock signal clk1.

[0082] Step S3: Generate a ramp voltage RAMP_BK, and use the ramp voltage RAMP_BK and the error signal eao to generate a reset signal BK_c;

[0083] Step S4: Control the high-side switch MH to turn on and off according to the set signal V1 and the reset signal BK_c.

[0084] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims and their equivalents.

Claims

1. A control circuit for a switching converter, the switching converter including a high-side switch and an inductor, the control circuit controlling the power transfer from input voltage to output voltage by controlling the on and off states of the high-side switch, the control circuit comprising: An error signal generation module is used to generate an error signal whose voltage magnitude is negatively correlated with the difference between the first feedback voltage and the first reference voltage of the output voltage of the switching converter when the first control signal is in an invalid state, and to set the voltage magnitude of the error signal to a first preset value when the first control signal is in an valid state. The PFM control module is configured to generate a first control signal based on the magnitude relationship between the first feedback voltage and the first reference voltage, the magnitude relationship between the first feedback voltage and the third reference voltage, and the error signal; generate a second control signal based on the magnitude relationship between the first feedback voltage and the second reference voltage and the first control signal; and generate a first set signal based on the second control signal and a first clock signal, wherein the second reference voltage is greater than the first reference voltage and less than the third reference voltage. A reset signal generation module is used to generate a ramp voltage and generate a first reset signal using the ramp voltage and the error signal; The logic and drive module is used to control the on and off of the high-side switch transistor according to the first set signal and the first reset signal. The second control signal is related to the load level of the switching converter. When the second control signal is high, the switching converter is in a light load state, and when the second control signal is low, the switching converter is in a relatively heavy load state.

2. The control circuit according to claim 1, wherein, The PFM control module is configured as follows: When the first control signal is in an invalid state, if the voltage magnitude of the error signal meets a preset condition, the first control signal is controlled to become an valid state. When the first control signal is in an invalid state, if the first feedback voltage is greater than the third reference voltage, then the first control signal is controlled to become an valid state. When the first control signal is in an active state, if the first feedback voltage is less than the first reference voltage, then the first control signal is controlled to become in an inactive state.

3. The control circuit according to claim 2, wherein, The preset condition includes that the sum of the voltage magnitude of the error signal and the second feedback voltage of the output voltage is less than a second preset value; Wherein, when the sum of the voltage magnitude of the error signal and the second feedback voltage of the output voltage is the second preset value, if the switching converter is in DCM mode, then the equivalent duty cycle of the high-side switching transistor of the switching converter reaches a preset ratio with the equivalent duty cycle of the high-side switching transistor of the switching converter in CCM mode, and the preset ratio is less than 1.

4. The control circuit according to any one of claims 1 to 3, wherein, The PFM control module includes: The first comparator receives the first reference voltage at its positive input terminal, receives the first feedback voltage at its negative input terminal, and provides a first comparison signal at its output terminal. The first buffer has a positive input terminal that receives the second feedback voltage of the output voltage, a negative input terminal that is grounded, a first output terminal that receives the error signal, and a second output terminal that provides a duty cycle signal. The duty cycle signal is obtained by superimposing the second feedback voltage of the output voltage and the error signal. The second feedback voltage of the output voltage is greater than the first feedback voltage of the output voltage. The second comparator receives a second preset value at its positive input terminal, receives the duty cycle signal at its negative input terminal, and provides a second comparison signal at its output terminal. The third comparator receives the first feedback voltage at its positive input terminal, receives the third reference voltage at its negative input terminal, and provides a third comparison signal at its output terminal. OR gate, the first input terminal receives the third comparison signal, the second input terminal receives the second comparison signal, and the output terminal is used to provide the first logic signal; The first AND gate receives the first logic signal at its first input terminal, receives the clock signal at its second input terminal, and provides a second set signal at its output terminal. The first flip-flop has a reset terminal that receives the first comparison signal, a set terminal that receives the second set signal, and an output terminal that provides the first control signal. The fourth comparator receives the first feedback voltage at its positive input terminal, receives the second reference voltage at its negative input terminal, and provides a fourth comparison signal at its output terminal. The second AND gate has a first input terminal receiving the fourth comparison signal, a second input terminal receiving the first control signal, and an output terminal used to provide the second control signal. The NOR gate receives the clock signal at its first input, the second control signal at its second input, and provides the first set signal at its output.

5. The control circuit according to claim 1, wherein, The error signal generation module includes: A first transconductance amplifier receives a first feedback voltage of the output voltage at its positive input terminal and a first reference voltage at its negative input terminal. The first transconductance amplifier is used to differentially amplify the first feedback voltage and the first reference voltage of the output voltage. An amplification module is used to amplify the output of the first transconductance amplifier; A compensation module is used to compensate the output of the amplification module; Output module, including: The second transconductance amplifier receives the fourth reference voltage at its positive input terminal and is connected to the compensation module at its negative input terminal. A first switch is connected between the positive and negative input terminals of the second transconductance amplifier; and A first reference voltage source and a second switch are sequentially connected between the output terminal of the second transconductance amplifier and ground. The first reference voltage source is used to provide the first preset value. The first switch and the second switch are controlled by the first control signal.

6. The control circuit according to claim 1, wherein, The reset signal generation module is configured to: generate a ramp voltage with a first slope according to a second clock signal when the first control signal is in an invalid state; and generate a ramp voltage with a second slope according to the second clock signal when the first control signal is in an valid state, wherein the first slope is less than the second slope.

7. The control circuit according to claim 1 or 6, wherein, The reset signal generation module includes: The third switch has a first terminal that receives the first feedback voltage of the input voltage, a second terminal that is connected to the first node, and a control terminal that receives the first control signal. The fourth switch has a first terminal that receives the second feedback voltage of the input voltage, and a second terminal that is connected to the first node. The second feedback voltage of the input voltage is greater than the first feedback voltage of the input voltage. An inverter is connected between the first control signal and the control terminal of the fourth switch; The third transconductance amplifier has its positive input terminal connected to the first node and its negative input terminal grounded. It is used to amplify the voltage of the first node and the ground voltage differentially to obtain a differential signal. The first capacitor has its first end connected to the output terminal of the third transconductance amplifier and its second end grounded. The fifth switch has its first terminal connected to the first terminal of the first capacitor, its second terminal grounded, and its control terminal connected to the second clock signal. The second buffer has a positive input terminal connected to the first terminal of the fifth switch, a negative input terminal grounded, a first output terminal grounded through a second reference voltage source, and a second output terminal used to superimpose the voltage of the first terminal of the fifth switch with the voltage provided by the second reference voltage source and then output it. The third buffer has a positive input terminal connected to the output voltage, a negative input terminal grounded, a first output terminal receiving the error signal, and a second output terminal used to superimpose the output voltage and the error signal before outputting. The fifth comparator has its positive input terminal connected to the second output terminal of the second buffer, its negative input terminal connected to the second output terminal of the third buffer, and its output terminal used to provide the first reset signal.

8. The control circuit according to claim 1, wherein, The logic and driver modules include: The second flip-flop has a set terminal that receives the first set signal, a reset terminal that receives the first reset signal, and an output terminal that provides a pulse width modulation signal. A driving circuit is used to provide a driving signal according to the pulse width modulation signal to control the on and off of the high-side switching transistor.

9. A switching converter, comprising: The control circuit as described in any one of claims 1-8; as well as Power stage circuitry, including: High-side switching transistors and inductors, The power stage circuit controls the power transfer from the input voltage to the output voltage by turning the high-side switch on and off.

10. A control method for a switching converter, the switching converter including a high-side switch and an inductor, the control method controlling the power transfer from input voltage to output voltage by controlling the on and off states of the high-side switch, the control method comprising: When the first control signal is in an invalid state, an error signal whose voltage magnitude is negatively correlated with the first reference voltage is generated based on the difference between the first feedback voltage and the first reference voltage of the output voltage of the switching converter. When the first control signal is active, the voltage magnitude of the error signal is set to a first preset value; The first control signal is generated based on the magnitude relationship between the first feedback voltage and the first reference voltage, the magnitude relationship between the first feedback voltage and the third reference voltage, and the error signal. The second control signal is generated based on the magnitude relationship between the first feedback voltage and the second reference voltage and the first control signal. The first set signal is generated based on the second control signal and the first clock signal. The second reference voltage is greater than the first reference voltage and less than the third reference voltage. A ramp voltage is generated, and a first reset signal is generated using the ramp voltage and the error signal; The high-side switch is turned on and off according to the first set signal and the first reset signal. The second control signal is related to the load level of the switching converter. When the second control signal is high, the switching converter is in a light load state, and when the second control signal is low, the switching converter is in a relatively heavy load state.

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