Boost converter

Abstract

A boost converter includes a bridge rectifier, a first capacitor, a supply circuit, a first inductor, a current compensation circuit, a power switch, an output stage circuit, a feedback compensation circuit, and a microcontroller. The bridge rectifier generates a rectified voltage based on a first input voltage and a second input voltage. The first inductor receives the rectified voltage. The output stage circuit is coupled to the first inductor and the current compensation circuit, and generates an output voltage. The feedback compensation circuit generates a feedback voltage based on the output voltage. The microcontroller monitors and limits a duty cycle of a clock voltage. If the duty cycle reaches a maximum threshold, the microcontroller enables the current compensation circuit to provide an additional current, thereby increasing the output power of the boost converter.

Description

Technical Field

[0001] This invention relates to a boost converter, and more particularly to a boost converter that can increase circuit stability. Background Technology

[0002] Because gaming laptops require significant power, traditional designs typically increase the overall output power by extending the duty cycle of the power switch. However, excessively long duty cycles can easily lead to circuit oscillations and decreased stability. Therefore, a novel solution is needed to overcome the limitations of previous technologies. Summary of the Invention

[0003] In a preferred embodiment, the present invention provides a boost converter comprising: a bridge rectifier for generating a rectified potential based on a first input potential and a second input potential; a first capacitor for storing the rectified potential; a supply circuit for generating a supply potential based on the rectified potential; a first inductor for receiving the rectified potential; a current compensation circuit; a power switch for selectively coupling the first inductor to a ground potential based on a clock potential; an output stage circuit coupled to the first inductor and the current compensation circuit and generating an output potential; a feedback compensation circuit for generating a feedback potential based on the output potential, wherein the feedback compensation circuit includes a linear optocoupler; and a microcontroller powered by the supply potential and generating the clock potential based on the feedback potential; wherein the microcontroller further monitors and limits a duty cycle of the clock potential, and if the duty cycle reaches a maximum threshold value, the microcontroller enables the current compensation circuit to provide an additional current, thereby increasing the output power of the boost converter.

[0004] In some embodiments, the bridge rectifier includes: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node; and a third diode having an anode and a cathode. The first input node comprises a third diode having an anode and a cathode, wherein the anode of the third diode is coupled to the ground potential and the cathode of the third diode is coupled to the first input node; and a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential and the cathode of the fourth diode is coupled to the second input node; wherein the first capacitor has a first terminal and a second terminal, the first terminal of the first capacitor being coupled to the first node to receive and store the rectified potential, and the second terminal of the first capacitor being coupled to the ground potential.

[0005] In some embodiments, the supply circuit includes: a first resistor having a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the first node to receive the rectified potential, and the second terminal of the first resistor is coupled to a supply node to output the supply potential to the microcontroller; a second resistor having a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the supply node, and the second terminal of the second resistor is coupled to the ground potential; and a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the supply node, and the second terminal of the second capacitor is coupled to the ground potential; wherein a first inductor has a first terminal and a second terminal, the first terminal of the first inductor is coupled to the first node to receive the rectified potential, and the second terminal of the first inductor is coupled to a second node.

[0006] In some embodiments, the current compensation circuit includes: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is coupled to a control node to receive a control potential, the first terminal of the first transistor is coupled to a third node, and the second terminal of the first transistor is coupled to the supply node; a second inductor having a first terminal and a second terminal, wherein the first terminal of the second inductor is coupled to the third node, and the second terminal of the second inductor is coupled to the second node to selectively output the additional current; and a third capacitor having a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the control node, and the second terminal of the third capacitor is coupled to a switching node.

[0007] In some embodiments, the power switch includes: a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is coupled to the switching node to receive the clock potential, the first terminal of the second transistor is coupled to the ground potential, and the second terminal of the second transistor is coupled to the second node.

[0008] In some embodiments, the output stage circuit includes: a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the second node and the cathode of the fifth diode is coupled to an output node to output the output potential; and a fourth capacitor having a first terminal and a second terminal, wherein the first terminal of the fourth capacitor is coupled to the output node and the second terminal of the fourth capacitor is coupled to the ground potential.

[0009] In some embodiments, the linear optocoupler includes a light-emitting diode (LED) and a bipolar junction transistor (BJT). The LED has an anode and a cathode. The anode of the LED is coupled to a voltage divider node to receive a voltage divider potential. The cathode of the LED is coupled to a fourth node. The BJT has a collector and an emitter. The collector of the BJT is used to output the feedback potential to the microcontroller, and the emitter of the BJT is coupled to a fifth node.

[0010] In some embodiments, the feedback compensation circuit further includes: a third resistor having a first terminal and a second terminal, wherein the first terminal of the third resistor is coupled to the output node to receive the output potential, and the second terminal of the third resistor is coupled to the voltage divider node to output the voltage divider potential; a fourth resistor having a first terminal and a second terminal, wherein the first terminal of the fourth resistor is coupled to the voltage divider node, and the second terminal of the fourth resistor is coupled to the ground potential; a fifth resistor having a first terminal and a second terminal, wherein the first terminal of the fifth resistor is coupled to the output node, and the second terminal of the fifth resistor is coupled to a sixth node; and a sixth resistor having a first terminal and a second terminal, wherein the first terminal of the fifth resistor is coupled to the output node, and the second terminal of the fifth resistor is coupled to a sixth node; The first terminal of the six resistor is coupled to the sixth node, and the second terminal of the sixth resistor is coupled to the ground potential; a fifth capacitor having a first terminal and a second terminal, wherein the first terminal of the fifth capacitor is coupled to the fourth node, and the second terminal of the fifth capacitor is coupled to the sixth node; a sixth capacitor having a first terminal and a second terminal, wherein the first terminal of the sixth capacitor is coupled to the fifth node, and the second terminal of the sixth capacitor is coupled to the ground potential; and a voltage regulator having an anode, a cathode, and a reference terminal, wherein the anode of the voltage regulator is coupled to the ground potential, the cathode of the voltage regulator is coupled to the fourth node, and the reference terminal of the voltage regulator is coupled to the sixth node.

[0011] In some embodiments, the microcontroller includes: a comparator having a positive input, a negative input, and an output, wherein the positive input of the comparator is used to receive the feedback potential, the negative input of the comparator is used to receive a triangular wave potential, and the output of the comparator is coupled to the switching node to output the clock potential; and a detection and control circuit that monitors the duty cycle of the clock potential and generates the control potential accordingly.

[0012] In some embodiments, if the duty cycle has reached the maximum threshold, the detection and control circuit will output the control potential with a high logic level to enable the first transistor; if the duty cycle has not reached the maximum threshold, the detection and control circuit will output the control potential with a low logic level to disable the first transistor. Attached Figure Description

[0013] Figure 1 This is a schematic diagram showing a boost converter according to an embodiment of the present invention.

[0014] Figure 2 This is a schematic diagram showing a boost converter according to an embodiment of the present invention.

[0015] Figure 3This is a waveform diagram showing the clock potential according to an embodiment of the present invention.

[0016] Figure 4 This is a waveform diagram showing the total current according to an embodiment of the present invention.

[0017] The reference numerals in the attached figures are explained as follows:

[0018] 100, 200: Boost converter

[0019] 110, 210: Bridge rectifier

[0020] 120, 220: Supply circuit

[0021] 130, 230: Current compensation circuit

[0022] 140, 240: Power Switch

[0023] 150, 250: Output stage circuit

[0024] 160, 260: Feedback compensation circuit

[0025] 162, 262: Linear optical couplers

[0026] 170, 270: Microcontrollers

[0027] 264: Voltage Regulator

[0028] 272: Comparator

[0029] 274: Detection and Control Circuit

[0030] C1: First capacitor

[0031] C2: Second capacitor

[0032] C3: Third capacitor

[0033] C4: Fourth capacitor

[0034] C5: Fifth capacitor

[0035] C6: Sixth capacitor

[0036] D: Responsibility Period

[0037] D1: First diode

[0038] D2: Second diode

[0039] D3: Third diode

[0040] D4: Fourth diode

[0041] D5: Fifth diode

[0042] DL: Light Emitting Diode

[0043] DMAX: Maximum Critical Value

[0044] IA: Additional Current

[0045] IL: Inductor current

[0046] IM: Total Current

[0047] L1: First Inductor

[0048] L2: Second inductor

[0049] M1: First transistor

[0050] M2: Second transistor

[0051] N1: First node

[0052] N2: Second node

[0053] N3: Third Node

[0054] N4: Fourth Node

[0055] N5: Fifth Node

[0056] N6: Sixth Node

[0057] NC: Control Node

[0058] ND: Voltage divider node

[0059] NIN1: First input node

[0060] NIN2: Second input node

[0061] NOUT: Output node

[0062] NS: Supply Node

[0063] NW: Switch Node

[0064] Q3: Bipolar junction transistor

[0065] R1: First resistor

[0066] R2: Second resistor

[0067] R3: Third resistor

[0068] R4: Fourth resistor

[0069] R5: Fifth resistor

[0070] R6: Sixth resistor

[0071] T: The complete cycle of the clock potential

[0072] TS: Specific time point

[0073] TON: Duration of high logic level

[0074] VA: Clock potential

[0075] VC: Control potential

[0076] VCC: Supply Potential

[0077] VD: Voltage divider potential

[0078] VF: Feedback potential

[0079] VIN1: First input potential

[0080] VIN2: First input potential

[0081] VOUT: Output potential

[0082] VR: Rectifying potential

[0083] VSS: Grounding Potential

[0084] VT: Triangular wave potential Detailed Implementation

[0085] To make the objectives, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below in conjunction with the accompanying drawings for detailed explanation.

[0086] Certain terms are used in the specification and claims to refer to specific elements. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same element. This specification and claims do not distinguish elements by differences in name, but rather by differences in function. The terms "comprising" and "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising but not limited to." The term "generally" means that within an acceptable margin of error, those skilled in the art can solve the technical problem and achieve the basic technical effect within a certain margin of error. Furthermore, the term "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device via other devices or connection means.

[0087] Figure 1This is a schematic diagram showing a boost converter 100 according to an embodiment of the present invention. For example, the boost converter 100 can be applied to a desktop computer, a laptop computer, or an all-in-one computer. Figure 1 As shown, the boost converter 100 includes: a bridge rectifier 110, a first capacitor C1, a supply circuit 120, a first inductor L1, a current compensation circuit 130, a power switch 140, an output stage circuit 150, a feedback compensation circuit 160, and a microcontroller 170. It should be noted that, although not shown in... Figure 1 However, the boost converter 100 may also include other components, such as a voltage regulator or (and) a negative feedback circuit.

[0088] Bridge rectifier 110 generates a rectified potential VR based on a first input potential VIN1 and a second input potential VIN2, wherein an AC voltage with arbitrary frequency and amplitude can be formed between the first input potential VIN1 and the second input potential VIN2. For example, the frequency of the AC voltage can be approximately 50Hz or 60Hz, and the root mean square value of the AC voltage can be approximately from 90V to 264V, but is not limited thereto. First capacitor C1 stores the rectified potential VR. Supply circuit 120 generates a supply potential VCC based on the rectified potential VR. First inductor L1 receives the rectified potential VR. Power switch 140 selectively couples the first inductor L1 to a ground potential VSS (e.g., 0V) based on a clock potential VA. For example, if the clock potential VA is a high logic level (i.e., logic "1"), the power switch 140 can couple the first inductor L1 to the ground potential VSS (i.e., the power switch 140 can approximate a short-circuit path); conversely, if the clock potential VA is a low logic level (i.e., logic "0"), the power switch 140 will not couple the first inductor L1 to the ground potential VSS (i.e., the power switch 140 can approximate an open-circuit path). The output stage circuit 150 is coupled to the first inductor L1 and the current compensation circuit 130 and can generate an output potential VOUT. For example, the output potential VOUT can be a DC potential with a level of approximately 400V, but is not limited to this. The feedback compensation circuit 160 can generate a feedback potential VF based on the output potential VOUT, wherein the feedback compensation circuit 160 includes a linear optocoupler 162. The microcontroller 170 can be powered by the supply potential VCC and can generate a clock potential VA based on the feedback potential VF. Specifically, the microcontroller 170 can monitor and limit a duty cycle D of the clock potential VA. If the duty cycle D has reached a maximum threshold DMAX, the microcontroller 170 can enable the current compensation circuit 130 to provide an additional current IA, thereby increasing the output power of the boost converter 100. Conversely, if the duty cycle D has not reached the maximum threshold DMAX, the microcontroller 170 can disable the current compensation circuit 130 and stop outputting the aforementioned additional current IA. With this design, the boost converter 100 will not use a clock potential VA with an excessively large duty cycle D, thus significantly improving its overall circuit stability.

[0089] The following embodiments will describe the detailed structure and operation of the boost converter 100. It must be understood that these figures and descriptions are merely examples and are not intended to limit the scope of the invention.

[0090] Figure 2 This is a schematic diagram showing a boost converter 200 according to an embodiment of the present invention. Figure 2In this embodiment, the boost converter 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes a bridge rectifier 210, a first capacitor C1, a supply circuit 220, a first inductor L1, a current compensation circuit 230, a power switch 240, an output stage circuit 250, a feedback compensation circuit 260, and a microcontroller 270. The first input node NIN1 and the second input node NIN2 of the boost converter 200 can be used to receive a first input potential VIN1 and a second input potential VIN2. The output node NOUT of the boost converter 200 can be used to output an output potential VOUT.

[0091] The bridge rectifier 210 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The first diode D1 has an anode and a cathode, wherein the anode of the first diode D1 is coupled to a first input node NIN1, and the cathode of the first diode D1 is coupled to a first node N1 to output a rectified potential VR. The second diode D2 has an anode and a cathode, wherein the anode of the second diode D2 is coupled to a second input node NIN2, and the cathode of the second diode D2 is coupled to the first node N1. The third diode D3 has an anode and a cathode, wherein the anode of the third diode D3 is coupled to a ground potential VSS, and the cathode of the third diode D3 is coupled to the first input node NIN1. The fourth diode D4 has an anode and a cathode, wherein the anode of the fourth diode D4 is coupled to a ground potential VSS, and the cathode of the fourth diode D4 is coupled to the second input node NIN2.

[0092] The first capacitor C1 has a first terminal and a second terminal, wherein the first terminal of the first capacitor C1 is coupled to the first node N1 to receive and store the rectified potential VR, and the second terminal of the first capacitor C1 is coupled to the ground potential VSS.

[0093] The supply circuit 220 includes a first resistor R1, a second resistor R2, and a second capacitor C2. The first resistor R1 has a first terminal and a second terminal, wherein the first terminal of the first resistor R1 is coupled to a first node N1 to receive a rectified potential VR, and the second terminal of the first resistor R1 is coupled to a supply node NS to output a supply potential VCC to the microcontroller 270. The second resistor R2 has a first terminal and a second terminal, wherein the first terminal of the second resistor R2 is coupled to the supply node NS, and the second terminal of the second resistor R2 is coupled to a ground potential VSS. The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal of the second capacitor C2 is coupled to the supply node NS, and the second terminal of the second capacitor C2 is coupled to a ground potential VSS.

[0094] A first inductor L1 has a first terminal and a second terminal, wherein the first terminal of the first inductor L1 is coupled to a first node N1 to receive a rectified potential VR, and the second terminal of the first inductor L1 is coupled to a second node N2. An inductor current IL can flow through the first inductor L1.

[0095] The current compensation circuit 230 includes a first transistor M1, a second inductor L2, and a third capacitor C3. For example, the first transistor M1 may be an N-type metal-oxide-semiconductor field-effect transistor. The first transistor M1 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the first transistor M1 is coupled to a control node NC to receive a control potential VC. The first terminal of the first transistor M1 is coupled to a third node N3, and the second terminal of the first transistor M1 is coupled to a supply node NS. The second inductor L2 has a first terminal and a second terminal. The first terminal of the second inductor L2 is coupled to the third node N3, and the second terminal of the second inductor L2 is coupled to a second node N2 to selectively output an additional current IA. The third capacitor C3 has a first terminal and a second terminal. The first terminal of the third capacitor C3 is coupled to the control node NC, and the second terminal of the third capacitor C3 is coupled to a switching node NW. In some embodiments, the total current IM flowing into the second node N2 is defined according to the following equation (1):

[0096] IM = IL + IA (1)

[0097] The power switch 240 includes a second transistor M2. For example, the second transistor M2 may be an N-type metal-oxide-semiconductor field-effect transistor. The second transistor M2 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the second transistor M2 is coupled to a switching node NW to receive a clock potential VA, the first terminal of the second transistor M2 is coupled to a ground potential VSS, and the second terminal of the second transistor M2 is coupled to a second node N2. For example, if the clock potential VA is a high logic level, the second transistor M2 will be enabled; conversely, if the clock potential VA is a low logic level, the second transistor M2 will be disabled.

[0098] The output stage circuit 250 includes a fifth diode D5 and a fourth capacitor C4. The fifth diode D5 has an anode and a cathode, wherein the anode of the fifth diode D5 is coupled to the second node N2, and the cathode of the fifth diode D5 is coupled to the output node NOUT. The fourth capacitor C4 has a first terminal and a second terminal, wherein the first terminal of the fourth capacitor C4 is coupled to the output node NOUT, and the second terminal of the fourth capacitor C4 is coupled to ground potential VSS.

[0099] The feedback compensation circuit 260 includes a linear optocoupler 262, a voltage regulator 264, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a fifth capacitor C5, and a sixth capacitor C6.

[0100] In some embodiments, the linear optocoupler 262 is implemented using a PC817 electronic component. The linear optocoupler 262 includes a light-emitting diode (LED) DL and a bipolar junction transistor (BJT) Q3 (e.g., NPN type). The LED DL has an anode and a cathode, wherein the anode of the LED DL is coupled to a voltage divider node ND to receive a voltage divider potential VD, and the cathode of the LED DL is coupled to a fourth node N4. The BJT Q3 has a collector and an emitter, wherein the collector of the BJT Q3 is used to output a feedback potential VF to the microcontroller 270, and the emitter of the BJT Q3 is coupled to a fifth node N5.

[0101] The third resistor R3 has a first terminal and a second terminal, wherein the first terminal of the third resistor R3 is coupled to the output node NOUT, and the second terminal of the third resistor R3 is coupled to the voltage divider node ND to output a voltage divider potential VD. The fourth resistor R4 has a first terminal and a second terminal, wherein the first terminal of the fourth resistor R4 is coupled to the voltage divider node ND, and the second terminal of the fourth resistor R4 is coupled to the ground potential VSS. The fifth resistor R5 has a first terminal and a second terminal, wherein the first terminal of the fifth resistor R5 is coupled to the output node NOUT, and the second terminal of the fifth resistor R5 is coupled to a sixth node N6. The sixth resistor R6 has a first terminal and a second terminal, wherein the first terminal of the sixth resistor R6 is coupled to the sixth node N6, and the second terminal of the sixth resistor R6 is coupled to the ground potential VSS. The fifth capacitor C5 has a first terminal and a second terminal, wherein the first terminal of the fifth capacitor C5 is coupled to the fourth node N4, and the second terminal of the fifth capacitor C5 is coupled to the sixth node N6. The sixth capacitor C6 has a first terminal and a second terminal, wherein the first terminal of the sixth capacitor C6 is coupled to the fifth node N5, and the second terminal of the sixth capacitor C6 is coupled to ground potential VSS.

[0102] In some embodiments, regulator 264 is implemented by a TL431 electronic component. Regulator 264 has an anode, a cathode, and a reference terminal, wherein the anode of regulator 264 is coupled to ground potential VSS, the cathode of regulator 264 is coupled to a fourth node N4, and the reference terminal of regulator 264 is coupled to a sixth node N6.

[0103] The microcontroller 270 includes a comparator 272 and a detection and control circuit 274. Specifically, the comparator 272 has a positive input, a negative input, and an output. The positive input of the comparator 272 receives a feedback potential VF, the negative input receives a triangular wave potential VT, and the output of the comparator 272 is coupled to a switching node NW to output a clock potential VA. For example, if the feedback potential VF is higher than or equal to the triangular wave potential VT, the comparator 272 can output a clock potential VA with a high logic level; conversely, if the feedback potential VF is lower than the triangular wave potential VT, the comparator 272 can output a clock potential VA with a low logic level.

[0104] The clock potential VA has a duty period D. The detection and control circuit 274 monitors the duty period D of the clock potential VA and generates a control potential VC accordingly. Specifically, the detection and control circuit 274 compares the duty period D with a maximum threshold value DMAX. For example, if the duty period D has reached the maximum threshold value DMAX (i.e., D = DMAX), the detection and control circuit 274 outputs a control potential VC with a high logic level to enable the first transistor M1; conversely, if the duty period D has not reached the maximum threshold value DMAX (i.e., D < DMAX), the detection and control circuit 274 outputs a control potential VC with a low logic level to disable the first transistor M1. In other words, the detection and control circuit 274 has a limiting function that prevents the duty period D of the clock potential VA from exceeding the maximum threshold value DMAX (i.e., D > DMAX).

[0105] Figure 3 This is a waveform diagram showing the clock potential VA according to an embodiment of the present invention, where the horizontal axis represents time and the vertical axis represents the potential level of the clock potential VA. Figure 3 As shown, the duration of the high logic level in each complete cycle T of the clock potential VA is TON. In some embodiments, the duty period D of the clock potential VA is defined according to the following equation (2):

[0106]

[0107] Figure 4This is a waveform diagram showing the total current IM according to an embodiment of the present invention, where the horizontal axis represents time and the vertical axis represents the current value of the total current IM. Initially, the duty period D of the clock potential VA is very small, and the first transistor M1 is disabled, so the current compensation circuit 230 does not output any additional current IA. When a larger output power is required, the duty period D of the clock potential VA of the boost converter 200 gradually increases, so both the inductor current IL and the total current IM gradually increase. It should be noted that if the duty period D of the clock potential VA has reached the maximum critical value DMAX (for example, at a specific time point TS), the detection and control circuit 274 will enable the first transistor M1, so that the current compensation circuit 230 can provide an additional current IA. At this time, the duty period D of the clock potential VA will remain at the maximum critical value DMAX, and the current value of the total current IM will increase rapidly due to the addition of the additional current IA, thereby effectively improving the output power of the boost converter 200. With this design, the circuit stability of the boost converter 200 can be significantly improved because the duty cycle D of the clock potential VA will not exceed the maximum critical value DMAX. On the other hand, according to actual measurement results, the addition of the third capacitor C3 can prevent high-frequency noise between the first transistor M1 and the second transistor M2 from interfering with each other when both are enabled.

[0108] In some embodiments, the component parameters of the boost converter 200 may be as follows: The inductance value of the first inductor L1 may be between 255μH and 345μH, preferably 300μH. The inductance value of the second inductor L2 may be between 43.2μH and 52.8μH, preferably 48μH. The capacitance value of the first capacitor C1 may be between 108μF and 132μF, preferably 120μF. The capacitance value of the second capacitor C2 may be between 42.3μF and 51.7μF, preferably 47μF. The capacitance value of the third capacitor C3 may be between 90nF and 110nF, preferably 100nF. The capacitance value of the fourth capacitor C4 may be between 544μF and 816μF, preferably 680μF. The capacitance of the fifth capacitor C5 can be between 1.43nF and 1.58nF, preferably 1.5nF. The capacitance of the sixth capacitor C6 can be between 90pF and 110pF, preferably 100pF. The resistance of the first resistor R1 can be between 2.13MΩ and 3.19MΩ, preferably 2.66MΩ. The resistance of the second resistor R2 can be between 1.06MΩ and 1.59MΩ, preferably 1.33MΩ. The resistance of the third resistor R3 can be between 69.3KΩ and 84.7KΩ, preferably 77KΩ. The resistance of the fourth resistor R4 can be between 2.7KΩ and 3.3KΩ, preferably 3KΩ. The resistance of the fifth resistor R5 can be between 134.1KΩ and 163.9KΩ, preferably 149KΩ. The resistance value of the sixth resistor R6 can be between 0.9KΩ and 1.1KΩ, preferably 1KΩ. The maximum critical value DMAX can be 72%, 75%, or any value in between. The above parameter ranges are derived from the results of multiple experiments and help to optimize the circuit stability of the boost converter 200.

[0109] This invention proposes a novel boost converter that limits the maximum duty cycle of the clock potential of a power switch. Based on actual measurement results, the boost converter designed above effectively improves overall circuit stability, making it well-suited for various applications.

[0110] It is worth noting that the potential, current, resistance, inductance, capacitance, and other component parameters mentioned above are not limiting conditions of this invention. Designers can adjust these settings according to different needs. The boost converter of this invention is not limited to... Figures 1-4 The state illustrated. This invention may include only... Figures 1-4Any one or more features of any one or more embodiments. In other words, not all illustrated features need to be implemented simultaneously in the boost converter of the present invention. Although the embodiments of the present invention use metal-oxide-semiconductor field-effect transistors as examples, the present invention is not limited thereto. Those skilled in the art can use other types of transistors, such as junction field-effect transistors or fin field-effect transistors, without affecting the effects of the present invention.

[0111] The ordinal numbers in this specification and claims, such as "first," "second," "third," etc., are not sequential in any particular order; they are only used to distinguish between two different elements with the same name.

[0112] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the scope of the invention. Any person skilled in the art may make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A boost converter, comprising: A bridge rectifier generates a rectified potential based on a first input potential and a second input potential; A first capacitor stores the rectified potential; A supply circuit generates a supply potential based on the rectified potential; A first inductor receives the rectified potential; A current compensation circuit; A power switch selectively couples the first inductor to a ground potential based on a clock potential; An output stage circuit is coupled to the first inductor and the current compensation circuit, and generates an output potential; A feedback compensation circuit generates a feedback potential based on the output potential, wherein the feedback compensation circuit includes a linear optocoupler. as well as A microcontroller is powered by the supply potential and generates the clock potential based on the feedback potential; The microcontroller limits the clock potential to a duty cycle, and if the duty cycle reaches a maximum threshold, the microcontroller will enable the current compensation circuit to provide an additional current, thereby increasing the output power of the boost converter.

2. The boost converter of claim 1, wherein the bridge rectifier comprises: A first diode has an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the rectified potential; A second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node; A third diode has an anode and a cathode, wherein the anode of the third diode is coupled to the ground potential, and the cathode of the third diode is coupled to the first input node; as well as A fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node; The first capacitor has a first terminal and a second terminal. The first terminal of the first capacitor is coupled to the first node to receive and store the rectified potential, while the second terminal of the first capacitor is coupled to the ground potential.

3. The boost converter of claim 2, wherein the supply circuit comprises: A first resistor has a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the first node to receive the rectified potential, and the second terminal of the first resistor is coupled to a supply node to output the supply potential to the microcontroller. A second resistor having a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the supply node, and the second terminal of the second resistor is coupled to the ground potential; as well as A second capacitor has a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the supply node, and the second terminal of the second capacitor is coupled to the ground potential; The first inductor has a first terminal and a second terminal. The first terminal of the first inductor is coupled to the first node to receive the rectified potential, and the second terminal of the first inductor is coupled to a second node.

4. The boost converter of claim 3, wherein the current compensation circuit comprises: A first transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is coupled to a control node to receive a control potential, the first terminal of the first transistor is coupled to a third node, and the second terminal of the first transistor is coupled to a supply node. A second inductor having a first terminal and a second terminal, wherein the first terminal of the second inductor is coupled to the third node, and the second terminal of the second inductor is coupled to the second node to selectively output the additional current; as well as A third capacitor has a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the control node, and the second terminal of the third capacitor is coupled to a switching node.

5. The boost converter of claim 4, wherein the power switch comprises: A second transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is coupled to the switching node to receive the clock potential, the first terminal of the second transistor is coupled to the ground potential, and the second terminal of the second transistor is coupled to the second node.

6. The boost converter of claim 4, wherein the output stage circuit comprises: A fifth diode has an anode and a cathode, wherein the anode of the fifth diode is coupled to the second node, and the cathode of the fifth diode is coupled to an output node to output the output potential; as well as A fourth capacitor has a first terminal and a second terminal, wherein the first terminal of the fourth capacitor is coupled to the output node, and the second terminal of the fourth capacitor is coupled to the ground potential.

7. The boost converter of claim 6, wherein the linear optocoupler includes a light-emitting diode (LED) and a bipolar junction transistor (BJT), the LED having an anode and a cathode, the anode of the LED being coupled to a voltage divider node to receive a voltage divider potential, the cathode of the LED being coupled to a fourth node, the BJT having a collector and an emitter, the collector of the BJT being used to output the feedback potential to the microcontroller, and the emitter of the BJT being coupled to a fifth node.

8. The boost converter of claim 7, wherein the feedback compensation circuit further comprises: A third resistor has a first terminal and a second terminal, wherein the first terminal of the third resistor is coupled to the output node to receive the output potential, and the second terminal of the third resistor is coupled to the voltage divider node to output the voltage divider potential. A fourth resistor has a first terminal and a second terminal, wherein the first terminal of the fourth resistor is coupled to the voltage divider node, and the second terminal of the fourth resistor is coupled to the ground potential; A fifth resistor has a first terminal and a second terminal, wherein the first terminal of the fifth resistor is coupled to the output node, and the second terminal of the fifth resistor is coupled to a sixth node; A sixth resistor has a first terminal and a second terminal, wherein the first terminal of the sixth resistor is coupled to the sixth node, and the second terminal of the sixth resistor is coupled to the ground potential; A fifth capacitor has a first terminal and a second terminal, wherein the first terminal of the fifth capacitor is coupled to the fourth node, and the second terminal of the fifth capacitor is coupled to the sixth node. A sixth capacitor has a first terminal and a second terminal, wherein the first terminal of the sixth capacitor is coupled to the fifth node, and the second terminal of the sixth capacitor is coupled to the ground potential. as well as A voltage regulator has an anode, a cathode, and a reference terminal, wherein the anode of the voltage regulator is coupled to the ground potential, the cathode of the voltage regulator is coupled to the fourth node, and the reference terminal of the voltage regulator is coupled to the sixth node.

9. The boost converter of claim 8, wherein the microcontroller comprises: A comparator has a positive input, a negative input, and an output, wherein the positive input of the comparator is used to receive the feedback potential, the negative input of the comparator is used to receive a triangular wave potential, and the output of the comparator is coupled to the switching node to output the clock potential. as well as A detection and control circuit monitors the clock potential during its duty cycle and generates the control potential accordingly.

10. The boost converter of claim 9, wherein if the duty cycle has reached the maximum threshold, the detection and control circuit outputs the control potential with a high logic level to enable the first transistor, and if the duty cycle has not reached the maximum threshold, the detection and control circuit outputs the control potential with a low logic level to disable the first transistor.

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