Pre-amplifier for dynamic comparators and related devices

Abstract

This invention relates to the field of chip technology, providing a preamplifier, dynamic comparator, analog-to-digital converter, chip, and electronic device for use in dynamic comparators. The device includes a transistor amplifier circuit and a tail current adjustment unit. The transistor amplifier circuit is connected to a first signal input terminal, a second signal input terminal, a first clock signal terminal, and a target node. During the comparison phase, under the control of the first clock signal, the transistor amplifier circuit amplifies the first input signal input at the first signal input terminal and the second input signal input at the second signal input terminal, generating a first amplified signal and a second amplified signal. During the amplification process, a tail current is output through the target node. The tail current adjustment unit adjusts the tail current through a discharge process. This solves the problem of poor reliability of the dynamic comparator when the PVT or the input common-mode voltage changes, thus improving the reliability of the dynamic comparator.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a preamplifier and related devices used in dynamic comparators. Background Technology

[0002] The comparator is the core of a successive approximation register-type analog-to-digital converter. Parameters such as process technology, power supply voltage, temperature (PVT), and input common-mode voltage have a significant impact on the comparator's performance, such as comparison speed.

[0003] During PVT environmental changes, the biggest factor affecting comparator performance is the change in the MOSFET threshold voltage. With decreasing power supply voltage and advancements in manufacturing processes, the decrease in the MOSFET threshold voltage is no longer proportional to the decrease in power supply voltage.

[0004] Thus, the comparator's reliability will decrease when the PVT or the input common-mode voltage changes. Summary of the Invention

[0005] This invention provides a preamplifier and related devices for use in dynamic comparators, which solves the problem of low reliability of dynamic comparators in the prior art when PVT changes or the input common-mode voltage changes. It realizes the insensitivity of dynamic comparators to PVT changes or the input common-mode voltage and improves the circuit operation reliability of dynamic comparators.

[0006] This invention provides a preamplifier for use in a dynamic comparator, comprising: a transistor amplifier circuit and a tail current adjustment unit;

[0007] The transistor amplifier circuit is connected to the first signal input terminal, the second signal input terminal, the first clock signal terminal, and the target node, respectively; when the first clock signal provided by the first clock signal terminal is at a high level, the dynamic comparator is in the comparison phase.

[0008] The transistor amplifier circuit is used in the comparison stage to amplify the first input signal input to the first signal input terminal and the second input signal input to the second signal input terminal under the control of the first clock signal, to generate a first amplified signal and a second amplified signal, and to output a tail current through the target node during the amplification process;

[0009] The tail current adjustment unit is connected to the first clock signal terminal and the target node respectively, and is used to adjust the tail current through the discharge process under the control of the first clock signal during the comparison phase.

[0010] According to the present invention, a preamplifier for a dynamic comparator is provided, wherein the tail current adjustment unit includes: a first capacitor unit and a control unit;

[0011] The first capacitor unit is connected to the target node through the control unit;

[0012] The control unit is connected to the first clock signal terminal and is used to control the first capacitor unit to adjust the tail current through the discharge process under the control of the first clock signal during the comparison phase.

[0013] According to the present invention, a preamplifier for a dynamic comparator is provided, wherein the control unit includes a first transistor and a second transistor;

[0014] The first terminal of the first capacitor unit is connected to the source of the first transistor; the second terminal of the first capacitor unit is connected to the drain of the second transistor.

[0015] The drain of the first transistor is connected to the target node;

[0016] The gate of the second transistor is connected to the first clock signal terminal, and the source of the second transistor is connected to the ground terminal;

[0017] The first transistor and the second transistor are turned on when the first clock signal is high, causing the first capacitor unit to discharge in order to regulate the tail current.

[0018] According to the present invention, a preamplifier applied to a dynamic comparator is provided, wherein the dynamic comparator is in a reset phase when the first clock signal is low.

[0019] The control unit is also connected to a power input terminal, a second clock signal terminal, and a ground terminal, respectively, and is used to provide the power signal input from the power input terminal to the second terminal of the first capacitor unit under the control of the first clock signal during the reset phase, and to connect the first terminal of the first capacitor unit to the ground terminal under the control of the second clock signal input from the second clock signal terminal, so as to charge the first capacitor unit.

[0020] According to the present invention, a preamplifier for a dynamic comparator is provided, wherein the control unit further includes a third transistor and a fourth transistor;

[0021] The gate of the third transistor is connected to the first clock signal terminal, the source of the third transistor is connected to the second terminal of the first capacitor unit, and the drain of the third transistor is connected to the power input terminal. The third transistor is turned on when the first clock signal is low, so as to provide the power signal input from the power input terminal to the second terminal of the first capacitor unit.

[0022] The gate of the fourth transistor is connected to the second clock signal terminal, the source of the fourth transistor is connected to the first terminal of the first capacitor unit, and the drain of the fourth transistor is connected to the ground terminal. The fourth transistor is turned on when the second clock signal provided by the second clock signal terminal is at a high level, so as to connect the first terminal of the first capacitor unit to the ground terminal.

[0023] According to the present invention, a preamplifier for a dynamic comparator further includes a gain boosting unit;

[0024] The gain boosting unit is connected to the output terminal of the first amplified signal, the output terminal of the second amplified signal, and the third clock signal terminal, respectively, and is used to boost the gain of the preamplifier under the control of the third clock signal provided by the third clock signal terminal.

[0025] According to the present invention, a preamplifier for a dynamic comparator is provided, wherein the gain boosting unit includes: a gain boosting circuit and a noise suppression circuit;

[0026] The first input terminal of the gain boosting circuit is connected to the output terminal of the first amplified signal, the second input terminal of the gain boosting circuit is connected to the output terminal of the second amplified signal, and the third input terminal of the gain boosting circuit is connected to the third clock signal terminal; the gain boosting circuit is used to boost the gain of the preamplifier under the control of the third clock signal.

[0027] The noise suppression circuit is connected to the ground terminal and the output terminal of the gain boosting circuit, respectively, and is used to reduce the noise of the gain boosting circuit.

[0028] According to the present invention, a preamplifier applied to a dynamic comparator is provided, wherein the gain boosting circuit includes a fifth transistor, a sixth transistor, and a seventh transistor;

[0029] The drain of the fifth transistor and the gate of the sixth transistor are respectively connected to the first input terminal of the gain boosting circuit;

[0030] The gate of the fifth transistor and the drain of the sixth transistor are respectively connected to the second input terminal of the gain boosting circuit;

[0031] The source of the fifth transistor and the source of the sixth transistor are respectively connected to the drain of the seventh transistor; the gate of the seventh transistor is connected to the third clock signal terminal, and the source of the seventh transistor is connected to the output terminal of the gain boosting circuit.

[0032] The seventh transistor is used to turn on when the third clock signal is high, so that the gain boosting circuit can work.

[0033] The third clock signal transitions from low to high after the rising edge of the first clock signal, and then transitions from high to low after the falling edge of the first clock signal.

[0034] According to the present invention, a preamplifier for a dynamic comparator is provided, wherein the noise suppression circuit includes a second capacitor unit;

[0035] The first terminal of the second capacitor unit is connected to the source of the seventh transistor; the second terminal of the second capacitor unit is connected to the ground terminal.

[0036] According to the present invention, a preamplifier applied to a dynamic comparator is provided, wherein the dynamic comparator is in a reset phase when the first clock signal is low; the noise suppression circuit further includes an eighth transistor.

[0037] The gate of the eighth transistor is connected to the second clock signal terminal, the source of the eighth transistor is connected to the second terminal of the second capacitor unit, and the drain of the eighth transistor is connected to the first terminal of the second capacitor unit.

[0038] The eighth transistor is used to turn on under the control of the second clock signal provided at the second clock signal terminal during the reset phase, so as to discharge the second capacitor unit.

[0039] According to the present invention, a preamplifier for a dynamic comparator is provided, wherein the transistor amplification circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor;

[0040] The source of the ninth transistor and the source of the tenth transistor are respectively connected to the power input terminal;

[0041] The gates of the ninth transistor and the tenth transistor are respectively connected to the first clock signal terminal.

[0042] The drains of the ninth transistor and the eleventh transistor are respectively connected to the first amplified signal output terminal; the drains of the tenth transistor and the twelfth transistor are respectively connected to the second amplified signal output terminal.

[0043] The source of the eleventh transistor and the source of the twelfth transistor are respectively connected to the target node.

[0044] The present invention also provides a dynamic comparator, including a preamplifier as described in any of the preceding claims for use in a dynamic comparator.

[0045] The present invention also provides an analog-to-digital converter, including the dynamic comparator described in any of the preceding claims.

[0046] The present invention also provides a chip comprising the analog-to-digital converter described in any of the preceding claims.

[0047] The present invention also provides an electronic device comprising the chip described in any of the preceding claims.

[0048] The present invention provides a preamplifier and related devices for a dynamic comparator, including a transistor amplifier circuit and a tail current adjustment unit. In the comparison stage of the dynamic comparator, in related technologies, when the PVT changes or the input common-mode voltage changes, the tail current in the preamplifier will drop rapidly, thereby reducing the comparison speed in the dynamic comparator. In this case, the reliability of the dynamic comparator is poor. However, the tail current adjustment unit of the present invention can adjust the tail current through the discharge process, thereby improving the reliability of the dynamic comparator circuit when the PVT changes or the input common-mode voltage changes.

[0049] To more clearly illustrate the technical solutions in this invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0051] Figure 1 This is one of the structural schematic diagrams of a preamplifier applied to a dynamic comparator provided in an embodiment of the present invention;

[0052] Figure 2 This is a second schematic diagram of the structure of a preamplifier applied to a dynamic comparator according to an embodiment of the present invention;

[0053] Figure 3 One of the circuit structure diagrams of a preamplifier applied to a dynamic comparator provided in an embodiment of the present invention;

[0054] Figure 4 This is one of the schematic diagrams of the circuit structure of a traditional preamplifier in related technologies;

[0055] Figure 5 This is a schematic diagram of the structure of a dynamic comparator provided in an embodiment of the present invention;

[0056] Figure 6 A second schematic diagram of the circuit structure of a preamplifier applied to a dynamic comparator provided in an embodiment of the present invention;

[0057] Figure 7 A timing diagram of the clock signal provided in an embodiment of the present invention;

[0058] Figure 8 The third schematic diagram of the circuit structure of the preamplifier applied to the dynamic comparator provided in the embodiment of the present invention;

[0059] Figure 9 Provided for embodiments of the present invention Figure 8 A schematic diagram of the equivalent structure of the NMOS transistor cross-coupled pair.

[0060] Figure label:

[0061] 100: Transistor amplifier circuit; 200: Tail current adjustment unit; 300: Gain boosting unit; 310: Gain boosting circuit; 311: NMOS transistor cross-coupled pair; 320: Noise suppression circuit. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0063] In the description of the embodiments of the present invention, it should be noted that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of the present invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0064] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of the present invention based on the specific circumstances.

[0065] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0066] This invention provides a preamplifier for use in dynamic comparators, such as... Figure 1 , Figure 2 and Figure 3 As shown, it may include: a transistor amplifier circuit 100 and a tail current adjustment unit 200;

[0067] The transistor amplifier circuit 100 is connected to the first signal input terminal, the second signal input terminal, the first clock signal terminal, and the target node, respectively; when the first clock signal provided by the first clock signal terminal is at a high level, the dynamic comparator is in the comparison phase;

[0068] The transistor amplifier circuit 100 is used to amplify the first input signal input to the first signal input terminal and the second input signal input to the second signal input terminal under the control of the first clock signal during the comparison stage, to generate a first amplified signal and a second amplified signal, and output tail current through the target node during the amplification process;

[0069] The tail current adjustment unit 200 is connected to the first clock signal terminal and the target node respectively, and is used to adjust the tail current through the discharge process under the control of the first clock signal during the comparison phase.

[0070] It should be noted that this invention relates to the field of chip manufacturing. In the physical process of chip manufacturing, PVT (process, voltage, and temperature) is a major factor affecting the performance of integrated circuits. For dynamic comparators, the factor with the greatest impact on PVT is the threshold voltage V. th The change; in addition, the input common-mode voltage V cm The performance of dynamic comparators is also significantly affected. The preamplifier for dynamic comparators provided in this embodiment of the invention addresses an improvement on a conventionally used preamplifier. To distinguish it from the preamplifier provided in this embodiment, we can refer to the improved preamplifier as a conventional preamplifier. The structure of a conventional preamplifier is as follows... Figure 4 As shown, it includes: 5 MOSFETs, denoted as m1, m2, m3, m4, and m5, and 2 signal input terminals for receiving input signal V. in1 and V ip1 The input common-mode voltage V cm =(V in1 +V ip1 ) / 2. Two signal output terminals are used to output the amplified signal V. op1 and V on1 Traditional preamplifiers are controlled by a clock signal clk. The connection relationship of the five MOSFETs is consistent with related technologies, and their working principle can also be found in related technologies, so it will not be repeated here. This includes the dynamic comparator of the traditional preamplifier for PVT and input common-mode voltage V. cm The sensitivity analysis to the changes is as follows:

[0071] First, it should be stated that the output descent rate of all preamplifiers depends on the tail current I. cm The magnitude of the tail current I cm The larger the value, the faster the output common-mode voltage drops, and the faster the comparison speed of the dynamic comparator containing the preamplifier.

[0072] During PVT environmental changes, the biggest factor affecting the performance of the dynamic comparator is the threshold voltage V. th Regarding the changes, it should be noted that the threshold voltage V affects the performance of the dynamic comparator. th This refers to the threshold voltage of the MOSFET at the input terminal. For example... Figure 4 As shown, the input MOSFETs include the first transistor m1 and the second transistor m2, and the output MOSFETs include the third transistor m3 and the fourth transistor m4.

[0073] like Figure 4 As shown, when the input common-mode voltage V cmWhen the threshold voltage V of the MOSFET at the input of the dynamic comparator is kept constant, if at certain PVT process corners... th The gate-source voltage V input to the first MOSFET m1 increases due to the change in PVT. gs1 The increase leads to an increase in the drain-source voltage V of the fifth MOSFET m5. ds5 The value decreases, and the fifth MOSFET m5 can also be called the tail current transistor. For the tail current transistor m5, its overdrive voltage V gs5 -V th5 It will also decrease. According to formula (1), the tail current I cm This will cause a sharp drop, severely impacting the comparison speed of the dynamic comparator.

[0074]

[0075] Where, μ n C represents carrier mobility. ox V is the gate oxide capacitance; W is the MOS channel width, and correspondingly, W1 is the channel width of the first MOS transistor m1; L is the MOS channel length, and correspondingly, L1 is the channel length of the first MOS transistor m1; V gs5 V is the gate-source voltage of the tail current transistor m5; th5 V is the threshold voltage of the tail current transistor m5; ds5 The drain-source voltage of the tail current transistor m5.

[0076] like Figure 4 As shown, at the input common-mode voltage V cm Regarding the changes, the threshold voltage V is set. th The gate-source voltage V of the first MOSFET m1 is kept constant. gs1 The input common-mode voltage V remains constant. cm When the voltage drops, the drain-source voltage V of the fifth MOSFET m5... ds5 Decrease, according to formula (1), V ds5 This reduces and consequently leads to tail current I cm This reduces the speed of comparison in dynamic comparators.

[0077] Additionally, if the input common-mode voltage V cm The voltage V below the threshold voltage V of the MOSFET input pair for m1 and m2 th Then the input pairs of MOSFETs m1 and m2 will operate in the cutoff region. Therefore, at the input common-mode voltage V... cm In low-power conditions, the circuitry of a conventional preamplifier in such a dynamic comparator may not even be able to perform its amplification function properly.

[0078] To address the above problems, this invention proposes a preamplifier for a dynamic comparator, comprising a transistor amplifier circuit 100 and a tail current adjustment unit 200, which adjusts the input common-mode voltage V in the first and second input signals under varying PVT conditions. cm Under changing conditions, the tail current generated by the transistor amplifier circuit 100 can be adjusted by the tail current adjustment unit 200. Compared with the traditional preamplifier without tail current adjustment function, the preamplifier in this embodiment improves the performance of the dynamic comparator and the reliability of the working circuit.

[0079] It should be noted that the preamplifier provided in this embodiment of the invention is applied to a dynamic comparator, which is driven by a clock signal. Therefore, the dynamic comparator in this embodiment may include multiple clock signal terminals for receiving corresponding clock signals. Correspondingly, the preamplifier applied to the dynamic comparator may also include at least one clock signal terminal for receiving the corresponding clock signal. The dynamic comparator may include a reset phase and a comparison phase during operation.

[0080] Furthermore, such as Figure 5 As shown, the dynamic comparator corresponding to the preamplifier applied to the dynamic comparator provided in this embodiment of the invention may further include a latch. For example... Figure 5 As shown, the preamplifier includes a positive input terminal Vip, a negative input terminal Vin, a positive output terminal Vop, and a negative output terminal Von. The two output terminals are connected to a pair of input terminals of a latch. The latch includes a pair of output terminals DP and DN, which are connected to the output circuit of the next stage to output the comparison result signal of the dynamic comparator. It should be noted that... Figure 5 The output circuit of the next stage is not shown in the diagram.

[0081] Figure 5 The dynamic comparator illustrated in the diagram and the dynamic comparator corresponding to the preamplifier applied to the dynamic comparator provided in the embodiments of the present invention can be referenced and corresponded to each other.

[0082] In this embodiment, as Figure 1 and Figure 2 As shown, the preamplifier includes a first signal input terminal Vin, a second signal input terminal Vip, a first amplified signal output terminal Vop, a second amplified signal output terminal Von, and a first clock signal terminal. The first clock signal terminal is used to receive the first clock signal CLK.

[0083] The dynamic comparator in this embodiment operates through a reset phase and a comparison phase. The transistor amplifier circuit 100 in the preamplifier can process the first input signal V. in Second input signal V ipAmplification is performed. When the first clock signal CLK received at the first clock signal terminal is high, the dynamic comparator is in the comparison phase. During the comparison phase, the target node in the preamplifier can output the tail current I. cm When the input common-mode voltage V in the first input signal and the second input signal cm Or the threshold voltage V of the MOSFET at the input of the preamplifier. th When the tail current decreases due to the change in PVT, resulting in a decrease in the comparison speed of the dynamic comparator, the tail current adjustment unit 200 in the preamplifier of this embodiment can appropriately adjust the tail current, so that the tail current I generated in this embodiment... cm Compared to traditional preamplifier structures, it generates a larger tail current, thus ensuring the comparison speed and operational reliability of the dynamic comparator.

[0084] Since the preamplifier for dynamic comparators provided in this embodiment of the invention is an improvement over conventional preamplifiers, therefore, as Figure 3 , Figure 6 As shown, in an exemplary embodiment, the transistor amplifier circuit 100 applied to the preamplifier of the dynamic comparator may include: a ninth transistor M9, a tenth transistor M... 10 11th transistor M 11 and the twelfth transistor M 12 The source of the ninth transistor M9 and the tenth transistor M 10 The sources of transistors M9 and M10 are connected to the power input terminal VDD; the gate of the ninth transistor M9 and the gate of the tenth transistor M10 are connected to the power input terminal VDD. 10 The gates of the transistors are connected to the first clock signal terminal; the drain of the ninth transistor M9 and the eleventh transistor M... 11 The drains of the transistors are connected to the first amplified signal output terminal Vop; the tenth transistor M 10 The drain of the twelfth transistor M 12 The drains of the transistors are connected to the second amplified signal output terminal Von; the eleventh transistor M... 11 The source and the twelfth transistor M 12 The source poles are connected to the target node respectively.

[0085] Specifically, such as Figure 3 , Figure 6 As shown, the ninth transistor M9 can be a PMOS transistor, and the tenth transistor M... 10 It could be a PMOS transistor, or the eleventh transistor M. 11 It can be an NMOS transistor, the twelfth transistor M. 12 It can be an NMOS transistor. NMOS transistor M 11 and NMOS transistor M 12It can be an input pair of a transistor amplifier circuit 100 used to receive input signals.

[0086] Specifically, such as Figure 3 As shown, the target node can be the eleventh transistor M. 11 The source and the twelfth transistor M 12 The current flowing out of the target node at node a, where the source of the transistor is connected to the first transistor M1, can be called the tail current.

[0087] In an exemplary embodiment, such as Figure 2 As shown, the tail current adjustment unit 200 may include: a first capacitor unit and a control unit;

[0088] The first capacitor unit is connected to the target node through the control unit;

[0089] The control unit is connected to the first clock signal terminal and is used to control the first capacitor unit to adjust the tail current through the discharge process under the control of the first clock signal during the comparison phase.

[0090] Specifically, the first capacitor unit may include a first capacitor Cap1. By utilizing the charging and discharging characteristics of the capacitor, in this embodiment, when the dynamic comparator is in the comparison phase, the control unit can control the discharge of the first capacitor Cap1 to adjust the tail current accordingly, thereby ensuring the reliability of the dynamic comparator.

[0091] Entering a place, such as Figure 3 , Figure 6 As shown, the control unit may include a first transistor M1 and a second transistor M2;

[0092] The first terminal of the first capacitor unit is connected to the source of the first transistor M1; the second terminal of the first capacitor unit is connected to the drain of the second transistor M2.

[0093] The drain of the first transistor M1 is connected to the target node;

[0094] The gate of the second transistor M2 is connected to the first clock signal terminal, and the source of the second transistor M2 is connected to the ground terminal.

[0095] The first transistor M1 and the second transistor M2 are turned on when the first clock signal CLK is high, causing the first capacitor unit to discharge to regulate the tail current.

[0096] Specifically, the first transistor M1 can be an NMOS transistor, and the second transistor M2 can be an NMOS transistor. The first clock signal terminal is used to receive the first clock signal CLK.

[0097] In this embodiment, the first capacitor Cap1, NMOS transistors M1 and M2 can form a tail current source. When the first clock signal CLK is high, the dynamic comparator is in the comparison phase. The first clock signal simultaneously triggers NMOS transistors M1 and M2 to turn on, allowing the tail current adjustment unit 200, where the tail current source is located, to regulate the tail current by controlling the discharge of the first capacitor unit to ensure the reliability of the dynamic comparator. It should be noted that the first capacitor unit has already completed the charging process under the control of the control unit during the reset phase. The charging process is as described in the following embodiments.

[0098] In an exemplary embodiment, such as Figure 3 , Figure 6 and Figure 7 As shown, when the first clock signal CLK is low, the dynamic comparator is in the reset phase;

[0099] The control unit is also connected to the power input terminal, the second clock signal terminal, and the ground terminal respectively. During the reset phase, under the control of the first clock signal CLK, it provides the power signal VDD input from the power input terminal to the second terminal of the first capacitor unit, and under the control of the second clock signal CLKB input from the second clock signal terminal, it connects the first terminal of the first capacitor unit to the ground terminal to charge the first capacitor unit.

[0100] Specifically, the clock signal timing diagram of the dynamic comparator in this embodiment is shown in Figure 7. When the dynamic comparator is in the reset phase, the first clock signal CLK is low and the second clock signal CLKB is high.

[0101] Specifically, the voltage at the voltage input terminal can be VDD. The voltage at the ground terminal is VSS.

[0102] In this embodiment, when the dynamic comparator is in the reset phase, the control unit controls the top voltage V at the first terminal of the first capacitor Cap1. Cap1 Reset to VSS, controlling the bottom voltage V at the second terminal of the first capacitor Cap1. Cap1_n The voltage is reset to VDD, causing the voltage potential at the second terminal (lower terminal) of the first capacitor to be higher than the voltage potential at the first terminal (upper terminal). Thus, when the dynamic comparator is in the early stage of the comparison phase, the second terminal (lower terminal) of the first capacitor discharges, causing the voltage at the top of the first terminal (upper terminal) to rise to VDD. Cap1 It can be reduced to a negative voltage below 0, so the voltage potential at the target node a in this embodiment can be higher than the voltage potential at the corresponding node in a conventional preamplifier structure, and thus the tail current generated at the target node a in this embodiment is also I. cmThis is greater than the tail current output at the corresponding node in the traditional preamplifier structure, thus achieving the tail current regulation function in this embodiment to ensure the reliability of the dynamic comparator.

[0103] Furthermore, such as Figure 3 , Figure 6 As shown, the control unit may also include a third transistor M3 and a fourth transistor M4;

[0104] The gate of the third transistor M3 is connected to the first clock signal terminal, the source of the third transistor M3 is connected to the second terminal of the first capacitor unit, and the drain of the third transistor M3 is connected to the power input terminal. The third transistor M3 is turned on when the first clock signal CLK is low, so as to provide the power signal input from the power input terminal to the second terminal of the first capacitor unit.

[0105] The gate of the fourth transistor M4 is connected to the second clock signal terminal, the source of the fourth transistor M4 is connected to the first terminal of the first capacitor unit, and the drain of the fourth transistor M4 is connected to the ground terminal. The fourth transistor M4 is turned on when the second clock signal CLKB provided by the second clock signal terminal is at a high level, so as to connect the first terminal of the first capacitor unit to the ground terminal.

[0106] Specifically, the third transistor M3 can be a PMOS transistor, and the fourth transistor M4 can be an NMOS transistor.

[0107] This embodiment describes the specific charging process of the first capacitor Cap1 during the reset phase. The capacitor is charged by triggering the corresponding MOS transistor through a relevant clock signal, which further facilitates the adjustment of the tail current.

[0108] The following uses a specific implementation method one, combined with... Figure 6 and Figure 7 The process of adjusting the tail current is explained in detail.

[0109] like Figure 6 As shown, in the preamplifier applied to the dynamic comparator provided in this embodiment, the first transistor is NMOS transistor M1, the second transistor is NMOS transistor M2, the third transistor is PMOS transistor M3, the fourth transistor is NMOS transistor M4, the ninth transistor is PMOS transistor M9, and the tenth transistor is PMOS transistor M1. 10 The eleventh transistor is an NMOS transistor M. 11 The twelfth transistor is an NMOS transistor M. 12 .

[0110] The operation of a dynamic comparator is controlled by a clock signal and consists of two phases: a reset phase and a comparison phase. The dynamic comparator performs one comparison per clock cycle.

[0111] like Figure 7 As shown, during the reset phase of the dynamic comparator, the first clock signal CLK is low and the second level signal CLKB is high.

[0112] During the reset phase, triggered by the second clock signal CLKB, NMOS transistor M4 is turned on, and the drain of M4 is grounded. Therefore, the voltage V at the top of the first capacitor Cap1 connected to the source of M4 is... Cap1 The circuit is reset to VSS; at this time, the first clock signal is CLK low, PMOS transistor M3 is turned on, and the drain voltage of PMOS transistor M3 is VDD. Therefore, the bottom voltage V at the second terminal of the first capacitor Cap1 connected to the source of PMOS transistor M3 is VDD. Cap1_n It is reset to VDD, where VDD is the voltage of the power supply signal; obviously, V Cap1_n Greater than V Cap1 Based on this, the charging process of the first capacitor Cap1 is completed.

[0113] like Figure 6 As shown, assuming the input common-mode voltage V cm The NMOS transistor input pair M is kept constant as const1. 11 and M 12 Threshold voltage V th Because of the change in PVT, the NMOS transistor M increases. 11 Gate-source voltage V gs11 During the comparison phase, the tail current I increases accordingly. cm The corresponding current decreases. In this case, the tail current adjustment unit 200 in this embodiment can play a corresponding adjustment role, because the bottom voltage V at the second end of the first capacitor Cap1 is smaller. Cap1_n During the reset phase, it has been reset to VDD and is higher than V. Cap1 Therefore, in the early stage of the comparison phase of the dynamic comparator, the second terminal of the first capacitor Cap1 can be discharged through the NMOS transistor M2. This discharge process causes the top voltage V at the first terminal of the first capacitor to decrease. Cap1 It can be reduced to a negative voltage below 0 potential; therefore, the gate-source voltage V of NMOS transistor M1... gs1 It can be extended, and at the same time, due to V Cap1 The decrease in voltage reduces the drain-source voltage V of NMOS transistor M1. ds1 Also than Figure 4 The traditional preamplifier structure has a large drain-source voltage, which causes the tail current I to be large. cm Compare Figure 4 The tail current corresponding to the traditional preamplifier structure is also large. At this time, although the NMOS transistor input to M... 11 and M 12 Threshold voltage Vth The speed increases, but the dynamic comparator can maintain a high comparison speed.

[0114] Furthermore, the preamplifier provided in this embodiment also has strong resistance to input common-mode voltage V. cm The ability to maintain performance under changes. For example... Figure 6 As shown, assume the NMOS transistor input pair M 11 and M 12 Threshold voltage V th If the constant value is const2, then the NMOS transistor M 11 Gate-source voltage V gs11 The input common-mode voltage V is constant. cm If the input of the NMOS transistor is reduced, then the input of the NMOS transistor to M... 11 and M 12 Source voltage V s Decrease, NMOS transistor M 11 Gate-source voltage V gs11 and drain-source voltage V ds11 All of them are consumed, tail current I cm The corresponding current decreases. In this case, the tail current adjustment unit 200 in this embodiment can play a corresponding adjustment role, because the bottom voltage V at the second end of the first capacitor Cap1 is smaller. Cap1_n During the reset phase, it has been reset to VDD and is higher than V. Cap1 Since the voltage is 0, in the early stage of the comparison phase of the dynamic comparator, the second terminal of the first capacitor Cap1 can be discharged through the NMOS transistor M2. This discharge process causes the top voltage V at the first terminal of the first capacitor to decrease. Cap1 It can be reduced to a negative voltage below 0 potential; therefore, the gate-source voltage V of NMOS transistor M1... gs1 It can be extended, and at the same time, due to V Cap1 The reduction in voltage Vd of NMOS transistor M1 in this embodiment reduces the drain-source voltage Vd. ds1 Also than Figure 4 The traditional preamplifier structure corresponds to a large drain-source voltage, which results in a large tail current I in this embodiment. cm Compare Figure 4 The tail current corresponding to the traditional preamplifier structure is also large. At this time, although the input common-mode voltage V cm The speed is reduced, but the dynamic comparator can maintain a high comparison speed.

[0115] It should be noted that, in this embodiment, as Figure 7As shown, the second clock signal CLKB and the first clock signal CLK are two non-overlapping clocks. The second clock signal CLKB jumps to VSS before the rising edge of the first clock signal CLK. This is because if the second clock signal CLKB controlling the NMOS transistor M4 overlaps with the first clock signal CLK, then when the top voltage V of the first capacitor Cap1... Cap1 When the voltage drops below VSS, the gate-source voltage V of NMOS transistor M4... gs4 It may exceed its corresponding threshold voltage V th4 This leads to leakage current in M4. Subsequently, the current from NMOS transistor M1 charges the first capacitor Cap1, causing the top voltage V at the first terminal of the first capacitor Cap1 to rise. Cap1 It gradually rose to above VSS.

[0116] In an exemplary embodiment, such as Figure 3 As shown, the preamplifier applied to the dynamic comparator may further include a gain boosting unit 300, which is connected to the output terminal of the first amplified signal, the output terminal of the second amplified signal, and the third clock signal terminal, respectively, and is used to boost the gain of the preamplifier under the control of the third clock signal CLKD provided by the third clock signal terminal.

[0117] Specifically, such as Figure 3 As shown, the gain boosting unit 300 may include a gain boosting circuit and a noise suppression circuit 320;

[0118] The first input terminal of the gain boosting circuit 310 is connected to the output terminal of the first amplified signal, the second input terminal of the gain boosting circuit 310 is connected to the output terminal of the second amplified signal, and the third input terminal of the gain boosting circuit 310 is connected to the third clock signal terminal; the gain boosting circuit 310 is used to boost the gain of the preamplifier under the control of the third clock signal CLKD.

[0119] The noise suppression circuit 320 is connected to the ground terminal and the output terminal of the gain boost circuit 310, respectively, to reduce the noise of the gain boost circuit 310.

[0120] Furthermore, such as Figure 3 As shown, the gain boosting circuit 310 may include a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7;

[0121] The drain of the fifth transistor M5 and the gate of the sixth transistor M6 are respectively connected to the first input terminal of the gain boosting circuit 310.

[0122] The gate of the fifth transistor M5 and the drain of the sixth transistor M6 are connected to the second input terminal of the gain boosting circuit 310, respectively.

[0123] The source of the fifth transistor M5 and the source of the sixth transistor M6 are connected to the drain of the seventh transistor M7, respectively; the gate of the seventh transistor M7 is connected to the third clock signal terminal, and the source of the seventh transistor M7 is connected to the output terminal of the gain boosting circuit 310.

[0124] The seventh transistor M7 is used to turn on when the third clock signal CLKD is high, so that the gain boosting circuit 310 can work.

[0125] like Figure 7 As shown, the third clock signal transitions from low to high after the rising edge of the first clock signal, and then transitions from high to low after the falling edge of the first clock signal.

[0126] Specifically, such as Figure 3 As shown, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 can all be NMOS transistors.

[0127] Specifically, NMOS transistors M5 and M6 can be referred to as an NMOS transistor cross-coupled pair. Unlike the cross-coupling of NMOS transistors in related technologies, which is controlled by VDD, the cross-coupled pair M5 and M6 in this embodiment is controlled by the third clock signal CLKD, which can save more power consumption.

[0128] Additionally, the cross-coupling of the NMOS transistors contributes noise to M5 and M6 as part of the preamplifier load. To address this issue, such as... Figure 7 As shown, the rising edge of the third clock signal CLKD is set later than the rising edge of the first clock signal CLK. This means that the seventh transistor M7 turns on later. When the NMOS transistor cross-coupling pairs M5 and M6 start working, the gain of the preamplifier is already slightly higher, thus suppressing the noise contributed by the NMOS transistor cross-coupling pairs to M5 and M6. Specifically, the timing diagram of the clock signals is as follows: Figure 7 As shown, the third clock signal CLKD transitions from low to high after a first preset duration Δt1 following the rising edge of the first clock signal CLK, and then transitions from high to low after a second preset duration Δt2 following the falling edge of the first clock signal. Furthermore, the first preset duration Δt1 and the second preset duration Δt2 can be set according to actual conditions.

[0129] Furthermore, by employing dynamic bias during the regeneration process, the tail current I corresponding to M5 and M6 corresponding to the NMOS transistor cross-coupling is reduced. cm2 It can also effectively reduce the noise of M5 and M6.

[0130] Furthermore, the positive feedback formed by the cross-coupling of the NMOS transistors to M5 and M6 can amplify the first amplified signal V. op Second amplified signal Von The difference between them increases the gain of the preamplifier. The derivation of this principle is explained in detail in Implementation Method Two below.

[0131] In an exemplary embodiment, such as Figure 3 As shown, the noise suppression circuit 320 includes a second capacitor unit;

[0132] The first terminal of the second capacitor unit is connected to the source of the seventh transistor M7; the second terminal of the second capacitor unit is connected to the ground terminal.

[0133] Specifically, such as Figure 3 As shown, the second capacitor may include a second capacitor Cap2.

[0134] In this embodiment, the charging process of the second capacitor can be used to reduce the tail current I of the NMOS transistor cross-coupling to M5 and M6. cm2 This reduces the transconductance of NMOS transistor cross-coupling to M5 and M6, ultimately reducing the noise contribution of NMOS transistor cross-coupling to M5 and M6. The derivation of this principle is explained in detail in Implementation Method Two below.

[0135] In an exemplary embodiment, such as Figure 3 As shown, when the first clock signal CLK is low, the dynamic comparator is in the reset phase; the noise suppression circuit 320 also includes an eighth transistor M8;

[0136] The gate of the eighth transistor M8 is connected to the second clock signal terminal, the source of the eighth transistor M8 is connected to the second terminal of the second capacitor unit, and the drain of the eighth transistor M8 is connected to the first terminal of the second capacitor unit.

[0137] The eighth transistor M8 is used to turn on during the reset phase under the control of the second clock signal CLKB provided at the second clock signal terminal, so as to discharge the second capacitor cell.

[0138] Specifically, the eighth transistor M8 can be an NMOS transistor.

[0139] In this embodiment, the control process of charging and discharging the second capacitor is described in detail to ensure the noise suppression effect.

[0140] The following uses specific implementation method two, combined with Figure 8 The working principle of the preamplifier applied to the dynamic comparator provided in this embodiment will be further analyzed and explained.

[0141] like Figure 8As shown, in the preamplifier applied to the dynamic comparator provided in this embodiment, the first transistor can be NMOS transistor M1, the second transistor can be NMOS transistor M2, the third transistor can be PMOS transistor M3, the fourth transistor can be NMOS transistor M4, the fifth transistor can be NMOS transistor M5, the sixth transistor can be NMOS transistor M6, the seventh transistor can be NMOS transistor M7, the eighth transistor can be NMOS transistor M8, the ninth transistor can be PMOS transistor M9, and the tenth transistor can be PMOS transistor M1. 10 The eleventh transistor can be an NMOS transistor M. 11 The twelfth transistor can be an NMOS transistor M. 12 Among them, NMOS transistor M 11 and NMOS transistor M 12 It can be an NMOS transistor input pair in a transistor amplifier circuit, used to receive input signals. NMOS transistors M5 and M6 can be a cross-coupled pair 311 of NMOS transistors used to increase the gain of the preamplifier in this embodiment.

[0142] During the comparison phase of the dynamic comparator, according to formulas (2)-(5), the differential current ΔI at the output terminal is as shown in formula (7).

[0143]

[0144] ΔV IN =V ip -V in (3)

[0145]

[0146]

[0147] I cm =I1+I2=2I cm_in (6)

[0148]

[0149] V ip V is the first input signal; in This is the second input signal; V cm For NMOS transistor input pair M 11 and M 12 The input common-mode voltage, that is, the input common-mode voltage in the first input signal and the second input signal; V th11 For NMOS transistor M 11 Threshold voltage; ΔV IN It is the input differential voltage; V s For NMOS transistor input pair M 11and M 12 The source voltage; I1 is the NMOS transistor M 11 Operating current; I2 is the operating current of NMOS transistor M 12 Operating current; W 11 For MOSFET M 11 The width of the channel; L 11 For MOSFET M 11 The length of the channel; W 12 For MOSFET M 12 The width of the channel; L 12 For MOSFET M 12 The length of the channel; V th11 For MOSFET M 11 Threshold voltage; V th12 For MOSFET M 12 Threshold voltage; I cm For NMOS transistor input pair M 11 and M 12 Tail current; I cm_in For NMOS transistor input pair M 11 and M 12 common-mode current; g m It is a transconductor.

[0150] As shown in equation (8), for the preamplifier in the dynamic comparator, t int This is the integration time, while the drop in the common-mode voltage at the output of the preamplifier is ΔV. cmo C is the parasitic capacitance at the output of the preamplifier. Common-mode current I... cm_in The larger the value, the larger the first amplified signal V output from the output terminal. op Second amplified signal V on The faster the descent, the higher the speed of the comparator.

[0151] As shown in formula (9), ΔV OUT This is the differential-mode voltage at the output of the preamplifier. The voltage V at the top of the first terminal of the first capacitor. Cap1 First, the voltage drops to a negative value, at which point the NMOS transistor input to M... 11 and M 12 It operates in the strong inversion region SI. When the tail current I... cm1 When charging the first terminal (i.e., the upper terminal) of the second terminal of the first capacitor Cap1, the top voltage V of the first terminal of the first capacitor Cap1 is... Cap1 The voltage gradually rises to a positive value, therefore the common-mode current I... cm_in (t) will change over time, rather than remain constant.

[0152]

[0153]

[0154] NMOS transistor input pair M 11 and M 12 Source voltage V s It will also be affected by the top voltage V Cap1 The rise in the value causes the NMOS transistor input to rise relative to M. 11 and M 12 The operating state gradually transitions from the strong inversion region (SI region) to the weak inversion region (WI region), which means that the NMOS transistor input to M... 11 and M 12 transconductance efficiency g m / i d Changes occur during the comparison phase. In this case, the average transconductance efficiency (g) can be used. m / I cm_in ) avg To simplify the circuit model. In the weak inversion region, i.e., the WI region, the cross-coupling of NMOS transistors affects the transconductance efficiency g of M5 and M6. m / i d This can be viewed as q / nkT, thus yielding a conventional preamplifier operating in the SI region (as explained above). Figure 4 The gain A of the conventional preamplifier shown SI As shown in Equation (10), the gain A of a conventional preamplifier operating in the WI region is... WI As shown in formula (11), the gain A of the dynamic preamplifier proposed in this embodiment is shown in formula (12), where q is the electron charge, k is the Boltzmann constant, n is the ideality factor, and T is the temperature.

[0155]

[0156]

[0157]

[0158] According to formula (13), the equivalent gain of the preamplifier in this embodiment is between two gains A of the conventional preamplifier. SI and A WI Therefore, it can be seen that the preamplifier provided in this embodiment effectively suppresses the noise generated by the subsequent latch while ensuring the high-speed comparison performance of the dynamic comparator. By adjusting the values ​​of NMOS transistor M2 and the first capacitor Cap1, the top voltage V Cap1 It can drop below VSS and then slowly rise again throughout the comparison cycle. An excessively large channel width-to-length ratio (W / L) of NMOS transistor M2 will cause the first capacitor Cap1 to discharge too quickly through M2, resulting in a decrease in the gate-source voltage V of M4. gs4Exceeding the corresponding threshold voltage V th4 This can cause leakage in M4. If the W / L ratio of M2 is set too low, it can lead to a voltage V on the top of the first capacitor Cap1. Cap1 The descent is slow, and the tail current I cm The smaller size is detrimental to the comparison speed of the dynamic comparator. However, in this embodiment, the NMOS transistor cross-coupling settings for 311M5 and M6 can change this situation.

[0159]

[0160] The NMOS transistors cross-coupled to operate in the WI region (311M5 and M6) can further increase the gain of the dynamic comparator. In this embodiment, as... Figure 8 and Figure 9 As shown, the NMOS transistor cross-coupled pair 311M5 and M6 can be regarded as a pair of voltage-controlled current sources, and their respective currents can be abstractly simplified to βV. op and βV on , where β is the equivalent transconductance of the NMOS transistor cross-coupled pair 311M5 and M6. At the output node Von, the KCL equation is shown in Equation (14); at the output node Vop, the KCL equation is shown in Equation (15).

[0161]

[0162]

[0163]

[0164] The equivalent gain A' of the preamplifier after adding the NMOS transistor cross-coupled pair 311M5 and M6 can be obtained using formulas (7), (14), (15) and (16), as shown in formula (17). If the NMOS transistor cross-coupled pair M5 and M6 are removed from the preamplifier circuit, the corresponding gain becomes A in formula (18).

[0165]

[0166]

[0167] Comparing formulas (17) and (18), it can be seen that the cross-coupling of NMOS transistors can indeed effectively improve the equivalent gain of the preamplifiers M5 and M6.

[0168] Regarding noise performance, the noise of the dynamic comparator in this embodiment is mainly caused by the following NMOS transistor input pair M 11 and M 12 The cross-coupling of NMOS transistors contributes to M5, M6, and the latch.

[0169] For the NMOS transistor input pair M 11 and M 12 In the comparison phase, as the top voltage V... Cap1 The improvement allows it to operate from the SI region to the WI region. The NMOS transistor operating in the SI region has an input pair M... 11 and M 12 Equivalent output integral noise E o_SI As shown in formula (19), the input pair M of the NMOS transistor operating in the WI region 11 and M 12 Equivalent output integral noise E o_WI As shown in equation (20), the equivalent output integral noise E of the preamplifier o As shown in formula (21), where γ is the noise factor.

[0170]

[0171]

[0172] When the NMOS transistor input is M 11 and M 12 When operating in the SI region, its equivalent input noise power is as shown in formula (22). When the NMOS transistor input is to M 11 and M 12 When operating in the WI region, its equivalent input noise power is shown in Equation (23), and the equivalent input noise of the preamplifier is shown in Equation (24).

[0173]

[0174]

[0175]

[0176] The NMOS transistors cross-coupled to M5 and M6 serve as the load of the preamplifier in this embodiment. They always operate in WI. The transconductance g of the NMOS transistors cross-coupled to M5 and M6... m5，6 The smaller the value, the smaller the noise contribution.

[0177]

[0178]

[0179] V ds7 V is the drain-source voltage of M7. th7 This is the threshold voltage of M7.

[0180] When the second capacitor Cap2 is subjected to common-mode current I cm2During charging, the voltage V at the first terminal of the second capacitor Cap2 Cap2 It will gradually increase, leading to the corresponding common-mode current I. cm2 Reduce the transconductance g of NMOS transistor cross-coupling on M5 and M6 m5，6 As shown in equation (26), the noise decreases continuously during the comparison process, thus reducing the noise contribution of NMOS transistor cross-coupling to M5 and M6. According to the derivation, after the arrival of the first clock signal CLK, the differential output first decreases rapidly, while during the regeneration phase, the NMOS transistor input to M... 11 and M 12 When operating in the WI region, the preamplifier has a higher gain, which can suppress the equivalent input noise power contributed by the latch.

[0181] This invention also provides a dynamic comparator, including the preamplifier used in the dynamic comparator in any of the above embodiments.

[0182] In an exemplary embodiment, the dynamic comparator may further include a latch, which includes a fourth clock signal terminal for receiving a fourth clock signal.

[0183] Specifically, such as Figure 7 As shown, the fourth clock signal NCLK can be used to reset the latch. In addition, the potentials of the first amplified signal output terminal Vop and the second amplified signal output terminal Von of the dynamic preamplifier are reset to VDD and VSS, respectively. The potentials of the first output terminal DP and the second output terminal DN of the latch are reset to VDD and VSS, respectively.

[0184] In an exemplary embodiment, the dynamic comparator may further include a clock module, which includes multiple clock signal output terminals, each corresponding one-to-one with a multiple clock signal of the dynamic comparator.

[0185] This invention also provides an analog-to-digital converter, including a preamplifier applied to a dynamic comparator as described in any of the above embodiments, or including a dynamic comparator as described in any of the above embodiments.

[0186] This invention also provides a chip that includes a preamplifier applied to a dynamic comparator as described in any of the above embodiments, or includes a dynamic comparator as described in any of the above embodiments, or includes an analog-to-digital converter as described in any of the above embodiments.

[0187] This invention also provides an electronic device, including a preamplifier applied to a dynamic comparator as described in any of the above embodiments, or including a dynamic comparator as described in any of the above embodiments, or including an analog-to-digital converter as described in any of the above embodiments, or including a chip as described in any of the above embodiments.

[0188] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

[0189] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0190] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A preamplifier applied to a dynamic comparator, characterized in that, include: Transistor amplifier circuit and tail current regulation unit; The transistor amplifier circuit is connected to the first signal input terminal, the second signal input terminal, the first clock signal terminal, and the target node, respectively. When the first clock signal provided by the first clock signal terminal is at a high level, the dynamic comparator is in the comparison phase; The transistor amplifier circuit is used in the comparison stage to amplify the first input signal input to the first signal input terminal and the second input signal input to the second signal input terminal under the control of the first clock signal, to generate a first amplified signal and a second amplified signal, and to output a tail current through the target node during the amplification process; The tail current adjustment unit is connected to the first clock signal terminal and the target node respectively, and is used to adjust the tail current through the discharge process under the control of the first clock signal during the comparison phase. The tail current adjustment unit includes: a first capacitor unit and a control unit; the first capacitor unit is connected to the target node through the control unit; the control unit is connected to the first clock signal terminal and is used to control the first capacitor unit to adjust the tail current through a discharge process under the control of the first clock signal during the comparison phase. The control unit includes a first transistor and a second transistor; a first terminal of the first capacitor unit is connected to the source of the first transistor; a second terminal of the first capacitor unit is connected to the drain of the second transistor; the drain of the first transistor is connected to the target node; the gate of the second transistor is connected to the first clock signal terminal, and the source of the second transistor is connected to the ground terminal; the first transistor and the second transistor are turned on when the first clock signal is high, causing the first capacitor unit to discharge to adjust the tail current; When the first clock signal is low, the dynamic comparator is in the reset phase; the control unit is also connected to the power input terminal, the second clock signal terminal and the ground terminal respectively, and is used to provide the power signal input from the power input terminal to the second terminal of the first capacitor unit under the control of the first clock signal during the reset phase, and to connect the first terminal of the first capacitor unit to the ground terminal under the control of the second clock signal input from the second clock signal terminal, so as to charge the first capacitor unit; The control unit further includes a third transistor and a fourth transistor; the gate of the third transistor is connected to the first clock signal terminal, the source of the third transistor is connected to the second terminal of the first capacitor unit, and the drain of the third transistor is connected to the power input terminal; the third transistor is turned on when the first clock signal is low, so as to provide the power signal input from the power input terminal to the second terminal of the first capacitor unit; the gate of the fourth transistor is connected to the second clock signal terminal, the source of the fourth transistor is connected to the first terminal of the first capacitor unit, and the drain of the fourth transistor is connected to the ground terminal; the fourth transistor is turned on when the second clock signal provided by the second clock signal terminal is high, so as to connect the first terminal of the first capacitor unit to the ground terminal; The second clock signal and the first clock signal are two non-overlapping clocks.

2. The preamplifier applied to a dynamic comparator according to claim 1, characterized in that, It also includes a gain boosting unit; The gain boosting unit is connected to the output terminal of the first amplified signal, the output terminal of the second amplified signal, and the third clock signal terminal, respectively, and is used to boost the gain of the preamplifier under the control of the third clock signal provided by the third clock signal terminal.

3. The preamplifier applied to a dynamic comparator according to claim 2, characterized in that, The gain enhancement unit includes: a gain enhancement circuit and a noise suppression circuit; The first input terminal of the gain boosting circuit is connected to the output terminal of the first amplified signal, the second input terminal of the gain boosting circuit is connected to the output terminal of the second amplified signal, and the third input terminal of the gain boosting circuit is connected to the third clock signal terminal; the gain boosting circuit is used to boost the gain of the preamplifier under the control of the third clock signal. The noise suppression circuit is connected to the ground terminal and the output terminal of the gain boosting circuit, respectively, and is used to reduce the noise of the gain boosting circuit.

4. The preamplifier applied to a dynamic comparator according to claim 3, characterized in that, The gain boosting circuit includes a fifth transistor, a sixth transistor, and a seventh transistor; The drain of the fifth transistor and the gate of the sixth transistor are respectively connected to the first input terminal of the gain boosting circuit; The gate of the fifth transistor and the drain of the sixth transistor are respectively connected to the second input terminal of the gain boosting circuit; The source of the fifth transistor and the source of the sixth transistor are respectively connected to the drain of the seventh transistor; the gate of the seventh transistor is connected to the third clock signal terminal, and the source of the seventh transistor is connected to the output terminal of the gain boosting circuit. The seventh transistor is used to turn on when the third clock signal is high, so that the gain boosting circuit can work. The third clock signal transitions from low to high after the rising edge of the first clock signal, and then transitions from high to low after the falling edge of the first clock signal.

5. The preamplifier applied to a dynamic comparator according to claim 4, characterized in that, The noise suppression circuit includes a second capacitor unit; The first terminal of the second capacitor unit is connected to the source of the seventh transistor; the second terminal of the second capacitor unit is connected to the ground terminal.

6. The preamplifier applied to a dynamic comparator according to claim 5, characterized in that, When the first clock signal is low, the dynamic comparator is in the reset phase; the noise suppression circuit also includes an eighth transistor. The gate of the eighth transistor is connected to the second clock signal terminal, the source of the eighth transistor is connected to the second terminal of the second capacitor unit, and the drain of the eighth transistor is connected to the first terminal of the second capacitor unit. The eighth transistor is used to be turned on during the reset phase under the control of the second clock signal provided at the second clock signal terminal, so as to discharge the second capacitor unit.

7. The preamplifier applied to a dynamic comparator according to claim 1, characterized in that, The transistor amplifier circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; The source of the ninth transistor and the source of the tenth transistor are respectively connected to the power input terminal. The gates of the ninth transistor and the tenth transistor are respectively connected to the first clock signal terminal. The drains of the ninth transistor and the eleventh transistor are respectively connected to the first amplified signal output terminal; the drains of the tenth transistor and the twelfth transistor are respectively connected to the second amplified signal output terminal. The source of the eleventh transistor and the source of the twelfth transistor are respectively connected to the target node.

8. A dynamic comparator, characterized in that, Includes a preamplifier applied to a dynamic comparator as described in any one of claims 1 to 7.

9. An analog-to-digital converter, characterized in that, Includes the dynamic comparator as described in claim 8.

10. A chip, characterized in that, Includes the analog-to-digital converter as described in claim 9.

11. An electronic device, characterized in that, Includes the chip as described in claim 10.

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