A low flatness high precision analog switch circuit with low injected charge

Abstract

The application belongs to the field of integrated circuit design, and particularly relates to a low flatness high-precision analog switch circuit with low injected charge; comprising: a first delay control circuit output end connected with a P1 gate and a second delay control circuit input end; a second delay control circuit output end and a P1 substrate both connected with a first substrate control circuit; a signal connected with the first delay control circuit input end and the first substrate control circuit; a third delay control circuit output end connected with an N1 gate and a fourth delay control circuit input end; a fourth delay control circuit output end and an N1 substrate both connected with a second substrate control circuit; a signal CK connected with the third delay control circuit input end and the second substrate control circuit; an input signal V IN connected with the P1 and N1 drain and the first and second substrate control circuits respectively; and the P1 and N1 source serving as an output signal V OUT together; the application can improve the flatness of the analog switch and reduce the injected charge, and realizes high-precision signal acquisition.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, specifically relating to a low-flatness, high-precision analog switch circuit with low injected charge. Background Technology

[0002] Analog switches are frequently used in integrated circuits, especially in signal acquisition circuit systems, to transmit high-precision analog signals. Many systems now require extremely high signal acquisition accuracy. If the resistance flatness of the switching transistor is poor or the injected charge is large, it will cause significant distortion in the input signal acquisition, leading to signal sampling errors.

[0003] Currently, commonly used analog switching circuits are generally composed of MOSFET transistors, which can be roughly divided into three types: ① single NMOS transistor, ② single PMOS transistor, and ③ bidirectional CMOS transistor, such as... Figure 1 As shown, the transistor's on / off state is controlled by controlling its gate voltage. The relationship between its on-resistance and the signal voltage is as follows: Figure 2 As shown, analog switches composed of single N-type or single P-type MOSFET transistors exhibit a high flatness between their on-resistance and signal voltage. This nonlinear resistance can negatively impact signal acquisition, introducing errors in DC accuracy and AC distortion. While bidirectional CMOS switches can significantly reduce on-resistance and improve linearity, maintaining low flatness requires adjusting the size ratio of the PMOS and NMOS transistors. Generally, the PMOS transistor needs to be approximately three times the size of the NMOS transistor to maintain low flatness. The charge injection of a bidirectional CMOS switch is as follows... Figure 3 As shown, the significant size difference between PMOS and NMOS transistors leads to a large difference between Δq1 (hole charge) and Δq2 (electron charge), resulting in substantial injected charge. This significantly impacts input signal acquisition, causing sampling errors. Furthermore, the substrates of the PMOS and NMOS transistors are connected to the highest positive power supply VDD and the lowest negative power supply VSS, respectively. Since the acquired input signal is not a fixed value, the input signal VDD will vary. IN When VSS and VDD change, the substrate bias effect in the MOS transistor can further widen the depletion layer thickness of the field-induced junction, leading to an increase in the space charge surface density and consequently increasing the threshold voltage V of the transistor. TH The increase in on-resistance further leads to a larger on-resistance in the device itself. Under the same on-resistance, the substrate bias effect causes the area of ​​the MOSFET to increase. Summary of the Invention

[0004] To improve the flatness of analog switches, reduce injected charge, and achieve high-precision signal acquisition, this invention proposes a low-flatness, high-precision analog switch circuit with low injected charge. The circuit includes: a PMOS transistor P1, an NMOS transistor N1, a first delay control circuit, a second delay control circuit, a third delay control circuit, a fourth delay control circuit, a first substrate control circuit, and a second substrate control circuit. The output of the first delay control circuit is connected to the gate of the PMOS transistor P1 and the input of the second delay control circuit. The output of the second delay control circuit and the substrate of the PMOS transistor P1 are both connected to the first substrate control circuit. The signal CK is connected as an input signal to the input terminal of the first delay control circuit and the first substrate control circuit; the output terminal of the third delay control circuit is connected to the gate of NMOS transistor N1 and the input terminal of the fourth delay control circuit; the output terminal of the fourth delay control circuit and the substrate of NMOS transistor N1 are both connected to the second substrate control circuit; the signal CK is connected as an input signal to the input terminal of the third delay control circuit and the second substrate control circuit; the input signal V... IN The drain of PMOS transistor P1, the first substrate control circuit, the second substrate control circuit, and the drain of NMOS transistor N1 are connected respectively; the source of PMOS transistor P1 and the source of NMOS transistor N1 together serve as the output signal V. OUT .

[0005] Preferably, the first delay control circuit includes a PMOS transistor P4 and an NMOS transistor N4; the gates of the PMOS transistor P4 and the NMOS transistor N4 together serve as the input terminal of the first delay control circuit, and the drains of the PMOS transistor P4 and the NMOS transistor N4 together serve as the output terminal of the first delay control circuit; the source and substrate of the PMOS transistor P4 are connected to the positive power supply VDD, and the source and substrate of the NMOS transistor N4 are connected to the negative power supply VSS.

[0006] Furthermore, the first delay control circuit, the second delay control circuit, the third delay control circuit, and the fourth delay control circuit have the same structure.

[0007] Preferably, the first substrate control circuit includes a PMOS transistor P2, an NMOS transistor N2, and a first resistor R1; the gate of the NMOS transistor N2 is connected to the output terminal of the second delay control circuit, and the source of the NMOS transistor N2 and the substrate are connected to the input signal V. IN The drain of NMOS transistor N2 is connected to the substrate of PMOS transistor P1 and the drain of PMOS transistor P2; the gate of PMOS transistor P2 is connected to the input signal. The source and substrate of PMOS transistor P2 are connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the positive power supply VDD.

[0008] Preferably, the second substrate control circuit includes a PMOS transistor P3, an NMOS transistor N3, and a second resistor R2; the gate of the PMOS transistor P3 is connected to the output terminal of the fourth delay control circuit, and the source of the PMOS transistor P3 and the substrate are connected to the input signal V. IN The drain of PMOS transistor P3 is connected to the substrate of NMOS transistor N1 and the drain of NMOS transistor N3; the gate of NMOS transistor N3 is connected to the input signal CK; the source and substrate of NMOS transistor N3 are connected to one end of the second resistor R2; and the other end of the first resistor R2 is connected to the negative power supply VSS.

[0009] Preferably, the signal The CK signal and the CK signal are a pair of opposite complementary signals. Signal CP1 is generated by the first delay control circuit, and CP1 is... Signal inversion; CP1 generates signal CN2 through the second delay control circuit, and CN2 is the inversion of CP1 signal; CK generates signal CN1 through the third delay control circuit, and CN1 is the inversion of CK signal; CN1 generates signal CP2 through the fourth delay control circuit, and CP2 is the inversion of CN1 signal.

[0010] The beneficial effects of this invention are as follows: The low-injection-charge, low-flatness, high-precision analog switching circuit proposed in this invention, through reasonable design, can effectively reduce the size of switching transistors P1 and N1. Simultaneously, it enables P1 and N1 to generate output V... OUT The injected charge is canceled out; compared with the prior art, the present invention can effectively solve the problems of flatness and injected charge in analog switches, eliminate the substrate bias effect, and effectively reduce circuit area and output leakage current. Furthermore, the present invention can be widely applied in analog signal transmission equipment to achieve high-precision signal acquisition. Attached Figure Description

[0011] Figure 1 Schematic diagrams of three existing transistor structures;

[0012] Figure 2 The graph shows the relationship between the on-resistance and signal voltage for three types of existing transistors.

[0013] Figure 3 Schematic diagram of injecting charge into a bidirectional CMOS switch;

[0014] Figure 4 This is a schematic diagram of a low-flatness, high-precision analog switch circuit with low injected charge in this invention.

[0015] Figure 5 This is a schematic diagram of a preferred embodiment of the low-flatness, high-precision analog switch circuit with low injected charge in this invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] Maintaining low flatness leads to significant size differences between the P-type and N-type transistors in a bidirectional CMOS analog switch. This results in the injection charges of the P-type and N-type transistors not canceling out, ultimately causing the injected charges to couple to the output, interfering with the acquisition of the input signal and even causing sampling errors. To improve the flatness of the analog switch, reduce the injected charge, and achieve high-precision signal acquisition, this invention proposes a low-flatness, high-precision analog switch circuit with low injected charge, such as... Figure 4 As shown, the circuit includes: a PMOS transistor P1, an NMOS transistor N1, a first delay control circuit (delay control circuit 1), a second delay control circuit (delay control circuit 2), a third delay control circuit (delay control circuit 3), a fourth delay control circuit (delay control circuit 4), a first substrate control circuit (substrate control circuit 1), and a second substrate control circuit (substrate control circuit 2); the output terminal of the first delay control circuit is connected to the gate of the PMOS transistor P1 and the input terminal of the second delay control circuit; the output terminal of the second delay control circuit and the substrate of the PMOS transistor P1 are both connected to the first substrate control circuit; the signal... The signal CK is connected as an input signal to the input terminal of the first delay control circuit and the first substrate control circuit; the output terminal of the third delay control circuit is connected to the gate of NMOS transistor N1 and the input terminal of the fourth delay control circuit; the output terminal of the fourth delay control circuit and the substrate of NMOS transistor N1 are both connected to the second substrate control circuit; the signal CK is connected as an input signal to the input terminal of the third delay control circuit and the second substrate control circuit; the input signal V... IN The drain of PMOS transistor P1, the first substrate control circuit, the second substrate control circuit, and the drain of NMOS transistor N1 are connected respectively; the source of PMOS transistor P1 and the source of NMOS transistor N1 together serve as the output signal V. OUT .

[0018] Signal The CK signal and the CK signal are a pair of opposite complementary signals. Signal CP1 is generated by the first delay control circuit, and CP1 is... Signal inversion; CP1 generates signal CN2 through the second delay control circuit, and CN2 is the inversion of CP1 signal; CK generates signal CN1 through the third delay control circuit, and CN1 is the inversion of CK signal; CN1 generates signal CP2 through the fourth delay control circuit, and CP2 is the inversion of CN1 signal.

[0019] The implementation principle of this invention is as follows:

[0020] PMOS transistor P1 and NMOS transistor N1 are used as switching units; As the input signal of the first delay control circuit (delay control circuit 1), signals CP1 and CN2 are obtained through delay control circuit 1 and delay control circuit 2, wherein signal CP1 and signal CN2 are... In reverse, signal CN2 and signal In the same direction. CK serves as the input to delay control circuit 3, and through delay control circuits 3 and 4, signals CN1 and CP2 are obtained. Signal CN1 is in the opposite direction to signal CK, and signal CP2 is in the same direction as signal CK. Signals CP1 and CN1 serve as control signals for switching units P1 and N1, respectively, controlling the on and off states of transistors P1 and N1. Signal CN2 is in the same direction as signal CK. As input control signals of substrate control circuit 1, signals CP2 and CK are used to control the substrate potential of transistor P1; signals CP2 and CK are used as input control signals of substrate control circuit 2 to control the substrate potential of transistor N1.

[0021] The signal can be controlled through a delay control circuit. The dead time of signals CP1, CN2, CK, CN1, and CP2 is determined so that the substrate can follow the input signal V when P1 and N1 are turned on effectively. IN When turned off, the substrate potential of transistor P1 follows the highest potential VDD, and the substrate potential of transistor N1 follows the lowest potential VSS, effectively avoiding functional abnormalities caused by the forward bias of the internal PN junction of the transistors. Furthermore, the leakage current of the circuit can be effectively controlled by controlling the dead time of the control signal and the current-limiting structure in the substrate control circuit. And by rationally designing the substrate control circuit, the area of ​​transistors P1 and N1 can be effectively reduced, allowing the injected charges generated by P1 and N1 to cancel each other out, achieving a low injected charge effect.

[0022] like Figure 5As shown, in some preferred embodiments, the first delay control circuit includes a PMOS transistor P4 and an NMOS transistor N4; the gates of the PMOS transistor P4 and the NMOS transistor N4 together serve as the input terminals of the first delay control circuit, and the drains of the PMOS transistor P4 and the NMOS transistor N4 together serve as the output terminals of the first delay control circuit; the source and substrate of the PMOS transistor P4 are connected to the positive power supply VDD, and the source and substrate of the NMOS transistor N4 are connected to the negative power supply VSS.

[0023] The second delay control circuit includes PMOS transistor P5 and NMOS transistor N5; the third delay control circuit includes PMOS transistor P6 and NMOS transistor N6; and the fourth delay control circuit includes PMOS transistor P7 and NMOS transistor N7. Preferably, the first, second, third, and fourth delay control circuits have the same structure.

[0024] The first substrate control circuit includes a PMOS transistor P2, an NMOS transistor N2, and a first resistor R1; the gate of the NMOS transistor N2 is connected to the output terminal of the second delay control circuit, and the source of the NMOS transistor N2 and the substrate are connected to the input signal V. IN The drain of NMOS transistor N2 is connected to the substrate of PMOS transistor P1 and the drain of PMOS transistor P2; the gate of PMOS transistor P2 is connected to the input signal. The source and substrate of PMOS transistor P2 are connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the positive power supply VDD.

[0025] The second substrate control circuit includes a PMOS transistor P3, an NMOS transistor N3, and a second resistor R2; the gate of the PMOS transistor P3 is connected to the output of the fourth delay control circuit, and the source of the PMOS transistor P3 and the substrate are connected to the input signal V. IN The drain of PMOS transistor P3 is connected to the substrate of NMOS transistor N1 and the drain of NMOS transistor N3; the gate of NMOS transistor N3 is connected to the input signal CK; the source and substrate of NMOS transistor N3 are connected to one end of the second resistor R2; and the other end of the first resistor R2 is connected to the negative power supply VSS.

[0026] The specific implementation principle is as follows:

[0027] Signal CP1 is generated through P4 and N4, and CP1 is... The signal is reversed; through the above-mentioned reasonable design of P4 and N4, CP1 is made relative to... There is a certain delay to ensure that P2 is turned on before P1 is turned off, directly clamping the substrate voltage of P1 to the highest voltage VDD; because when the switch is turned off, V OUTThe potential of P1 transistor is in an indeterminate state, meaning the source of P1 transistor is in an indeterminate state and may be connected to the highest potential. The substrate of P1 transistor is an N-well. By turning on P2 before turning off P1, the potential of P1 transistor can be prevented from being affected by V. OUT The PN junction becomes forward biased when connected to the highest potential.

[0028] CP1 generates signal CN2 through P5 and N5. CN2 is the inverse of the CP1 signal. By properly designing P5 and N5, CN2 is delayed relative to CP1, ensuring that N2 is turned on only after the P1 transistor's leader has passed through. That is, P1 turns on first, and then the substrate of P1 follows the input voltage V. IN This effectively avoids forward bias of the PN junction between the P1 transistor source and the substrate, and eliminates the substrate bias effect of the P1 transistor, thus preventing the threshold voltage V caused by the substrate bias effect. THP Increasing the size of the resistor effectively reduces the circuit area under the same conditions. Simultaneously, the first resistor R1 serves as a current-limiting protection resistor; by setting this resistor, the output leakage current during circuit switching between on and off can be reduced.

[0029] CK generates signal CN1 through transistors P6 and N6, and CN1 is the inverse of the CK signal. By properly designing P6 and N6, a certain delay is created between CN1 and CK to ensure that N3 conducts before N1 turns off, directly clamping the substrate voltage of N1 to the lowest voltage VSS. This is because when the switch turns off, V... OUT The potential of N1 transistor is in an indeterminate state, meaning the source of N1 may be connected to the lowest potential. The substrate of N1 transistor is a P-type substrate. Turning on N3 before turning off N1 can prevent N1 from being turned off due to V... OUT The PN junction becomes forward biased when connected to the lowest potential.

[0030] CN1 generates signal CP2 through P7 and N7. CP2 is the inverse of the CN1 signal. By properly designing P7 and N5, CP2 is delayed relative to CN1 to ensure that N1 turns on first before P3 turns on. That is, N1 turns on first, and then the substrate of N1 follows the input voltage V. IN This structure effectively avoids forward bias of the PN junction between the source and substrate of the N1 transistor; furthermore, it eliminates the substrate bias effect of the N1 transistor, thus preventing the threshold voltage V caused by the substrate bias effect. THN Increasing the size of the resistor effectively reduces the circuit area under the same conditions. Simultaneously, the second resistor R2 serves as a current-limiting protection resistor; by setting this resistor, the output leakage current during circuit switching between on and off can be reduced.

[0031] This invention, through reasonable circuit design, can effectively reduce the size of switching transistors P1 and N1 while ensuring that P1 and N1 generate output V. OUTThe injected charge is canceled out, achieving an ultra-low injected charge level. This enables high-precision signal acquisition.

[0032] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-flatness, high-precision analog switching circuit with low injected charge, characterized in that, include: A PMOS transistor P1, an NMOS transistor N1, a first delay control circuit, a second delay control circuit, a third delay control circuit, a fourth delay control circuit, a first substrate control circuit, and a second substrate control circuit; the output of the first delay control circuit is connected to the gate of the PMOS transistor P1 and the input of the second delay control circuit; the output of the second delay control circuit and the substrate of the PMOS transistor P1 are both connected to the first substrate control circuit; signal The signal CK is connected as an input signal to the input terminal of the first delay control circuit and the first substrate control circuit; the output terminal of the third delay control circuit is connected to the gate of NMOS transistor N1 and the input terminal of the fourth delay control circuit; the output terminal of the fourth delay control circuit and the substrate of NMOS transistor N1 are both connected to the second substrate control circuit; the signal CK is connected as an input signal to the input terminal of the third delay control circuit and the second substrate control circuit; the input signal V... IN The drain of PMOS transistor P1, the first substrate control circuit, the second substrate control circuit, and the drain of NMOS transistor N1 are connected respectively; the source of PMOS transistor P1 and the source of NMOS transistor N1 together serve as the output signal V. OUT .

2. The low-flatness, high-precision analog switch circuit with low injected charge according to claim 1, characterized in that, The first delay control circuit includes a PMOS transistor P4 and an NMOS transistor N4; the gates of the PMOS transistor P4 and the NMOS transistor N4 together serve as the input terminals of the first delay control circuit, and the drains of the PMOS transistor P4 and the NMOS transistor N4 together serve as the output terminals of the first delay control circuit; the source and substrate of the PMOS transistor P4 are connected to the positive power supply VDD, and the source and substrate of the NMOS transistor N4 are connected to the negative power supply VSS.

3. A low-flatness, high-precision analog switch circuit with low injected charge according to claim 2, characterized in that, The first delay control circuit, the second delay control circuit, the third delay control circuit, and the fourth delay control circuit have the same structure.

4. The low-flatness, high-precision analog switch circuit with low injected charge according to claim 1, characterized in that, The first substrate control circuit includes a PMOS transistor P2, an NMOS transistor N2, and a first resistor R1; the gate of the NMOS transistor N2 is connected to the output terminal of the second delay control circuit, and the source of the NMOS transistor N2 and the substrate are connected to the input signal V. IN The drain of NMOS transistor N2 is connected to the substrate of PMOS transistor P1 and the drain of PMOS transistor P2; the gate of PMOS transistor P2 is connected to the input signal. The source and substrate of PMOS transistor P2 are connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the positive power supply VDD.

5. A low-flatness, high-precision analog switch circuit with low injected charge according to claim 1, characterized in that, The second substrate control circuit includes a PMOS transistor P3, an NMOS transistor N3, and a second resistor R2; the gate of the PMOS transistor P3 is connected to the output of the fourth delay control circuit, and the source of the PMOS transistor P3 and the substrate are connected to the input signal V. IN The drain of PMOS transistor P3 is connected to the substrate of NMOS transistor N1 and the drain of NMOS transistor N3; the gate of NMOS transistor N3 is connected to the input signal CK; the source and substrate of NMOS transistor N3 are connected to one end of the second resistor R2; and the other end of the second resistor R2 is connected to the negative power supply VSS.

6. A low-flatness, high-precision analog switch circuit with low injected charge according to claim 1, characterized in that, Signal The CK signal and the CK signal are a pair of opposite complementary signals. Signal CP1 is generated by the first delay control circuit, and CP1 is... Signal inversion; CP1 generates signal CN2 through the second delay control circuit, and CN2 is the inversion of CP1 signal; CK generates signal CN1 through the third delay control circuit, and CN1 is the inversion of CK signal; CN1 generates signal CP2 through the fourth delay control circuit, and CP2 is the inversion of CN1 signal.

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