High voltage analog switch circuit and control method

Abstract

A high-voltage analog switch circuit is characterized in that: the circuit comprises an analog switch unit, a switch driving unit and a switch clamping unit; wherein the analog switch unit is a CMOS high-voltage analog switch, and the gate and source of the CMOS are connected with the switch driving unit to realize the driving of the analog switch unit based on the control of the switch driving unit; the switch driving unit receives a switch control voltage and generates a control signal for the gate and source of the CMOS in the analog switch unit; the switch clamping unit is connected with the analog switch unit and the switch driving unit respectively, and is used for adjusting the gate voltage of the CMOS in cooperation with the switch driving unit. The circuit makes the number, size and other parameters of the voltage buffer tube more convenient and flexible to realize adjustment according to the use environment of the circuit, and improves the accuracy of the high-voltage analog switch output signal.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically, to a high-voltage analog switching circuit and control method. Background Technology

[0002] Currently, CMOS (Complementary Metal Oxide Semiconductor) analog switches are frequently used in various transmission circuits to achieve signal switching and transmission. Generally speaking, CMOS analog switches can turn the circuit on and off through logic control signals, so that the input signal is output from the output under the control of the switch control signal.

[0003] However, analog switches in the prior art are usually difficult to apply in high-voltage chips because the drain-source voltage and gate-source voltage that the MOSFETs in ordinary analog switches can withstand are limited.

[0004] In the existing technology, there are also circuits that use LDMOS (Laterally Diffused Metal Oxide Semiconductor) to realize high-voltage analog switches. However, since the input voltage range of such circuits is large and the power supply voltage fluctuation is also large, and the gate-source voltage difference of LDMOS transistors is limited by the characteristics of the components themselves, it is difficult to control the source and gate voltages of LDMOS transistors under normal operating conditions in analog switches to an ideal state.

[0005] Furthermore, even with precise control of the gate and source voltages of the LDMOS transistor in the analog switch, significant changes in the input voltage can still affect the output signal due to the gate-drain capacitance of the LDMOS transistor. This effect typically manifests as a downward dip at the start of a high-level output signal and an upward spike or glitches at the start of a low-level output signal. This severely compromises the integrity of the analog switch's output signal, thus degrading its performance.

[0006] To address the aforementioned problems, a new high-voltage analog switching circuit is urgently needed. Summary of the Invention

[0007] To address the shortcomings of existing technologies, the present invention aims to provide a high-voltage analog switch circuit and control method. By using a switch driving unit and a switch clamping unit to jointly control the gate voltage of the CMOS transistor in the analog switch unit, the analog switch unit can achieve synchronous output after receiving an input signal.

[0008] The present invention adopts the following technical solution.

[0009] In a first aspect, the present invention relates to a high-voltage analog switch circuit, wherein the circuit includes an analog switch unit, a switch driving unit, and a switch clamping unit; the analog switch unit is a CMOS high-voltage analog switch, and the gate and source of the CMOS are both connected to the switch driving unit to drive the analog switch unit based on the control of the switch driving unit; the switch driving unit receives a switch control voltage and generates control signals for the gate and source of the CMOS in the analog switch unit; the switch clamping unit is connected to the analog switch unit and the switch driving unit respectively, and is used to cooperate with the switch driving unit to adjust the gate voltage of the CMOS.

[0010] Preferably, the switch clamping unit includes an NMOS clamping unit and a PMOS clamping unit; wherein, the NMOS clamping unit is connected to the gate and source of the NMOS transistor in the analog switch unit and the NMOS driving unit in the switch driving unit, respectively; the PMOS clamping unit is connected to the gate and source of the PMOS transistor in the analog switch unit and the PMOS driving unit in the switch driving unit, respectively.

[0011] Preferably, the NMOS clamping unit and the PMOS clamping unit each include a current source, a first control transistor, a second control transistor, a voltage buffer transistor, a feedback transistor, and a regulating transistor; wherein, the first control transistor and the second control transistor respectively receive switch control signals to control the voltage buffer transistor and the regulating transistor; the voltage buffer transistor is used to realize high-low voltage switching between the first control transistor and the feedback transistor; the feedback transistor is used to receive the source voltage of the CMOS in the analog switching unit and control the conduction or cutoff state of the clamping unit; the regulating transistor adjusts the gate voltage of the CMOS based on the conduction or cutoff state of the clamping unit.

[0012] Preferably, the NMOS clamping unit includes a current source I1, a first control transistor Mp16, a second control transistor Mn15, voltage buffer transistors Mn13, Mn12, and Mn11, a feedback transistor Mp10, and a regulating transistor Mn14; wherein, one end of the current source I1 is connected to the power supply voltage, and the other end is connected to the source of the first control transistor Mp16, the gate of the first control transistor is connected to the first NMOS switch control signal nctrl_hv, and the drain is connected to the drain of the second control transistor Mn15, the gate and drain of the voltage buffer transistor Mn13, and the gate of the regulating transistor Mn14; the second The gate of the control transistor Mn15 is connected to the second NMOS switch control signal nsd, and its source is grounded; the source of the voltage buffer transistor Mn13 is connected to the gate and drain of the voltage buffer transistor Mn12, the source of the voltage buffer transistor Mn12 is connected to the gate and drain of the voltage buffer transistor Mn11, and the source of the voltage buffer transistor Mn11 is connected to the source of the feedback transistor Mp10; the gate of the feedback transistor Mp10 is connected to the source of the NMOS transistor in the analog switch unit, and its drain is grounded; the drain of the regulating transistor Mn14 is connected to the power supply voltage Vcc, and its source is connected to the gate of the NMOS transistor in the analog switch unit.

[0013] Preferably, when the first NMOS switch control signal nctrl_hv drives the NMOS drive unit to turn on, the regulating transistor Mn14 in the NMOS clamp unit is turned off, and the gate voltage of the NMOS transistor in the high-voltage analog switch is determined by the NMOS drive unit; when the input voltage Vin of the high-voltage analog switch is at the falling edge, the clamping voltage of the NMOS clamp unit overcomes the influence of the parasitic capacitance of the NMOS transistor in the analog switch unit and maintains the conduction state of the NMOS transistor in the analog switch unit.

[0014] Preferably, the PMOS clamping unit includes a current source I2, a first control transistor Mn16, a second control transistor Mp15, voltage buffer transistors Mp13, Mp12, and Mp11, a feedback transistor Mn10, and a regulating transistor Mp14; wherein, one end of the current source I2 is grounded, and the other end is connected to the source of the first control transistor Mn16, the gate of the first control transistor is connected to the first PMOS switch control signal pctrl_lv, and the drain is connected to the drain of the second control transistor Mp15, the gate and drain of the voltage buffer transistor Mp13, and the gate of the regulating transistor Mp14; the second control transistor Mp16... The gate of transistor 15 is connected to the second PMOS switch control signal psd, and its source is connected to the power supply voltage Vcc. The source of voltage buffer transistor Mp13 is connected to the gate and drain of voltage buffer transistor Mp12. The source of voltage buffer transistor Mp12 is connected to the gate and drain of voltage buffer transistor Mp11. The source of voltage buffer transistor Mp11 is connected to the source of feedback transistor Mn10. The gate of feedback transistor Mn10 is connected to the source of the PMOS transistor in the analog switch unit, and its drain is connected to the power supply voltage Vcc. The drain of regulating transistor Mp14 is grounded, and its source is connected to the gate of the PMOS transistor in the analog switch unit.

[0015] Preferably, when the first PMOS switch control signal pctrl_lv drives the PMOS drive unit to turn on, the regulating transistor Mp14 in the PMOS clamp unit is turned off, and the gate voltage of the PMOS transistor in the high-voltage analog switch is determined by the PMOS drive unit; when the input voltage Vin of the high-voltage analog switch is at the rising edge, the clamping voltage of the PMOS clamp unit overcomes the influence of the parasitic capacitance of the PMOS transistor in the analog switch unit and maintains the conduction state of the PMOS transistor in the analog switch unit.

[0016] Preferably, the on-state voltage drop of the voltage buffer transistor and the feedback transistor in the switch drive unit is greater than the on-state voltage drop of the voltage buffer transistor and the feedback transistor in the switch clamping unit.

[0017] Preferably, the current of the current source in the switch clamping unit is 1 / N times the current of the current source in the switch driving unit, where N is greater than 1.

[0018] In a second aspect, the present invention relates to a control method for a high-voltage analog switch circuit, wherein the control method is implemented using a high-voltage analog switch circuit as described in the first aspect of the present invention; wherein the on or off state of the CMOS in the analog switch unit is jointly controlled by a switch driving unit and a switch clamping unit.

[0019] The beneficial effects of this invention are that, compared with the prior art, the high-voltage analog switch circuit and its control method of this invention can jointly control the gate voltage of the CMOS transistor in the analog switch unit through a switch driving unit and a switch clamping unit, thereby enabling the analog switch unit to achieve synchronous output after receiving an input signal. This invention fully considers the characteristics of analog switches used in high-voltage chips and designs mutually matched switch driving units and switch clamping units, allowing for more convenient and flexible adjustment of parameters such as the number and size of voltage buffer transistors according to the circuit's operating environment, while simultaneously improving the accuracy of the high-voltage analog switch output signal. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the circuit structure of a CMOS analog switch in the prior art of this invention; Figure 2 This is a schematic diagram of the circuit structure of the analog switch unit under ideal conditions in a high-voltage analog switch circuit according to the present invention; Figure 3 This is a schematic diagram of the circuit structure of the switch driving unit in a high-voltage analog switch circuit according to the present invention; Figure 4 This is a connection diagram of a high-voltage analog switch circuit of the present invention when applied to load output; Figure 5This is a schematic diagram of the circuit structure of the analog switch unit in a high-voltage analog switch circuit under actual conditions according to the present invention; Figure 6 This is a timing diagram of the input and output signals of a high-voltage analog switch circuit of the present invention after being affected by actual conditions; Figure 7 This is a schematic diagram of the circuit structure of a switch clamping unit in a high-voltage analog switch circuit according to the present invention. Figure 8 This is a timing diagram of the input and output signals after adding a switch clamping unit to a high-voltage analog switch circuit according to the present invention. Detailed Implementation

[0021] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and should not be construed as limiting the scope of protection of the present application.

[0022] Figure 1 This is a schematic diagram of the circuit structure of a CMOS analog switch in the prior art of this invention. Figure 1 As shown, the structure of existing CMOS analog switch circuits is relatively simple. They typically use a PMOS transistor and an NMOS transistor connected in parallel with their source and drain terminals respectively to represent the input and output terminals of the analog switch. Simultaneously, the back gate of the PMOS transistor can be connected to the chip's power supply voltage Vcc, while the back gate of the NMOS transistor can be connected to ground. This allows the analog switch to perform its input / output logic when the input signal fluctuates between 0V and Vcc. Furthermore, the enable signal and its inverse signal are input to the gates of the two CMOS transistors respectively, thereby using the enable signal as logic to control the MOS transistors. However, the operating range of the gate-source voltage and drain-source voltage of ordinary PMOS and NMOS transistors is generally limited, with a maximum safe voltage of around 6V. Therefore, Figure 1 The analog switches in the circuit are often difficult to apply to high-voltage chips around 40V.

[0023] To address this problem, this invention proposes a high-voltage analog switch. Figure 2 This is a schematic diagram of the circuit structure of the analog switch unit under ideal conditions in a high-voltage analog switch according to the present invention. Figure 2 As shown, in this circuit, the high-voltage analog switch is composed of a laterally diffused MOSFET and a corresponding Zener diode.

[0024] In this switching circuit, since both the gate-drain and source-drain terminals of the laterally diffused MOSFET can withstand a voltage difference of 40V, it is well-suited for use in 40V high-voltage chips. On the other hand, since the gate-source voltage difference of the laterally diffused MOSFET is limited, excessively high voltage differences may damage the components. Therefore, in this application, a Zener diode can be connected between the gate and source terminals of all the diffused MOSFETs. When the gate-source voltage difference exceeds the reverse conduction voltage of the Zener diode, the Zener diode will conduct, thereby clamping the gate-source voltage difference within a safe range.

[0025] Figure 3 This is a schematic diagram of the circuit structure of the switch driving unit in a high-voltage analog switch according to the present invention. In order to enable this high-voltage analog switch to operate normally, the present invention provides a unit for generating switch driving signals suitable for high-voltage power supplies such as 40V, which is the switch driving unit in the present invention. Specifically, the switch driving unit includes an NMOS driving unit and a PMOS driving unit; wherein, both the NMOS driving unit and the PMOS driving unit include a current source, a switch control transistor, a source control transistor, a gate control transistor, a feedback transistor, and a voltage buffer transistor.

[0026] In this invention, the NMOS driving unit and the PMOS driving unit are used to control the gate and source voltages of the NMOS transistor and the PMOS transistor in the analog switching unit, respectively, so that the gate and source voltages of the NMOS transistor and the PMOS transistor can meet the requirements for normal operation of the analog switching unit.

[0027] In this driving unit, a current source provides appropriate current to multiple MOSFETs, resulting in suitable voltage drops during operation. The gate of the switch control transistor is responsible for acquiring the switch control signal, which, under the logic of the switch control signal, controls the gate and source voltages of the MOSFETs in the analog switching unit.

[0028] In addition, source control transistors and gate control transistors specifically refer to components that control the source and gate voltages of MOSFETs in the analog switching unit, thereby further controlling the state of the MOSFETs in the analog switching unit. The drain or source of these two control transistors can be connected to ground or power supply voltage, so that when the analog switching unit needs to be turned off, Mn1, Mn2, Mp1, and Mp2 are completely turned off through the control of the nsd and psd signals.

[0029] It is understandable that the specific connection method of the NMOS drive unit is as follows: Figure 3As described above, when the current source outputs current In, Mp7 is turned on under the control of the high switching control voltage nctrl_hv, causing current to flow through Mn6, Mn5, Mn4, and Mp3 respectively, generating corresponding voltage drops. The drain voltage of Mp7 serves as the gate voltage of the NMOS transistor in the analog switching unit. With control transistors Mn8 and Mn9 both off, Mn1 is turned on, causing the source voltages of Mn1 and Mn2 to change with the input voltage Vin. In other words, the gate voltage of Mp3 is equal to the input voltage Vin at this time. The gate voltages of Mn1 and Mn2 will then be increased by the voltage drops of Mp3, Mn4, Mn5, and Mn6 on top of the input voltage Vin. If the input voltage Vin is low, the sum of the voltage drops of Mp3, Mn4, Mn5, and Mn6 under normal operating conditions exceeds the threshold turn-on voltage of the NMOS transistor in the analog switching unit, allowing the NMOS transistor to be turned on, thus achieving the output of the high-voltage analog switch. If the input voltage Vin is high, Mp3 will be in the off state. At this time, the gate voltages of Mn1 and Mn2 will gradually increase to equal Vcc under the influence of the current source In. If the difference between Vcc and Vin is greater than the threshold turn-on voltage of the NMOS transistor in the analog switching unit, the NMOS transistor can still be turned on, realizing the output of the high-voltage analog switch. However, if the difference between Vcc and Vin is less than the threshold turn-on voltage of the NMOS transistor in the analog switching unit, the NMOS transistor cannot be turned on. Under this logic, Mn1 and Mn2 achieve conduction when Vin is low and turn-off when Vin is too high.

[0030] Additionally, if the circuit intends the analog switching unit to be completely off, the control signal nsd can be raised under the control of the timing circuit to turn on Mn8 and Mn9, thereby pulling down the gate and source voltages of Mn1 and Mn2 to 0V, thus ensuring that Mn1 and Mn2 are fully turned off.

[0031] On the other hand, the structure of the PMOS driver unit is very similar to that of the NMOS driver unit, except that the control transistor is connected to the power supply voltage, and the magnitudes of the control signals pctrl_lv and psd are different. Similarly, when the pctrl_lv signal controls Mn7 to conduct, the current from the current source Ip will sequentially pass through Mp6, Mp5, Mp4, and Mn3, resulting in a certain voltage drop. Since the drain voltage of Mp6 is low, Mp1 and Mp2 are in the conducting state, so the source voltages of Mp1 and Mp2 remain equal to the input voltage. In this case, the gate voltage of Mn3 is equal to the input voltage Vin. Controlled by Vin, Mn3 is turned on or off. When Vin is large and Mn3 is on, the voltage drops generated by Mn3, Mp4, Mp5, and Mp6, together with Vin, determine the magnitude of the gate voltage Vgp of Mp1 and Mp2. By properly setting the parameters of the current source Ip and Mn3, Mp4, Mp5, and Mp6, their total voltage drop is made higher than the threshold turn-on voltage of Mp1 and Mp2, thus ensuring that Mp1 and Mp2 are on when Mn3 is on. Similarly, if Vin is small, Mn3 may be in the off state. In this case, Vgp drops to 0V. As long as the voltage difference between Vin and ground is still greater than the threshold turn-on voltage of Mp1 and Mp2, Mp1 and Mp2 can still conduct. However, if Vin drops to a point where the difference between Vin and ground is less than the threshold turn-on voltage of Mp1 and Mp2, the PMOS transistor in the analog switching unit will be turned off.

[0032] It should be noted that the voltage difference between the high switching control voltage nctrl_hv and the PMOS control signal psd and the power supply voltage Vcc is less than the voltage of the sub-regulation unit in the circuit, which is 5.5V in one embodiment; the low switching control voltage pctrl_lv and the NMOS control signal nsd are also less than 5.5V.

[0033] In this invention, in order for the analog switch to output signals according to the logic described above, Mp7 and Mn7 need to be in a continuously on state, while Mn8, Mn9, Mp8, and Mp9 need to be in a continuously off state. The magnitudes of the control signals nctrl_hv, psd, pctrl_lv, and nsd can be jointly implemented using a sub-regulation unit and logic gates. In one embodiment of this invention, the output voltage of the sub-regulation unit is 5.5V, therefore the control signals can easily be implemented as 5.5V or Vcc-5.5V.

[0034] It should be noted that when the switch control transistor Mp7 is turned on, the sum of the voltage drop across the feedback transistor and the voltage drop across the voltage buffer transistor can be set to be greater than the threshold turn-on voltage of the NMOS transistor in the analog switch unit. When the switch transistor Mn7 is turned on, the sum of the voltage drop across the feedback transistor and the voltage drop across the voltage buffer transistor is set to be greater than the threshold turn-on voltage of the PMOS transistor in the analog switch unit.

[0035] As mentioned above, in order to ensure that the CMOS transistor is in a fully conducting state, the present invention should consider the sum of the voltage drops of the feedback transistor and the voltage buffer transistor, that is, the gate-source voltage difference of the CMOS transistor in the analog switching unit can reach the threshold turn-on voltage of the CMOS transistor.

[0036] Meanwhile, the threshold turn-on voltages of NMOS transistors Mn1 and Mn2 and PMOS transistors Mp1 and Mp2 in the analog switching unit are equal; the size and number of feedback transistors in the NMOS driving unit and PMOS driving unit are equal; the size and number of voltage buffer transistors in the NMOS driving unit and PMOS driving unit are equal; the sum of the voltage drop of the feedback transistor and the voltage drop of the voltage buffer transistor is less than the gate-source threshold voltage of the CMOS transistor.

[0037] It is understood that in this invention, in order to make the CMOS analog switching unit and its driving unit symmetrical, and also to simplify the design of the chip and circuit, the size and number of the two feedback transistors are made to be exactly the same. Similarly, the relevant parameters of the multiple voltage buffer transistors are also exactly the same.

[0038] In addition, in order to prevent the gate-source voltage difference of the CMOS transistor in the analog switch unit from being too high, which would prevent the MOS transistor in the analog switch from working properly, the above-mentioned voltage drop and the gate-source voltage of the CMOS transistor are set to be less than the maximum allowable gate-source voltage of the CMOS transistor. In this invention, this is referred to as the gate-source threshold voltage.

[0039] In one embodiment of the present invention, the power supply voltage is 40V, and the reverse breakdown voltage of the Zener diode is 5.5V. Furthermore, according to typical high-voltage chips, the regulation voltage generated by the chip's sub-regulation unit is set to 3V or 5V. Therefore, if the switch is to be in the on state, nctrl_hv can be set to Vcc-Vsub, where Vsub is the sub-regulation voltage. Additionally, pctrl_lv can be set to Vsub, and the voltages of the psd and nsd signals are the power supply voltage and ground voltage, respectively. If the switch is to be in the off state, nctrl_hv can be set to Vcc, pctrl_lv to 0V, psd to Vcc-Vsub, and nsd to Vsub. It can be understood that under the control of these signals, Mp7 and Mn7 in the switch driver unit are in the off state, while Mn8, Mn9, Mp8, and Mp9 are in the on state, thereby completely cutting off all CMOS transistors in the analog switch unit. At this point, regardless of the value of Vin, the analog switching unit will not generate an output signal Vout under the control of the four control signals.

[0040] Figure 4 This is a connection diagram of a high-voltage analog switch of the present invention applied to load output. Figure 4As shown, the high-voltage analog switch in this invention is the part labeled "switch" in the figure. Its input signal is In, and its output signal is Out. The subsequent stage of this switch is connected to resistor R. L Up, and through resistor R L Then it is connected to the load end. In this application, it is assumed that the power supply range of the load is about Vcc / 2.

[0041] Figure 5 This is a schematic diagram of the circuit structure of the analog switch unit in a real-world scenario within a high-voltage analog switch according to the present invention. (See diagram below.) Figure 5 As shown, in practice, based on the existing manufacturing process of CMOS transistors, parasitic capacitance will inevitably exist between the gate and drain of the transistor. When the input signal remains unchanged, and after a period of time the input signal is at a stable voltage, the parasitic capacitance will not affect the performance of the CMOS transistor. However, if the input signal continuously switches between high and low levels, it may significantly impact the output performance of the CMOS transistor.

[0042] Specifically, when Vin = 0V, because the chip's lowest voltage level is 0V, the gates of PMOS transistors Mp1 and Mp2 are at 0V, and the voltage drop across Cgd_p is 0V. When the input signal is at its rising edge, in the extreme case where Vin jumps from 0V to 40V, the voltage difference between the two plates of the parasitic capacitance Cgd_p does not have time to change and remains at 0V. At this time, as Vin increases, due to the effect of Cgd_p, ... Figure 5 The voltage Vgp in the circuit is exactly equal to Vin, thus keeping Mp1 and Mp2 in the off state. When the PMOS drive unit is turned on, Vgp needs to go through the discharge process of the parasitic capacitance Cgd_p before it can slowly decrease to the voltage that turns Mp1 and Mp2 on. Therefore, the output signals generated by Mp1 and Mp2 have a certain delay.

[0043] Similarly, when the input signal is at a falling edge, for example when Vin jumps from 40V to 0V, the voltage difference between the two plates of the parasitic capacitor Cgd_n does not have time to change. Therefore, the voltage drop of Vgn cannot respond instantaneously to the voltage change in the NMOS drive unit. As a result, Cgd_n is charged during this process, which causes a certain delay in the output signal. Figure 6 This is a timing diagram of the input and output signals of a high-voltage analog switch according to the present invention after being affected by actual conditions. Figure 6 As shown, the aforementioned delay causes a certain change in the signal waveform. On the rising edge, due to the instantaneous conduction of the PMOS drive unit, Vgp rises instantaneously, which has a certain impact on the actual conduction state of Mp1. Therefore, a waveform dip is observed in the output signal.

[0044] On the other hand, at the falling edge, due to the instantaneous conduction of the NMOS drive unit, Vgn will drop instantaneously, which will also affect the conduction of Mn1 and Mn2, resulting in a spike-shaped protrusion in the output signal.

[0045] Figure 7 This is a schematic diagram of the circuit structure of a switch clamping unit in a high-voltage analog switch circuit according to the present invention. Figure 7 As shown, to solve the above problems, a high-voltage analog switch circuit is added in this invention. Specifically, the circuit includes an analog switch unit, a switch driving unit, and a switch clamping unit. The analog switch unit is a CMOS high-voltage analog switch, and the gate and source of the CMOS are both connected to the switch driving unit to drive the analog switch unit based on the control of the switch driving unit. The switch driving unit receives the switch control voltage and generates control signals for the gate and source of the CMOS in the analog switch unit. The switch clamping unit is connected to both the analog switch unit and the switch driving unit and is used to cooperate with the switch driving unit to adjust the gate voltage of the CMOS.

[0046] The circuit structures and operating principles of the analog switching unit and switch driving unit described here are exactly the same as those of the corresponding circuit units described above. Even with the addition of the switch clamping unit, the circuit can only allow the switch clamping unit to control the regulation of the CMOS transistor gate voltage for a short period of time. However, for most of the time, the CMOS transistor gate voltage is still regulated and controlled by the switch driving unit.

[0047] Preferably, the switch clamping unit includes an NMOS clamping unit and a PMOS clamping unit; wherein, the NMOS clamping unit is connected to the gate and source of the NMOS transistor in the analog switch unit and the NMOS driving unit in the switch driving unit, respectively; the PMOS clamping unit is connected to the gate and source of the PMOS transistor in the analog switch unit and the PMOS driving unit in the switch driving unit, respectively.

[0048] In this invention, the switch driving unit is divided into two driving units: NMOS and PMOS. Similarly, the switch clamping unit clamps the gate voltages of the NMOS and PMOS in the CMOS transistor respectively through the NMOS clamping unit and the PMOS clamping unit.

[0049] Preferably, the NMOS clamping unit and the PMOS clamping unit each include a current source, a first control transistor, a second control transistor, a voltage buffer transistor, a feedback transistor, and a regulating transistor; wherein, the first control transistor and the second control transistor respectively receive switch control signals to control the voltage buffer transistor and the regulating transistor; the voltage buffer transistor is used to realize high-low voltage switching between the first control transistor and the feedback transistor; the feedback transistor is used to receive the source voltage of the CMOS in the analog switching unit and control the conduction or cutoff state of the clamping unit; the regulating transistor adjusts the gate voltage of the CMOS based on the conduction or cutoff state of the clamping unit.

[0050] The clamping unit in this invention mainly includes CMOS transistors. To achieve matching with high-voltage circuits or high-voltage chips, the CMOS transistors in the clamping unit of this invention are all LDMOS transistors. In addition, the clamping unit also includes a current source to further control the current when the MOS transistors are turned on, thereby keeping the voltage drop of multiple transistors within a reasonable range.

[0051] Preferably, the NMOS clamping unit includes a current source I1, a first control transistor Mp16, a second control transistor Mn15, voltage buffer transistors Mn13, Mn12, and Mn11, a feedback transistor Mp10, and a regulating transistor Mn14; wherein, one end of the current source I1 is connected to the power supply voltage, and the other end is connected to the source of the first control transistor Mp16, the gate of the first control transistor is connected to the first NMOS switch control signal nctrl_hv, and the drain is connected to the drain of the second control transistor Mn15, the gate and drain of the voltage buffer transistor Mn13, and the gate of the regulating transistor Mn14; the second The gate of the control transistor Mn15 is connected to the second NMOS switch control signal nsd, and its source is grounded; the source of the voltage buffer transistor Mn13 is connected to the gate and drain of the voltage buffer transistor Mn12, the source of the voltage buffer transistor Mn12 is connected to the gate and drain of the voltage buffer transistor Mn11, and the source of the voltage buffer transistor Mn11 is connected to the source of the feedback transistor Mp10; the gate of the feedback transistor Mp10 is connected to the source of the NMOS transistor in the analog switch unit, and its drain is grounded; the drain of the regulating transistor Mn14 is connected to the power supply voltage Vcc, and its source is connected to the gate of the NMOS transistor in the analog switch unit.

[0052] It is understood that the structure of the NMOS clamping unit in this invention is partially similar to that of the NMOS driving unit. For example, the connection methods of the current source I1, control transistor Mp16, voltage buffer transistors Mn13, Mn12, Mn11, and feedback transistor Mp10 are very similar to those in the NMOS driving unit. Furthermore, the gate voltages of control transistors Mp16 and Mp7 are both the first NMOS switch control signal nctrl_hv, and the gate voltages of feedback transistors Mp10 and Mp3 are both the source voltages of the NMOS transistors in the analog switching unit. In other words, under the influence of the control signal and the input voltage, their on and off states are similar.

[0053] In addition, a second control transistor Mn15 is added to the NMOS clamping unit. This transistor is turned on and off based on the second NMOS switch control signal nsd. Therefore, when the analog switch needs to be turned off, in addition to Mn8, Mn9, Mp8 and Mp9 in the NMOS drive unit and PMOS drive unit turning off the analog switch, Mn15 will also turn off the corresponding circuit in the switch clamping unit, thereby pulling Vgn1 low to ground level. Therefore, when the analog switch is turned off, Mn14 is cut off, and similarly, Mp14 is also cut off, which will not affect the off state of the analog switch. Preferably, when the input voltage Vin of the high-voltage analog switch is a DC level or a slowly changing AC signal, the NMOS driving unit is turned on and the NMOS clamping unit is turned off, and the gate voltage of the NMOS transistor in the high-voltage analog switch is determined by the NMOS driving unit; when the input voltage Vin of the high-voltage analog switch is at the falling edge, the clamping voltage of the NMOS clamping unit overcomes the influence of the parasitic capacitance of the NMOS transistor in the analog switch unit and maintains the conduction state of the NMOS transistor in the analog switch unit.

[0054] It is understood that in this invention, the waveform of the input voltage Vin of the high-voltage analog switch can be a rapidly changing square wave signal. Because a clamping unit is added to the circuit, the state switching is achieved based on the clamping voltage within the clamping unit.

[0055] Taking an input voltage Vin=0V as an example, the circuit's operating state when the input voltage is lower than the clamping voltage will be explained. At this time, the NMOS drive unit will be in the on state. In this invention, the Vgn1 of the NMOS clamping unit can be designed to be slightly lower than Vgn, thus the regulating transistor Mn14 is cut off. Therefore, the Vgn output by the NMOS drive unit can fully control the state of the NMOS transistor in the analog switching unit, and the circuit's operating state remains as described above.

[0056] However, when the input voltage is high, such as around 40V, Vcc is also 40V, the NMOS drive unit will be cut off, and Mp3 will also be in the cut-off state. Vgn will be pulled high to Vcc by the current source In. Since the voltage difference between Vgn and Vin is 0V, the NMOS transistor in the analog switch unit will not be turned on under the control of this voltage.

[0057] However, when the input voltage Vin of the analog switching unit is at its falling edge, rapidly dropping from, for example, 40V to 0V, the NMOS drive unit may not have enough time to start, or even if it does start, it may still be difficult to rise due to the parasitic gate-drain capacitance of the Mn1 transistor. In this case, due to the addition of the NMOS clamping unit, and because the clamping unit is not affected by the parasitic gate-drain capacitance of the Mn1 transistor, Vgn1 will always remain at... At this voltage, Vgn1 will promptly suppress the voltage drop of the parasitic capacitance on the gate side, thereby clamping Vgn at Vgn1 –V th-Mn14 At this point, the component parameters should be designed appropriately, ensuring that the value of Vgn is sufficient to keep Mn1 continuously conducting. In this way, the circuit prevents glitches in the output voltage waveform output by Mn1 during the falling edge.

[0058] Preferably, the PMOS clamping unit includes a current source I2, a first control transistor Mn16, a second control transistor Mp15, voltage buffer transistors Mp13, Mp12, and Mp11, a feedback transistor Mn10, and a regulating transistor Mp14; wherein, one end of the current source I2 is grounded, and the other end is connected to the source of the first control transistor Mn16, the gate of the first control transistor is connected to the first PMOS switch control signal pctrl_lv, and the drain is connected to the drain of the second control transistor Mp15, the gate and drain of the voltage buffer transistor Mp13, and the gate of the regulating transistor Mp14; the second control transistor Mp16... The gate of transistor 15 is connected to the second PMOS switch control signal psd, and its source is connected to the power supply voltage Vcc. The source of voltage buffer transistor Mp13 is connected to the gate and drain of voltage buffer transistor Mp12. The source of voltage buffer transistor Mp12 is connected to the gate and drain of voltage buffer transistor Mp11. The source of voltage buffer transistor Mp11 is connected to the source of feedback transistor Mn10. The gate of feedback transistor Mn10 is connected to the source of the PMOS transistor in the analog switch unit, and its drain is connected to the power supply voltage Vcc. The drain of regulating transistor Mp14 is grounded, and its source is connected to the gate of the PMOS transistor in the analog switch unit.

[0059] Using a similar approach, the present invention forms a PMOS clamping unit in a relatively symmetrical manner.

[0060] Preferably, when the first PMOS switch control signal pctrl_lv drives the PMOS drive unit to turn on, the gate voltage of the PMOS transistor in the high-voltage analog switch is determined by the PMOS drive unit.

[0061] The principles of the PMOS driving unit and PMOS clamping unit in this invention are similar to those of the NMOS driving unit and NMOS clamping unit, so they will not be described in detail.

[0062] It should be noted that during the rapid transition from a low to a high input voltage, the rapid increase in input voltage will cause both the PMOS drive unit and the PMOS clamp unit to conduct simultaneously. This conduction may take some time, and if the conduction is insufficient, the Vgp value generated by the PMOS drive unit may still be relatively high, and will become even higher due to the parasitic capacitance of Mp1.

[0063] With the addition of the PMOS clamping unit in this invention, before the rising edge, the PMOS clamping unit clamps Vgp1 to near max(Vin - Vgs_Mn10 - Vsg_Mp11 - Vsg_Mp12 - Vsg_Mp13, 0V). This voltage is relatively small, and even if the parasitic capacitance causes the PMOS gate voltage to rise, it will not rise to the point where Mp1 is turned off. Thus, Mp1 remains fully on during the rising edge, preventing waveform sag in the output signal. Preferably, the on-state voltage drop of the voltage buffer and feedback transistor in the switch drive unit is greater than the on-state voltage drop of the voltage buffer and feedback transistor in the switch clamping unit.

[0064] It should be noted that this configuration allows the voltage drop of the clamping unit to remain smaller, so the gate voltage of the CMOS transistor output by the clamping unit will not actually act on the analog switching unit, thus enabling the switching drive unit to accurately control the state of the CMOS transistor.

[0065] Preferably, the current of the current source in the switch clamping unit is 1 / N times the current of the current source in the switch driving unit, where N is greater than 1.

[0066] To achieve a larger voltage drop across the transistor in the drive unit and a smaller voltage drop across the transistor in the clamping unit, the output current of the current source in the clamping unit can be relatively smaller. In one embodiment of the invention, N=10 is set. In this way, the clamping unit can fully control the voltage drop across the transistor on the rising and falling edges, but will not affect the drive unit when it is turned on.

[0067] The method of this invention avoids changes to the parameters of other components by reasonably setting the current source multiplier. For example, all MOS transistors in the driving unit and all MOS transistors in the clamping unit of this invention can be exactly the same size, and can be manufactured on a single chip using the same method.

[0068] Figure 8 This is a timing diagram of the input and output signals after adding a switch clamping unit to a high-voltage analog switch circuit according to the present invention. Figure 8 As shown, under the action of the clamping unit of the present invention, the accuracy of the output signal is greatly improved, and the glitches and depressions of the waveform are effectively eliminated.

[0069] In a second aspect, the present invention provides a control method for a high-voltage analog switch circuit. This method is implemented using a high-voltage analog switch circuit as described in the first aspect of the present invention, and the on or off state of the CMOS in the analog switch unit is jointly controlled by the switch driving unit and the switch clamping unit.

[0070] The beneficial effects of this invention are that, compared with the prior art, the high-voltage analog switch circuit and its control method of this invention can jointly control the gate voltage of the CMOS transistor in the analog switch unit through a switch driving unit and a switch clamping unit, thereby enabling the analog switch unit to achieve synchronous output after receiving an input signal. This invention fully considers the characteristics of analog switches used in high-voltage chips and designs mutually matched switch driving units and switch clamping units, allowing for more convenient and flexible adjustment of parameters such as the number and size of voltage buffer transistors according to the circuit's operating environment, while simultaneously improving the accuracy of the high-voltage analog switch output signal.

[0071] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.

Claims

1. A high-voltage analog switch circuit, characterized in that: The circuit includes an analog switch unit, a switch driving unit, and a switch clamping unit; The analog switch unit is a CMOS high-voltage analog switch, and the gate and source of the CMOS are both connected to the switch driving unit so as to drive the analog switch unit based on the control of the switch driving unit. The switch driving unit receives the switch control voltage and generates control signals for the gate and source of the CMOS in the analog switch unit. The switch clamping unit includes an NMOS clamping unit and a PMOS clamping unit. The NMOS clamping unit is connected to the gate and source of the NMOS transistor in the analog switch unit and the NMOS driving unit in the switch driving unit, respectively. The PMOS clamping unit is connected to the gate and source of the PMOS transistor in the analog switch unit and the PMOS driving unit in the switch driving unit, respectively, thereby cooperating with the switch driving unit to adjust the gate voltage of the CMOS. Each NMOS clamping unit and PMOS clamping unit includes a current source, a first control transistor, a second control transistor, a voltage buffer transistor, a feedback transistor, and an adjustment transistor. The first and second control transistors receive switch control signals to control the voltage buffer transistor and the adjustment transistor, respectively. The voltage buffer transistor is used to switch between high and low voltages between the first control transistor and the feedback transistor. The feedback transistor receives the source voltage of the CMOS in the analog switch unit and controls the on or off state of the clamping unit. The adjustment transistor adjusts the gate voltage of the CMOS based on the on or off state of the clamping unit.

2. The high-voltage analog switch circuit according to claim 1, characterized in that: The NMOS clamping unit includes a current source I1, a first control transistor Mp16, a second control transistor Mn15, voltage buffer transistors Mn13, Mn12, and Mn11, a feedback transistor Mp10, and a regulating transistor Mn14; wherein... One end of the current source I1 is connected to the power supply voltage, and the other end is connected to the source of the first control transistor Mp16. The gate of the first control transistor is connected to the first NMOS switch control signal nctrl_hv, and the drain is connected to the drain of the second control transistor Mn15, the gate and drain of the voltage buffer transistor Mn13, and the gate of the regulating transistor Mn14. The gate of the second control transistor Mn15 is connected to the second NMOS switch control signal nsd, and the source is grounded; The source of the voltage buffer transistor Mn13 is connected to the gate and drain of the voltage buffer transistor Mn12, the source of the voltage buffer transistor Mn12 is connected to the gate and drain of the voltage buffer transistor Mn11, and the source of the voltage buffer transistor Mn11 is connected to the source of the feedback transistor Mp10. The gate of the feedback transistor Mp10 is connected to the source of the NMOS transistor in the analog switching unit, and the drain is grounded. The drain of the regulating transistor Mn14 is connected to the power supply voltage Vcc, and the source is connected to the gate of the NMOS transistor in the analog switching unit.

3. A high-voltage analog switch circuit according to claim 2, characterized in that: When the first NMOS switch control signal nctrl_hv drives the NMOS drive unit to turn on, the regulating transistor Mn14 in the NMOS clamp unit is turned off, and the gate voltage of the NMOS transistor in the high-voltage analog switch is determined by the NMOS drive unit. When the input voltage Vin of the high-voltage analog switch is at the falling edge, the clamping voltage of the NMOS clamping unit overcomes the influence of the parasitic capacitance of the NMOS transistor in the analog switch unit and maintains the conduction state of the NMOS transistor in the analog switch unit.

4. The high-voltage analog switch circuit according to claim 1, characterized in that: The PMOS clamping unit includes a current source I2, a first control transistor Mn16, a second control transistor Mp15, voltage buffer transistors Mp13, Mp12, and Mp11, a feedback transistor Mn10, and a regulating transistor Mp14; wherein... One end of the current source I2 is grounded, and the other end is connected to the source of the first control transistor Mn16. The gate of the first control transistor is connected to the first PMOS switch control signal pctrl_lv, and the drain is connected to the drain of the second control transistor Mp15, the gate and drain of the voltage buffer transistor Mp13, and the gate of the regulating transistor Mp14. The gate of the second control transistor Mp15 is connected to the second PMOS switch control signal psd, and the source is connected to the power supply voltage Vcc. The source of the voltage buffer transistor Mp13 is connected to the gate and drain of the voltage buffer transistor Mp12, the source of the voltage buffer transistor Mp12 is connected to the gate and drain of the voltage buffer transistor Mp11, and the source of the voltage buffer transistor Mp11 is connected to the source of the feedback transistor Mn10. The gate of the feedback transistor Mn10 is connected to the source of the PMOS transistor in the analog switching unit, and the drain is connected to the power supply voltage Vcc. The drain of the regulating transistor Mp14 is grounded, and its source is connected to the gate of the PMOS transistor in the analog switching unit.

5. A high-voltage analog switch circuit according to claim 4, characterized in that: When the first PMOS switch control signal pctrl_lv drives the PMOS drive unit to turn on, the regulating transistor Mp14 in the PMOS clamp unit is turned off, and the gate voltage of the PMOS transistor in the high voltage analog switch is determined by the PMOS drive unit. When the input voltage Vin of the high-voltage analog switch is at the rising edge, the clamping voltage of the PMOS clamping unit overcomes the influence of the parasitic capacitance of the PMOS transistor in the analog switch unit and maintains the conduction state of the PMOS transistor in the analog switch unit.

6. A high-voltage analog switch circuit according to claim 1, characterized in that: The on-state voltage drop of the voltage buffer transistor and the feedback transistor in the switch driving unit is greater than the on-state voltage drop of the voltage buffer transistor and the feedback transistor in the switch clamping unit.

7. A high-voltage analog switch circuit according to claim 1, characterized in that: The current of the current source in the switch clamping unit is 1 / N times the current of the current source in the switch driving unit, where N is greater than 1.

8. A control method for a high-voltage analog switch circuit, characterized in that: The control method is implemented using a high-voltage analog switch circuit as described in any one of claims 1-7; The on or off state of the CMOS in the analog switch unit is controlled jointly by the switch driving unit and the switch clamping unit.

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