Asynchronous clock SAR analog-to-digital converter and analog-to-digital conversion method

Abstract

This invention provides an asynchronous clock SAR analog-to-digital converter (ADC) and a method for ADC conversion. The asynchronous clock SAR ADC includes: a sample-and-hold circuit, a digital-to-analog converter array, a voltage comparator, a SAR controller, a metastability detection module, and a metastability correction module. The metastability detection module, connected to the SAR controller, receives and compares the asynchronous digital signal and a synchronous digital signal to generate a metastability flag. The metastability correction module, connected to the metastability detection module, receives the synchronous digital signal and the metastability flag, corrects the synchronous digital signal based on the metastability flag, and generates the final digital signal output. This invention's asynchronous clock SAR ADC and method, through the metastability detection module, can detect and locate the metastability of the voltage comparator during the comparison process, and through the metastability correction module, corrects the conversion result, thus improving the accuracy of the conversion result.

Description

Technical Field

[0001] This invention relates to the field of circuit design technology, and in particular to an asynchronous clock SAR analog-to-digital converter and an analog-to-digital conversion method. Background Technology

[0002] Successive Approximation Register (SAR) analog-to-digital converters have attracted widespread attention due to their simple analog structure, moderate conversion accuracy and speed, and low power consumption. Their main structure includes: a sample-and-hold circuit (S / H), a digital-to-analog converter array (DAC), a comparator, a SAR controller, and a clock controller. Following the principle of binary division (like a balance scale), the sampled and held analog signal is compared multiple times with different voltages output by the DAC array. The result of each comparison determines the next DAC output voltage to be compared, gradually approximating the input analog signal. The comparison is performed by the comparator. The SAR controller receives and records (using a flip-flop or latch) the current comparison result and generates the digital signal corresponding to the next DAC output voltage. The clock controller controls the sampling and conversion comparison process. When all comparisons are complete, the comparator output recorded by the SAR controller is the final digital output.

[0003] Synchronous clock SAR analog-to-digital converters (ADCs) use a consistent comparison time, typically one comparison clock cycle, to accommodate the setup time of the digital-to-analog converter array, comparator setup time, and related logic delays. Since different comparison stages require different delays, synchronous clock SAR ADCs introduce unnecessary delays by providing a fixed comparison time, thus limiting the converter's speed. Asynchronous clock SAR ADCs, through asynchronous control logic (usually monitoring whether the comparator has completed the comparison), can configure different delays to meet the requirements at different comparison stages, instead of a fixed comparison clock cycle, significantly improving the conversion speed. The size of the comparator input affects the comparator's setup time; the smaller the input, the longer the setup time. When the comparator input is very small, it takes a long time for the comparator to establish a valid logic output, indicating metastability.

[0004] For synchronous clock SAR analog-to-digital converters (ADCs), comparator metastability may cause triggers in the SAR controller to be in a metastable state, leading to errors in the current conversion result (often not causing errors in the final conversion result; the comparison result in the metastable state being 0 or 1 is not important, and the final result will approximate it again in the subsequent comparison process). It may even cause metastability in the updated digital input signal of the ADC array, compressing the comparison time of the next comparison (causing errors in the final conversion result, but with a low probability). For asynchronous clock SAR ADCs, comparator metastability lengthens the current comparison stage, further compressing the remaining comparison stage time, resulting in the inability to complete all comparison results within the specified conversion cycle, thus causing errors in the final conversion result. Compared to synchronous clock SAR ADCs, comparator metastability has a greater impact on high-speed asynchronous clock SAR ADCs. Summary of the Invention

[0005] Based on the aforementioned deficiencies in the prior art, the purpose of this invention is to provide an asynchronous clock SAR analog-to-digital converter and analog-to-digital conversion method with more accurate conversion results.

[0006] To achieve the above objectives, the present invention provides an asynchronous clock SAR analog-to-digital converter, comprising: The sample-and-hold circuit samples and holds the analog input signal and provides an analog voltage; A digital-to-analog converter array provides a reference voltage; A voltage comparator, connected to both the sample-and-hold circuit and the digital-to-analog converter array, receives the analog voltage provided by the sample-and-hold circuit and the reference voltage provided by the digital-to-analog converter array, compares the analog voltage and the reference voltage, and outputs a positive-phase comparison signal and an inverted-phase comparison signal that are opposite to each other. The SAR controller is connected to both the voltage comparator and the digital-to-analog converter array. It receives the positive phase comparison signal output by the voltage comparator, generates and stores asynchronous digital signals and synchronous digital signals, and sends the asynchronous digital signals to the digital-to-analog converter array to generate the reference voltage. A metastable state detection module, connected to the SAR controller, receives and compares the asynchronous digital signal and the synchronous digital signal to generate a metastable state flag. The metastable correction module, connected to the metastable detection module, receives the synchronous digital signal and the metastable flag, corrects the synchronous digital signal according to the metastable flag, and generates the final digital signal output.

[0007] In one embodiment, the analog-to-digital converter further includes: The effective detection module is connected to the voltage comparator, receives the positive comparison signal and the negative comparison signal, determines whether the output of the voltage comparator has reached an effective level, and generates a voltage comparison effective signal. A clock controller, connected to the effective detection module and the SAR controller, receives the voltage comparison effective signal, generates an asynchronous SAR control clock and a synchronous SAR control clock, and sends them to the SAR controller. The SAR controller updates the asynchronous digital signal and the synchronous digital signal under the asynchronous SAR control clock and the synchronous SAR control clock, respectively.

[0008] In one embodiment, the SAR controller includes a data latch, a first data trigger, and a SAR logic module connected to both the data latch and the first data trigger. The SAR logic module is connected to both the voltage comparator and the clock controller, receives a positive phase comparison signal output by the voltage comparator and a SAR control synchronization clock provided by the clock controller, and generates a digital signal under the SAR control synchronization clock. The first data trigger is connected to the clock controller, receives the SAR control synchronization clock provided by the clock controller, and saves the digital signal as a synchronous digital signal under the SAR control synchronization clock. The latch is connected to both the clock controller and the digital-to-analog converter array, receives an asynchronous SAR control clock provided by the clock controller, saves the digital signal as an asynchronous digital signal under the SAR control synchronization clock, and sends it to the digital-to-analog converter array.

[0009] In one embodiment, the metastability detection module includes: a second data trigger, a third data trigger, and a data comparator connected to both the second and third data triggers; the second data trigger is connected to the data latch and receives the asynchronous digital signal; the third data trigger is connected to the first data trigger and the metastability correction module, receives the synchronous digital signal, and outputs the synchronous digital signal to the metastability correction module; the data comparator compares whether the asynchronous digital signal and the synchronous digital signal are consistent, and if they are inconsistent, it outputs the metastability flag.

[0010] In one embodiment, the clock controller is connected to the sample-and-hold circuit, the voltage comparator, the metastability detection module, and the metastability correction module. The clock controller receives the system clock input, generates a sampling clock and sends it to the sample-and-hold circuit, generates a voltage comparison enable signal and a voltage comparison clock and sends them to the voltage comparator, generates a metastability detection clock and sends it to the metastability detection module, and also sends the SAR control synchronization clock to the metastability correction module. The metastability detection clock is out of phase with the SAR controller synchronization clock. The SAR control synchronization clock is synchronized with the system clock and is later than the SAR control asynchronous clock. The SAR control asynchronous clock is generated by ANDing the voltage comparison valid signal with the voltage comparison clock.

[0011] The present invention also provides an asynchronous clock SAR analog-to-digital conversion method, the analog-to-digital conversion method comprising: The sample-and-hold circuit samples and holds the analog input signal and provides an analog voltage. A reference voltage is provided via a digital-to-analog converter array; The voltage comparator receives the analog voltage provided by the sample-and-hold circuit and the reference voltage provided by the digital-to-analog converter array, compares the analog voltage and the reference voltage, and outputs positive and negative comparison signals that are opposite to each other. The SAR controller receives the positive phase comparison signal output by the voltage comparator, generates and stores asynchronous digital signals and synchronous digital signals, and sends the asynchronous digital signal to the digital-to-analog converter array to generate the reference voltage. The metastable state detection module receives and compares the asynchronous digital signal and the synchronous digital signal to generate a metastable state flag. The metastable correction module receives the synchronous digital signal and the metastable flag, corrects the synchronous digital signal according to the metastable flag, and generates the final digital signal output.

[0012] In one embodiment, the analog-to-digital conversion method further includes: The effective detection module receives the positive comparison signal and the negative comparison signal, determines whether the output of the voltage comparator has reached an effective level, and generates a voltage comparison effective signal. The clock controller receives the voltage comparison valid signal, generates a SAR control asynchronous clock and a SAR control synchronous clock, and sends them to the SAR controller. The SAR controller updates the asynchronous digital signal and the synchronous digital signal under the SAR control asynchronous clock and the SAR control synchronous clock, respectively.

[0013] In one embodiment, the SAR controller updates the asynchronous digital signal and the synchronous digital signal under the SAR control asynchronous clock and the SAR control synchronous clock, respectively, including: The SAR logic module receives the positive phase comparison signal output by the voltage comparator and the SAR control synchronization clock provided by the clock controller. Under the SAR control synchronization clock, a digital signal is generated based on the positive phase comparison signal output by the voltage comparator and the current cycle synchronization digital signal stored in the first data trigger. The digital signal is then stored in the first data trigger as the next cycle synchronization digital signal. Under the SAR control asynchronous clock, the digital signal is stored in a latch as the asynchronous digital signal.

[0014] In one embodiment, the step of receiving and comparing the asynchronous digital signal and the synchronous digital signal through the metastability detection module to generate a metastability flag includes: The asynchronous digital signal is received through a second data trigger, and the synchronous digital signal is received through a third data trigger. The asynchronous digital signal and the synchronous digital signal are compared by a data comparator to see if they are consistent. If they are inconsistent, the metastable state flag is output.

[0015] In one embodiment, the analog-to-digital conversion method further includes: receiving a system clock input via a clock controller, generating a sampling clock and sending it to the sample-and-hold circuit, generating a voltage comparison enable signal and a voltage comparison clock and sending them to the voltage comparator, generating a metastable detection clock and sending it to the metastable detection module, and also sending the SAR control synchronization clock to the metastable correction module; the metastable detection clock is out of phase with the SAR controller synchronization clock, the SAR control synchronization clock is synchronized with the system clock and is later than the SAR control asynchronous clock, and the SAR control asynchronous clock is generated by performing an AND gate logic between the voltage comparison valid signal and the voltage comparison clock.

[0016] In one embodiment, the step of generating a digital signal based on the positive phase comparison signal output by the voltage comparator and the current cycle synchronization digital signal stored in the first data trigger under the SAR control synchronization clock, and storing the digital signal in the first data trigger as the next cycle synchronization digital signal; and storing the digital signal in a latch as the asynchronous digital signal under the SAR control asynchronous clock includes: Each time, only two bits in the synchronous digital signal and the asynchronous digital signal are updated: the current comparison bit and the next comparison bit, while the other bits remain unchanged. The current comparison bit is updated to the positive comparison signal output by the voltage comparator, and the next comparison bit is updated to logic 1.

[0017] In one embodiment, the step of correcting the synchronization digital signal according to the metastability flag to generate the final digital signal output includes: when the metastability flag is 1, setting the previous comparison bit of the current synchronization digital signal to 1, clearing the current comparison bit to 0, and storing the other bits unchanged as the final digital signal output; subsequent comparisons are performed normally, but the comparison results are discarded.

[0018] This invention relates to an asynchronous clock SAR analog-to-digital converter and its conversion method. Through a metastability detection module, the metastability of the voltage comparator can be detected and located during the voltage comparator comparison process. A metastability correction module then corrects the conversion result, improving the accuracy of the conversion. Furthermore, the second and third data triggers in the metastability detection module perform secondary sampling on the outputs of the data latch and the first data trigger in the SAR controller, avoiding the problem of metastability flags appearing due to the metastability of the data latch and the first data trigger outputs. This effectively improves the stability of the asynchronous clock SAR analog-to-digital converter. In addition, most of the circuit modules in the asynchronous clock SAR analog-to-digital converter (clock controller, SAR controller, metastability detection module, metastability correction module) can be implemented in digital circuits, and the analog circuit (voltage comparator) is simple and easy to implement. Attached Figure Description

[0019] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of the invention in any way. Furthermore, the shapes and proportions of the components in the drawings are merely illustrative to aid in understanding the invention and are not intended to specifically limit the shapes and proportions of the components. Those skilled in the art, guided by the teachings of this invention, can select various possible shapes and proportions to implement the invention according to specific circumstances. In the drawings: Figure 1 A schematic diagram of the circuit structure of an asynchronous clock SAR analog-to-digital converter provided for the first embodiment of the present invention; Figure 2 A timing diagram of each clock during the operation of an asynchronous clock SAR analog-to-digital converter provided in the first embodiment of the present invention; Figure 3 A relationship diagram of various signals during normal operation of an asynchronous clock SAR analog-to-digital converter is provided for the first embodiment of the present invention; Figure 4 This is a diagram showing the relationship between various signals in the metastable state of an asynchronous clock SAR analog-to-digital converter, provided as a first embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0021] Please see Figure 1 As shown, the first embodiment of the present invention provides an asynchronous clock SAR analog-to-digital converter, comprising: The sample-and-hold circuit S / H samples and holds the analog input signal Vin and provides the analog voltage Vs; A digital-to-analog converter array (DAC) provides a reference voltage Vdac; A voltage comparator is connected to both the sample-and-hold circuit S / H and the digital-to-analog converter array (DAC). It receives the analog voltage Vs provided by the sample-and-hold circuit S / H and the reference voltage Vdac provided by the DAC. It compares the analog voltage Vs and the reference voltage Vdac and outputs a positive comparison signal cop and an inverse comparison signal con, which are opposite to each other. The SAR controller is connected to both the voltage comparator and the digital-to-analog converter array (DAC). It receives the positive phase comparison signal cop output by the voltage comparator, generates and saves the asynchronous digital signal code_lt and the synchronous digital signal code_dff, and sends the asynchronous digital signal code_lt to the DAC to generate the reference voltage Vdac. The metastability detection module, connected to the SAR controller, receives and compares the asynchronous digital signal code_lt and the synchronous digital signal code_dff to generate a metastability flag META. The metastability correction module, connected to the metastability detection module, receives the synchronous digital signal code_dff and the metastability flag META, corrects the synchronous digital signal code_dff according to the metastability flag, and generates the final digital signal output.

[0022] In one embodiment, the analog-to-digital converter further includes: The valid detection module is connected to the voltage comparator, receives the positive comparison signal cop and the negative comparison signal con, determines whether the output of the voltage comparator has reached the valid level, and generates a voltage comparison valid signal cvalid. A clock controller, connected to the valid detection module and the SAR controller, receives the voltage comparison valid signal cvalid, generates a SAR control asynchronous clock Lclk and a SAR control synchronous clock Dclk, and sends them to the SAR controller. The SAR controller updates the asynchronous digital signal code_lt and the synchronous digital signal code_dff under the SAR control asynchronous clock Lclk and the SAR control synchronous clock Dclk, respectively.

[0023] In one embodiment, the SAR controller includes a data latch, a first data trigger DFF1, and a SAR logic module connected to both the data latch and the first data trigger DFF1. The SAR logic module is connected to both the voltage comparator and the clock controller, receives the positive phase comparison signal cop output by the voltage comparator and the SAR control synchronization clock Dclk provided by the clock controller, and generates a digital signal under the SAR control synchronization clock Dclk. The first data trigger DFF1 is connected to the clock controller, receives the SAR control synchronization clock Dclk provided by the clock controller, and saves the digital signal as a synchronous digital signal code_dff under the SAR control synchronization clock Dclk. The latch is connected to both the clock controller and the digital-to-analog converter array (DAC), receives the SAR control asynchronous clock Lclk provided by the clock controller, saves the digital signal as the asynchronous digital signal code_lt under the SAR control asynchronous clock Lclk, and sends it to the digital-to-analog converter array (DAC).

[0024] In one embodiment, the metastability detection module includes: a second data trigger DFF2, a third data trigger DFF3, and a data comparator EQ connected to both the second data trigger DFF2 and the third data trigger DFF3; the second data trigger DFF2 is connected to the data latch, receives and stores the asynchronous digital signal (represented here as m_code_lt); the third data trigger DFF3 is connected to the first data trigger DFF1 and the metastability correction module, receives and stores the synchronous digital signal (represented here as m_code_dff), and outputs the synchronous digital signal code_dff to the metastability correction module; the data comparator EQ compares whether the asynchronous digital signal m_code_lt stored by the second data trigger DFF2 is consistent with the synchronous digital signal m_code_dff stored by the third data trigger DFF3, and if they are inconsistent, it outputs the metastability flag META.

[0025] In one implementation test, the clock controller is connected to the sample-and-hold circuit S / H, the voltage comparator, the metastability detection module, and the metastability correction module. The clock controller receives the system clock adc_clk input, generates a sampling clock sclk and sends it to the sample-and-hold circuit S / H, generates a voltage comparison enable signal cen and a voltage comparison clock cclk and sends them to the voltage comparator, generates a metastability detection clock Dclkn and sends it to the metastability detection module, and also sends the SAR control synchronization clock Dclk to the metastability correction module. The metastability detection clock Dclkn is out of phase with the SAR controller synchronization clock Dclk. The SAR control synchronization clock Dclk is synchronized with the system clock adc_clk and is later than the SAR control asynchronous clock Lclk. The SAR control asynchronous clock Lclk is generated by performing an AND gate logic between the voltage comparison valid signal cvalid and the voltage comparison clock cclk.

[0026] The working principle of the asynchronous clock SAR analog-to-digital converter provided in the first embodiment of the present invention is explained in detail below with a specific example. Please refer to... Figure 2 As shown in the timing diagram, the system clock `adc_clk` is the operating clock of the clock controller. A sampling clock `sclk` is generated according to a fixed sampling period. The sampling time depends on the actual application; in this specific embodiment, it is taken as 3 system clock `adc_clk` cycles. Outside of the sampling time is the comparison time. During this period, the voltage comparison enable signal `cen` is set to 1, and the voltage comparison clock `cclk` is enabled. The voltage comparison clock `cclk` is inversely related to the system clock `adc_clk`. The comparison time also depends on the accuracy requirements of the asynchronous clock SAR analog-to-digital converter in the actual application, i.e., it depends on the number of quantization bits, which can be 8 bits, 12 bits, 16 bits, etc. The corresponding comparison times are 8, 12, and 16 system clock `adc_clk` cycles, respectively. In this embodiment, 12-bit accuracy is used, i.e., 12 system clock `adc_clk` cycles. During the comparison process, the SAR control synchronization clock Dclk is synchronized with the system clock adc_clk. The SAR control asynchronous clock Lclk is generated by ANDing the voltage comparison valid signal cvalid and the voltage comparison clock cclk. The voltage comparison valid signal cvalid is generated by ORing the positive comparison signal cop and the negative comparison signal con output by the voltage comparator. Of course, the generation of the voltage comparison valid signal cvalid is not limited to the ORing logic in this embodiment, and can be any other method for detecting the output level of the comparator.

[0027] The number of data latches and first data triggers (DFF1) is n, where n depends on the accuracy requirements of the asynchronous clock SAR analog-to-digital converter in the actual application, i.e., on the number of quantization bits, which can be 8 bits, 12 bits, 16 bits, etc., corresponding to n=8, 12, 16. In this embodiment, n=12. The data latches and first data triggers (DFF1) are used to store the asynchronous digital signal code_lt and the synchronous digital signal code_dff of the current comparison cycle. The SAR logic module is used to generate the asynchronous digital signal code_lt and the synchronous digital signal code_dff of the next comparison cycle based on the synchronous digital signal code_dff stored in the current cycle and the positive phase comparison signal cop output by the voltage comparator. Specifically, this includes: updating only two bits in the asynchronous digital signal code_lt and the synchronous digital signal code_dff each time, the current comparison bit and the next comparison bit, while keeping other bits unchanged. The current comparison bit is updated to the positive phase comparison signal cop output by the voltage comparator, and the next comparison bit is updated to logic 1. For example, when the comparison reaches the m-th comparison cycle (m takes the value 1-12), the (m-1)-th bit (takes the value 0-11, where 0 represents the most significant bit) in the asynchronous digital signal code_lt and the synchronous digital signal code_dff is updated to the positive phase comparison signal cop output by the voltage comparator as the current comparison bit, the m-th bit is updated to 1 for the next comparison bit, and the other bits remain unchanged.

[0028] Before the first comparison cycle, the asynchronous digital signal code_lt and the synchronous digital signal code_dff are initialized to half of the full-scale output of the digital-to-analog converter (DAC). In this embodiment, the asynchronous digital signal code_lt and the synchronous digital signal code_dff are initialized to 800h. When the voltage comparison enable signal cen=1, the voltage comparator starts working. In the first comparison cycle, when the voltage comparison clock cclk is 0, the voltage comparator can perform comparisons but its output is reset. The positive comparison signal cop and the negative comparison signal con output by the voltage comparator are 0 at this time. When the voltage comparison clock cclk is set to 1, the voltage comparator output is enabled, and the positive comparison signal cop and the negative comparison signal con are set to 1 or 0 and locked. Once the positive comparison signal cop and the negative comparison signal con are established to valid logic levels, the voltage comparison valid signal cvalid is set to 1, the SAR control asynchronous clock Lclk is set to 1, and the data latch updates the asynchronous digital signal code_lt for the next comparison cycle. This continues until the end of the first comparison cycle, when the SAR control synchronous clock Dclk is set to 1, the first data flip-flop DFF1 updates the synchronous digital signal code_dff for the next comparison cycle. At this point, the asynchronous digital signal code_lt equals the synchronous digital signal code_dff. Simultaneously, the voltage comparison clock cclk is cleared to 0, and the positive comparison signal cop and the negative comparison signal con output by the voltage comparator are reset to 0 again. The SAR control asynchronous clock Lclk is also cleared to 0. The second comparison cycle then begins, and the comparison process is exactly the same as the first cycle. Because of the presence of the SAR-controlled asynchronous clock Lclk and the data latch, once the voltage comparator output is locked during the current comparison cycle (the voltage comparison valid signal cvalid is set to 1), the digital signal input of the digital-to-analog converter array for the next comparison, i.e., the asynchronous digital signal code_lt, is updated. In other words, the next comparison can start immediately (the voltage comparator output remains locked until it is reset at the start of the next comparison cycle). In this way, the next comparison cycle can use the idle time of the previous comparison cycle for comparison, realizing asynchronous conversion and greatly improving the comparison rate.

[0029] Please see Figure 3As shown, when the voltage comparator is working normally, in the m-th comparison cycle, if the input signal of the voltage comparator is relatively large, the voltage comparator outputs the positive comparison signal cop and the negative comparison signal con, which can be established and locked in time. In the (m+1)-th comparison cycle, before the falling edge of the SAR control synchronization clock Dclk (i.e., before the rising edge of the metastability detection clock Dclkn) arrives, the asynchronous digital signal code_lt and the synchronous digital signal code_dff have both been updated to the digital signals for the next comparison (the current comparison bit is updated to the positive comparison signal cop, the next comparison bit is updated to 1, and other comparison bits remain unchanged), and the two are equal (m_code_lt == m_code_dff). Therefore, the metastability flag META in the metastability detection module will not be set to 1. When all comparison cycles are completed and META is not set to 1, the synchronous digital signal code_dff is stored as the final digital signal converted by the asynchronous clock SAR analog-to-digital converter and output.

[0030] Please see Figure 4 As shown, in the m-th comparison cycle, if the input signal of the voltage comparator is small, the voltage comparator outputs the positive comparison signal cop and the negative comparison signal con, which cannot be established and locked in time. The voltage comparison valid signal cvalid is not set to 1 or is set too late, so that the SAR control asynchronous clock Lclk is not generated or the pulse width is too narrow. The data latch fails to update or updates the asynchronous digital signal code_lt for the next comparison cycle with an error. However, the first data flip-flop DFF1 can update the correct synchronous digital signal code_dff (except for the currently compared bit, which may sample an incorrect signal because it needs to be updated to the positive comparison signal cop; the other bits are held or set to 1 (next comparison bit)). At this time, the two data samples obtained by the second data flip-flop DFF2 and the third data flip-flop DFF3 in the metastability detection module are inconsistent (m_code_lt!=m_code_dff). Therefore, the metastability flag META output by the data comparator EQ based on the comparison of the two data is set to 1. The metastability correction module determines whether to correct the output data based on the metastability flag META. When the metastability flag META=1, the previous comparison bit of the current synchronous digital signal code_dff is set to 1, the current comparison bit is cleared to 0, and the other bits remain unchanged and are stored as the output of the digital signal Dout converted by the asynchronous clock SAR analog-to-digital converter. Subsequent comparisons proceed normally, but the comparison results are discarded.

[0031] Therefore, correspondingly, the second embodiment of the present invention provides an asynchronous clock SAR analog-to-digital conversion method, the analog-to-digital conversion method comprising: The sample-and-hold circuit samples and holds the analog input signal and provides an analog voltage. A reference voltage is provided via a digital-to-analog converter array; The voltage comparator receives the analog voltage provided by the sample-and-hold circuit and the reference voltage provided by the digital-to-analog converter array, compares the analog voltage and the reference voltage, and outputs positive and negative comparison signals that are opposite to each other. The SAR controller receives the positive phase comparison signal output by the voltage comparator, generates and stores asynchronous digital signals and synchronous digital signals, and sends the asynchronous digital signal to the digital-to-analog converter array to generate the reference voltage. The metastable state detection module receives and compares the asynchronous digital signal and the synchronous digital signal to generate a metastable state flag. The metastable correction module receives the synchronous digital signal and the metastable flag, corrects the synchronous digital signal according to the metastable flag, and generates the final digital signal output.

[0032] In one embodiment, the analog-to-digital conversion method further includes: The effective detection module receives the positive comparison signal and the negative comparison signal, determines whether the output of the voltage comparator has reached an effective level, and generates a voltage comparison effective signal. The clock controller receives the voltage comparison valid signal, generates a SAR control asynchronous clock and a SAR control synchronous clock, and sends them to the SAR controller. The SAR controller updates the asynchronous digital signal and the synchronous digital signal under the SAR control asynchronous clock and the SAR control synchronous clock, respectively.

[0033] In one embodiment, the SAR controller updates the asynchronous digital signal and the synchronous digital signal under the SAR control asynchronous clock and the SAR control synchronous clock, respectively, including: The SAR logic module receives the positive phase comparison signal output by the voltage comparator and the SAR control synchronization clock provided by the clock controller. Under the SAR control synchronization clock, a digital signal is generated based on the positive phase comparison signal output by the voltage comparator and the current cycle synchronization digital signal stored in the first data trigger. The digital signal is then stored in the first data trigger as the next cycle synchronization digital signal. Under the SAR control asynchronous clock, the digital signal is stored in a latch as the asynchronous digital signal.

[0034] In one embodiment, the step of receiving and comparing the asynchronous digital signal and the synchronous digital signal through the metastability detection module to generate a metastability flag includes: The asynchronous digital signal is received through a second data trigger, and the synchronous digital signal is received through a third data trigger. The asynchronous digital signal and the synchronous digital signal are compared by a data comparator to see if they are consistent. If they are inconsistent, the metastable state flag is output.

[0035] In one embodiment, the analog-to-digital conversion method further includes: receiving a system clock input via a clock controller, generating a sampling clock and sending it to the sample-and-hold circuit, generating a voltage comparison enable signal and a voltage comparison clock and sending them to the voltage comparator, generating a metastable detection clock and sending it to the metastable detection module, and also sending the SAR control synchronization clock to the metastable correction module; the metastable detection clock is out of phase with the SAR controller synchronization clock, the SAR control synchronization clock is synchronized with the system clock and is later than the SAR control asynchronous clock, and the SAR control asynchronous clock is generated by performing an AND gate logic between the voltage comparison valid signal and the voltage comparison clock.

[0036] In one embodiment, the step of generating a digital signal based on the positive phase comparison signal output by the voltage comparator and the current cycle synchronization digital signal stored in the first data trigger under the SAR control synchronization clock, and storing the digital signal in the first data trigger as the next cycle synchronization digital signal; and storing the digital signal in a latch as the asynchronous digital signal under the SAR control asynchronous clock includes: Each time, only two bits in the synchronous digital signal and the asynchronous digital signal are updated: the current comparison bit and the next comparison bit, while the other bits remain unchanged. The current comparison bit is updated to the positive comparison signal output by the voltage comparator, and the next comparison bit is updated to logic 1.

[0037] In one embodiment, correcting the synchronization digital signal according to the metastability flag to generate the final digital signal output includes: when the metastability flag is 1, setting the previous comparison bit of the current synchronization digital signal to 1, clearing the current comparison bit to 0, and storing the other bits unchanged as the final digital signal output; subsequent comparisons are performed normally, but the comparison results are discarded.

[0038] This invention relates to an asynchronous clock SAR analog-to-digital converter and its conversion method. Through a metastability detection module, the metastability of the voltage comparator can be detected and located during the voltage comparator comparison process. A metastability correction module then corrects the conversion result, improving the accuracy of the conversion. Furthermore, the second and third data triggers in the metastability detection module perform secondary sampling on the outputs of the data latch and the first data trigger in the SAR controller, avoiding the problem of metastability flags appearing due to the metastability of the data latch and the first data trigger outputs. This effectively improves the stability of the asynchronous clock SAR analog-to-digital converter. In addition, most of the circuit modules in the asynchronous clock SAR analog-to-digital converter (clock controller, SAR controller, metastability detection module, metastability correction module) can be implemented in digital circuits, and the analog circuit (voltage comparator) is simple and easy to implement.

[0039] It should be understood that the above description is for illustrative purposes and not for limitation. Many embodiments and applications beyond the provided examples will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of this teaching should not be determined by reference to the above description, but rather by reference to the foregoing claims and the full scope of their equivalents. For purposes of completeness, all articles and references, including disclosures of patent inventions and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended as a waiver of that subject matter, nor should it be construed as an indication that the inventors have not considered that subject matter as part of the disclosed inventive subject matter.

Claims

1. An asynchronous clock SAR analog-to-digital converter, characterized in that, The analog-to-digital converter includes: The sample-and-hold circuit samples and holds the analog input signal and provides an analog voltage; A digital-to-analog converter array provides a reference voltage; A voltage comparator, connected to both the sample-and-hold circuit and the digital-to-analog converter array, receives the analog voltage provided by the sample-and-hold circuit and the reference voltage provided by the digital-to-analog converter array, compares the analog voltage and the reference voltage, and outputs a positive-phase comparison signal and an inverted-phase comparison signal that are opposite to each other. The SAR controller is connected to both the voltage comparator and the digital-to-analog converter array. It receives the positive phase comparison signal output by the voltage comparator, generates and stores asynchronous digital signals and synchronous digital signals, and sends the asynchronous digital signals to the digital-to-analog converter array to generate the reference voltage. A metastable state detection module, connected to the SAR controller, receives and compares the asynchronous digital signal and the synchronous digital signal to generate a metastable state flag. The metastable correction module, connected to the metastable detection module, receives the synchronous digital signal and the metastable flag, corrects the synchronous digital signal according to the metastable flag, and generates the final digital signal output.

2. The asynchronous clock SAR analog-to-digital converter as described in claim 1, characterized in that, The analog-to-digital converter also includes: The effective detection module is connected to the voltage comparator, receives the positive comparison signal and the negative comparison signal, determines whether the output of the voltage comparator has reached an effective level, and generates a voltage comparison effective signal. A clock controller, connected to the effective detection module and the SAR controller, receives the voltage comparison effective signal, generates an asynchronous SAR control clock and a synchronous SAR control clock, and sends them to the SAR controller. The SAR controller updates the asynchronous digital signal and the synchronous digital signal under the asynchronous SAR control clock and the synchronous SAR control clock, respectively.

3. The asynchronous clock SAR analog-to-digital converter as described in claim 2, characterized in that, The SAR controller includes a data latch, a first data trigger, and a SAR logic module connected to both the data latch and the first data trigger. The SAR logic module is connected to both the voltage comparator and the clock controller, receives the positive phase comparison signal output by the voltage comparator and the SAR control synchronization clock provided by the clock controller, and generates a digital signal under the SAR control synchronization clock. The first data trigger is connected to the clock controller, receives the SAR control synchronization clock provided by the clock controller, and saves the digital signal as a synchronous digital signal under the SAR control synchronization clock. The latch is connected to both the clock controller and the digital-to-analog converter array, receives the SAR control asynchronous clock provided by the clock controller, saves the digital signal as the asynchronous digital signal under the SAR control synchronization clock, and sends it to the digital-to-analog converter array.

4. The asynchronous clock SAR analog-to-digital converter as described in claim 3, characterized in that, The metastability detection module includes: a second data trigger, a third data trigger, and a data comparator connected to both the second and third data triggers; the second data trigger is connected to the data latch and receives the asynchronous digital signal; the third data trigger is connected to the first data trigger and the metastability correction module, receives the synchronous digital signal, and outputs the synchronous digital signal to the metastability correction module; the data comparator compares whether the asynchronous digital signal and the synchronous digital signal are consistent, and if they are inconsistent, it outputs the metastability flag.

5. The asynchronous clock SAR analog-to-digital converter as described in claim 4, characterized in that, The clock controller is connected to the sample-and-hold circuit, the voltage comparator, the metastability detection module, and the metastability correction module. The clock controller receives the system clock input, generates a sampling clock and sends it to the sample-and-hold circuit, generates a voltage comparison enable signal and a voltage comparison clock and sends them to the voltage comparator, generates a metastability detection clock and sends it to the metastability detection module, and also sends the SAR control synchronization clock to the metastability correction module. The metastability detection clock is out of phase with the SAR controller synchronization clock. The SAR control synchronization clock is synchronized with the system clock and is later than the SAR control asynchronous clock. The SAR control asynchronous clock is generated by ANDing the voltage comparison valid signal with the voltage comparison clock.

6. An asynchronous clock SAR analog-to-digital conversion method, characterized in that, The analog-to-digital conversion method includes: The sample-and-hold circuit samples and holds the analog input signal and provides an analog voltage. A reference voltage is provided via a digital-to-analog converter array; The voltage comparator receives the analog voltage provided by the sample-and-hold circuit and the reference voltage provided by the digital-to-analog converter array, compares the analog voltage and the reference voltage, and outputs positive and negative comparison signals that are opposite to each other. The SAR controller receives the positive phase comparison signal output by the voltage comparator, generates and stores asynchronous digital signals and synchronous digital signals, and sends the asynchronous digital signal to the digital-to-analog converter array to generate the reference voltage. The metastable state detection module receives and compares the asynchronous digital signal and the synchronous digital signal to generate a metastable state flag. The metastable correction module receives the synchronous digital signal and the metastable flag, corrects the synchronous digital signal according to the metastable flag, and generates the final digital signal output.

7. The asynchronous clock SAR analog-to-digital conversion method as described in claim 6, characterized in that, The analog-to-digital conversion method further includes: The effective detection module receives the positive comparison signal and the negative comparison signal, determines whether the output of the voltage comparator has reached an effective level, and generates a voltage comparison effective signal. The clock controller receives the voltage comparison valid signal, generates a SAR control asynchronous clock and a SAR control synchronous clock, and sends them to the SAR controller. The SAR controller updates the asynchronous digital signal and the synchronous digital signal under the SAR control asynchronous clock and the SAR control synchronous clock, respectively.

8. The asynchronous clock SAR analog-to-digital conversion method as described in claim 7, characterized in that, The SAR controller updates the asynchronous digital signal and the synchronous digital signal under the SAR control asynchronous clock and the SAR control synchronous clock, respectively, including: The SAR logic module receives the positive phase comparison signal output by the voltage comparator and the SAR control synchronization clock provided by the clock controller. Under the SAR control synchronization clock, a digital signal is generated based on the positive phase comparison signal output by the voltage comparator and the current cycle synchronization digital signal stored in the first data trigger. The digital signal is then stored in the first data trigger as the next cycle synchronization digital signal. Under the SAR control asynchronous clock, the digital signal is stored in a latch as the asynchronous digital signal.

9. The asynchronous clock SAR analog-to-digital conversion method as described in claim 8, characterized in that, The step of receiving and comparing the asynchronous digital signal and the synchronous digital signal through the metastability detection module to generate a metastability flag includes: The asynchronous digital signal is received through a second data trigger, and the synchronous digital signal is received through a third data trigger. The asynchronous digital signal and the synchronous digital signal are compared by a data comparator to see if they are consistent. If they are inconsistent, the metastable state flag is output.

10. The asynchronous clock SAR analog-to-digital conversion method as described in claim 9, characterized in that, The analog-to-digital conversion method further includes: receiving a system clock input via a clock controller, generating a sampling clock and sending it to the sample-and-hold circuit, generating a voltage comparison enable signal and a voltage comparison clock and sending them to the voltage comparator, generating a metastable detection clock and sending it to the metastable detection module, and also sending the SAR control synchronization clock to the metastable correction module; the metastable detection clock is out of phase with the SAR controller synchronization clock, the SAR control synchronization clock is synchronized with the system clock and is later than the SAR control asynchronous clock, and the SAR control asynchronous clock is generated based on an AND gate logic between the voltage comparison valid signal and the voltage comparison clock.

11. The asynchronous clock SAR analog-to-digital conversion method as described in claim 8, characterized in that, The process involves generating a digital signal based on the positive phase comparison signal output by the voltage comparator and the current cycle synchronization digital signal stored in the first data trigger under the SAR control synchronization clock, and storing the digital signal in the first data trigger as the next cycle synchronization digital signal. Saving the digital signal in the latch as the asynchronous digital signal under the SAR control asynchronous clock includes: Each time, only two bits in the synchronous digital signal and the asynchronous digital signal are updated: the current comparison bit and the next comparison bit, while the other bits remain unchanged. The current comparison bit is updated to the positive comparison signal output by the voltage comparator, and the next comparison bit is updated to logic 1.

12. The asynchronous clock SAR analog-to-digital conversion method as described in claim 8, characterized in that, The step of correcting the synchronization digital signal according to the metastability flag to generate the final digital signal output includes: when the metastability flag is 1, the previous comparison bit of the current synchronization digital signal is set to 1, the current comparison bit is cleared to 0, and the other bits remain unchanged and stored as the final digital signal output. Subsequent comparisons are performed normally, but the comparison results are discarded.

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