Integrated assembly and method of forming an integrated assembly

Abstract

Some embodiments include an integrated assembly having a memory region and another region adjacent to the memory region. A column of channel material is disposed within the memory region, and a conductive pillar is disposed within the other region. A source structure is coupled to a lower region of the column of channel material. A panel extends across the memory region and the other region, and separates a first memory block region from a second memory block region. A doped semiconductor material is immediately adjacent to the panel within the memory region and the other region. A ring laterally surrounds a lower region of the conductive pillar. The ring is between the conductive pillar and the doped semiconductor material. The ring includes a laminate of two or more materials, where at least one of the two or more materials is insulating. Some embodiments include methods of forming an integrated assembly.

Description

[0001] Relevant patent information

[0002] This application claims priority and benefit to U.S. Patent Application No. 17 / 223,254, filed April 6, 2021, the disclosure of which is incorporated herein by reference. Technical Field

[0003] A method for forming an integrated assembly (e.g., an integrated memory device). Integrated assembly. Background Technology

[0004] Memory provides data storage devices for electronic systems. Flash memory is a type of memory widely used in modern computers and devices. For example, modern personal computers store the BIOS on flash memory chips. As another example, it is increasingly common for computers and other devices to use flash memory, in the form of solid-state drives, instead of traditional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and allows manufacturers to provide the ability to remotely upgrade devices for enhanced features.

[0005] NAND can be the basic architecture of flash memory and can be configured to include vertically stacked memory cells.

[0006] Before specifically describing NAND, it may be helpful to describe the relationships of memory arrays within an integrated arrangement more generally. Figure 1 shows a block diagram of a prior art device 1000 including: a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns; access lines 1004 (e.g., word lines for conducting signals WL0 to WLm); and first data lines 1006 (e.g., bit lines for conducting signals BL0 to BLn). Access lines 1004 and first data lines 1006 are used to transfer information to and from memory cells 1003. Row decoders 1007 and column decoders 1008 decode address signals A0 to AX on address lines 1009 to determine which memory cells in memory cells 1003 to access. Sensing amplifier circuitry 1015 operates to determine the value of information read from memory cells 1003. I / O circuitry 1017 transfers the value of information between memory array 1002 and input / output (I / O) lines 1005. Signals DQ0 to DQN on I / O lines 1005 represent values ​​of information read from or to be written to memory cell 1003. Other devices can communicate with device 1000 via I / O line 1005, address line 1009, or control line 1020. Memory control unit 1018 controls memory operations to be performed on memory cell 1003 and utilizes signals on control line 1020. Device 1000 can receive supply voltage signals Vcc and Vss on first supply line 1030 and second supply line 1032, respectively. Device 1000 includes selection circuitry 1040 and input / output (I / O) circuitry 1017. Selection circuit 1040 can respond to signals CSEL1 to CSELn via I / O circuit 1017 to select signals on first data line 1006 and second data line 1013, the signals representing values ​​of information to be read from or programmed into memory cell 1003. Column decoder 1008 can selectively activate CSEL1 to CSELn signals based on address signals A0 to AX on address line 1009. Selection circuit 1040 can select signals on first data line 1006 and second data line 1013 to enable communication between memory array 1002 and I / O circuit 1017 during read and program operations.

[0007] The memory array 1002 of Figure 1 may be a NAND memory array, and Figure 2 shows a schematic diagram of a three-dimensional NAND memory device 200 that can be used with the memory array 1002 of Figure 1. Device 200 includes multiple strings of charge storage devices. In a first direction (Z-Z'), each string of charge storage devices may include, for example, thirty-two charge storage devices stacked one on top of the other, where each charge storage device corresponds to one of, for example, thirty-two layers (e.g., Tier 0 to Tier 31). The charge storage devices in the respective strings may share a common channel region, such as formed in pillars of a corresponding semiconductor material (e.g., polysilicon), the charge storage device strings being formed around said semiconductor material pillars. In a second direction (X-X'), each first group of the multiple strings, for example, sixteen first groups, may include, for example, eight strings sharing multiple (e.g., thirty-two) access lines (i.e., "global control gate (CG) lines," also referred to as word lines WL). Each of the access lines may couple a charge storage device within a layer. When each charge storage device includes a cell capable of storing two bits of information, charge storage devices coupled by the same access line (and therefore corresponding to the same layer) can be logically grouped into, for example, two pages, such as P0 / P32, P1 / P33, P2 / P34, etc. In the third direction (Y-Y'), each second group in the multiple strings, for example, eight second groups, may include sixteen strings coupled by corresponding data lines of eight data lines. The size of the memory block may include 1,024 pages and approximately 16 MB in total (e.g., 16WL × 32 layers × 2 bits = 1,024 pages / block, block size = 1,024 pages × 16KB / page = 16 MB). The number of strings, layers, access lines, data lines, first groups, second groups, and / or pages may be larger or smaller than those shown in Figure 2.

[0008] Figure 3 shows a cross-sectional view of a memory block 300 of the 3D NAND memory device 200 of Figure 2 in the X-X' direction. The memory block contains fifteen strings of charge storage devices in one of sixteen first groups relative to the strings described in Figure 2. The multiple strings of the memory block 300 can be divided into multiple subsets 310, 320, 330 (e.g., tile columns), such as tile columns. I Puzzle Series j and puzzle series KEach subset (e.g., a tile array) includes a “partial block” (sub-block) of memory block 300. A global drain-side select-gate (SGD) line 340 may be coupled to the SGDs of multiple strings. For example, the global SGD line 340 may be coupled to multiple (e.g., three) sub-SGD lines 342, 344, 346 via corresponding sub-SGD drivers of multiple (e.g., three) sub-SGD drivers 332, 334, 336, where each sub-SGD line corresponds to a corresponding subset (e.g., a tile array). Each sub-SGD driver of sub-SGD drivers 332, 334, 336 may simultaneously couple or disconnect the SGD of the corresponding partial block (e.g., a tile array) of strings, independently of the SGDs of the strings of other partial blocks. A global source-side select-gate (SGS) line 360 ​​may be coupled to the SGS of multiple strings. For example, a global SGS line 360 ​​may be coupled to a plurality of sub-SGS lines 362, 364, and 366 via corresponding sub-SGS drivers among a plurality of sub-SGS drivers 322, 324, and 326, wherein each sub-SGS line corresponds to a corresponding subset (e.g., a tile column). Each of the sub-SGS drivers 322, 324, and 326 may simultaneously couple or disconnect the SGS of the corresponding partial block (e.g., a tile column) string, independent of the SGS of the strings of other partial blocks. A global access line (e.g., a global CG line) 350 may be coupled to a charge storage device corresponding to a corresponding layer of each of the multiple strings. Each global CG line (e.g., global CG line 350) may be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, and 356 via corresponding sub-string drivers among a plurality of sub-string drivers 312, 314, and 316. Each substring driver in the substring driver can simultaneously couple or disconnect the charge storage device corresponding to the corresponding subblock and / or layer, independently of the charge storage devices of other subblocks and / or other layers. The charge storage devices corresponding to the corresponding subset (e.g., a subblock) and the corresponding layer may include charge storage devices of a “sublayer” (e.g., a single “patch”). The string corresponding to the corresponding subset (e.g., a subblock) may be coupled to the corresponding subsource in subsources 372, 374, and 376 (e.g., “patch source”), wherein each subsource is coupled to a corresponding power source.

[0009] Alternatively, the NAND memory device 200 is described with reference to the schematic illustration of FIG4.

[0010] Memory array 200 includes word lines 2021 to 202 N And bit lines 2281 to 228 M .

[0011] Memory array 200 also includes NAND strings 2061 to 206 M Each NAND string contains 2081 to 208 charge storage transistors. NCharge storage transistors can store charge using floating gate materials (e.g., polysilicon) or charge trapping materials (e.g., silicon nitride, metal nanodots, etc.).

[0012] Charge storage transistor 208 is located at the intersection of word line 202 and string 206. Charge storage transistor 208 represents a non-volatile memory cell for storing data. The charge storage transistor 208 of each NAND string 206 is connected in series from source to drain between a source select device (e.g., source-side select gate SGS) 210 and a drain select device (e.g., drain-side select gate SGD) 212. Each source select device 210 is located at the intersection of string 206 and source select line 214, and each drain select device 212 is located at the intersection of string 206 and drain select line 215. Select devices 210 and 212 can be any suitable access device and are generally illustrated by the boxes in FIG4.

[0013] The source of each source select device 210 is connected to a common source line 216. The drain of each source select device 210 is connected to the source of the first charge storage transistor 208 of the corresponding NAND string 206. For example, the drain of source select device 2101 is connected to the source of the charge storage transistor 2081 of the corresponding NAND string 2061. The source select device 210 is connected to the source select line 214.

[0014] The drain of each drain selector 212 is connected to the bit line (i.e., digital line) 228 at its drain contact. For example, the drain of drain selector 2121 is connected to bit line 2281. The source of each drain selector 212 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 206. For example, the source of drain selector 2121 is connected to the charge storage transistor 208 of the corresponding NAND string 2061. N The drain electrode.

[0015] The charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The control gate 236 of the charge storage transistor 208 is coupled to a word line 202. Columns of the charge storage transistor 208 are those transistors coupled to a given positioning line 228 within a NAND string 206. Rows of the charge storage transistor 208 are those transistors typically coupled to a given word line 202.

[0016] Block erasure of vertically stacked memory cells in a three-dimensional NAND architecture can be performed by generating hole carriers beneath them and then using an electric field to sweep the hole carriers upwards along the memory cells.

[0017] A gate-induced drain leakage (GIDL) can be provided using a transistor's gating structure, which generates holes for block erasure of memory cells. The transistor can be a source-side selected (SGS) device as described above. The channel material associated with the memory cell string can be configured as channel material pillars, and regions of these pillars can be gated and coupled to the SGS device. The gated portion of the channel material pillar overlaps with the gate of the SGS device.

[0018] It may be desirable that at least some of the gated coupling portions of the channel material be heavily doped. In some applications, it may be desirable that the gated coupling portions comprise both a heavily doped lower region and a lightly doped upper region; wherein both regions overlap with the gate of the SGS device. Specifically, overlapping with the lightly doped region provides the SGS device with non-drain "off" characteristics, and overlapping with the heavily doped region provides the SGS device with drain GIDL characteristics. The terms "heavily doped" and "lightly doped" are used relative to each other rather than relative to a particular conventional meaning. Thus, a "heavily doped" region is more heavily doped than the adjacent "lightly doped" region and may or may not include heavy doping in the conventional sense. Similarly, a "lightly doped" region is less doped than the adjacent "heavily doped" region and may or may not include light doping in the conventional sense. In some applications, the term "lightly doped" refers to having a doping density of less than or equal to about 10. 18 atoms / cm 3 Semiconductor materials with doped materials, and the term "heavily doped" refers to materials with a dopant concentration greater than or equal to about 10. 22 atoms / cm 3 Semiconductor materials with dopants.

[0019] The channel material can be initially doped to a light doping level, and then a heavily doped region can be formed by diffusion from the bottom doped semiconductor material outward.

[0020] It is desirable to develop improved methods for forming integrated memories (e.g., NAND memory). It is also desirable to develop improved memory devices. Attached Figure Description

[0021] Figure 1 shows a block diagram of a prior art memory device having a memory array with memory cells.

[0022] Figure 2 shows a schematic diagram of the prior art memory device of Figure 1 in the form of a 3D NAND memory device.

[0023] Figure 3 shows a cross-sectional view of the prior art 3D NAND memory device of Figure 2 in the X-X' direction.

[0024] Figure 4 is a schematic diagram of a conventional NAND memory array.

[0025] Figure 5-5B This is a schematic top view of a region of the instance integration assembly during the instance processing phase of an instance embodiment method for forming an instance memory device. Figure 5 ) and a pair of schematic cross-sectional side views ( Figure 5A and 5B ). Figure 5A and 5B The cross-sectional side views are respectively along Figure 5 Lines AA and BB. Figure 5 The top view is along Figure 5A and 5B The line CC.

[0026] Figure 6 and 6A They are in Figure 5-5B The instance process phase after the instance process phase Figure 5-5B The example integrates the area of ​​the assembly with diagrammatic top and side views. Figure 6A The view is along Figure 6 Line AA.

[0027] Figure 7 and 7A They are respectively in Figure 6 and 6A The instance process phase after the instance process phase Figure 5-5B The example integrates the area of ​​the assembly with diagrammatic top and side views. Figure 7A The view is along Figure 7 Line AA.

[0028] Figure 8-8B Is Figure 7 and 7A The instance processing phase following the instance processing phase. Figure 5-5B The example integrates the area of ​​the assembly with diagrammatic top and side views. Figure 8A and 8B The cross-sectional side views are respectively along Figure 8 Lines AA and BB. Figure 8 The top view is along Figure 8A and 8B The line CC.

[0029] Figure 9A and 9B Is Figure 8-8B The instance processing phase following the instance processing phase. Figure 5-5B A schematic cross-sectional side view of the area of ​​an example integrated assembly. Figure 9A and 9B The cross-sectional side view is along the same direction as... Figure 5A and 5BSame cross-section.

[0030] Figure 10A and 10B Is Figure 9A and 9B The instance processing phase following the instance processing phase. Figure 5-5B A schematic cross-sectional side view of the area of ​​an example integrated assembly. Figure 10A and 10B The cross-sectional side view is along the same direction as... Figure 5A and 5B Same cross-section.

[0031] Figure 11A and 11B Is Figure 10A and 10B The instance processing phase following the instance processing phase. Figure 5-5B A schematic cross-sectional side view of the area of ​​an example integrated assembly. Figure 11A and 11B The cross-sectional side view is along the same direction as... Figure 5A and 5B Same cross-section.

[0032] Figure 12A and 12B Is Figure 11A and 11B The instance processing phase following the instance processing phase. Figure 5-5B A schematic cross-sectional side view of the area of ​​an example integrated assembly. Figure 12A and 12B The cross-sectional side view is along the same direction as... Figure 5A and 5B Same cross-section.

[0033] Figure 13A and 13B Is Figure 12A and 12B The instance processing phase following the instance processing phase. Figure 5-5B A schematic cross-sectional side view of the area of ​​an example integrated assembly. Figure 13A and 13B The cross-sectional side view is along the same direction as... Figure 5A and 5B Same cross-section.

[0034] Figure 14A and 14B Is Figure 13A and 13B The instance processing phase following the instance processing phase. Figure 5-5B A schematic cross-sectional side view of the area of ​​an example integrated assembly. Figure 14A and 14BThe cross-sectional side view is along the same direction as... Figure 5A and 5B Same cross-section.

[0035] Figure 15A and 15B yes Figure 14A and 14B A schematic cross-sectional side view of the area of ​​the example integrated assembly, and in addition to Figure 14A and 14B In addition to those shown, additional vertical extensions of such assemblies are also shown.

[0036] Figure 15C yes Figure 15A and 15B A top view of the assembly. Figure 15A and 15B The cross-sectional side views are respectively along Figure 15C Lines AA and BB. Figure 15C The top view is along Figure 15A and 15B The line CC.

[0037] Figure 16 Is Figure 5A After the process stage and replacement Figure 6A Instances of process phases Figure 5A A schematic cross-sectional side view of the assembly.

[0038] Figure 17 Is Figure 6A The instance process phase following the process phase Figure 5A A schematic cross-sectional side view of the assembly.

[0039] Figure 18A yes Figure 17 A schematic cross-sectional side view of the area of ​​the example integrated assembly, and in addition to Figure 17 In addition to those shown, additional vertical extensions of such assemblies are also shown.

[0040] Figure 18B Is Figure 18A Along the process stages Figure 5B A diagrammatic cross-sectional side view of the cross-section of the region. Figure 18B The view is the same as Figure 15B The view.

[0041] Figure 18C yes Figure 18A and 18B A top view of the assembly. Figure 18A and 18B The cross-sectional side views are respectively along Figure 18C Lines AA and BB. Figure 18CThe top view is along Figure 18A and 18B The line CC.

[0042] Figure 19 and 19A They are in Figure 5-5B After the instance process phase and replaced by Figure 6 and 6A The instance process phase of the instance process phase Figure 5-5B The example integrates the area of ​​the assembly with diagrammatic top and side views. Figure 19A The view is along Figure 19 Line AA.

[0043] Figure 20 Is Figure 19A The instance process phase following the process phase Figure 5A A schematic cross-sectional side view of the assembly.

[0044] Figure 21 Is Figure 20 The instance process phase following the process phase Figure 5A A schematic cross-sectional side view of the assembly.

[0045] Figure 22A yes Figure 21 A schematic cross-sectional side view of the area of ​​the example integrated assembly, and in addition to Figure 21 In addition to those shown, additional vertical extensions of such assemblies are also shown.

[0046] Figure 22B Is Figure 22A Along the process stages Figure 5A A diagrammatic cross-sectional side view of the cross-section of the region. Figure 22B The view is the same as Figure 15B The view.

[0047] Figure 22C yes Figure 22A and 22B A top view of the assembly. Figure 22A and 22B The cross-sectional side views are respectively along Figure 22C Lines AA and BB. Figure 22C The top view is along Figure 22A and 22B The line CC. Detailed Implementation

[0048] Some embodiments include the use of a protective material to protect the lower region of the conductive pillar during material etching associated with the integrated assembly. The protective material may be incorporated into a ring (i.e., annular rings, ring structures, loops, etc.). The ring may include a laminate containing the protective material and one or more other materials. Some embodiments include an integrated assembly having a ring laterally surrounding the lower region of the conductive pillar, wherein such a ring includes a laminate containing the protective material. Reference Figure 5 -22 Describes example implementations.

[0049] Figure 5 A top view is shown along several instance regions of the instance integrated assembly 10. The shown region of assembly 10 includes a pair of memory regions (memory array regions) 12a and 12b (array-1 and array-2), and includes an intermediate region 14 between the memory regions. In some embodiments, memory regions 12a and 12b may be referred to as a first region laterally displaced (laterally offset) relative to each other, and the intermediate region 14 may be referred to as another region (or a second region) situated between the laterally displaced (laterally offset) first regions. Relative to Figure 5 The top view provides an x / y axis system to provide a reference for a first direction and an orthogonal second direction. The first direction can be one of the x-axis direction and the y-axis direction, and the second direction can be the other of the x-axis direction and the y-axis direction. The intermediate region 14 may ultimately include a number of regions associated with the integrated memory, including, for example, stepped regions, peak regions, bridging regions, etc.

[0050] Figure 5A and 5B Cross-sectional side views of the intermediate region 14 and the memory region 12a are shown respectively. Figure 5A The view is along Figure 5 The line AA, and Figure 5B The view is along Figure 5 BB line. Figure 5 The view is along Figure 5A and 5B The line CC. Figure 5A and 5B The view is shown graphically in Figure 5 The instance structure is shown in the top view, but not in accordance with... Figure 5 Provided in the same proportion.

[0051] Figure 5A and 5B An example configuration is shown in which insulating material 50 forms a support structure for stacking 52.

[0052] The insulating material 50 may include any suitable composition, and in some embodiments may include silicon dioxide, be composed primarily of silicon dioxide, or be composed of silicon dioxide.

[0053] In the illustrated embodiment, the conductive structure 54 is located within the insulating material 50. The conductive structure 54 may include any suitable conductive material; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.) and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.).

[0054] One or more of the conductive structures 54 may be coupled to a logic circuit system (e.g., CMOS) disposed beneath the insulating material 50. Figure 5A A logic circuit system is shown, which may include components 56a and 56b corresponding to, for example, a control circuit system and / or a sensing circuit system (e.g., a sense amplifier circuit system, a driver circuit system, etc.). Figure 5B This illustrates a logic circuit system configured to include a component 56c (e.g., a control circuit system) coupled to a source structure including stack 52.

[0055] The logic circuit system 56 may be supported by a semiconductor material (not shown). Such semiconductor materials may include, for example, monocrystalline silicon (Si), consist primarily of monocrystalline silicon (Si), or consist entirely of monocrystalline silicon (Si). The semiconductor material may be referred to as a semiconductor substrate or a semiconductor base. The term "semiconductor substrate" means any construction that includes semiconductor material, including but not limited to bulk semiconductor material, such as a semiconductor wafer (alone or in a combination of other materials), and a layer of semiconductor material (alone or in a combination of other materials). The term "substrate" refers to any support structure that includes (but is not limited to) the semiconductor substrate described above. The configuration described herein may be referred to as an integrated configuration supported by a semiconductor substrate and therefore may be considered as an integrated assembly.

[0056] Stack 52 can be referred to as the first stack and can be considered as spanning... Figure 5 The memory regions (12a and 12b) and intermediate region (14) extend from each other. The stack 52 contains conductive material 58 and includes regions 60 and 62 above the conductive material 58. Region 60 may be referred to as a semiconductor material-containing region.

[0057] In the illustrated embodiment, three of regions 60 are present, and these regions are labeled 60a, 60b, and 60c. Regions 60a and 60c contain semiconductor material 64. Such semiconductor material may include conductively doped semiconductor material, such as conductively doped silicon. In some embodiments, the silicon may be n-type doped, and therefore may be doped with one or both of phosphorus and arsenic. The conductively doped silicon in regions 60a and 60c may be doped to at least about 10⁻⁶ with one or more suitable conductivity-enhancing dopants. 22 atoms / cm 3The concentration. The semiconductor material in region 60a may be the same as the semiconductor material in region 60c, as shown in the figure, or it may be different from the semiconductor material in region 60c.

[0058] Central region 60b includes material 34. Material 34 may include undoped semiconductor material, such as undoped silicon. The term "undoped" does not necessarily mean that there are absolutely no dopants present in the semiconductor material, but rather that the amount of any dopants present in such semiconductor material is generally understood to be negligible. For example, depending on the context, undoped silicon can be understood to include less than about 10 16 atoms / cm 3 Less than approximately 10 15 atoms / cm 3 The dopant concentration, etc. In some embodiments, material 34 may include silicon, be primarily composed of silicon, or be composed of silicon. In some embodiments, material 34 is a sacrificial material (as referenced below). Figure 10A and 10B The process described is discussed in more detail), and therefore material 34 may include any suitable sacrificial material, including but not limited to undoped semiconductor materials (e.g., undoped silicon).

[0059] Regions 60a-c can be considered as vertically stacked one on top of the other, wherein region 60b is the central semiconductor region (in some embodiments) and is vertically located between regions 60a and 60c.

[0060] Intermediate region 62 alternates with region 60 within stack 52. Region 62 includes material 66. Material 66 may be insulating, conductive, etc. In some embodiments, material 66 may be insulating and may include one or more of, consist primarily of, or consist of one or more of the following: silicon dioxide, alumina, hafnium dioxide, silicon nitride, silicon oxynitride, etc. Regions 62a and 62b may contain the same composition as each other (as shown), or may contain compositions different from each other. One or both of regions 62 may include a homogeneous composition (as shown), or may include a laminate of two or more different compositions.

[0061] Although stack 52 is shown as including three regions 60 (which may be semiconductor material-containing regions) and two interposer regions 62, it should be understood that the stack may include any suitable number of regions 60 and 62. In some embodiments, stack 52 may include at least three regions 60 and at least two interposer regions 62.

[0062] Region 60 can be formed to any suitable thickness, and in some embodiments, it can be formed to a thickness in the range of about 100 nanometers (nm) to about 300 nm. Region 62 can be formed to any suitable thickness, and in some embodiments, it can be formed to a thickness in the range of about 5 nm to about 20 nm.

[0063] Material 58 may be a metallic material, and in some embodiments may include one or more of tungsten, tungsten silicide, etc., be mainly composed of one or more of tungsten, tungsten silicide, etc., or be composed of one or more of tungsten, tungsten silicide, etc.

[0064] The opening 80 is formed as a stack 52 extending through the intermediate region 14. The opening 80 is annular and forms the stacked region as an island 41, wherein the lower portion of the island 41 (lower conductive structure) is as follows: Figure 5A The island 40 of the conductive material 58 is shown. The annular opening 80 is in... Figure 5 The opening is shown as a square in the top view. In other embodiments, the opening may have other suitable closed shapes in such a top view, and may be, for example, elliptical, circular, rectangular, polygonal, etc.

[0065] In some embodiments, opening 80 may be referred to as a first opening. Each opening 80 has a lateral width W. Such width can be any suitable width, and in some embodiments, it can be in the range of about 5 nanometers to about 10 micrometers.

[0066] Figure 5-5A The integrated assembly can be considered as corresponding to construction 77.

[0067] See Figure 6 and 6A Materials 81, 30 and 83 are formed above the surface of stack 52 and within opening 80.

[0068] Materials 81 and 83 may comprise any suitable composition, and in some embodiments may comprise silicon dioxide, silicon nitride, aluminum oxide, etc., primarily composed of silicon dioxide, silicon nitride, aluminum oxide, etc., or composed of silicon dioxide, silicon nitride, aluminum oxide, etc. Materials 81 and 83 may or may not be the same composition as each other. Materials 81 and 83 may be formed to any suitable thickness, and may or may not be formed to the same thickness as each other. In some embodiments, materials 81 and 83 will be formed to be in a position from about The thickness is approximately one-third of the width W of the opening 80 (where the width W is within...). Figure 5 and 5A (as shown in the image).

[0069] In some embodiments, material 30 may be referred to as a protective material because it can withstand subsequent etching conditions (see below). Figure 10A and 11A (Description of such etching conditions). In some embodiments, material 30 may be an insulating material. Alternatively, material 30 may be a conductive material.

[0070] Material 30 may comprise any suitable composition. In some embodiments, material 30 may comprise one or more of a metallic material, a semiconductor material, doped silicon oxide, doped silicon nitride, silicon oxynitride, and carbon. For example, material 30 may comprise carbon-doped silicon oxide (e.g., silicon dioxide), silicon oxide primarily composed of carbon-doped silicon oxide (e.g., silicon dioxide), or silicon oxide primarily composed of carbon-doped silicon oxide (e.g., silicon dioxide); wherein the carbon concentration is about 10. 15 atoms / cm 3 To about 10 25 atoms / cm 3 Within the range. As another example, material 30 may comprise carbon-doped silicon nitride, silicon nitride primarily composed of carbon-doped silicon nitride, or silicon nitride composed of carbon-doped silicon nitride; wherein the carbon concentration is approximately 10. 15 atoms / cm 3 To about 10 25 atoms / cm 3 Within the range. As another example, material 30 may include SiON, be primarily composed of SiON, or be composed of SiON, wherein the chemical formula indicates the major component rather than a specific stoichiometry. In some embodiments, SiON may be referred to as silicon oxynitride. Si and O may be present at concentrations ranging from about 20 atomic percent (atomic %) to about 70 atomic %, and nitrogen may be present at concentrations ranging from about 0.01 atomic % to about 35 atomic %, within a range of about 10 15 atoms / cm 3 To about 10 25 atoms / cm 3 The material is present at a concentration within a certain range. As another example, material 30 may include carbon, be primarily composed of carbon, or be composed of carbon. Carbon may be in any suitable form and in some embodiments may be completely amorphous, or at least substantially completely amorphous, wherein the term "substantially completely amorphous" means completely amorphous within reasonable tolerances of manufacturing and measurement. As another example, material 30 may include metals, metal nitrides, etc., and may include, for example, tungsten (W), titanium (Ti), tungsten nitride (WN), and titanium nitride (TiN), primarily composed of tungsten (W), titanium (Ti), tungsten nitride (WN), and titanium nitride (TiN), or composed of tungsten (W), titanium (Ti), tungsten nitride (WN), and titanium nitride (TiN). As another example, material 30 may include semiconductor materials and may include, for example, silicon (e.g., polycrystalline silicon, amorphous silicon, etc.), primarily composed of silicon, or be composed of silicon.

[0071] Material 30 can have any suitable thickness, and in some embodiments, it can have a thickness ranging from about 5 angstroms. The thickness is approximately one-third of the width W of the opening 80 (where the width W is within...). Figure 5 and 5A (as shown in the image).

[0072] refer to Figure 7 and 7A The planarized surface 61 is formed to extend across the upper surface of the stack 52 and across the materials 30, 81, and 83 within the opening 80. The planarized surface 61 can be formed using any suitable process, including, for example, chemical-mechanical polishing (CMP).

[0073] The planarization surface 61 is formed by removing excess sacrificial materials 30, 81, and 83 from above the stack 52, and forming the remaining materials 30, 81, and 83 into a plug 85. The plug 85 is annular and may alternatively be referred to as a ring, loop, annular structure, ring, etc. The ring 85 comprises a laminate of the three materials 30, 81, and 83. In other embodiments, other materials may be incorporated into the ring 85. Generally, the ring 85 will comprise at least two materials; at least one of the materials is a protective material 30, and at least one of the materials is an insulating material. In some embodiments, the protective material may be an insulating material of the laminate, and there may be another material of the laminate that may or may not be insulating.

[0074] A ring 85 surrounds an island 41 and includes a lower conductive structure 40 surrounding such an island.

[0075] refer to Figure 8-8B A second stack 68 is formed above the first stack 52. The second stack 68 has alternating first levels 70 and second levels 72. The first level 70 includes material 74, and the second level 72 includes material 76. Materials 74 and 76 may include any suitable composition. In some embodiments, material 74 may include silicon nitride, and may be composed primarily of silicon nitride or of silicon nitride; and material 76 may include silicon dioxide, and may be composed primarily of silicon dioxide or of silicon dioxide. Material 74 may be referred to as a sacrificial material, and material 76 may be referred to as an insulating material. Stack 68 may include any suitable number of levels 70 and 72, and in some embodiments may include more than Figure 8A and 8B More of these levels are explained in the document.

[0076] Unit material pillars 16 are formed within memory regions 12a and 12b. Pillars 16 may be substantially identical to each other, where the term "substantially identical" means identical within reasonable manufacturing and measurement tolerances. Pillars 16 may be arranged in a compact package, such as a hexagonal close-packed (HCP) arrangement, within each of memory regions 12a and 12b. Hundreds, thousands, millions, etc., of pillars 16 may be arranged within each of memory regions 12a and 12b.

[0077] Each of the pillars 16 includes an outer region 18 containing memory cell material, a channel material 20 adjacent to the outer region 18, and an insulating material 22 surrounded by the channel material 20.

[0078] The cell material within region 18 may include tunneling materials, charge storage materials, and charge blocking materials. The tunneling material (also referred to as the gate dielectric material) may include any suitable composition; and in some embodiments may include one or more of silicon dioxide, alumina, hafnium dioxide, zirconium oxide, etc. The charge storage material may include any suitable composition; and in some embodiments may include a floating gate material (e.g., polycrystalline silicon) or a charge trapping material (e.g., one or more of silicon nitride, silicon oxynitride, conductive nanodots, etc.). The charge blocking material may include any suitable composition; and in some embodiments may include one or more of silicon dioxide, alumina, hafnium oxide, zirconium oxide, etc.

[0079] The channel material 20 includes a semiconductor material. The semiconductor material may include any suitable composition, and in some embodiments may include one or more of, or consist primarily of, or consist of: silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; wherein the term III / V semiconductor material refers to a semiconductor material comprising elements selected from Groups III and V of the periodic table (where Groups III and V are old nomenclature and are now referred to as Groups 13 and 15). In some embodiments, the semiconductor material may include suitably doped silicon, consist primarily of suitably doped silicon, or consist of suitably doped silicon.

[0080] The channel material 20 can be considered as configured as channel material pillars 24. In the illustrated embodiment, the channel material pillars 24 are configured as Figure 8 The rings in the top view, where such rings surround the insulating material 22. This configuration of the channel material pillars can be considered as corresponding to a “hollow” channel configuration, where the insulating material 22 is disposed within the cavities of the channel material pillars. In other embodiments, the channel material 22 may be configured as solid pillars. In some embodiments, the channel material pillars within memory region 12a may be referred to as first channel material pillars, and the channel material pillars within memory region 12b may be referred to as second channel material pillars. The channel material pillars may be arranged in any suitable configuration within the first memory region 12a and the second memory region 12b. In some embodiments, the channel material pillars may be arranged in a compact package configuration, for example, in a hexagonal close-packed (HCP) configuration.

[0081] The insulating material 22 may include any suitable composition, and in some embodiments may include silicon dioxide, be composed primarily of silicon dioxide, or be composed of silicon dioxide.

[0082] The unit material column 16 is formed to extend through the first stack 68 and partially into the second stack 52, as shown. Figure 8BAs shown in the illustration. In the illustrated embodiment, the unit material pillar 16 extends into the lower region 60a of the stack 52, but does not extend into the conductive material 58.

[0083] The pillar 26 is formed to extend through the second stack 68 within the intermediate region 14 and into the island 41. In the illustrated embodiment, the pillar 26 directly abuts against the upper surface of the conductive material 58 of the island 41. In other embodiments, the pillar may extend into the conductive material 58 or may terminate above the conductive material 58.

[0084] Each of the pillars 26 comprises a conductive material 28 laterally surrounded by an insulating liner 29. The pillars 26 can be arranged in any suitable configuration and may or may not have the same size and composition as each other. Hundreds, thousands, millions, etc., of pillars 26 may be arranged within the intermediate zone 14.

[0085] The conductive material 28 may include any suitable conductive composition, such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, the conductive material 28 may include one or more of tungsten, titanium nitride, and tungsten nitride. For example, the conductive material 28 may include a conductive liner comprising one or both of titanium nitride and silicon nitride along the insulating liner material 29, and may include tungsten filler laterally surrounded by the conductive liner.

[0086] The insulating liner 29 may include any suitable composition, and in some embodiments may include silicon dioxide, consisting primarily of silicon dioxide, or consisting of silicon dioxide.

[0087] In some embodiments, the conductive material 28 of the pillar 26 may be configured as a conductive pillar 32. Such a conductive pillar may be "live" and therefore can be used as an electrical interconnect. Alternatively, the pillar may be "dummy" and may be used solely to provide structural support.

[0088] The lower portion of the conductive post 32 is shown as being laterally surrounded by a ring 85. In some embodiments, the ring 85 may be considered as being spaced apart from the material 28 of the conductive post 32 by an intermediate region 37, which includes lining material 29 and portions of materials 34, 64, and 66 of regions 60a, 60b, 60c, 62a, and 62b.

[0089] In the illustrated embodiment, each of the islands 41 supports one of the conductive posts 32. In other embodiments, at least one of the islands 41 may support two or more of the conductive posts 32.

[0090] Intermediate region 14 may include a number of regions associated with the integrated memory, including, for example, stepped regions, peak regions, bridging regions, etc. If pillar 26 is a charged pillar, such pillars can be used to interconnect components associated with memory regions 12a and 12b to the circuitry below the illustrated region of the integrated assembly 10. For example, conductive pillars can be used to connect bit lines to sensing circuitry (e.g., sensing amplifier circuitry), to connect SGD devices to control circuitry, etc.

[0091] The described pillar 26 extends through the first stack 68, through regions 60 and 62 of the second stack 52, and reaches the conductive material 58, as shown. Figure 8A As shown in the diagram, conductive pillar 32 is electrically coupled to conductive island 40, which includes conductive material 58. In embodiments where the conductive pillar is a "charged" pillar, it may be coupled to CMOS circuitry 56. Alternatively, in embodiments where at least some of the conductive pillars are provided in a "dummy" configuration for structural support rather than for electrical connection, at least some of the conductive pillars may not be coupled to the CMOS circuitry.

[0092] The slit opening 82 is formed to extend across memory regions 12a and 12b and across intermediate region 14. Figure 8 It is shown in a dashed (shadow) view to indicate its location. Figure 8 The cross-section shown is above.

[0093] The slit opening 82 passes through the first stack 68 and enters the second stack 52. In the illustrated embodiment, the slit opening stops at material 34. In other embodiments, the slit opening may extend into material 34.

[0094] In the illustrated embodiment, the slit opening has a generally vertical sidewall surface; the term "generally vertical" means vertical within reasonable manufacturing and measurement tolerances. In other embodiments, the sidewall surface of the slit opening may be tapered.

[0095] A protective material 84 is formed within the slit opening 82 and along the sidewall surface of the slit opening. The protective material 84 may comprise any suitable composition. In some embodiments, the protective material 84 may comprise silicon, be primarily composed of silicon, or be composed of silicon; and specifically may comprise effectively undoped silicon (e.g., including an inherent dopant concentration, and in some embodiments, including less than or equal to about 10). 16 atoms / cm 3 (dopant concentration). In some embodiments, the protective material 84 may include one or more of the following: metals (e.g., tungsten, titanium, etc.), metal-containing materials (e.g., metal silicides, metal nitrides, metal carbides, metal borides, etc.) and semiconductor materials (e.g., silicon, germanium, etc.).

[0096] refer to Figure 9A and 9B One or more etching operations are used to penetrate the protective material 84 at the bottom of the slit opening 82 to expose the central semiconductor material region 60b of the first stack 52. Removing the protective material 84 from the bottom of the slit opening 82 exposes the memory region (e.g., Figure 9B Within memory area 12a) and intermediate area 14 Figure 9A Material 34 within )

[0097] refer to Figure 10A and 10B The sacrificial material 34 in the central region 60b is removed to form a conduit 86 in regions 12a, 12b and 14 (where regions 12a and 14 are in Figure 10B and 10A (as shown in the image).

[0098] The conduit 86 can be formed using any suitable process, and in some embodiments it can be formed using one or more etchants containing hydrofluoric acid. In the illustrated embodiment, intermediate regions 62a and 62b are retained after the conduit 86 is formed. In other embodiments, depending on the composition of the intermediate regions and the composition of the etchant used to remove material 34, such intermediate regions can be removed during conduit formation.

[0099] Figure 10A The diagram illustrates the etching of material 81 during the formation of conduit 86, and the protective material 30 being resistant to the etchant used to form conduit 86. In some embodiments, material 34 exposed within slit 82 may be considered selectively removed relative to the protective material 30. For the purposes of interpreting this disclosure and the appended claims, if the removal rate of the first material is faster than that of the second material, then the first material is considered selectively removed relative to the second material; this may include, but is not limited to, a condition where the first material is 100% selective relative to the second material.

[0100] The removal of the area of ​​material 81 along the conduit 85 exposes material 30 along the outer transverse edge 65 of the ring (plug) 85.

[0101] refer to Figure 11B The conduit 86 extends through the unit material 18 to expose the sidewall surface of the semiconductor material (channel material) 20. Figure 11A This demonstrates that no significant changes occur within the intermediate region 14 during the extension of the conduit 86 through the unit material 18. In other words, the protective material 30 is resistant to etching used to extend the conduit 86 through the unit material 18.

[0102] See Figure 12A and 12B The conductive doped semiconductor material 88 is formed inside the conduit 86. Figure 11A and 11B Semiconductor material 88 may comprise any suitable composition; and in some embodiments may comprise one or more of, consist primarily of, or consist of one or more of the following: silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc. In some embodiments, semiconductor material 88 may comprise heavily doped (e.g., doped to at least about 10) with an n-type dopant (e.g., phosphorus, arsenic, etc.). 22 atoms / cm 3 The silicon concentration is ( ). The conductive material 88 can be considered as a source structure component 90 configured to be coupled to the lower region of the channel material pillar 24. In some embodiments, Figure 12B The material within the first stack 52 can all be considered as part of the conductive electrode structure 43. Regions 62a and 62b can be... Figure 10A and 10B The catheter 86 was removed during its formation (as referenced above). Figure 10A and 10B (as discussed), such regions are not part of the source structure including stack 52. In some embodiments, regions 62a and 62b may be conductive so that they do not adversely affect the conductivity along source structure 43, or may be insulating and kept thin enough so that they do not problematically affect the conductivity along source structure 43.

[0103] Material 88 is transformed into memory regions 12a and 12b (in Figure 12B The central region 60b of the stack 52 in region 12a) is shown, and the channel material 20 is in direct contact with the channel material column 24.

[0104] In the illustrated embodiment, material 88 directly contacts protective material 30 along the outer lateral edge 65 of ring 85 within intermediate region 14. Figure 12A In some embodiments, the protective material 30 may be a metal-containing material, and such a metal-containing material may directly contact the doped semiconductor material 88.

[0105] Ring 85 has an uppermost surface 87 that extends together with the uppermost surface of stack 52 and thus with the uppermost surface of source structure 43 within memory regions 12a and 12b.

[0106] In some embodiments, material 88 may be referred to as a first semiconductor material, and material 34 may be referred to as a second semiconductor material. The first semiconductor material and the second semiconductor material may comprise the same semiconductor composition as each other (e.g., may comprise silicon, be primarily composed of silicon, or be composed of silicon), or may comprise semiconductor compositions that are different from each other.

[0107] A ring 85 is located between the conductive post 32 and the doped first semiconductor material 88. In the illustrated embodiment, the outer lateral edge 65 of the ring 85 directly contacts the first semiconductor material 88, and the intervening region 37 between the conductive post 32 and the ring 85 contains a second semiconductor material 34.

[0108] refer to Figure 13A and 13B Materials 84 and 88 are removed from the opening (slit) 82 by one or more suitable etching processes. Any suitable etchant can be used to remove the material. The slit opening 82 can be punched to any suitable depth within the source structure 43.

[0109] The dopant diffuses outward from the conductive doped semiconductor material 88 into the semiconductor material (channel material) 20 to form a heavily doped region 92 in the lower portion of the channel material pillar 24. The approximate upper boundary of the dopant within the heavily doped region 92 is indicated by line 93.

[0110] Outward diffusion from the doped material 88 to the semiconductor material 20 can be achieved by any suitable process, including, for example, suitable heat treatment (e.g., heat treatment at a temperature exceeding about 300°C for a duration of at least about two minutes).

[0111] Tier 1, 70 sacrificial materials, 74 ( Figure 12A and 12B The conductive material 94 is removed and replaced with conductive material 94. Although conductive material 94 is shown to completely fill the first layer 70, in other embodiments, at least some of the materials disposed within the first layer 70 may be insulating materials (e.g., dielectric barrier materials).

[0112] The conductive material 94 may include any suitable composition; and in some embodiments may include a tungsten core at least partially surrounded by titanium nitride. The dielectric barrier material may include any suitable composition; and in some embodiments may include one or more of alumina, hafnium dioxide, zirconium oxide, etc.

[0113] Figure 13A The first layer 70 of 213B is a conductive layer, and the stack 68 can be considered as including alternating insulating layers (intervention layers) 72 and conductive layers 70.

[0114] In the illustrated embodiment, the conductive material 94 of the conductive layer 70 is spaced apart from the conductive material 28 of the pillar 26 by the insulating liner material 29.

[0115] See Figure 14A and 14BPanel material 96 is formed within the slit opening 82. Panel material 96 may comprise any suitable composition; and in some embodiments may comprise, consist primarily of, or consist of silicon dioxide. Although panel material 96 is shown as a single homogeneous composition, in other embodiments, panel material may comprise a laminate of two or more different compositions.

[0116] Panel material 96 is formed across the memory region (e.g., Figure 14B 12a) and the intermediate area ( Figure 14A The extended panel 98 of area 14)

[0117] Figure 14B The assembly 10 can be considered as a memory device including memory cell 100 and select device (SGS device) 102. The lowermost of the conductive layer 70 is designated 70a, and the doped region 92 extends into the conductive layer 70a. The conductive layer 70a includes the SGS device 102. In the illustrated embodiment, the dopant extends partially across layer 70a to achieve the desired balance between the non-drain "off" characteristics and the leakage GIDL characteristics of the SGS device.

[0118] Although only one of the conductive layers is shown as being incorporated into the SGS device, in other embodiments, multiple conductive layers may be incorporated into the SGS device. The conductive layers may be electrically coupled (joined together) to be incorporated into the long-channel SGS device. If multiple conductive layers are incorporated into the SGS device, outwardly diffusing dopant may extend upward across two or more conductive layers 70 incorporated into the SGS device.

[0119] Memory cells 100 (e.g., NAND memory cells) are stacked vertically on top of each other. Each memory cell includes a region of semiconductor material (channel material) 20 and a region of conductive layer 70 (control gate region). Regions of conductive layer 70 not included by memory cell 100 may be considered word line regions (or wiring regions) that couple the control gate region to driver circuitry and / or other suitable circuitry. Memory cell 100 includes cell material (e.g., tunneling material, charge storage material, and charge blocking material) within region 18.

[0120] In some embodiments, the conductive level 70 associated with memory cell 100 may be referred to as a word line / control gate level (or memory cell level) because it contains word lines and control gates associated with the vertically stacked memory cells of the NAND string. The NAND string may include any suitable number of memory cell levels. For example, a NAND string may have 8 memory cell levels, 16 memory cell levels, 32 memory cell levels, 64 memory cell levels, 512 memory cell levels, 1024 memory cell levels, etc.

[0121] Source structure 43 may be similar to source structure 216 described in the "Background Art" section. The source structure is shown coupled to a control circuitry system (e.g., CMOS) 56c, as illustrated. The control circuitry system may be located within the source structure (as illustrated) or in any other suitable location. The source structure may be coupled to the control circuitry system 56c at any suitable processing stage.

[0122] In some embodiments, the channel material column 24 can be considered as representing a span. Figure 14B The memory region 12a extends from a plurality of substantially identical channel material pillars, wherein the term “substantially identical” means identical within reasonable manufacturing and measurement tolerances. Panel 98 may be divided into pillars between a first block region 104 and a second block region 106. Therefore, a memory cell 100 on one side of panel 98 may be considered to be within the first block region (memory block region) 104, and a memory cell 100 on the other side of panel 98 may be considered to be within the second block region (memory block region) 106. Block regions 104 and 106 may be similar to the memory block (or memory sub-block) described above in the “Background Art” section of this disclosure.

[0123] Figure 15A and 15B Show Figure 14A and 14B The configuration is shown, and various structures extending vertically and coupled to additional circuit elements are illustrated (e.g., panel 98, conductive pillar 26, and unit material pillar 16). Stack 68 may extend vertically to extend along a considerable portion of structures 98, 26, and 16.

[0124] Figure 15B The unit material column 16 extends upward to the bit line 108. The SGD device 110 is shown in the schematic as adjacent to the upper region of the column 16 and below the bit line 108.

[0125] Bit line 108 can extend into and out relative to Figure 15B The page with the cross-sectional view.

[0126] Pillar 16, bit line 108, SGD device 110, SGS device 102 and memory cell 100 can be considered together as forming a NAND-type configuration similar to those described above with reference to Figures 1-4.

[0127] exist Figure 15B In the view, the SGD device 110 is indicated to be coupled to the conductive post 32, and... Figure 15AIn the view, conductive post 32 is indicated to be coupled to SGD device 110. Therefore, in some embodiments, SGD device 110 associated with memory region 12a can be coupled to logic circuitry (e.g., 56a and 56b) via conductive post 32 associated with intermediate region 14.

[0128] SGD device 110 is an example of a component that can be associated with cell material pillar 16 and coupled to a logic circuit system via conductive pillar 32. In other embodiments, as an alternative to or supplement to SGD device 110, other components may be coupled to the logic circuit system via one or more of the conductive pillars 32. For example, bit lines may be coupled to the logic circuit system via conductive pillar 32, and in such embodiments, the logic circuit system may include sensing circuitry (e.g., sensing amplifier circuitry) coupled to bit lines via conductive pillar 32. Typically, one or more components may be operatively located near cell material pillar 16 (and / or channel material pillar 24) and coupled to the logic circuit system 56 via conductive pillar 32.

[0129] Figure 15C Show along Figure 15A and 15B A top view of section CC. Panel 98 extends across memory regions 12a and 12b and across intermediate region 14. Panel 98 is laterally positioned between first memory block region 104 and second memory block region 106, and further divides the first memory block region 104 and second memory block region 106 (i.e., separates the first memory block region from the second memory block).

[0130] In the illustrated embodiment, the doped semiconductor material 88 is adjacent to segments of panel 98 within the intermediate region 14, memory region 12a, and memory region 12b. The doped semiconductor material 88 within memory regions 12a and 12b is adjacent to and electrically coupled to channel material pillars 24. In contrast, the doped semiconductor material 88 is not adjacent to conductive pillars 32, but is spaced apart from such conductive pillars by a plurality of materials; at least one of these materials is electrically insulating.

[0131] Figure 15C The illustrated panel 98 may be one of a plurality of panels extending across regions 12a, 12b, and 14 and spacing the first and second memory block regions apart from each other. Therefore, the illustrated memory block regions 104 and 106 may represent regions that can be constructed by means of... Figure 15C The processing stage represents the formation of a large number of memory blocks.

[0132] In some embodiments, Figure 15A and 15CThe ring (plug) 85 can be considered as a laminate of two or more materials, and the laminate shown includes three materials 81, 30, and 83. At least one of the materials is configured as a groove, and at least one of the other materials extends into said groove. For example, material 81 can be considered as configured as a groove, and materials 30 and 83 can be considered as extending into this groove. Furthermore, material 30 can be considered as configured as a groove, and material 83 can be considered as extending into this groove.

[0133] In some embodiments, ring 85 can be considered as corresponding to Figure 15C The outer ring in the arrangement, and such an outer ring can be regarded as an inner ring 89 surrounding the semiconductor material 34.

[0134] refer to Figure 16 -18 describes another example implementation. Figure 16 Shown in Figure 5A The intermediate zone 14 of the assembly 10 after the process stage. Materials 30 and 83 are formed above the surface of the stack 52 and within the opening 80.

[0135] See Figure 17 The planarization surface 61 is formed to extend across the upper surface of the stack 52 and across materials 30 and 83. The formation of the planarization surface 61 removes excess sacrificial materials 30 and 83 from above the stack 52 and forms the remaining materials 30 and 83 into an annular plug 85. The plug 85 comprises a laminate of the two materials 30 and 83.

[0136] See Figures 18A-18C The second stack 68 is formed above the first stack 52, and utilizes a similar method to that described above relative to... Figure 8 The process described in -15 is used to form various structures (e.g., panel 98, conductive pillar 26, cell material pillar 16, memory cell 100, SGS device 102, etc.). Cell material pillar 16 extends upward to bit line 108. SGD device 110 is below bit line 108 and is indicated to be coupled to conductive pillar 32. Figure 18C The top view shows panel 98 extending across memory regions 12a and 12b and across intermediate region 14. Panel 98 is laterally positioned between first memory block region 104 and second memory block region 106, and further divides the first memory block region 104 and the second memory block region 106.

[0137] refer to Figure 19 -22 describes another example implementation. Figure 19 and 19A Shown in Figure 5 and 5AThe assembly 10 is in the area following the process stage. Material 81 is formed above the surface of the stack 52 and within the opening 80 to form a deep groove within the opening and thus narrow the opening. The narrowed area of ​​the opening 80 retained within the deep groove can be considered as a seam.

[0138] See Figure 20 Protective material 30 is formed within the joint to fill the opening 80.

[0139] See Figure 21 The planarization surface 61 is formed to extend across the upper surface of the stack 52 and across materials 30 and 81. The formation of the planarization surface 61 removes excess sacrificial materials 30 and 81 from above the stack 52 and forms the remaining materials 30 and 81 into an annular plug 85. The plug 85 comprises a laminate of the two materials 30 and 81.

[0140] See Figures 22A-22C The second stack 68 is formed above the first stack 52, and utilizes a similar method to that described above relative to... Figure 8 The process described in -15 is used to form various structures (e.g., panel 98, conductive pillar 26, cell material pillar 16, memory cell 100, SGS device 102, etc.). Cell material pillar 16 extends upward to bit line 108. SGD device 110 is below bit line 108 and is indicated to be coupled to conductive pillar 32. Figure 22C The top view shows panel 98 extending across memory regions 12a and 12b and across intermediate region 14. Panel 98 is laterally positioned between first memory block region 104 and second memory block region 106, and further divides the first memory block region 104 and the second memory block region 106.

[0141] The assemblies and structures discussed above can be utilized within integrated circuits (where the term "integrated circuit" refers to electronic circuits supported by a semiconductor substrate); and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and so on.

[0142] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0143] The terms “dielectric” and “insulating” can be used to describe materials having insulating electrical properties. These terms are considered synonymous in this invention. The term “dielectric” in some cases and the term “insulating” (or “electrically insulating”) in others may be used within this disclosure to provide linguistic variation to simplify the premises of the following claims, rather than to indicate any significant chemical or electrical differences.

[0144] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. The terms are considered synonymous. The use of one term in some instances and another in others may be to provide linguistic variation within this disclosure to simplify the presuppositions in the appended claims.

[0145] The specific orientations of the various embodiments in the figures are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. The descriptions provided herein and the appended claims relate to any structure having the described relationships between various features, regardless of whether the structure is in the specific orientation of the figures or rotated relative to such an orientation.

[0146] Unless otherwise specified, the cross-sectional views in the accompanying drawings show only the features within the plane of the cross-section and do not show the material behind the plane of the cross-section in order to simplify the drawings.

[0147] When a structure is referred to as "on another structure," "adjacent to another structure," or "against another structure," the structure may be directly on the other structure or there may be an intervening structure. Conversely, when a structure is referred to as "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there is no intervening structure. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless otherwise explicitly stated), but instead indicate upright alignment.

[0148] A structure (e.g., a layer, material, etc.) may be referred to as “vertically extending” to indicate that the structure extends generally upward from the underlying substrate (e.g., a base plate). A vertically extending structure may or may not extend generally orthogonally relative to the upper surface of the substrate.

[0149] Some embodiments include an integrated assembly having a memory region and another region adjacent to the memory region. Channel material pillars are disposed within the memory region, and conductive pillars are disposed within the other region. A source structure is coupled to a lower region of the channel material pillars. A panel extends across the memory region and the other region, and separates a first memory block region from a second memory block. Doped semiconductor material is disposed adjacent to the panel within the memory region and the other region. The doped semiconductor material is at least a portion of the source structure within the memory region. A ring laterally surrounds the lower region of the conductive pillars. The ring is located between the conductive pillars and the doped semiconductor material. The ring comprises a laminate of two or more materials, at least one of which is insulating. At least one of the materials is configured as a trench, and another of the materials extends into the trench.

[0150] Some embodiments include an integrated assembly comprising a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. A first channel material pillar is disposed within the first memory region. A second channel material pillar is disposed within the second memory region. Conductive pillars are disposed within the intermediate region. A panel extends across the first memory region, the intermediate region, and the second memory region. The panel is laterally positioned between the first and second memory block regions. A first doped semiconductor material is disposed within the first, second, and intermediate regions and adjacent to the panel. The first doped semiconductor material is at least a portion of the conductive electrode structure within the first and second memory regions. A ring laterally surrounds the lower region of the conductive pillars and is located between the conductive pillars and the first doped semiconductor material. The ring comprises a laminate of two or more materials. An inner region of the ring is spaced from the conductive pillars by an intermediate region comprising a second semiconductor material. The first doped semiconductor material directly contacts the outer lateral edge of the ring.

[0151] Some embodiments include a method of forming an integrated assembly. The configuration is formed to include a first memory region, a second memory region laterally offset from the first memory region, and an intermediate region laterally located between the first and second memory regions. The configuration includes a first stack extending across the first memory region, the second memory region, and the intermediate region. The first stack includes a metallic material, and alternating semiconductor material regions and intermediate regions above the metallic material. At least three semiconductor material regions are present, one of which is a central semiconductor material region and vertically located between two other semiconductor material regions. A ring is formed to extend through the first stack. Island-like structures of the first stack are surrounded by the ring, wherein the island-like structures include a lower conductive structure comprising a metallic material. The ring includes a laminate of two or more materials, at least one of which is insulating. A second stack is formed above the first stack and the ring. The second stack includes alternating first and second levels, wherein the first level includes a sacrificial material and the second level includes an insulating material. A pillar is formed to extend through the second stack of the first and second memory regions and at least partially enter the first stack of the first and second memory regions. The pillar includes cell material and channel material. Conductive pillars extend through a second stack in the intermediate region and into an island. The conductive pillars are electrically coupled to the lower structure of the island. A slit opening is formed to extend through the second stack and reach a central semiconductor material region in the first stack. The slit opening extends across a first memory region, an intermediate region, and a second memory region. The central semiconductor material region is removed from the first memory region, the intermediate region, and the second memory region, wherein one or more etchants flow into the slit opening. At least one of the ring materials is resistant to the one or more etchants. The removal of the central semiconductor material region forms a conduit in the first stack within the first and second memory regions. The conduit extends through the cell material and reaches the channel material of the pillar. A doped semiconductor material is formed within the extending conduit. Dopant diffuses outward from the doped semiconductor material into the channel material. The outwardly diffused dopant extends upward to at least one of the first layers. At least some of the sacrificial materials in the first layers are replaced with conductive material.

[0152] As per the regulations, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes exemplary embodiments. Therefore, the claims have the full scope as stated in the writings and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. An integrated assembly comprising: The memory area and another area adjacent to the memory area; Channel material pillars arranged in the memory region and conductive pillars arranged in the other region; A source structure coupled to the lower region of the channel material pillar; A panel that extends across the memory region and the other region, and separates the first memory block region from the second memory block region; A doped semiconductor material is disposed adjacent to the panel in the memory region and the other region; the doped semiconductor material is at least a portion of the source structure in the memory region; as well as A ring that laterally surrounds the lower region of the conductive pillar; the ring is between the conductive pillar and the doped semiconductor material; the ring comprises a laminate of two or more materials, wherein at least one of the materials is configured as a groove and another of the materials extends into the groove; and wherein one or more of the materials are insulating.

2. The integrated assembly of claim 1, wherein the uppermost surface of the ring extends together with the uppermost surface of the source structure.

3. The integrated assembly of claim 1, wherein at least some of the conductive pillars are coupled to a logic circuit system beneath the at least some of the conductive pillars.

4. The integrated assembly of claim 1, wherein the doped semiconductor material comprises silicon.

5. The integrated assembly of claim 1, wherein one of the materials of the laminate comprises silicon dioxide.

6. The integrated assembly of claim 1, wherein one of the materials of the laminate comprises carbon-doped silicon oxide.

7. The integrated assembly according to claim 6, wherein the carbon concentration is approximately 10. 15 atoms / cm 3 To about 10 25 atoms / cm 3 Within the range.

8. The integrated assembly of claim 1, wherein one of the materials of the laminate comprises carbon-doped silicon nitride.

9. The integrated assembly according to claim 8, wherein the carbon concentration is approximately 10%. 15 atoms / cm 3 To about 10 25 atoms / cm 3 Within the range.

10. The integrated assembly of claim 1, wherein one of the materials of the laminate comprises SiON, wherein the chemical formula indicates a major component rather than a specific stoichiometry.

11. The integrated assembly of claim 1, wherein one of the materials of the laminate is a metallic material.

12. The integrated assembly of claim 11, wherein the metal-containing material is a metal nitride.

13. The integrated assembly of claim 11, wherein the metallic material comprises one or more of W, Ti, WN, and TiN.

14. The integrated assembly of claim 1, wherein one of the materials of the laminate is composed of silicon.

15. The integrated assembly of claim 1, wherein one of the materials of the laminate is substantially composed of carbon.

16. The integrated assembly of claim 15, wherein the carbon is substantially entirely in an amorphous phase.

17. The integrated assembly of claim 1, comprising a vertically stacked conductive layer above the memory region and the other region; and wherein the channel material pillars and the pillars extend through the vertically stacked conductive layer.

18. The integrated assembly of claim 17, wherein the upper conductive layer of the vertically stacked conductive layers is a memory cell layer, and the lower conductive layer of the vertically stacked conductive layers is a selection device layer.

19. The integrated assembly of claim 1, wherein each of the rings is an outer ring that laterally surrounds an inner ring comprising a second semiconductor material.

20. The integrated assembly of claim 19, wherein the second semiconductor material is composed of silicon.

21. An integrated assembly comprising: A first memory region, a second memory region offset from the first memory region, and an intermediate region between the first memory region and the second memory region; A first channel material column is arranged within the first memory region; The second channel material column is arranged within the second memory region; Conductive pillars are arranged within the intermediate area; A panel that extends across the first memory region, the intermediate region, and the second memory region; the panel is laterally positioned between the first memory block region and the second memory block region. A first semiconductor material is doped within and adjacent to the panel in the first memory region, the second memory region, and the intermediate region; the doped first semiconductor material is at least a portion of the conductive electrode structure in the first memory region and the second memory region. as well as A ring laterally surrounds the lower region of the conductive pillar and lies between the conductive pillar and the doped first semiconductor material; the ring comprises a laminate of two or more materials; the inner region of the ring is spaced apart from the conductive pillar by an intervening region comprising a second semiconductor material; the doped first semiconductor material directly contacts the outer lateral edge of the ring.

22. The integrated assembly of claim 21, wherein one of the materials of the laminate comprises carbon-doped silicon oxide.

23. The integrated assembly of claim 21, wherein one of the materials of the laminate comprises carbon-doped silicon nitride.

24. The integrated assembly of claim 21, wherein one of the materials of the laminate comprises SiON, wherein the chemical formula indicates a major component rather than a specific stoichiometry.

25. The integrated assembly of claim 21, wherein one of the materials of the laminate is substantially composed of carbon.

26. The integrated assembly of claim 21, wherein one of the materials of the laminate is substantially composed of silicon.

27. The integrated assembly of claim 21, wherein one of the materials of the laminate is a metallic material.

28. The integrated assembly of claim 27, wherein the outer lateral edge in direct contact with the doped first semiconductor material comprises the metal-containing material.

29. The integrated assembly of claim 27, wherein the metallic material comprises one or both of Ti and W.

30. The integrated assembly of claim 27, wherein the metal-containing material comprises a metal nitride.

31. The integrated assembly of claim 21, wherein both the first semiconductor material and the second semiconductor material comprise silicon.

32. The integrated assembly of claim 21, wherein the component is operatively close to the channel material pillar and coupled to the conductive pillar, and wherein the conductive pillar is electrically coupled to a logic circuit system.

33. The integrated assembly of claim 32, wherein the component is an SGD device.

34. A method of forming an integrated assembly, comprising: The configuration comprises a first memory region, a second memory region laterally offset from the first memory region, and an intermediate region laterally located between the first memory region and the second memory region; the configuration comprises a first stack extending across the first memory region, the second memory region, and the intermediate region; the first stack comprises a metallic material and alternating semiconductor material regions and intermediate regions above the metallic material; at least three semiconductor material regions are present, wherein one of the semiconductor material regions is a central semiconductor material region and is vertically located between the other two semiconductor material regions; The ring extends through the first stack; islands of the first stack are surrounded by the ring, wherein the islands include a lower conductive structure comprising the metallic material; the ring comprises a laminate of two or more materials, wherein at least one of the two or more materials is insulating; A second stack is formed above the first stack and the ring; the second stack includes alternating first and second levels, wherein the first level includes sacrificial material and the second level includes insulating material; A pillar is formed that extends through the first memory region and the second memory region and at least partially enters the first stack of the first memory region and the second memory region, the pillar comprising cell material and channel material; A second stack is formed extending through the intermediate region and into the island, the conductive pillar being electrically coupled to the lower conductive structure of the island; A slit opening is formed that passes through the second stack and reaches the central semiconductor material region of the first stack; The slit opening extends across the first memory region, the intermediate region, and the second memory region; The central semiconductor material region is removed from the first memory region, the intermediate region, and the second memory region by one or more etchants flowing into the slit opening, at least one of the materials of the ring being resistant to the one or more etchants; the removal of the central semiconductor material region forms a conduit in the first stack within the first memory region and the second memory region; The conduit extends through the unit material and reaches the channel material of the column; Doped semiconductor material is formed within the extended conduit; The dopant diffuses outward from the doped semiconductor material into the channel material, and the outwardly diffused dopant extends upward to at least one of the first layers; as well as Replace at least some of the sacrificial materials in the first layer with conductive materials.

35. The method of claim 34, further comprising forming the source selection device to include at least one of the first layers.

36. The method of claim 34, wherein the two or more materials of the ring further comprise a metal.

37. The method of claim 34, wherein the two or more materials of the ring further comprise a metal nitride.

38. The method of claim 34, wherein the two or more materials of the ring further comprise carbon-doped silicon oxide.

39. The method of claim 34, wherein the two or more materials of the ring further comprise carbon-doped silicon nitride.

40. The method of claim 34, wherein the two or more materials of the ring further comprise SiON, wherein the chemical formula indicates a major component rather than a specific stoichiometry.

41. The method of claim 34, wherein at least one of the two or more materials of the ring is composed of silicon.

42. The method of claim 34, wherein at least one of the two or more materials of the ring is composed of carbon.

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