Flat panel detector, driving method thereof, and x-ray detection apparatus

Abstract

The application provides a flat panel detector, a driving method thereof and an X-ray detection device. The flat panel detector comprises a substrate, a plurality of data lines on the substrate, a plurality of multiplexing circuits respectively coupled to one end of each data line, and a plurality of holding capacitors respectively coupled to the other end of each data line in one-to-one correspondence, wherein each holding capacitor is used to maintain the potential of other data lines as a fixed potential when reading the detection signal of the coupled data line through the multiplexing circuit. The application avoids noise interference in the data reading process of the flat panel detector and improves the image quality of the flat panel detector.

Description

Technical Field

[0001] This invention relates to the field of detection technology, and in particular to a flat panel detector, its driving method, and an X-ray detection device. Background Technology

[0002] X-rays have a high penetrating power, capable of passing through many materials that are opaque to visible light, such as paper and wood. Because X-ray detectors (FPXD) can sense the intensity distribution of X-rays after they pass through an object, they can display images of the object's internal structure on a screen, leading to a wide range of applications in medicine, science, and industry.

[0003] Existing X-ray detection devices typically employ flat panel detectors (FPDs) to convert X-ray information into digital image information. A typical FPD includes multiple intersecting grid lines and data lines, as well as photosensitive pixels defined by these grid lines and data lines. Each photosensitive pixel may include a photodiode and a thin-film transistor (TFT) coupled to the photodiode. The TFT is also connected to the grid lines and data lines. During operation, a scintillator located on the surface of the FPD converts the attenuated X-rays after passing through the human body into visible light. The photodiode converts the visible light into an electrical signal, storing a charge on its own capacitance. A gate scan signal transmitted through the grid lines drives each photosensitive pixel to turn on, allowing the stored charge of each photosensitive pixel to be read out via the data lines connected to the photosensitive pixels. This stored charge is then used to form a digital X-ray image. However, as the refresh rate of FPDs increases and the transistor turn-on time decreases, the delay in transmitting electrical signals becomes larger, reducing the accuracy of the digital X-ray image. Summary of the Invention

[0004] This invention provides a flat panel detector, its driving method, and an X-ray detection device to avoid noise interference during the data reading process of the flat panel detector and improve the image quality of the flat panel detector.

[0005] In a first aspect, embodiments of the present invention provide a flat panel detector, comprising:

[0006] The substrate has multiple data lines on it, a multiplexing circuit coupled to one end of each data line, and multiple holding capacitors coupled to the other end of each data line respectively. Each holding capacitor is used to keep the potential of the other data lines at a fixed potential when the detection signal of the coupled data line is read by the multiplexing circuit.

[0007] In one possible implementation, each of the holding capacitors includes a first electrode and a second electrode that are sequentially separated from the substrate, the second electrode being coupled to the other end of the corresponding data line, and the first electrodes being interconnected and having a potential of the fixed potential.

[0008] In one possible implementation, the flat panel detector further includes a readout circuit coupled to the multiplexing circuit, wherein when the readout circuit reads the detection signal through the multiplexing circuit, the reference potential of the readout circuit is the fixed potential.

[0009] In one possible implementation, the capacitance values ​​of each of the holding capacitors are the same.

[0010] In one possible implementation, the substrate includes a detection region and a peripheral region surrounding the detection region, each of the data lines extends along the detection region in a direction pointing towards the peripheral region, and each of the holding capacitors is disposed on one side near the other end of the corresponding data line.

[0011] In one possible implementation, the plurality of holding capacitors are located in the detection area or the surrounding area.

[0012] In one possible implementation, the detection area includes a gate layer, a gate insulating layer, a semiconductor layer, a first conductive layer, an interlayer insulating layer, a second conductive layer, a photosensitive layer, a transparent wiring layer, and a bias electrode layer, which are sequentially separated from the substrate. Each of the first electrode plates is fabricated in the same layer as the first conductive layer, and each of the second electrode plates is fabricated in the same layer as the bias electrode layer.

[0013] In one possible implementation, the detection region further includes a first passivation layer, a planarization layer, and a second passivation layer located between the transparent trace layer and the bias electrode layer and sequentially facing away from the substrate, an intermediate dielectric layer between each of the first electrode and the second electrode, and a film layer co-fabricated with at least one of the interlayer insulating layer, the first passivation layer, and the second passivation layer.

[0014] In one possible implementation, the flat panel detector further includes a plurality of bonded electrodes located in the peripheral region, each of the first electrode plates being coupled to the transparent electrode layer through a via penetrating the first passivation layer, the planarization layer, and the second passivation layer, and being coupled to the plurality of bonded electrodes.

[0015] In one possible implementation, the flat panel detector further includes a system motherboard located in the peripheral region and a gate drive circuit coupled to the system motherboard, with the plurality of bonding electrodes located on the gate drive circuit.

[0016] In one possible implementation, the flat panel detector further includes a system motherboard located in the peripheral region and coupled to the reading circuit, wherein the plurality of bonding electrodes are located on the reading circuit.

[0017] In one possible implementation, the flat panel detector further includes a plurality of detection units arranged in an array, each detection unit including a switch control unit, the multiplexing circuit including a plurality of switch selection units, wherein each switch selection unit is coupled to one end of a corresponding data line, and the active layer of the transistor included in each switch selection unit and the active layer of the transistor included in each switch control unit are both made of low-temperature polycrystalline silicon material.

[0018] Secondly, embodiments of the present invention also provide an X-ray detection device, comprising:

[0019] Flat panel detectors as described in any of the above items.

[0020] Thirdly, embodiments of the present invention also provide a driving method for a flat panel detector as described in any of the above claims, comprising:

[0021] When the detection signal is read through the multiplexing circuit, a fixed potential is applied to each of the holding capacitors.

[0022] The beneficial effects of this invention are as follows:

[0023] This invention provides a flat panel detector, its driving method, and an X-ray detection device. The flat panel detector includes a substrate, multiple data lines on the substrate, a multiplexing circuit coupled to one end of each data line, and multiple holding capacitors coupled to the other end of each data line. Thus, one end of each data line is coupled to the multiplexing circuit, and the other end is coupled to the multiple holding capacitors. Furthermore, each holding capacitor maintains the potential of other data lines at a fixed potential when the detection signal of the coupled data line is read by the multiplexing circuit. Since each holding capacitor maintains the potential of other data lines at a fixed potential when the detection signal of the coupled data line is read by the multiplexing circuit, noise from other data lines is not introduced during the reading process, thereby avoiding noise interference during the data reading process of the flat panel detector and improving the image quality of the flat panel detector. Attached Figure Description

[0024] Figure 1 A schematic diagram of a portion of the circuit structure of a flat panel detector provided in an embodiment of the present invention;

[0025] Figure 2 for Figure 1The circuit structure shown is a timing diagram of one of the circuit structures;

[0026] Figure 3 This is a schematic diagram of one structure of a flat panel detector provided in an embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of one structure of a flat panel detector provided in an embodiment of the present invention;

[0028] Figure 5 This is a schematic diagram of one structure of a flat panel detector provided in an embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram of one structure of a flat panel detector provided in an embodiment of the present invention;

[0030] Figure 7 For along Figure 3 A schematic diagram of one type of cross-sectional structure in the direction shown in MM;

[0031] Figure 8 For along Figure 3 A schematic diagram of one type of cross-sectional structure in the direction shown in the middle NN;

[0032] Figure 9 This is a schematic diagram of one structure of a flat panel detector provided in an embodiment of the present invention;

[0033] Figure 10 This is a schematic diagram of one structure of a flat panel detector provided in an embodiment of the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Furthermore, the embodiments and features in the embodiments of the present invention can be combined with each other without conflict. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains. The terms "comprising" or "including," or similar terms as used in this invention, mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0036] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0037] In their practical research, the inventors discovered that flat panel detectors employ a large number of readout integrated circuits (ROICs) for reading detection signals, resulting in high costs. Furthermore, limitations in the bonding process prevent effective reduction in product size. Combined with... Figure 1 and Figure 2 As shown, the signal can be read by adding a multiplexer (MUX) unit, where... Figure 1 This is a schematic diagram of a portion of the circuit structure of a flat panel detector. Figure 2 for Figure 1 One corresponding timing diagram shows that Gate1 represents the first row of gate lines, Gate2 represents the second row of gate lines, and Gate3 represents the third row of gate lines. However, different signal lines within the same MUX unit can interfere with each other. Figure 1 The MUX unit 00 in the image includes three units: Mux01, Mux02, and Mux03. These three MUX units are used to control the signal acquisition of three columns of pixels. When the first column of pixels is acquiring signals, the TFTs of the other two columns of pixels are in the off state. Due to process defects, the TFTs have leakage current. Electrons on the two signal lines in the off state can still leak through the corresponding TFTs into the first column of signals being acquired, ultimately forming image noise.

[0038] In view of this, embodiments of the present invention provide a flat panel detector, its driving method, and an X-ray detection device.

[0039] like Figure 3 As shown, an embodiment of the present invention provides a flat panel detector, comprising:

[0040] The substrate 10 has multiple data lines D on it, a multiplexing circuit 20 coupled to one end of each data line D, and multiple holding capacitors 30 coupled to the other end of each data line D. Each holding capacitor 30 is used to maintain the potential of the other data lines D at a fixed potential when the detection signal of the coupled data line D is read by the multiplexing circuit 20.

[0041] The flat panel detector provided in this embodiment of the invention uses a multiplexer circuit 20 coupled to one end of each data line D, and multiple holding capacitors 30 correspondingly coupled to the other end of each data line D. Each holding capacitor 30 maintains the potential of the other data lines D at a fixed potential while the detection signal of the coupled data line D is read by the multiplexer circuit 20. Because each holding capacitor 30 maintains the potential of the other data lines D at a fixed potential while the detection signal of the coupled data line D is read by the multiplexer circuit 20, noise from other data lines D is not introduced during the reading process, thus avoiding noise interference during the data reading process of the flat panel detector and improving the image quality of the flat panel detector.

[0042] In embodiments of the present invention, such as Figure 4 As shown, each of the holding capacitors 30 includes a first electrode 301 and a second electrode 302 that are sequentially opposite to the substrate 10. The second electrode 302 is coupled to the other end of the corresponding data line D. The first electrodes 301 are interconnected and have a potential of the fixed potential.

[0043] Still combined Figure 4 As shown, each holding capacitor 30 includes a first electrode 301 and a second electrode 302 sequentially facing away from the substrate 10. Each second electrode 302 is coupled to the other end of the corresponding data line D. Each first electrode 301 is interconnected and has a fixed potential, where REF represents a fixed potential. This improves the noise immunity of the flat panel detector when reading the detection signal of the coupled data line D through the multiplexing circuit 20.

[0044] In this embodiment of the invention, the flat panel detector further includes a reading circuit 40 coupled to the multiplexing circuit 20. When the reading circuit 40 reads the detection signal through the multiplexing circuit 20, the reference potential of the reading circuit 40 is the fixed potential.

[0045] In specific implementation, each multiplexing circuit 20 includes multiple multiplexing units 201, each multiplexing unit 201 being coupled to one end of multiple data lines D. The flat panel detector also includes a readout circuit 40 coupled to the multiplexing circuit 20, each readout circuit 40 including multiple readout units 400, each corresponding to one of the multiple multiplexing units 201. The number of readout units 400 is the same as the number of multiple multiplexing units 201, and they are configured in a one-to-one correspondence. Figure 5In the exemplary embodiment shown, each multiplexing unit 201 is coupled to three data lines D, and one multiplexing circuit 20 is coupled to one read circuit 40. Of course, the number of multiplexing units 201, the number of read units 400, and the number of data lines D coupled to each multiplexing unit 201 can be set according to actual application needs, and are not limited here. Furthermore, since the multiplexing circuit 20 is coupled to one end of each data line D in this embodiment of the invention, the number of read units 400 in the read circuit 40 is simplified, reducing the manufacturing cost of the flat panel detector and effectively reducing the size of the product, ensuring a thin and light design for the flat panel detector.

[0046] In the embodiments of the present invention, it is still combined with Figure 5 As shown, each read unit 400 in the read circuit 40 can be a ROIC, specifically including an operational amplifier OP, an integrating capacitor CF, and a reset control switch INTRST. The positive input terminal of the operational amplifier OP is used to receive a reference potential, the negative input terminal of the operational amplifier OP is coupled to a multiplexer, and the output terminal of the operational amplifier OP is coupled to the image signal output terminal Vout. The first terminal of the integrating capacitor CF is coupled to the negative input terminal of the operational amplifier OP, and the second terminal of the integrating capacitor CF is coupled to the output terminal of the operational amplifier OP. The first terminal of the reset control switch INTRST is coupled to the first terminal of the integrating capacitor CF, and the second terminal of the reset control switch INTRST is coupled to the second terminal of the integrating capacitor CF. In practical applications, the operational amplifier OP, the integrating capacitor CF, and the reset control switch INTRST can have essentially the same structure as in the prior art, which should be understood by those skilled in the art. Therefore, they are not described in detail here and should not be construed as limiting the present invention.

[0047] In this embodiment of the invention, the capacitance values ​​of each holding capacitor 30 are the same, which ensures the uniformity of noise immunity of each holding capacitor 30 and the uniformity of the image of the flat panel detector.

[0048] In the embodiments of the present invention, it is still combined with Figure 5 As shown, the substrate 10 includes a detection area AA and a peripheral area BB surrounding the detection area AA. Each data line D extends along the direction from the detection area AA to the peripheral area BB. Each holding capacitor 30 is disposed on one side near the other end of the corresponding data line D.

[0049] In a specific implementation, the substrate 10 includes a detection region AA and a surrounding region BB that surrounds the detection region AA. The distribution of the detection region AA and the surrounding region BB can be as follows: Figure 5As shown, since each data line D extends along the detection area AA towards the surrounding area BB, each holding capacitor 30 is located on one side close to the other end of the corresponding data line D. In other words, each holding capacitor 30 is located on one side close to the other end of the corresponding data line D. In this way, while ensuring the noise immunity of the holding capacitor 30, the uniformity of each holding capacitor 30 in noise immunity is also ensured, thus ensuring the image uniformity of the flat panel detector.

[0050] In this embodiment of the invention, the plurality of holding capacitors 30 are located in the detection area AA or the surrounding area BB. Figure 5 The diagram illustrates one scenario where multiple holding capacitors 30 are located in the surrounding area BB. In practice, the multiple holding capacitors 30 can also be located in the detection area AA. Figure 6 As shown, multiple holding capacitors 30 can be arranged as the last row of the detection area AA, pointing from the detection area AA to the surrounding area BB. Of course, the specific positions of the multiple holding capacitors 30 can also be set according to the actual application needs, which will not be detailed here.

[0051] In this embodiment of the invention, the detection area AA includes a gate layer 101, a gate insulating layer 102, a semiconductor layer 103, a first conductive layer 104, an interlayer insulating layer 105, a second conductive layer 106, a photosensitive layer 107, a transparent wiring layer 108, and a bias electrode layer 109, which are sequentially opposite to the substrate 10. Each first electrode 301 is fabricated in the same layer as the first conductive layer 104, and each second electrode 302 is fabricated in the same layer as the bias electrode layer 109.

[0052] In the specific implementation process, such as Figure 7 The image shows along Figure 3The diagram shows one possible cross-sectional structure along the MM direction. The detection region AA includes, sequentially away from the substrate 10, a gate layer 101, a gate insulating layer 102, a semiconductor layer 103, a first conductive layer 104, an interlayer insulating layer 105, a second conductive layer 106, a photosensitive layer 107, a transparent wiring layer 108, and a bias electrode layer 109. In one exemplary embodiment, the semiconductor layer 103 can be made of low-temperature polycrystalline silicon semiconductor material. Alternatively, the semiconductor layer 103 can also be made of metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO). This ensures the mobility of the corresponding transistor. The first conductive layer 104 can be a first source / drain electrode layer, and the second conductive layer 106 can be a second source / drain electrode layer. The photosensitive layer 107 can include a P-layer structure, an I-layer structure, and an N-layer structure sequentially away from the substrate 10. The bias electrode layer 109 can input a bias voltage to the photodetector 901 in the flat panel detector. When the photodetector 901 receives an optical signal, it can generate an electrical signal through photoelectric conversion. The photodetector 901 can be, for example, a photodiode (PIN). Furthermore, the first electrode 301 of each holding capacitor 30 is fabricated in the same layer as the first conductive layer 104. In actual fabrication, the same patterning process can be used to fabricate the first electrode 301 and the first conductive layer 104, thereby improving fabrication efficiency. Similarly, the second electrode 302 of each holding capacitor 30 is fabricated in the same layer as the bias electrode layer 109. In actual fabrication, the same patterning process can be used to fabricate the second electrode 302 and the bias electrode layer 109, thereby improving fabrication efficiency.

[0053] In this embodiment of the invention, the detection area AA further includes a first passivation layer 50, a planarization layer 60 and a second passivation layer 70 located between the transparent wiring layer 108 and the bias electrode layer 109 and sequentially away from the substrate 10, an intermediate dielectric layer 303 between each of the first electrode 301 and the second electrode 302, and is fabricated in the same layer as at least one of the interlayer insulating layer 105, the first passivation layer 50 and the second passivation layer 70.

[0054] In the specific implementation process, such as Figure 8 The image shows along Figure 3The diagram shows one possible cross-sectional structure along the NN direction. The detection region AA also includes a first passivation layer 50, a planarization layer 60, and a second passivation layer 70 located between the transparent trace layer 108 and the bias electrode layer 109, and sequentially facing away from the substrate 10. An intermediate dielectric layer 303 between each of the first electrode 301 and the second electrode 302 is also included, and is fabricated in the same layer as at least one of the interlayer insulating layer 105, the first passivation layer 50, and the second passivation layer 70. The first passivation layer 50, the planarization layer 60, the second passivation layer 70, the gate insulating layer 102, and the interlayer insulating layer 105 are made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or a composite layer. Figure 8 The diagram illustrates one possible structure where the intermediate dielectric layer 303 is fabricated in the same layer as the first passivation layer 50, the planarization layer 60, and the second passivation layer 70. This allows for the use of the same patterning process to fabricate the intermediate dielectric layer 303, the first passivation layer 50, the planarization layer 60, and the second passivation layer 70, thereby improving fabrication efficiency. Of course, other film structures can be selected to fabricate the intermediate dielectric layer 303 according to actual application needs, and this is not limited here. Furthermore, in addition to the film structures mentioned above, the flat panel detector of this embodiment can also incorporate other film structures according to actual application needs, such as adhesive layers, cover plates, etc. Specific implementations can be found in related technologies and will not be detailed here.

[0055] In this embodiment of the invention, the flat panel detector further includes a plurality of bonding electrodes 80 located in the peripheral region BB. Each of the first electrode plates 301 is coupled to the transparent electrode layer through a via penetrating the first passivation layer 50, the planarization layer 60 and the second passivation layer 70, and is also coupled to the plurality of bonding electrodes 80.

[0056] In practical implementation, the flat panel detector also includes multiple bonding electrodes 80 located in the surrounding area BB. The specific number of bonding electrodes 80 can be set according to actual application needs and is not limited here. The first electrode plate 301 of each holding capacitor 30 is coupled to the transparent electrode layer through vias penetrating the first passivation layer 50, the planarization layer 60, and the second passivation layer 70, and is also coupled to the multiple bonding electrodes 80. That is, the first electrode plate 301 of each holding capacitor 30 can be coupled to the transparent electrode layer through the aforementioned vias, and ultimately coupled to the multiple bonding electrodes 80. In this way, the required signal can be loaded onto the corresponding first electrode plate 301 through the multiple bonding electrodes 80, thereby improving the performance of the flat panel detector.

[0057] It should be noted that the aforementioned flat panel detector also includes multiple grid lines G intersecting with multiple data lines D, and multiple detection units 90 defined by the multiple data lines D and the multiple grid lines G. These multiple detection units 90 are arrayed in the detection area AA. Each detection unit 90 includes a photoelectric detection device 901 and a switch control unit 902 for controlling the data acquisition of the photoelectric detection device 901. Furthermore, the surrounding area BB includes a system motherboard 100 and a gate drive circuit 101. The gate drive circuit 101 can be single-sided or double-sided, without limitation. The system motherboard 100 can load the required signals to the coupled circuits, thereby ensuring the performance of the flat panel detector.

[0058] In this embodiment of the invention, there are two possible implementation methods for setting multiple bonding electrodes 80, but it is not limited to these two implementation methods.

[0059] In the first implementation, such as Figure 9 As shown, the flat panel detector also includes a system motherboard 100 located in the peripheral area BB and a gate driving circuit 101 coupled to the system motherboard 100, and the plurality of bonding electrodes 80 are located on the gate driving circuit 101.

[0060] Still combined Figure 9 As shown, the flat panel detector also includes a system motherboard 100 located in the peripheral area BB and a gate drive circuit 101 coupled to the system motherboard 100. Multiple bonding electrodes 80 are located on the gate drive circuit 101. The gate drive circuit 101 includes a flexible circuit board, and the multiple bonding electrodes 80 can be coupled to the system motherboard 100 through vias H penetrating the flexible circuit board. In this way, the system motherboard 100 can apply a voltage signal with a required fixed potential to the first plate 301 of each holding capacitor 30 through the multiple bonding electrodes 80. Because the wiring length between the first plate 301 and the multiple bonding electrodes 80 is relatively short, the control efficiency of the system motherboard 100 over the first plate 301 is improved.

[0061] In the second implementation, the flat panel detector further includes a system motherboard 100 located in the peripheral area BB and coupled to the reading circuit 40, with the plurality of bonding electrodes 80 located on the reading circuit 40. Of course, multiple bonding electrodes 80 can be configured according to actual application needs, and this is not limited here.

[0062] In embodiments of the present invention, such as Figure 10As shown, the flat panel detector also includes a plurality of detection units 90 arranged in an array, each detection unit 90 including a switch control unit 902, and the multiplexing circuit 20 including a plurality of switch selection units 200, wherein each switch selection unit 200 is coupled to one end of the corresponding data line D, and the active layer of the transistor included in each switch selection unit 200 and the active layer of the transistor included in each switch control unit 902 are both made of low-temperature polycrystalline silicon material.

[0063] Still combined Figure 10 As shown, the flat panel detector also includes multiple detection units 90 arranged in an array. Each detection unit 90 includes a photoelectric detection device 901 and a switch control unit 902 for controlling the data acquisition of the switch detection device. Each multiplexing unit 201 includes multiple switch selection units 200 for controlling the conduction between multiple data lines D and the reading circuit 40. Each switch selection unit 200 is coupled to one end of the corresponding data line D. The active layer of the transistors included in each switch selection unit 200 and the active layer of the transistors included in each switch control unit 902 are both made of low-temperature polycrystalline silicon. Of course, the specific number of multiple detection units 90 and multiple switch selection units 200 can be set according to actual application needs, and is not limited here.

[0064] In practical research, the inventors discovered that when the active layer of each transistor in the flat panel detector is made of low-temperature polycrystalline silicon, the carrier mobility of the corresponding device is about 100 times that of the a-Si currently used. In this way, the turn-on resistance of each transistor in the embodiment of the present invention is smaller, and the RC delay in the corresponding circuit is lower during signal acquisition, thereby ensuring the performance of the flat panel detector.

[0065] It should be noted that the transistors included in each switch control unit 902 and the transistors included in each switch selection unit 200 can be of the same type, for example, both being P-type transistors; or both being N-type transistors. Furthermore, the transistors included in each switch control unit 902 and the transistors included in each switch selection unit 200 can be of different types, for example, each switch control unit 902 may include P-type transistors and each switch selection unit 200 may include N-type transistors; or each switch control unit 902 may include N-type transistors and each switch selection unit 200 may include P-type transistors. Of course, the type of each transistor can be set according to actual application needs, and is not limited here. Further, the transistors mentioned above can be TFTs or metal-oxide-semiconductor field-effect transistors (MOS), and are not limited here.

[0066] The following is based on Figure 10 The structure of the flat panel detector shown illustrates the working process of the flat panel detector provided in this embodiment of the invention. It should be noted that this embodiment is for better explanation of the invention and does not limit the specific implementation of the invention.

[0067] Still combined Figure 10 As shown, the flat panel detector includes detection units 90 defined by a grid line G and a data line D. Each row of detection units 90 is coupled to one grid line G, and each column of detection units 90 is coupled to one data line D. The first multiplexing unit 201 includes three switching transistors: MUX011, MUX012, and MUX013. Each detection unit 90 includes a photodiode and a switching control transistor for transmitting the electrical signal generated by the photodiode to the data line D. The process by which this detection unit 90 performs X-ray detection is the same as in the prior art and will not be described in detail here.

[0068] Initially, all transistors in the flat panel detector are turned off, and the potentials of the Vp capacitor and the holding capacitor 30 are consistent with the reference potential of the readout circuit 40. After the flat panel detector receives exposure, all photodiodes generate photoelectrons and store them in the Vp capacitor. When the first row of gate lines G is turned on, some electrons in each Vp capacitor in this row are read away by the holding capacitor 30 and stored in the holding capacitor 30, while the other part remains stored in the Vp capacitor. Then, the first column MUX011 in the first multiplexer unit 201 is turned on, and the voltage of the Vp capacitor corresponding to the detection unit 90 located in the first row and first column is increased. All electrons in the holding capacitor 30 coupled to the first column MUX011 are read out and transmitted to the ROIC for data processing. Simultaneously, the reference potential of the ROIC charges the Vp capacitor and the holding capacitor 30. Since MUX012 and MUX013 are both in the off state when MUX011 reads electrons, and because the potential of the holding capacitor 30 and the reference potential of the ROIC are the same fixed potential with identical capacitance, there is no current leakage through the transistors corresponding to MUX012 and MUX013. Therefore, no noise from other data lines D is introduced during the MUX011 reading process. The above steps are repeated until the detection signal of the entire flat panel detector has been read.

[0069] Based on the same inventive concept, embodiments of the present invention also provide an X-ray detection device, including the aforementioned flat panel detector provided in the embodiments of the present invention. The principle by which this X-ray detection device solves the problem is similar to that of the aforementioned flat panel detector; therefore, the implementation of this X-ray detection device can refer to the implementation of the aforementioned flat panel detector, and repeated details will not be elaborated further. Furthermore, other essential components of this X-ray detection device are all understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the present invention.

[0070] Based on the same inventive concept, embodiments of the present invention also provide a driving method for a flat panel detector provided in embodiments of the present invention, the driving method comprising:

[0071] When the detection signal is read through the multiplexing circuit 20, a fixed potential is applied to each of the holding capacitors 30.

[0072] The specific implementation process of this driving method can be found in the description of the relevant sections mentioned above, and will not be repeated here.

[0073] This invention provides a flat panel detector, its driving method, and an X-ray detection device. The flat panel detector includes a substrate 10, multiple data lines D on the substrate 10, a multiplexing circuit 20 coupled to one end of each data line D, and multiple holding capacitors 30 correspondingly coupled to the other end of each data line D. Thus, one end of each data line D is coupled to the multiplexing circuit 20, and the other end is correspondingly coupled to the multiple holding capacitors 30. Furthermore, each holding capacitor 30 maintains the potential of other data lines D at a fixed potential when the detection signal of the coupled data line D is read by the multiplexing circuit 20. Since each holding capacitor 30 maintains the potential of other data lines D at a fixed potential when the detection signal of the coupled data line D is read by the multiplexing circuit 20, noise from other data lines D is not introduced during the reading process, thereby avoiding noise interference during the data reading process of the flat panel detector and improving the image quality of the flat panel detector.

[0074] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0075] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A flat panel detector, characterized in that, include: The substrate includes multiple data lines located on it, a multiplexing circuit coupled to one end of each data line, and multiple holding capacitors coupled to the other end of each data line. Each holding capacitor is used to maintain the potential of the other data lines at a fixed potential when the detection signal of the coupled data line is read by the multiplexing circuit. Each holding capacitor includes a first electrode and a second electrode sequentially separated from the substrate. The second electrode is coupled to the other end of the corresponding data line, and the first electrodes are interconnected and have the fixed potential.

2. The flat panel detector as described in claim 1, characterized in that, The flat panel detector also includes a reading circuit coupled to the multiplexing circuit. When the reading circuit reads the detection signal through the multiplexing circuit, the reference potential of the reading circuit is the fixed potential.

3. The flat panel detector as described in claim 2, characterized in that, All of the holding capacitors have the same capacitance value.

4. The flat panel detector as described in claim 3, characterized in that, The substrate includes a detection area and a peripheral area surrounding the detection area. Each data line extends along the detection area in a direction pointing towards the peripheral area, and each holding capacitor is disposed on one side near the other end of the corresponding data line.

5. The flat panel detector as described in claim 4, characterized in that, The plurality of holding capacitors are located in the detection area or the surrounding area.

6. The flat panel detector as described in claim 5, characterized in that, The detection area includes a gate layer, a gate insulating layer, a semiconductor layer, a first conductive layer, an interlayer insulating layer, a second conductive layer, a photosensitive layer, a transparent wiring layer, and a bias electrode layer, which are sequentially separated from the substrate. Each first electrode plate is fabricated in the same layer as the first conductive layer, and each second electrode plate is fabricated in the same layer as the bias electrode layer.

7. The flat panel detector as described in claim 6, characterized in that, The detection area also includes a first passivation layer, a planarization layer, and a second passivation layer located between the transparent trace layer and the bias electrode layer and sequentially away from the substrate, an intermediate dielectric layer between each of the first electrode plates and the second electrode plates, and a film layer co-fabricated with at least one of the interlayer insulating layer, the first passivation layer, and the second passivation layer.

8. The flat panel detector as described in claim 7, characterized in that, The flat panel detector also includes a plurality of bonding electrodes located in the peripheral region. Each of the first electrode plates is coupled to the bias electrode layer through a via penetrating the first passivation layer, the planarization layer and the second passivation layer, and is also coupled to the plurality of bonding electrodes.

9. The flat panel detector as described in claim 8, characterized in that, The flat panel detector also includes a system motherboard located in the peripheral area and a gate driving circuit coupled to the system motherboard, with the plurality of bonding electrodes located on the gate driving circuit.

10. The flat panel detector as described in claim 8, characterized in that, The flat panel detector also includes a system motherboard located in the peripheral area and coupled to the reading circuit, and the plurality of bonding electrodes are located on the reading circuit.

11. The flat panel detector according to any one of claims 4-7, characterized in that, The flat panel detector also includes multiple detection units arranged in an array, each detection unit including a switch control unit, and the multiplexing circuit including multiple switch selection units. Each switch selection unit is coupled to one end of the corresponding data line, and the active layer of the transistor included in each switch selection unit and the active layer of the transistor included in each switch control unit are both made of low-temperature polycrystalline silicon material.

12. An X-ray detection device, characterized in that, include: The flat panel detector as described in any one of claims 1-11.

13. The driving method for a flat panel detector as described in any one of claims 1-11, characterized in that, include: When reading the detection signal through the multiplexing circuit, a fixed potential is applied to each of the holding capacitors.

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