A multi-format compatible multi-precision fused multiply-add operation apparatus and method

Abstract

The application provides a multi-precision fusion multiply-accumulate operation device and method compatible with multiple formats, the device comprising a multi-precision decoder, a multi-precision multiply-accumulate operation module and a multi-precision encoder; the multi-precision decoder and the multi-precision encoder are respectively used for decoding input operands and encoding output results; the multi-precision multiply-accumulate module accepts the output of the multi-precision decoder, completes the multiply-accumulate calculation of multi-precision, and the calculation result is taken as the input of the multi-precision encoder. The application supports various formats such as IEEE-754 floating point format, Posit format, fixed point format, BFloat16 and TensorFloat32, and for the processes such as mantissa multiplication, operand addition, operand shift and leading zero count in the multiply-accumulate operation process, the application provides an efficient multi-precision implementation device through segmentation and hardware reuse, so that the overall operation unit realizes high area efficiency and energy efficiency.

Description

Technical Field

[0001] This invention relates to the field of floating-point arithmetic technology, and in particular to a multi-precision fusion multiply-accumulate arithmetic device and method compatible with multiple formats. Background Technology

[0002] In recent years, deep neural networks have been widely used, achieving great success in fields such as image classification, object detection, and speech recognition. However, the hardware deployment of neural networks typically requires substantial resources, especially the multiply-accumulate (FMA) operation, which consumes a significant amount of computation. Therefore, designing a hardware-efficient multiply-accumulate unit is crucial for deploying neural networks on resource-constrained devices. On the other hand, existing multiply-accumulate units primarily support single-precision operations. However, different network layers and operations in neural network applications often require different computational precisions. By using a multi-precision multiply-accumulate unit, flexible precision configuration can be achieved during operations, significantly improving computational efficiency, reducing energy consumption, and decreasing the storage requirements of the neural network even under low-precision operations. Therefore, designing a hardware-efficient multi-precision multiply-accumulate unit can better meet the needs of neural network hardware deployment.

[0003] Furthermore, although the IEEE-754 floating-point format is widely used, some newer formats such as Posit, BFloat16, and TensorFloat32 have also shown unique advantages in some neural network applications. Therefore, the compatibility and support of the computing unit for these multiple formats can greatly improve its flexibility and expand its application scenarios.

[0004] To support multi-precision multiply-accumulate operations of various formats in neural network computation, one approach is to simultaneously implement single-precision multiply-accumulate units of various formats and precisions in hardware, enabling the corresponding units to complete the operation according to the precision requirements. However, this approach greatly increases hardware overhead and is not conducive to the deployment of neural networks on resource-constrained devices. In addition, the literature "Xie Xin'ang, Li Kai, Li Boyu et al. A reconfigurable floating-point multiply-accumulate unit and method suitable for multi-precision computing [P]. Guangdong Province: CN112860220B, 2023-03-24" proposes a reconfigurable floating-point multiply-accumulate unit suitable for multi-precision computing. However, it only optimizes multi-precision multiplication operations and does not support efficient multi-precision shifting, multi-precision addition, multi-precision leading zero counting, etc., thus limiting further improvements in hardware area efficiency and energy efficiency. The literature “Zhang H, Chen D, Ko S B. Efficient multiple-precision floating-point fused multiply-add with mixed-precision support[J]. IEEE Transactions on Computers, 2019, 68(7): 1035-1048.”, “Zhang H, Chen D, Ko S B. New flexible multiple-precision multiply-accumulate unit for deep neural network training and inference[J]. IEEE Transactions on Computers, 2019, 69(1): 26-38.”, and “Tan H, Tong G, Huang L, et al. Multiple-Mode-Supporting Floating-Point FMA Unit for Deep Learning Processors[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022” proposes a multi-precision floating-point multiply-accumulate unit, but it only supports a limited number of floating-point or fixed-point formats. Summary of the Invention

[0005] Objective: The technical problem this invention aims to solve is to address the shortcomings of existing technologies by providing a multi-precision fusion multiply-accumulate arithmetic device and method compatible with multiple formats. This device supports the selection of different numerical formats during the decoding input and encoding output stages. Furthermore, during the multiply-accumulate calculation stage between decoding and encoding, resource sharing between different precisions is achieved through segmentation and hardware multiplexing, thereby reducing the hardware overhead for supporting multi-precision operations. Compared to directly instantiating different arithmetic units to support multiple precisions, this design achieves lower area overhead and higher energy efficiency, thus better meeting the needs of neural network hardware deployment.

[0006] The device of the present invention includes a multi-precision decoder, a multi-precision multiply-accumulate operation module, and a multi-precision encoder;

[0007] The multi-precision decoder and multi-precision encoder are used to decode the input operands and encode the output results, respectively.

[0008] The multi-precision multiply-accumulate operation module receives the output of the multi-precision decoder, completes the multi-precision multiply-accumulate calculation, and uses the calculation result as the input of the multi-precision encoder.

[0009] The multi-precision decoder and multi-precision encoder support multi-precision input and output, and also allow users to customize and add decoding and encoding modules of various formats according to the unified decoder and encoder input and output data arrangement rules, thereby achieving compatibility support for various formats.

[0010] The multi-precision decoder takes a 32-bit operand as input and outputs the operand's sign (4 bits), exponent (32 bits, for signed numbers), and mantissa (32 bits, left-aligned, i.e., the decimal point is after the most significant bit). In different precision modes, the significant data bits of the output sign, exponent, and mantissa change as follows, with invalid data bits padded with 0s:

[0011] In 8-bit precision mode, all 4 bits of the output sign are valid, representing the sign of each of the four input 8-bit operands; all 32 bits of the output exponent are valid, with each 8 bits representing a signed number and indicating the significant exponent of each of the four input 8-bit operands; all 32 bits of the output mantissa are valid, with each 8 bits representing the significant mantissa of each of the four input 8-bit operands.

[0012] In 16-bit precision mode, the 2nd and 4th bits of the output sign are valid, representing the sign of each of the two input 16-bit operands; each 14 bits of the output exponent are valid, representing the valid exponent of each of the two input 16-bit operands; and all 32 bits of the output mantissa are valid, with each 16 bits representing the valid mantissa of each of the two input 16-bit operands.

[0013] In 32-bit precision mode, only the most significant bit of the output sign is valid, representing the sign of the input 32-bit operand; only the lower 14 bits of the output exponent are valid, representing the significant exponent of the input 32-bit operand; all 32 bits of the output mantissa are valid, representing the significant mantissa of the input 32-bit operand.

[0014] The multi-precision encoder takes as input a sign (4-bit), an exponent (32-bit, signed number), and a mantissa (32-bit, left-aligned, i.e., the decimal point is after the most significant bit), and outputs a 32-bit encoded result. In different precision modes, the valid data bits of the input sign, exponent, and mantissa change as follows, while invalid data bits are 0:

[0015] In 8-bit precision mode, all 4 bits of the input sign are valid, representing the sign of each of the four 8-bit output results; all 32 bits of the input exponent are valid, with each 8 bits representing a signed number, indicating the significant exponent of each of the four 8-bit output results; all 32 bits of the input mantissa are valid, with each 8 bits representing the significant mantissa of each of the four 8-bit output results.

[0016] In 16-bit precision mode, the 2nd and 4th bits of the input sign are valid, representing the sign of each of the two 16-bit output results; each 14 bits of the input exponent are valid, representing the valid exponent of each of the two 16-bit output results; all 32 bits of the input mantissa are valid, with each 16 bits representing the valid mantissa of each of the two 16-bit output results.

[0017] In 32-bit precision mode, only the most significant bit of the input sign is valid, representing the sign of the 32-bit output result; only the lower 14 bits of the input exponent are valid, representing the exponent of the 32-bit output result; all 32 bits of the input mantissa are valid, representing the mantissa of the 32-bit operand to be output.

[0018] The multi-precision decoder receives 32-bit input operands, generates a unified decoder output, and sends the output of the multi-precision decoder to the multi-precision multiply-accumulate operation module for processing to obtain a unified encoder input, which is then sent to the multi-precision encoder to obtain a 32-bit multi-precision operation result.

[0019] The multi-precision multiplication and accumulation operation module includes a multi-precision mantissa multiplication module, a multi-precision exponent addition module, a multi-precision exponent difference module, a multi-precision mantissa alignment module, a multi-precision mantissa addition module, a multi-precision mantissa normalization and exponent adjustment module, and a multi-precision mantissa rounding module.

[0020] Within the multi-precision mantissa multiplication module, multiplication between two 32-bit mantissas is performed according to the precision mode to obtain a 64-bit product result. Specifically, this includes: in 32-bit precision mode, the two 32-bit input mantissas are multiplied by a 32-bit multiplier to obtain a 64-bit product result; in 16-bit precision mode, the lower 16 bits of each of the two 32-bit input mantissas are multiplied by a 16-bit multiplier to obtain the lower 32-bit value of the 64-bit product result, and the higher 16 bits are multiplied to obtain the higher 32-bit value of the 64-bit product result; in 8-bit precision mode, each 8-bit of each of the two 32-bit input mantissas is multiplied by an 8-bit multiplier, and the four sets of 16-bit product results are combined to obtain the 64-bit product result.

[0021] Divide the two 32-bit input mantissas A and B into 8-bit segments to obtain four suboperands A3, A2, A1, A0 and B3, B2, B1, B0 respectively. Then implement 16 8-bit submultipliers, namely A0*B0, A0*B1, A1*B0, A0*B2, A1*B1, A2*B0, A0*B3, A1*B2, A2*B1, A3*B0, A1*B3, A2*B2, A3*B1, A2*B3, A3*B2, A3*B3;

[0022] The 32-bit, 16-bit, and 8-bit multipliers under different precision modes are all implemented through the 16 8-bit sub-multipliers. The required number of sub-multipliers is enabled according to the different precision modes, and the results are then added together, thereby achieving support for multi-precision multiplication operations in the same hardware. Specifically, this includes:

[0023] In 16-bit precision mode, the multiplication of the lower 16 bits of the 32-bit mantissas A and B is calculated as follows:

[0024] ,

[0025] The multiplication of the input 32-bit mantissa A and the high 16 bits of mantissa B is calculated as follows:

[0026] ,

[0027] In 16-bit precision mode, the result of mantissa multiplication can be obtained by shifting and adding the results of the eight sub-multipliers A0*B0, A0*B1, A1*B0, A1*B1, A2*B2, A2*B3, A3*B2, and A3*B3.

[0028] In 32-bit precision mode, the result of mantissa multiplication can be obtained by shifting and adding the results of all 16 sub-multipliers.

[0029] In 8-bit precision mode, the result of the mantissa multiplication operation in 8-bit precision mode can be obtained by shifting and adding the results of the four sub-multipliers A0*B0, A1*B1, A2*B2, and A3*B3.

[0030] Within the multi-precision exponent addition module, multi-precision exponent difference module, multi-precision mantissa addition module, and multi-precision mantissa normalization and exponent adjustment module, a segmented addition method is used to complete the addition of two multi-precision data.

[0031] First, the two input multi-precision data are each divided into four sub-operands: A3, A2, A1, A0 and B3, B2, B1, B0. These four sub-adders (A3+B3, A2+B2, A1+B1, A0+B0) are then added in parallel. In 8-bit precision mode, the result of the four sub-adders is the final result. In 16-bit precision mode, the carry generated by sub-adders A0+B0 and A2+B2 needs to be propagated forward, i.e., it is combined with the carry generated by sub-adders A1+B1, A2+B2, A3+B3, A2+B2, A1+B1, A0+B0 respectively. The results of A3+B3 are added together. In 32-bit precision mode, the carry generated by the four sub-adders needs to be propagated to higher bits. That is, the carry generated by sub-adder A0+B0 needs to be added to the result of sub-adder A1+B1. The carry generated by the result of the addition continues to be propagated to higher bits and added to the result of sub-adder A2+B2. The carry generated by the addition continues to be added to the result of sub-adder A3+B3 to obtain the final multi-precision addition result.

[0032] Within the multi-precision mantissa alignment module, the mantissas of the multi-precision addend and multiplier need to be aligned based on the difference in exponents between the addend and multiplier. The mantissa alignment process is as follows:

[0033] In 8-bit precision mode, the 8-bit addend is initially placed to the left of the 16-bit multiplier. Then, the addend is right-shifted and aligned according to the difference E between the exponents of the addend and the multiplier: when E is greater than or equal to 9, the right shift of the addend is 0; when E is less than or equal to -15, the right shift of the addend is 24; otherwise, the right shift of the addend is (9-E).

[0034] In 16-bit precision mode, the 16-bit addend is initially placed to the left of the 32-bit multiplier. Then, the addend is right-shifted and aligned according to the difference E between the exponents of the addend and the multiplier: when E is greater than or equal to 17, the right shift of the addend is 0; when E is less than or equal to -31, the right shift of the addend is 48; otherwise, the right shift of the addend is (17-E).

[0035] In 32-bit precision mode, the 32-bit addend is initially placed to the left of the 64-bit multiplier. Then, the addend is right-shifted and aligned according to the difference E between the exponents of the addend and the multiplier: when E is greater than or equal to 33, the right shift of the addend is 0; when E is less than or equal to -63, the right shift of the addend is 96; otherwise, the right shift of the addend is (33-E).

[0036] The mantissa data of the multi-precision addend and multiplier are rearranged according to the precision mode control signal to ensure that the initial position of the addend value is to the left of its corresponding multiplier in 8-bit, 16-bit and 32-bit precision modes; the mantissa of the multi-precision addend is the mantissa of the input multi-precision operand C; the mantissa of the multiplier is the product of the mantissas of the input multi-precision operands A and B.

[0037] After obtaining the rearranged mantissas of the addend and multiplier, the mantissa of the addend needs to be shifted to the right according to the difference between the exponents of the addend and multiplier in order to align with the mantissa of the multiplier.

[0038] Segmented shifting reduces the hardware overhead for supporting dynamic shifting in multi-precision modes, specifically including:

[0039] In 8-bit precision mode, the rearranged addends have their own right shift amount for each 24 bits, with the shift amount ranging from 0 to 24; each 24 bits corresponds to a set of input operand addends, for a total of four sets;

[0040] In 16-bit precision mode, the rearranged addends have their own right shift amount for each 48-bit interval, with the shift amount ranging from 0 to 48; each 48-bit interval corresponds to a set of input operand addends, for a total of two sets;

[0041] In 32-bit precision mode, the rearranged 96-bit addend has a uniform right shift amount, which is between 0 and 96.

[0042] Based on the precision mode control signal, the shift amount of each 24-bit valid data segment d, c, b, a can be determined, which are sft_amt_d, sft_amt_c, sft_amt_b, and sft_amt_a, respectively. The shift amounts sft_amt_d, sft_amt_c, sft_amt_b, and sft_amt_a are all represented by a 7-bit data width, i.e., sft_amt_d[6:0], sft_amt_c[6:0], sft_amt_b[6:0], and sft_amt_a[6:0].

[0043] After determining the alignment shift amount for each segment of the addend, multi-precision shifting is supported through segmented and hierarchical shifting. Specifically, for each 24-bit addend, it is fed into its respective shifter in parallel to complete five levels of shifting, i.e., the shift amount is the value represented by the lower 5 bits of its respective shift amount, and the shift amounts are: sft_amt_d[4:0], sft_amt_c[4:0], sft_amt_b[4:0], sft_amt_a[4:0]; after completing the shifting of levels 1 to 5, the shifted result is determined by the precision mode control signal to perform a bitwise OR operation with the shifted-out higher bits:

[0044] In 8-bit precision mode, no bitwise OR operation is required;

[0045] In 16-bit precision mode, the result of shifting segment c needs to be bitwise ORed with the bit shifted out of segment d, and the result of shifting segment a needs to be bitwise ORed with the bit shifted out of segment b.

[0046] In 32-bit precision mode, the results of shifting segments a, b, and c all need to be bitwise ORed with the bits shifted out from higher segments;

[0047] After completing the segmented shifts of levels 1 to 5, the results of shifting a and b, and c and d are used as a whole 48-bit data to participate in the shift of level 6. That is, based on the value of the 6th bit of the shift amount sft_amt_b[5], sft_amt_d[5], it is determined whether a 32-bit right shift is needed: when the value is 1, a 32-bit right shift is needed; when the value is 0, no shift is needed. When in 32-bit precision mode, the result after the shift of the lower 48-bits needs to be bitwise ORed with the shifted-out bits of the higher 48-bits.

[0048] After completing the 6th level shift, the two 48-bit shift results form a 96-bit whole to participate in the 7th level shift. That is, according to the value of the 7th bit of the shift amount sft_amt_d[6], it is selected whether to shift right by 64 bits. When the value is 1, shift right by 64 bits; when the value is 0, do not shift. The final output result is the result of addend shift alignment in multi-precision mode.

[0049] Within the multi-precision mantissa normalization and exponent adjustment module, the result of adding the mantissas of the addend and multiplier after shift alignment needs to be normalized and shifted. This includes two processes: multi-precision leading zero counting to determine the shift amount, and multi-precision shifting based on the shift amount.

[0050] For multi-precision leading zero counting, in 8-bit precision mode, the leading zero counts cpm[3], cpm[2], cpm[1] and cpm[0] of each 24-bit result (four groups in total) need to be calculated; in 16-bit precision mode, the leading zero counts cph[1] and cph[0] of each 48-bit result (two groups in total) need to be calculated; in 32-bit precision mode, the leading zero count cps of the overall 96-bit result needs to be calculated.

[0051] A device employing segmented leading zero counting: For each 24-bit input d, c, b, a, the leading zero count cpm and the valid data signal vpm are counted in parallel by a 24-bit leading zero counting module, respectively cpm[3], cpm[2], cpm[1], cpm[0] and vpm[3], vpm[2], vpm[1], vpm[0]. The leading zero count is the normalized shift amount of each segment operand in 8-bit precision mode. For the two sets of leading zero count cph[1], cph[0] and two sets of valid data signals vph[1], vph[0] in 16-bit precision mode, they are obtained by a selector and an adder based on the leading zero count and valid data signal in 8-bit precision mode. For the leading zero count cps and valid data signal vps in 32-bit precision mode, they are obtained by a selector and an adder based on the leading zero count and valid data signal in 16-bit precision mode.

[0052] Based on the results of the segmented leading zero count, the normalized shift amount of the multi-precision mantissa can be determined. The subsequent normalized shift process of the multi-precision mantissa can be achieved through segmented and graded shifting.

[0053] This invention also provides a multi-precision fusion multiplication-accumulation operation method compatible with multiple formats, comprising the following steps:

[0054] Step 1: Input three 32-bit operands A, B, and C, and the corresponding configuration signals. The configuration signals include the precision mode and data format. The precision mode supports 32-bit, 16-bit, and 8-bit precision; the data format supports traditional floating-point format, POSIT format, and fixed-point format. The multi-precision operation A*B+C will be performed in subsequent steps 2-8.

[0055] In 32-bit precision mode, it supports 1*32-bit operations. The entire 32-bit of the output result D is the result of multiplying and accumulating the 32-bit inputs A, B, and C, expressed as: D[31:0]=A[31:0]*B[31:0]+C[31:0]; D[31:0] is the value of the entire 32-bit of the output result D. Similarly, in the following text, D[15:0] means the value of the lower 16-bit of the output result D, and D[31:16] is the value of the higher 16-bit of the output result D.

[0056] In 16-bit precision mode, it supports 2*16-bit operations. The lower 16-bit and higher 16-bit values ​​of the output result D are the results of multiplying and accumulating the lower 16-bit and higher 16-bit values ​​of the 32-bit inputs A, B, and C respectively: D[15:0]=A[15:0]*B[15:0]+C[15:0], D[31:16]=A[31:16]*B[31:16]+C[31:16];

[0057] In 8-bit precision mode, it supports 4*8-bit operations. The value of each 8-bit of the output result D is the result of multiplying and accumulating the values ​​of each 8-bit of the 32-bit inputs A, B, and C respectively, as follows: D[7:0]=A[7:0]*B[7:0]+C[7:0], D[15:8]=A[15:8]*B[15:8]+C[15:8], D[23:16]=A[23:16]*B[23:16]+C[23:16], D[31:24]=A[31:24]*B[31:24]+C[31:24];

[0058] Step 2: According to the configuration signal, call the corresponding decoder to complete the decoding process of the input data and output the valid sign, exponent and mantissa values ​​of the three operands A, B and C respectively;

[0059] Step 3: The exponents of the three operands A, B, and C are sequentially added and compared in the multi-precision exponent addition module and the multi-precision exponent difference module, respectively. Simultaneously, the mantissas of A and B are multiplied in the multi-precision mantissa multiplication module to obtain the mantissa of the multiplier. The exponent addition refers to adding the exponent of A to the exponent of B, and the result is the exponent of the multiplier. The exponent comparison and difference refers to calculating the difference between the exponent of the addend C and the exponent of the multiplier.

[0060] Step 4: Based on the results obtained in Step 3, complete the alignment of the mantissas of the multiplier and addend within the multi-precision mantissa alignment module;

[0061] Step 5: In the multi-precision mantissa addition module, complete the accumulation of the aligned multiplier mantissa and addend mantissa;

[0062] Step 6: In the multi-precision mantissa normalization and exponent adjustment module, complete the normalization shift of the mantissa; at the same time, adjust the exponent value of the final result according to the shift amount.

[0063] Step 7: In the multi-precision mantissa rounding module, complete the rounding of the normalized mantissa to obtain the final mantissa value.

[0064] Step 8: Call the corresponding encoder according to the configuration signal to complete the encoding process of the final result and output the calculation result.

[0065] Beneficial effects: This invention, by unifying the input and output data arrangement of the decoder and encoder, can support various formats including IEEE-754 floating-point format, Posit format, fixed-point format, BFloat16, and TensorFloat32. Furthermore, for processes such as mantissa multiplication, operand addition, operand shifting, and leading zero counting in multiplication-accumulation operations, this invention provides an efficient multi-precision implementation device through segmentation and hardware multiplexing, enabling the overall arithmetic unit to achieve high area efficiency and energy efficiency. Attached Figure Description

[0066] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, and the advantages of the present invention in the above and / or other aspects will become clearer.

[0067] Figure 1 This is a schematic diagram of the overall architecture of a multi-precision fusion multiply-accumulate operation unit that is compatible with multiple formats.

[0068] Figure 2 This is a schematic diagram showing the effective bit arrangement of the decoder output data and the encoder input data under different precision modes.

[0069] Figure 3 It is a flowchart of the calculation process between the decoder and the encoder.

[0070] Figure 4 This is a schematic diagram illustrating the calculation to be performed by mantissa multiplication under different precision modes.

[0071] Figure 5 This is a schematic diagram of a 32-bit multiplication device implemented using an 8-bit sub-multiplier.

[0072] Figure 6 This is a schematic diagram of a multi-precision segmented adder device.

[0073] Figure 7 This is a schematic diagram of the mantissa alignment process of addends and multipliers in 8-bit precision mode.

[0074] Figure 8 This is a diagram illustrating the rearrangement of the addend and multiplier mantissas under different precision modes.

[0075] Figure 9 This is a schematic diagram of a multi-precision segmented and hierarchical operand shifting device.

[0076] Figure 10 This is a schematic diagram of a multi-precision segmented leading zero counting device. Detailed Implementation

[0077] like Figure 1 As shown, this invention provides a multi-precision multiply-accumulate operation device compatible with multiple formats, including a multi-precision decoder, a multi-precision multiply-accumulate operation module, and a multi-precision encoder. The multi-precision decoder and multi-precision encoder are used for decoding the input operands and encoding the output result, respectively; the multi-precision multiply-accumulate operation module receives the output of the multi-precision decoder, completes the multi-precision multiply-accumulate calculation, and uses the calculation result as the input of the multi-precision encoder.

[0078] The multi-precision decoder and multi-precision encoder support multi-precision input and output, and also allow users to customize and add decoding and encoding modules of various formats according to the unified decoder and encoder input and output data arrangement rules, thereby achieving compatibility support for various formats.

[0079] This invention also provides a multi-precision fusion multiplication-accumulation operation compatible with multiple formats, comprising the following steps:

[0080] Step 1: Input three 32-bit operands A, B, and C, and the corresponding configuration signals. The configuration signals include the precision mode and data format. The precision mode supports 32-bit, 16-bit, and 8-bit precision; the data format supports traditional floating-point format, POSIT format, and fixed-point format. The multi-precision operation A*B+C will be performed in subsequent steps 2-8.

[0081] In 32-bit precision mode, it supports 1*32-bit operations. The entire 32-bit of the output result D is the result of multiplying and accumulating the 32-bit inputs A, B, and C, expressed as: D[31:0]=A[31:0]*B[31:0]+C[31:0]; D[31:0] is the value of the entire 32-bit of the output result D. Similarly, in the following text, D[15:0] means the value of the lower 16-bit of the output result D, and D[31:16] is the value of the higher 16-bit of the output result D.

[0082] In 16-bit precision mode, it supports 2*16-bit operations. The lower 16-bit and higher 16-bit values ​​of the output result D are the results of multiplying and accumulating the lower 16-bit and higher 16-bit values ​​of the 32-bit inputs A, B, and C respectively: D[15:0]=A[15:0]*B[15:0]+C[15:0], D[31:16]=A[31:16]*B[31:16]+C[31:16];

[0083] In 8-bit precision mode, it supports 4*8-bit operations. The value of each 8-bit of the output result D is the result of multiplying and accumulating the values ​​of each 8-bit of the 32-bit inputs A, B, and C respectively, as follows: D[7:0]=A[7:0]*B[7:0]+C[7:0], D[15:8]=A[15:8]*B[15:8]+C[15:8], D[23:16]=A[23:16]*B[23:16]+C[23:16], D[31:24]=A[31:24]*B[31:24]+C[31:24];

[0084] Step 2: According to the configuration signal, call the corresponding decoder to complete the decoding process of the input data and output the valid sign, exponent and mantissa values ​​of the three operands A, B and C respectively;

[0085] Step 3: The exponents of the three operands A, B, and C are sequentially added and compared in the multi-precision exponent addition module and the multi-precision exponent difference module, respectively. Simultaneously, the mantissas of A and B are multiplied in the multi-precision mantissa multiplication module to obtain the mantissa of the multiplier. The exponent addition refers to adding the exponent of A to the exponent of B, and the result is the exponent of the multiplier. The exponent comparison and difference refers to calculating the difference between the exponent of the addend C and the exponent of the multiplier.

[0086] Step 4: Based on the results obtained in Step 3, complete the alignment of the mantissas of the multiplier and addend within the multi-precision mantissa alignment module;

[0087] Step 5: In the multi-precision mantissa addition module, complete the accumulation of the aligned multiplier mantissa and addend mantissa;

[0088] Step 6: In the multi-precision mantissa normalization and exponent adjustment module, complete the normalization shift of the mantissa; at the same time, adjust the exponent value of the final result according to the shift amount.

[0089] Step 7: In the multi-precision mantissa rounding module, complete the rounding of the normalized mantissa to obtain the final mantissa value.

[0090] Step 8: Call the corresponding encoder according to the configuration signal to complete the encoding process of the final result and output the calculation result.

[0091] Compared to traditional single-precision multiply-accumulate architectures, this invention adds control logic to the highest supported precision (32-bit) calculation path, fully utilizing segmentation and hardware multiplexing to enable parallel low-precision (16-bit or 8-bit) operations with minimal hardware overhead. Furthermore, by defining a unified data arrangement pattern for decoder and encoder inputs and outputs, this invention supports adding custom decoders and encoders based on various formats, such as traditional floating-point, Posit, and fixed-point formats, to achieve support for operations in multiple formats.

[0092] The following will detail the unified data arrangement mode of the decoder encoder, as well as the hardware-efficient implementation method and apparatus for multi-precision mantissa multiplication, multi-precision operand addition, multi-precision mantissa alignment, and multi-precision mantissa normalization proposed in this invention.

[0093] Unified data layout pattern for decoders and encoders:

[0094] To improve the flexibility of the arithmetic unit and expand its application scenarios, this invention unifies the data arrangement mode of the decoder and encoder input and output, enabling the proposed multi-precision fusion multiply-accumulate arithmetic unit to support different data formats, such as IEEE-754 floating-point format, Posit format, BFloat16 / TensorFloat-32 and fixed-point formats.

[0095] Specifically, the multi-precision decoder takes a 32-bit operand as input and outputs the operand's sign (4-bit), exponent (32-bit, for signed numbers), and mantissa (32-bit, left-aligned, i.e., the decimal point is after the most significant bit). In different precision modes, the significant data bits of the output sign, exponent, and mantissa change as follows, with invalid data bits padded with 0s:

[0096] In 8-bit precision mode, all 4 bits of the output sign are valid, representing the sign of each of the four input 8-bit operands; all 32 bits of the output exponent are valid, with each 8 bits representing a signed number and indicating the significant exponent of each of the four input 8-bit operands; all 32 bits of the output mantissa are valid, with each 8 bits representing the significant mantissa of each of the four input 8-bit operands.

[0097] In 16-bit precision mode, the 2nd and 4th bits of the output sign are valid, representing the sign of each of the two input 16-bit operands; each 14 bits of the output exponent are valid, representing the valid exponent of each of the two input 16-bit operands; and all 32 bits of the output mantissa are valid, with each 16 bits representing the valid mantissa of each of the two input 16-bit operands.

[0098] In 32-bit precision mode, only the most significant bit of the output sign is valid, representing the sign of the input 32-bit operand; only the lower 14 bits of the output exponent are valid, representing the significant exponent of the input 32-bit operand; all 32 bits of the output mantissa are valid, representing the significant mantissa of the input 32-bit operand.

[0099] The multi-precision encoder takes as input a sign (4-bit), an exponent (32-bit, signed number), and a mantissa (32-bit, left-aligned, i.e., the decimal point is after the most significant bit), and outputs a 32-bit encoded result. In different precision modes, the valid data bits of the input sign, exponent, and mantissa change as follows, while invalid data bits are 0:

[0100] In 8-bit precision mode, all 4 bits of the input sign are valid, representing the sign of each of the four 8-bit output results; all 32 bits of the input exponent are valid, with each 8 bits representing a signed number, indicating the significant exponent of each of the four 8-bit output results; all 32 bits of the input mantissa are valid, with each 8 bits representing the significant mantissa of each of the four 8-bit output results.

[0101] In 16-bit precision mode, the 2nd and 4th bits of the input sign are valid, representing the sign of each of the two 16-bit output results; each 14 bits of the input exponent are valid, representing the valid exponent of each of the two 16-bit output results; all 32 bits of the input mantissa are valid, with each 16 bits representing the valid mantissa of each of the two 16-bit output results.

[0102] In 32-bit precision mode, only the most significant bit of the input sign is valid, representing the sign of the 32-bit output result; only the lower 14 bits of the input exponent are valid, representing the exponent of the 32-bit output result; all 32 bits of the input mantissa are valid, representing the mantissa of the 32-bit operand to be output.

[0103] The schematic diagram of the output sign, exponent, and mantissa valid data of the overall decoder is shown below. Figure 2 As shown, the gray-filled parts are valid data bits, while the blank parts are invalid data bits, filled with zeros.

[0104] like Figure 3 As shown, the overall calculation process is as follows: The multi-precision decoder receives 32-bit input operands and generates a unified decoder output (i.e., the sign, exponent, and tail value that conform to the above rules). The output of the multi-precision decoder is sent to the multi-precision multiply-accumulate operation module, which processes it to obtain a unified encoder input (i.e., the sign, exponent, and tail value of the operation result that conforms to the above rules). Then, it is sent to the multi-precision encoder to obtain a 32-bit multi-precision operation result.

[0105] Under the above input / output rules, users can customize and add decoders and encoders of different formats, enabling the corresponding decoders and encoders according to the data format control signals during computation. Alternatively, only decoders and encoders of specific formats can be retained in the hardware to reduce additional area overhead.

[0106] Furthermore, the data arrangement pattern proposed in this invention can also easily expand the decoding and encoding modules to support higher precision (such as 64-bit input).

[0107] Multi-precision mantissa multiplication module:

[0108] Within the multi-precision mantissa multiplication module, the multiplication of two 32-bit mantissas (i.e., the mantissas of A and B) is performed according to the precision mode, resulting in a 64-bit product. The calculations to be performed by the multi-precision mantissa multiplication module under different precision modes are as follows: Figure 4 As shown, A3, A2, A1, A0 are 8-bit suboperands, A3A2, A1A0 are 16-bit suboperands, and A3A2A1A0 is a 32-bit operand (B is represented similarly):

[0109] To reduce the hardware overhead of supporting multi-precision multiplication operations, this invention decomposes the 32-bit multiplier into 16 8-bit sub-multipliers according to the lowest supported precision mode, such as... Figure 5As shown, by enabling the required sub-multipliers according to different precision modes and then adding the results together, support for multi-precision multiplication operations can be achieved in the same hardware.

[0110] Taking 16-bit precision mode as an example, the multiplication of the lower 16 bits of the 32-bit mantissas A and B is calculated as follows:

[0111] ,

[0112] The multiplication of the input 32-bit mantissa A and the high 16 bits of mantissa B is calculated as follows:

[0113] ,

[0114] Therefore, in 16-bit precision mode, the result of mantissa multiplication can be obtained by shifting and adding the results of the eight sub-multipliers A0*B0, A0*B1, A1*B0, A1*B1, A2*B2, A2*B3, A3*B2, and A3*B3.

[0115] In 32-bit precision mode, the result of mantissa multiplication can be obtained by shifting and adding the results of all 16 sub-multipliers.

[0116] In 8-bit precision mode, the result of the mantissa multiplication operation in 8-bit precision mode can be obtained by shifting and adding the results of the four sub-multipliers A0*B0, A1*B1, A2*B2, and A3*B3.

[0117] By decomposing the multiplier into sub-multipliers and enabling the necessary sub-multipliers according to the precision mode while bypassing the unnecessary sub-multipliers, support for multi-precision multiplication is achieved with minimal increase in hardware overhead, while reducing dynamic power consumption during low-precision operations.

[0118] Furthermore, based on the above approach, it is easy to extend the support of multi-precision multipliers to support multiplication operations of lower precision such as 4-bit, or higher precision such as 64-bit, 128-bit.

[0119] Multi-precision operand addition module:

[0120] The addition of two multi-precision data points is involved in the multi-precision exponent addition module, the multi-precision exponent difference module, the multi-precision mantissa addition module, and the multi-precision exponent adjustment module. This invention employs a segmented addition method, which reduces computational latency and avoids the expensive hardware overhead associated with supporting multi-precision addition.

[0121] like Figure 6 As shown, specifically, the two input multi-precision data are first divided into four sub-operands, namely A3, A2, A1, A0 and B3, B2, B1, B0. The four sub-adders A3+B3, A2+B2, A1+B1, and A0+B0 are then added in parallel. In 8-bit precision mode (i.e., m[1:0]=2'b00), the result of the four sub-adders is the final result. In 16-bit precision mode (i.e., m[1:0]=2'b01), the carry generated by sub-adders A0+B0 and A2+B2 needs to be propagated forward, that is, combined with sub-adders A1+B1, A2+B2, A3+B3, A2+B2, A1+B1, A0+B0 respectively. The results of A3+B3 are added together. In 32-bit precision mode (i.e., m[1:0]=2'b10), the carry generated by the four sub-adders needs to be propagated to higher bits. That is, the carry generated by sub-adder A0+B0 needs to be added to the result of sub-adder A1+B1. The carry generated by the result after addition continues to be propagated to higher bits and added to the result of sub-adder A2+B2. The carry generated continues to be added to the result of sub-adder A3+B3 to obtain the final multi-precision addition result.

[0122] The multi-precision segmented adder described above can perform multi-precision addition of two operands with arbitrary bit widths. Furthermore, based on the above design concept, the multi-precision adder can be easily extended to support higher precisions such as 64-bit and 128-bit.

[0123] Multi-precision mantissa alignment module:

[0124] Within the multi-precision mantissa alignment module, the mantissas of the addend and multiplier need to be aligned based on the difference in exponents between the addend and multiplier. Taking 8-bit single-precision mode as an example, the mantissa alignment shift process is as follows: Figure 7 As shown (where the filled pattern represents the valid addend or multiplier mantissa, and the blank part represents zero): In 8-bit precision mode, the 8-bit addend is initially placed to the left of the 16-bit multiplier, and then the addend is right-shifted and aligned according to the difference E between the exponents of the addend and multiplier: when E is greater than or equal to 9, the right shift of the addend is 0; when E is less than or equal to -15, the right shift of the addend is 24; otherwise, the right shift of the addend is (9-E).

[0125] In 16-bit precision mode, the 16-bit addend is initially placed to the left of the 32-bit multiplier. Then, the addend is right-shifted and aligned according to the difference E between the exponents of the addend and the multiplier: when E is greater than or equal to 17, the right shift of the addend is 0; when E is less than or equal to -31, the right shift of the addend is 48; otherwise, the right shift of the addend is (17-E).

[0126] In 32-bit precision mode, the 32-bit addend is initially placed to the left of the 64-bit multiplier. Then, the addend is right-shifted and aligned according to the difference E between the exponents of the addend and the multiplier: when E is greater than or equal to 33, the right shift of the addend is 0; when E is less than or equal to -63, the right shift of the addend is 96; otherwise, the right shift of the addend is (33-E).

[0127] To support mantissa alignment in multi-precision multiply-accumulate operations, one approach is to follow... Figure 7 The previous approach implemented alignment and shift modules for different precision modes within a hardware unit, enabling the corresponding module based on the precision mode during computation. While the design is simple, it incurs significant hardware overhead, especially the redundant dynamic shifting process, which not only reduces hardware utilization but also greatly increases power consumption. Therefore, this invention proposes a segmented multi-precision mantissa shifting and alignment scheme. Based on a 32-bit single-precision shifting and alignment device, it adds only some selection or control logic to support mantissa alignment shifting in low-precision mode, achieving high hardware utilization.

[0128] Specifically, the selector first rearranges the mantissa of the addend (i.e., the mantissa of the input operand C) and the mantissa of the multiplier (i.e., the product of the mantissas of the input operands A and B) under different data precision modes, such as... Figure 8 As shown (where the filled parts are the actual valid addends or multipliers, and the blank parts are zero).

[0129] The mantissa data of the multi-precision addend and multiplier are rearranged according to the precision mode control signal to ensure that the initial position of the addend value is to the left of its corresponding multiplier in 8-bit, 16-bit and 32-bit precision modes; the mantissa of the multi-precision addend is the mantissa of the input multi-precision operand C; the mantissa of the multiplier is the product of the mantissas of the input multi-precision operands A and B.

[0130] After obtaining the rearranged mantissas of the addend and multiplier, the mantissa of the addend needs to be shifted to the right according to the difference in exponents of the addend and multiplier to align with the mantissa of the multiplier. This invention reduces the hardware overhead of dynamic shifting in multi-precision modes by using segmented shifting.

[0131] Specifically, in 8-bit precision mode, each 24-bit of the rearranged addend has its own right shift amount, which is between 0 and 24 (this shift amount can be represented by a 5-bit number); each 24-bit corresponds to a set of input operand addends, for a total of four sets;

[0132] In 16-bit precision mode, the rearranged addends have their own right shift amount for each 48-bit interval, with the shift amount ranging from 0 to 48 (this shift amount can be represented by a 6-bit number); each 48-bit interval corresponds to a set of input operand addends, for a total of two sets;

[0133] In 32-bit precision mode, the rearranged 96-bit addend has a uniform right shift amount, which is between 0 and 96 (this shift amount can be represented by a 7-bit number).

[0134] Based on the precision mode control signal, the shift amount of each 24-bit valid data segment d, c, b, a can be determined, which are sft_amt_d, sft_amt_c, sft_amt_b, and sft_amt_a, respectively. The shift amounts sft_amt_d, sft_amt_c, sft_amt_b, and sft_amt_a are all represented by a 7-bit data width, i.e., sft_amt_d[6:0], sft_amt_c[6:0], sft_amt_b[6:0], and sft_amt_a[6:0].

[0135] After determining the alignment shift amount for each segment of the addend, multi-precision shifting is supported through segmented and hierarchical shifting. Specifically, for each 24-bit addend, it enters its respective shifter in parallel to complete five-level shifting (five-level shifting can be achieved, for example, by a bucket shifter). The shift amounts are the values ​​represented by the lower 5 bits of their respective shift amounts, which are: sft_amt_d[4:0], sft_amt_c[4:0], sft_amt_b[4:0], sft_amt_a[4:0]. After completing the shifting of levels 1 to 5, the shifted result is determined by the precision mode control signal (m[1:0]) to decide whether to perform a bitwise OR operation with the shifted-out higher bits.

[0136] In 8-bit precision mode (i.e., m[1:0]=2'b00), no bitwise OR operation is required;

[0137] In 16-bit precision mode (i.e., m[1:0]=2'b01), the result of shifting segment c needs to be bitwise ORed with the bit shifted out of segment d, and the result of shifting segment a needs to be bitwise ORed with the bit shifted out of segment b.

[0138] In 32-bit precision mode (i.e., m[1:0]=2'b10), the results of shifting segments a, b, and c all need to be bitwise ORed with the bits shifted out from higher segments.

[0139] After completing the segmented shifts of levels 1 to 5, the results of shifting a and b, and c and d are used as a whole 48-bit data to participate in the shift of level 6. That is, based on the value of the 6th bit of the shift amount sft_amt_b[5], sft_amt_d[5], it is determined whether a 32-bit right shift is needed: when the value is 1, a 32-bit right shift is needed; when the value is 0, no shift is needed. When in 32-bit precision mode (i.e., m[1:0]=2'b10), the result of the shifted lower 48 bits needs to be bitwise ORed with the shifted-out bits of the higher 48 bits.

[0140] After completing the 6th level shift, the two 48-bit shift results are combined into a 96-bit whole to participate in the 7th level shift. That is, the value of the 7th bit of the shift amount, sft_amt_d[6], determines whether to shift right by 64 bits. When the value is 1, shift right by 64 bits; when the value is 0, do not shift. The final output result is the result of the addend shift alignment in multi-precision mode. The overall operation process is as follows: Figure 9 As shown.

[0141] Following the above design concept, multi-precision shifting with other bit widths and other precisions can be easily supported.

[0142] Within the multi-precision mantissa normalization and exponent adjustment module, the result of adding the mantissas of the addend and multiplier after shift alignment needs to be normalized and shifted. This includes two processes: multi-precision leading zero counting to determine the shift amount, and multi-precision shifting based on the shift amount.

[0143] For multi-precision leading zero counting, in 8-bit precision mode, the leading zero counts cpm[3], cpm[2], cpm[1] and cpm[0] of each 24-bit result (four groups in total) need to be calculated; in 16-bit precision mode, the leading zero counts cph[1] and cph[0] of each 48-bit result (two groups in total) need to be calculated; in 32-bit precision mode, the leading zero count cps of the overall 96-bit result needs to be calculated.

[0144] In 16-bit precision mode, the number of leading zeros for each 48-bit result needs to be calculated, namely cph[1], cph[0]; in 32-bit precision mode, the number of leading zeros for the overall 96-bit result is calculated, namely cps. In order to reduce hardware overhead, a segmented leading zero counting device is adopted: for each 24-bit input d, c, b, a, the number of leading zeros cpm and the data valid signal vpm are counted in parallel by the 24-bit leading zero counting module (for the output of the leading zero counting module, generally, vpm=1, cpm is the number of leading zeros; but when the input is all 0, vpm=0, cpm=0), respectively cpm[3], cpm[2], cpm[1], cpm[0] and vpm[3], vpm[2], vpm[1], vpm[0]. The number of leading zeros is the normalized shift amount of each segment operand in 8-bit precision mode;

[0145] For the two sets of leading zeros cph[1], cph[0] and two sets of valid data signals vph[1], vph[0] in 16-bit precision mode, they are obtained by a selector and an adder based on the leading zeros and valid data signals in 8-bit precision mode. For example, for cph[1], when vpm[3] equals 1, cph[1] equals cpm[3]; when vpm[3] equals 0, the vpm[2] signal is judged. If vpm[2] equals 1, then cph[1] equals cpm[2]+24; otherwise, cph[1] equals 0. The value of cph[0] is calculated in the same way.

[0146] For the leading zero count (cps) and valid data signal (vps) in 32-bit precision mode, they are obtained by using a selector and an adder based on the leading zero count and valid data signal in 16-bit precision mode.

[0147] The calculation process of multi-precision leading zero counting is as follows: Figure 10 As shown, based on this design concept, it is also easy to extend support to other precisions (such as 64-bit).

[0148] Based on the results of the segmented leading zero count, the normalized shift amount of the multi-precision mantissa can be determined. The process of multi-precision normalized shift is similar to the multi-precision mantissa alignment shift described above. It adopts a segmented and hierarchical shifting method. At the same time, it determines whether the shifted result needs to be bitwise ORed with the bit shifted out of the previous segment based on the precision mode. This enables support for multi-precision normalized shift with minimal increase in hardware overhead.

[0149] Example

[0150] In a specific embodiment, based on the multi-precision fusion multiply-accumulate arithmetic device and method compatible with multiple formats proposed in this invention, a 32-bit multi-precision Posit multiply-accumulate arithmetic unit is implemented, which supports 1*32-bit, 2*16-bit, or 4*8-bit multi-precision arithmetic. Meanwhile, to achieve the above functions using existing Posit single-precision multiply-accumulate arithmetic units, four 8-bit single-precision Posit multiply-accumulate arithmetic units (Posit8-FMA), two 16-bit single-precision Posit multiply-accumulate arithmetic units (Posit16-FMA), and one 32-bit single-precision Posit multiply-accumulate arithmetic unit (Posit32-FMA) need to be implemented in hardware simultaneously, thereby enabling the required single-precision multiply-accumulate arithmetic units according to the precision mode control signal.

[0151] The 32-bit multi-precision Posit multiply-accumulate unit implemented in this scheme was integrated with existing single-precision multiply-accumulate units based on 8-bit, 16-bit, and 32-bit technologies using TSMC's 28 nm process. The area, power consumption, latency, computational performance, area efficiency, and energy efficiency of the two units were compared, as shown in Table 1.

[0152] Table 1

[0153]

[0154] As can be seen, this solution, based on a 32-bit single-precision multiply-accumulate unit, achieves efficient support for low-precision parallel computing through segmentation and hardware reuse, with only a slight increase in latency and area overhead. Furthermore, for low-precision parallel 8-bit or 16-bit operations, this solution achieves a 1.65x and 1.23x performance improvement respectively compared to the corresponding single-precision implementation. For 32-bit operations, only a slight performance loss is incurred despite the addition of control and selection logic. More importantly, to achieve the same multi-precision support functionality using existing single-precision multiply-accumulate units, a combination of four 8-bit multiply-accumulate units, two 16-bit multiply-accumulate units, and one 32-bit multiply-accumulate unit is required. In comparison, this solution achieves a 45.82% reduction in area and a 78.66% reduction in power consumption, achieving high area efficiency and energy efficiency.

[0155] In addition to supporting the Posit format in this embodiment, this device can also be easily extended to support other formats, such as traditional floating-point formats and fixed-point formats, so that it can be flexibly applied to different computing scenarios.

[0156] This invention provides a multi-precision fusion multiplication-accumulation arithmetic device and method compatible with multiple formats. Many methods and approaches exist for implementing this technical solution; the above description is merely a preferred embodiment of the invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this invention, and these improvements and modifications should also be considered within the scope of protection of this invention. All components not explicitly stated in this embodiment can be implemented using existing technologies.

Claims

1. A multi-precision fusion multiply-accumulate arithmetic device compatible with multiple formats, characterized in that, Includes a multi-precision decoder, a multi-precision multiply-accumulate operation module, and a multi-precision encoder; The multi-precision decoder and multi-precision encoder are used to decode the input operands and encode the output results, respectively. The multi-precision multiply-accumulate operation module receives the output of the multi-precision decoder, completes the multi-precision multiply-accumulate calculation, and uses the calculation result as the input of the multi-precision encoder; The multi-precision decoder and multi-precision encoder support multi-precision input and output, and also allow users to customize and add decoding and encoding modules of various formats according to the unified decoder and encoder input and output data arrangement rules, thereby achieving compatibility support for various formats. The multi-precision decoder takes a 32-bit operand as input and outputs the sign, exponent, and mantissa of the operand. In different precision modes, the valid data bits of the output sign, exponent, and mantissa change as follows, with invalid data bits padded with 0s: In 8-bit precision mode, all 4 bits of the output sign are valid, representing the sign of each of the four input 8-bit operands; all 32 bits of the output exponent are valid, with each 8 bits representing a signed number and indicating the significant exponent of each of the four input 8-bit operands; all 32 bits of the output mantissa are valid, with each 8 bits representing the significant mantissa of each of the four input 8-bit operands. In 16-bit precision mode, the 2nd and 4th bits of the output sign are valid, representing the sign of each of the two input 16-bit operands; each 14 bits of the output exponent are valid, representing the valid exponent of each of the two input 16-bit operands; and all 32 bits of the output mantissa are valid, with each 16 bits representing the valid mantissa of each of the two input 16-bit operands. In 32-bit precision mode, only the most significant bit of the output sign is valid, representing the sign of the input 32-bit operand; only the lower 14 bits of the output exponent are valid, representing the significant exponent of the input 32-bit operand; all 32 bits of the output mantissa are valid, representing the significant mantissa of the input 32-bit operand. The multi-precision encoder takes the sign, exponent, and mantissa as input and outputs a 32-bit encoded result. In different precision modes, the valid data bits of the input sign, exponent, and mantissa change as follows, while the invalid data bits are 0: In 8-bit precision mode, all 4 bits of the input sign are valid, representing the sign of each of the four 8-bit output results; all 32 bits of the input exponent are valid, with each 8 bits representing a signed number, indicating the significant exponent of each of the four 8-bit output results; all 32 bits of the input mantissa are valid, with each 8 bits representing the significant mantissa of each of the four 8-bit output results. In 16-bit precision mode, the 2nd and 4th bits of the input sign are valid, representing the sign of each of the two 16-bit output results; each 14 bits of the input exponent are valid, representing the valid exponent of each of the two 16-bit output results; all 32 bits of the input mantissa are valid, with each 16 bits representing the valid mantissa of each of the two 16-bit output results. In 32-bit precision mode, only the most significant bit of the input sign is valid, representing the sign of the 32-bit output result; only the lower 14 bits of the input exponent are valid, representing the exponent of the 32-bit output result; all 32 bits of the input mantissa are valid, representing the mantissa of the 32-bit operand to be output. The multi-precision decoder receives 32-bit input operands, generates a unified decoder output, and sends the output of the multi-precision decoder to the multi-precision multiply-accumulate operation module for processing to obtain a unified encoder input, which is then sent to the multi-precision encoder to obtain a 32-bit multi-precision operation result.

2. The apparatus according to claim 1, characterized in that, The multi-precision multiplication and accumulation operation module includes a multi-precision mantissa multiplication module, a multi-precision exponent addition module, a multi-precision exponent difference module, a multi-precision mantissa alignment module, a multi-precision mantissa addition module, a multi-precision mantissa normalization and exponent adjustment module, and a multi-precision mantissa rounding module. Within the multi-precision mantissa multiplication module, multiplication between two 32-bit mantissas is performed according to the precision mode to obtain a 64-bit product result. Specifically, this includes: in 32-bit precision mode, the two 32-bit input mantissas are multiplied by a 32-bit multiplier to obtain a 64-bit product result; in 16-bit precision mode, the lower 16 bits of each of the two 32-bit input mantissas are multiplied by a 16-bit multiplier to obtain the lower 32-bit value of the 64-bit product result, and the higher 16 bits are multiplied to obtain the higher 32-bit value of the 64-bit product result; in 8-bit precision mode, each 8-bit of each of the two 32-bit input mantissas is multiplied by an 8-bit multiplier, and the four sets of 16-bit product results are combined to obtain the 64-bit product result. Divide the two 32-bit input mantissas A and B into 8-bit segments to obtain four suboperands A3, A2, A1, A0 and B3, B2, B1, B0 respectively. Then implement 16 8-bit submultipliers, namely A0*B0, A0*B1, A1*B0, A0*B2, A1*B1, A2*B0, A0*B3, A1*B2, A2*B1, A3*B0, A1*B3, A2*B2, A3*B1, A2*B3, A3*B2, A3*B3; The 32-bit, 16-bit, and 8-bit multipliers under different precision modes are all implemented through the 16 8-bit sub-multipliers. The required number of sub-multipliers is enabled according to the different precision modes, and the results are then added together, thereby achieving support for multi-precision multiplication operations in the same hardware. Specifically, this includes: In 16-bit precision mode, the multiplication of the lower 16 bits of the 32-bit mantissas A and B is calculated as follows: ， The multiplication of the input 32-bit mantissa A and the high 16 bits of mantissa B is calculated as follows: ， In 16-bit precision mode, the result of the mantissa multiplication operation in 16-bit precision mode can be obtained by shifting and adding the results of the eight sub-multipliers A0*B0, A0*B1, A1*B0, A1*B1, A2*B2, A2*B3, A3*B2, and A3*B3. In 32-bit precision mode, the result of mantissa multiplication can be obtained by shifting and adding the results of all 16 sub-multipliers. In 8-bit precision mode, the result of the mantissa multiplication operation in 8-bit precision mode can be obtained by shifting and adding the results of the four sub-multipliers A0*B0, A1*B1, A2*B2, and A3*B3.

3. The apparatus according to claim 2, characterized in that, Within the multi-precision exponent addition module, multi-precision exponent difference module, multi-precision mantissa addition module, and multi-precision mantissa normalization and exponent adjustment module, a segmented addition method is used to complete the addition of two multi-precision data. First, the two input multi-precision data are each divided into four sub-operands: A3, A2, A1, A0 and B3, B2, B1, B0. These four sub-adders (A3+B3, A2+B2, A1+B1, A0+B0) are then added in parallel. In 8-bit precision mode, the result of the four sub-adders is the final result. In 16-bit precision mode, the carry generated by sub-adders A0+B0 and A2+B2 needs to be propagated forward, i.e., it is combined with the carry generated by sub-adders A1+B1, A2+B2, A3+B3, A2+B2, A1+B1, A0+B0 respectively. The results of A3+B3 are added together. In 32-bit precision mode, the carry generated by the four sub-adders needs to be propagated to higher bits. That is, the carry generated by sub-adder A0+B0 needs to be added to the result of sub-adder A1+B1. The carry generated by the result of the addition continues to be propagated to higher bits and added to the result of sub-adder A2+B2. The carry generated by the addition continues to be added to the result of sub-adder A3+B3 to obtain the final multi-precision addition result.

4. The apparatus according to claim 3, characterized in that, Within the multi-precision mantissa alignment module, the mantissas of the multi-precision addend and multiplier need to be aligned based on the difference in exponents between the addend and multiplier. The mantissa alignment process is as follows: In 8-bit precision mode, the 8-bit addend is initially placed to the left of the 16-bit multiplier. Then, the addend is right-shifted and aligned according to the difference E between the exponents of the addend and the multiplier: when E is greater than or equal to 9, the right shift of the addend is 0; when E is less than or equal to -15, the right shift of the addend is 24; otherwise, the right shift of the addend is 9-E. In 16-bit precision mode, the 16-bit addend is initially placed to the left of the 32-bit multiplier. Then, the addend is right-shifted and aligned according to the difference E between the exponents of the addend and the multiplier: when E is greater than or equal to 17, the right shift of the addend is 0; when E is less than or equal to -31, the right shift of the addend is 48; otherwise, the right shift of the addend is 17-E. In 32-bit precision mode, the 32-bit addend is initially placed to the left of the 64-bit multiplier. Then, the addend is right-shifted and aligned according to the difference E between the exponents of the addend and the multiplier: when E is greater than or equal to 33, the right shift of the addend is 0; when E is less than or equal to -63, the right shift of the addend is 96; otherwise, the right shift of the addend is 33-E.

5. The apparatus according to claim 4, characterized in that, The mantissa data of the multi-precision addend and multiplier are rearranged according to the precision mode control signal to ensure that the initial position of the addend value is to the left of its corresponding multiplier in 8-bit, 16-bit and 32-bit precision modes; the mantissa of the multi-precision addend is the mantissa of the input multi-precision operand C; the mantissa of the multiplier is the product of the mantissas of the input multi-precision operands A and B. After obtaining the rearranged mantissas of the addend and multiplier, the mantissa of the addend needs to be shifted to the right according to the difference between the exponents of the addend and multiplier in order to align with the mantissa of the multiplier. Segmented shifting reduces the hardware overhead for supporting dynamic shifting in multi-precision modes, specifically including: In 8-bit precision mode, the rearranged addends have their own right shift amount for each 24 bits, with the shift amount ranging from 0 to 24; each 24 bits corresponds to a set of input operand addends, for a total of four sets; In 16-bit precision mode, the rearranged addends have their own right shift amount for each 48-bit interval, with the shift amount ranging from 0 to 48; each 48-bit interval corresponds to a set of input operand addends, for a total of two sets; In 32-bit precision mode, the rearranged 96-bit addend has a uniform right shift amount, which is between 0 and 96. Based on the precision mode control signal, the shift amount of each 24-bit valid data segment d, c, b, a can be determined, which are sft_amt_d, sft_amt_c, sft_amt_b, and sft_amt_a, respectively. The shift amounts sft_amt_d, sft_amt_c, sft_amt_b, and sft_amt_a are all represented by 7-bit data widths, i.e., sft_amt_d[6:0], sft_amt_c[6:0], sft_amt_b[6:0], and sft_amt_a[6:0]. After determining the alignment shift amount for each segment of the addend, multi-precision shifting is supported through segmented and hierarchical shifting. Specifically, for each 24-bit addend, it is fed into its respective shifter in parallel to complete five levels of shifting, with shift amounts of sft_amt_d[4:0], sft_amt_c[4:0], sft_amt_b[4:0], and sft_amt_a[4:0]. After completing the shifting of levels 1 to 5, the shifted result is determined by the precision mode control signal to perform a bitwise OR operation with the shifted-out higher bits. In 8-bit precision mode, no bitwise OR operation is required; In 16-bit precision mode, the result of shifting segment c needs to be bitwise ORed with the bit shifted out of segment d, and the result of shifting segment a needs to be bitwise ORed with the bit shifted out of segment b. In 32-bit precision mode, the results of shifting segments a, b, and c all need to be bitwise ORed with the bits shifted out from higher segments; After completing the segmented shifts of levels 1 to 5, the results of shifting a and b, and c and d are used as a whole 48-bit data to participate in the shift of level 6. That is, based on the value of the 6th bit of the shift amount sft_amt_b[5], sft_amt_d[5], it is determined whether a 32-bit right shift is needed: when the value is 1, a 32-bit right shift is needed; when the value is 0, no shift is needed. When in 32-bit precision mode, the result after the shift of the lower 48-bits needs to be bitwise ORed with the shifted-out bits of the higher 48-bits. After completing the 6th level shift, the two 48-bit shift results form a 96-bit whole to participate in the 7th level shift. That is, according to the value of the 7th bit of the shift amount sft_amt_d[6], it is selected whether to shift right by 64 bits. When the value is 1, shift right by 64 bits; when the value is 0, do not shift. The final output result is the result of addend shift alignment in multi-precision mode.

6. The apparatus according to claim 5, characterized in that, Within the multi-precision mantissa normalization and exponent adjustment module, the result of adding the mantissas of the addend and multiplier after shift alignment needs to be normalized and shifted. This includes two processes: multi-precision leading zero counting to determine the shift amount, and multi-precision shifting based on the shift amount. For multi-precision leading zero counting, in 8-bit precision mode, the number of leading zeros cpm[3], cpm[2], cpm[1] and cpm[0] of each 24-bit result needs to be calculated; in 16-bit precision mode, the number of leading zeros cph[1] and cph[0] of each 48-bit result needs to be calculated; in 32-bit precision mode, the number of leading zeros cps of the overall 96-bit result needs to be calculated. A device employing segmented leading zero counting: For each 24-bit input d, c, b, a, the leading zero count cpm and the valid data signal vpm are counted in parallel by a 24-bit leading zero counting module, respectively cpm[3], cpm[2], cpm[1], cpm[0] and vpm[3], vpm[2], vpm[1], vpm[0]. The leading zero count is the normalized shift amount of each segment operand in 8-bit precision mode. For the two sets of leading zero count cph[1], cph[0] and two sets of valid data signals vph[1], vph[0] in 16-bit precision mode, they are obtained by a selector and an adder based on the leading zero count and valid data signal in 8-bit precision mode. For the leading zero count cps and valid data signal vps in 32-bit precision mode, they are obtained by a selector and an adder based on the leading zero count and valid data signal in 16-bit precision mode.

7. A method for multi-precision fusion multiplication-accumulation operations compatible with multiple formats for use in the apparatus as described in claim 1, characterized in that, Includes the following steps: Step 1: Input three 32-bit operands A, B, and C, and the corresponding configuration signals. The configuration signals include the precision mode and data format. The precision mode supports 32-bit, 16-bit, and 8-bit precision; the data format supports traditional floating-point format, POSIT format, and fixed-point format. The multi-precision operation A*B+C will be performed in subsequent steps 2-8. In 32-bit precision mode, it supports 1*32-bit operations. The output result D consists of all 32 bits, which is the sum of the 32-bit inputs A, B, and C, and is expressed as: D[31:0]=A[31:0]*B[31:0]+C[31:0]; D[31:0] is the value of all 32 bits of the output result D. In 16-bit precision mode, it supports 2*16-bit operations. The lower 16-bit and higher 16-bit values ​​of the output result D are the results of multiplying and accumulating the lower 16-bit and higher 16-bit values ​​of the 32-bit inputs A, B, and C respectively: D[15:0]=A[15:0]*B[15:0]+C[15:0], D[31:16]=A[31:16]*B[31:16]+C[31:16]; In 8-bit precision mode, it supports 4*8-bit operations. The value of each 8-bit of the output result D is the result of multiplying and accumulating the values ​​of each 8-bit of the 32-bit inputs A, B, and C respectively, as follows: D[7:0]=A[7:0]*B[7:0]+C[7:0], D[15:8]=A[15:8]*B[15:8]+C[15:8], D[23:16]=A[23:16]*B[23:16]+C[23:16], D[31:24]=A[31:24]*B[31:24]+C[31:24]; Step 2: According to the configuration signal, call the corresponding decoder to complete the decoding process of the input data and output the valid sign, exponent and mantissa values ​​of the three operands A, B and C respectively; Step 3: The exponents of the three operands A, B, and C are sequentially added and compared in the multi-precision exponent addition module and the multi-precision exponent difference module, respectively. Simultaneously, the mantissas of A and B are multiplied in the multi-precision mantissa multiplication module to obtain the mantissa of the multiplier. The exponent addition refers to adding the exponent of A to the exponent of B, and the result is the exponent of the multiplier. The exponent comparison and difference refers to calculating the difference between the exponent of the addend C and the exponent of the multiplier. Step 4: Based on the results obtained in Step 3, complete the alignment of the mantissas of the multiplier and addend within the multi-precision mantissa alignment module; Step 5: In the multi-precision mantissa addition module, complete the accumulation of the aligned multiplier mantissa and addend mantissa; Step 6: In the multi-precision mantissa normalization and exponent adjustment module, complete the normalization shift of the mantissa; at the same time, adjust the exponent value of the final result according to the shift amount. Step 7: In the multi-precision mantissa rounding module, complete the rounding of the normalized mantissa to obtain the final mantissa value. Step 8: Call the corresponding encoder according to the configuration signal to complete the encoding process of the final result and output the calculation result.

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