System-on-chip architecture and its data protection method

Abstract

The present application is a system on chip architecture, comprising: a non-volatile memory; and a system on chip. The system on chip comprises: a central processing unit, a volatile memory, a system bus, an instant encryption and decryption circuit, a memory interface, a timer and a key library. The central processing unit, the volatile memory and the instant encryption and decryption circuit are connected to the system bus. The memory interface is connected between the instant encryption and decryption circuit and the non-volatile memory. The instant encryption and decryption circuit is connected to the key library for selecting a plurality of keys in the key library to perform an encryption operation or a decryption operation. After a power is turned on, when the timer is not disabled, the timer resets the central processing unit after a specific time, so that the central processing unit changes a storage format of the non-volatile memory from an initial format to a working format.

Description

Technical Field

[0001] This invention relates to a circuit architecture and its data protection method, and more particularly to a system-on-a-chip (SoC) architecture with external non-volatile memory and its related data protection method. Background Technology

[0002] As is well known, embedded systems typically use a system-on-a-chip (SoC) as the control center. Generally, the SoC architecture in an embedded system consists of the SoC and external non-volatile memory. That is, in the SoC architecture, the SoC is connected to external non-volatile memory, which stores the program code that the SoC needs to execute. Essentially, competitors can easily spy on the program code in the external non-volatile memory and understand how the SoC operates.

[0003] In security-related embedded systems, the program code is first encrypted into ciphertext and stored in external non-volatile memory. That is, the encrypted program code can be considered ciphertext, and the decrypted program code can be considered plaintext. Because the ciphertext is stored in external non-volatile memory, even if a competitor steals the ciphertext from the external non-volatile memory, they cannot determine the operating mode of the system chip.

[0004] Please refer to Figure 1The diagram illustrates a system-on-a-chip (SoC) architecture for an existing embedded system. The SoC architecture 190 includes a SoC 100 and non-volatile memory 160. The SoC 100 includes a central processing unit (CPU) 110, embedded flash memory (eFlash) 120, a system bus 130, on-the-fly decryption (OTFDEC) circuitry 140, and a memory interface 150. The embedded flash memory 120 stores the boot code. Furthermore, the SoC 100 is connected to the external non-volatile memory 160 via the memory interface 150.

[0005] like Figure 1 As shown, when the power is turned on, the system chip 100 begins the initialization process based on the boot code in the embedded flash memory 120. First, the instruction pointer (IP) of the central processing unit 110 points to the address of the embedded flash memory 120. The central processing unit 110 reads and executes the boot code in the embedded flash memory 120 via the system bus 130 and completes the initialization process.

[0006] Once the initialization process is complete, the system chip 100 can operate normally. During normal operation of the embedded system, the instruction pointer of the central processing unit 110 points to the non-volatile memory 160, enabling the central processing unit 110 to access the ciphertext in the non-volatile memory 160. However, since the central processing unit 110 cannot directly execute the encrypted program code in the ciphertext, the OTFDEC circuit 140 uses the key 142 to perform encryption and decryption operations.

[0007] For example, the OTFDEC circuit 140 reads the ciphertext from the non-volatile memory 160 via the memory interface 150 and decrypts the ciphertext using the key 142. After being converted to plaintext, the central processing unit 110 can execute the decryption code in the plaintext. Alternatively, when the central processing unit 110 stores data into the non-volatile memory 160, the OTFDEC circuit 140 first encrypts the stored data and converts it into ciphertext, which is then stored in the non-volatile memory 160 via the memory interface 150.

[0008] As explained above, in the existing system-on-a-chip architecture 190, encrypted data is transmitted between the OTFDEC circuit 140, memory interface 150, and non-volatile memory 160. Plaintext data is transmitted between the central processing unit 110, embedded flash memory 120, and OTFDEC circuit 140. Therefore, the existing system-on-a-chip architecture can achieve the purpose of data protection.

[0009] Furthermore, because the central processing unit 110 needs to access data in the external non-volatile memory 160 in real time, excessive access latency will reduce the performance of the system chip 100. Therefore, the encryption and decryption algorithms in the OTFDEC circuit 140 must have low latency characteristics. In other words, the OTFDEC circuit 140 cannot use complex encryption and decryption algorithms. If the OTFDEC circuit 140 uses complex encryption and decryption algorithms, it will result in excessively long access latency.

[0010] Furthermore, to prevent competitors from observing the relationship between the plaintext and ciphertext and thus cracking the key 142, each OTFDEC circuit 140 in different system-on-a-chip architectures 190 uses a different key. Moreover, the key used by each OTFDEC circuit 140 is a unique key that cannot be read.

[0011] Please refer to Figure 2 The diagram illustrates n identical embedded systems. These n identical embedded systems share the same system-on-a-chip (SoC) architecture. Furthermore, each SoC 201-20n is connected to a corresponding non-volatile memory 261-26n. Each SoC 201-20n is identical to... Figure 1 The internal connections of the system single chip 100 will not be described in detail.

[0012] Basically, the central processing units (CPUs) within system chips 201-20n all operate based on the same plaintext. That is, the CPUs within system chips 201-20n all operate based on the same decryption code. Furthermore, each system chip 201-20n is equipped with different keys Key1-Key2. n To perform encryption and decryption operations, the ciphertexts ciphertext1 and ciphertext1 are completely different. n It will be stored in the corresponding non-volatile memory 216~26n.

[0013] For example, the system-on-a-chip 201 decrypts the ciphertext1 using key Key1 and converts it into plaintext, enabling the central processing unit (CPU) in the system-on-a-chip 201 to execute the decryption code in the plaintext. Furthermore, when the CPU in the system-on-a-chip 201 stores data in the non-volatile memory 261, the system-on-a-chip 201 encrypts the stored data using key Key1, converts it into ciphertext1, and stores it in the non-volatile memory 261.

[0014] As explained above, each system chip 201~20n must be paired with a corresponding key Key1~Key n Only then can it function properly. If, during the manufacturing process, the system chips 201-20n are connected to the wrong non-volatile memories 261-26n, the system chip architecture will fail to operate. For example, if system chip 201 is connected to non-volatile memory 262 storing the ciphertext2, it's obvious that the content after system chip 201 decrypts the ciphertext2 using key Key1 will not be plaintext. This will prevent system chip 201 from executing the decryption code, causing the system to crash and malfunction.

[0015] As explained above, during the production process of existing embedded systems, after storing the ciphertext1 generated by key Key1 into non-volatile memory 261, it is necessary to further verify that non-volatile memory 261 is connected to system chip 201. Otherwise, if the system chip is connected to the wrong non-volatile memory, the embedded system will still fail to operate. In other words, during the mass production of existing embedded systems, the connection relationship between system chips 201~20n and non-volatile memories 261~26n must be verified very carefully, which increases the manufacturer's management costs during production.

[0016] In addition, in existing embedded systems, the embedded flash memory 120 in the system chip 100 is used as the boot area, and the encryption and decryption management of the external non-volatile memory 160 is performed. Summary of the Invention

[0017] This invention relates to a system-on-a-chip (SoC) architecture, comprising: a non-volatile memory; and a SoC. The SoC is connected to the non-volatile memory. The SoC includes: a central processing unit (CPU), a volatile memory, a system bus, an instantaneous encryption / decryption circuit, a memory interface, a timer, and a key library. The CPU, the volatile memory, and the instantaneous encryption / decryption circuit are connected to the system bus. The memory interface is connected between the instantaneous encryption / decryption circuit and the non-volatile memory. The instantaneous encryption / decryption circuit is connected to the key library and is used to select multiple keys from the key library to perform an encryption or decryption operation. Upon power-on, when the timer is not disabled, the timer resets the CPU after a specific time, causing the CPU to change the storage format of the non-volatile memory from an initial format to an operating format.

[0018] This invention provides a data protection method for the aforementioned system-on-a-chip architecture, comprising the following steps: (a) after the power is turned on, the instantaneous encryption / decryption circuit is in a normal mode; (b) the central processing unit executes an encrypted boot code in the non-volatile memory, wherein the encrypted boot code includes a disable instruction to disable the timer; (c) when the timer is disabled, the central processing unit executes an encrypted program code in the non-volatile memory, enabling the system-on-a-chip architecture to operate normally; (d) when the timer is not disabled, after a specific time, the instantaneous encryption / decryption circuit is changed to a transparent mode, and the central processing unit is warm-reset; (e) after the central processing unit is warm-reset, the central processing unit executes an initial... (f) If the timer is not disabled, return to step (d); (g) If the timer is disabled, the central processing unit copies the initial power-on code from the non-volatile memory to the volatile memory and executes the initial power-on code in the volatile memory; (h) The central processing unit changes the instantaneous encryption / decryption circuit to a dual-key mode according to the initial power-on code in the volatile memory; (i) The central processing unit reads encrypted data from the non-volatile memory into the system chip according to the initial power-on code in the volatile memory and stores it back into the non-volatile memory; and (j) Perform a system reset.

[0019] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0020] Figure 1For existing embedded systems, it is a system-on-a-chip architecture; Figure 2 This is a schematic diagram of n identical embedded systems. Figure 3A This is the system single-chip architecture of the present invention; Figure 3B and Figure 3C This is a schematic diagram of the storage format in the non-volatile memory of the present invention; and Figure 4 This is a flowchart of a data protection method applied to the single-chip architecture of the system of this invention. The reference numerals in the attached figures are explained as follows: 100, 201~20n, 300: System-on-a-Chip 110, 310: Central Processing Unit 120: Embedded flash memory 130, 330: System bus 140, 340: Real-time encryption / decryption circuit 142: Key 150, 350: Memory interface 160, 261~26n, 380: Non-volatile memory 190, 390: System-on-a-Chip Architecture 320: Volatile Memory 360: Timer 370: Keystore S401~S422: Procedure Flow Detailed Implementation

[0021] Please refer to Figure 3A The diagram illustrates the system-on-a-chip architecture of the present invention. The system-on-a-chip architecture 390 includes a system-on-a-chip 300 and a non-volatile memory 380, and the system-on-a-chip 300 is connected to an external non-volatile memory 380.

[0022] The system-on-a-chip 300 includes a central processing unit 310, volatile memory 320, a system bus 330, on-the-fly decryption (OTFDEC) circuitry 340, a memory interface 350, a timer 360, and a key bank 370. The volatile memory 320 can be either dynamic random access memory (DRAM) or static random access memory (SRAM).

[0023] The central processing unit 310, volatile memory 320, and OTFDEC circuit 340 are connected to the system bus 330. Memory interface 350 is connected between OTFDEC circuit 340 and non-volatile memory 380. Furthermore, OTFDEC circuit 340 is connected to key repository 370 and can select from multiple keys provided by key repository 370 for encryption and decryption operations. Key repository 370 includes at least one initial key. I With a master key M Basically, the key stores 370 in multiple identical system-on-a-chip architectures 390 all contain the same initial key. I This can be entered by the manufacturer. Furthermore, the master key in each system-on-a-chip architecture 390... M They are all different, and the master key is... M The unique master key that can only be read by the OTFDEC circuit 340 M .

[0024] Furthermore, the OTFDEC circuit 340 has multiple operating modes. For example, normal mode, bypass mode, and two-key mode. In normal mode, the OTFDEC circuit 340 operates according to the master key. M In transparent mode, the OTFDEC circuit 340 does not use the key for encryption and decryption; instead, it directly transfers the contents of the non-volatile memory 380 to the central processing unit 310. In dual-key mode, the OTFDEC circuit 340 uses the initial key KEY to perform encryption and decryption operations. I To perform the decryption operation, the OTFDEC circuit 340 uses the master key. M To perform encryption.

[0025] According to an embodiment of the present invention, the timer 360 in the system chip 300 starts timing when power is supplied or when it is reset. When the timer 360 is disabled, it stops timing. After the timer 360 has been timing for a specific period, it generates a setting signal S to change the operation mode of the OTFDEC circuit 340. Additionally, the timer 360 also generates a warm reset signal Rst. W To the central processing unit 310.

[0026] Please refer to Figure 3B and Figure 3CThe diagram illustrates the data format in the non-volatile memory of the present invention. According to an embodiment of the present invention, the data format in the non-volatile memory 390 can be divided into an initial format and an operation format.

[0027] like Figure 3B As shown, the initial format in the non-volatile memory 390 includes: an initial boot code stored in the boot sector, and encrypted data stored in the program sector. The initial boot code is in plaintext, and the encrypted data is generated using the initial key. I The content after encryption. Basically, when the system-on-a-chip architecture 390 is manufactured, the storage format in the non-volatile memory 380 is the initial format.

[0028] like Figure 3C As shown, the operating format of the non-volatile memory 390 includes: an encrypted boot code stored in the boot area and an encrypted program code stored in the program area. Both the encrypted boot code and the encrypted program code utilize the master key. M The content after encryption.

[0029] According to an embodiment of the present invention, when the system-on-a-chip architecture 390 is powered on for the first time, the system-on-a-chip 300 will convert the storage format in the non-volatile memory 380 from the initial format to the working format. This will be described in detail below.

[0030] Please refer to Figure 4 The diagram illustrates a data protection method applied to the single-chip architecture of the system of this invention. When the power is on, the OTFDEC circuit 340 is in normal mode (step S401). At this time, the OTFDEC circuit 340 reads the master key Key from the key store 270. M And based on the master key Key M To perform encryption and decryption operations.

[0031] Next, with the OTFDEC circuit 340 in normal mode, the central processing unit 310 executes the encrypted boot code in the boot area of ​​the non-volatile memory 380 (step S403). The encrypted boot code includes a disable command to disable the timer 360.

[0032] When timer 360 is disabled (step S405), it indicates that the storage format in non-volatile memory 380 is... Figure 3C The operating format shown is as described, and the OTFDEC circuit 340 successfully utilizes the master key.M The encrypted boot code in non-volatile memory 380 is decrypted into plaintext executable by central processing unit 310. The process of central processing unit 310 executing plaintext (i.e., the decoded boot code) disables timer 360 and completes the initialization process.

[0033] Afterwards, the system single-chip architecture can operate normally (step S407). That is, the central processing unit 310 uses the decryption and encryption operations of the OTFDEC circuit 340 to execute the encrypted program code in the program area of ​​the non-volatile memory 380.

[0034] Basically, steps S401 to S407 constitute the normal operating procedure of the system-on-a-chip architecture. At this time, the content stored in the non-volatile memory 308 is the operation format. That is, during normal operation, the OTFDEC circuit 340 utilizes the master key. M To perform encryption and decryption operations.

[0035] Furthermore, when timer 360 is not disabled (step S405), it means that the OTFDEC circuit 340 cannot successfully decrypt the contents of non-volatile memory 380 into plaintext executable by the central processing unit 310, causing the system chip 300 to crash and thus failing to disable timer 360. At this time, the storage format of non-volatile memory 380 is not the operation format, but rather... Figure 3B The initial format shown represents the first power-on of the system single-chip architecture 390 of this invention.

[0036] Since the central processing unit 310 cannot disable the timer 360, after a specific period of time, the timer 360 changes the OTFDEC circuit 340 to a bypass mode and triggers a warm reset on the central processing unit 310 (step S410). In other words, after a specific period of time, the timer 360 generates a setting signal S, changing the OTFDEC circuit 340 to bypass mode. Additionally, the timer 360 also generates a warm reset signal Rst. W The central processing unit 310 causes the system-on-a-chip architecture 390 to be warm-reset.

[0037] According to an embodiment of the present invention, after a warm reset, the central processing unit 310 executes the initial boot code in the boot area of ​​the non-volatile memory 380 (step S412). That is, when the OTFDEC circuit 340 is in transparent mode, the OTFDEC circuit 340 does not require any key for encryption or decryption. Therefore, without the OTFDEC circuit 340 performing decryption, the central processing unit 310 directly executes the initial boot code in the non-volatile memory 380.

[0038] Similarly, the initial boot code includes a disable command to disable timer 360. That is, when the system single-chip architecture 390 is warm-reset, timer 360 restarts its countdown. When timer 360 is disabled (step S414), it means that the CPU 310 has successfully executed the initial boot code and disabled timer 360. Conversely, when timer 360 cannot be disabled (step S414), it means that the CPU 310 has failed to successfully execute the initial boot code and returns to step S410.

[0039] Next, the CPU 310 continues to execute the initial boot code in the non-volatile memory 380, and copies the initial boot code in the non-volatile memory 390 to the volatile memory 320, and executes the initial boot code in the volatile memory 320 (step S416). That is, after the initial boot code is copied from the non-volatile memory 380 to the volatile memory 320, the instruction pointer of the CPU 310 points to the address of the volatile memory 320, causing the CPU 310 to execute the initial boot code in the volatile memory 320.

[0040] Next, the central processing unit 310 changes the dual-key mode of the OTFDEC circuit 340 according to the initial power-on code in the volatile memory 320 (step S418). That is, the OTFDEC circuit 340 changes the dual-key mode according to the initial key KEY. I To perform the decryption operation, the OTFDEC circuit 340 uses the master key. M To perform encryption.

[0041] Next, the central processing unit 310 reads the encrypted data from the program area in the non-volatile memory 380 into the system chip 300 based on the initial power-on code in the volatile memory 320 and then stores it back into the non-volatile memory 380 (step S420). Since the OTFDEC circuit 340 operates in dual-key mode, when the encrypted data is read into the system chip 300, the OTFDEC circuit 340 uses the initial key Key. I Decrypt encrypted data into plaintext.

[0042] Additionally, when the central processing unit 310 stores plaintext to the non-volatile memory 380, the OTFDEC circuit 340 uses the master key Key M The plaintext is encrypted into an encrypted boot code and encrypted program code, and then overwritten into the non-volatile memory 380. Therefore, the storage format in the non-volatile memory 380 will change. Figure 3B The initial format shown has been changed to Figure 3C The operation format shown.

[0043] After step S420 is completed, the central processing unit 310 executes the system reset command in the initial boot code stored in the volatile memory 320. Therefore, the single-chip system architecture 390 of the present invention performs a system reset and returns to step S401.

[0044] After the system is reset in the system single-chip architecture 390, since the storage format in the non-volatile memory 380 has been changed to the operation format, the system single-chip architecture 390 will execute steps S401 to S407 and will not jump to steps S410 to S422.

[0045] As explained above, when the system single-chip architecture 390 of the present invention is powered on for the first time, the timer 360 is not disabled, allowing the timer 360 to control the central processing unit 310 to be warm-reset after a specific period of time. Afterwards, the central processing unit 310 controls the OTFDEC circuit 340 to use the initial key Key in the key library 370. I and master key M Change the storage format in the non-volatile memory 380 from the initial format to the working format.

[0046] Furthermore, when the system single-chip architecture 390 is reset or powered on again, the OTFDEC circuit 340 will use the master key... M The CPU 310 performs decryption and encryption operations, and can successfully execute the encrypted boot code in the non-volatile memory 380 and complete the initialization program, and then execute the encrypted program code in the non-volatile memory 380, thereby enabling the system single-chip architecture 390 to operate normally.

[0047] Since the system-on-a-chip architecture 390 uses the same initial storage format in its non-volatile memory 380 at the factory, there is no need to separately manage the pairing between the system-on-a-chip 300 and the non-volatile memory 380 during the production of the system-on-a-chip architecture 390. Therefore, production management costs can be saved.

[0048] Furthermore, each system chip 300 has a different master key. M After the power is turned on for the first time and the storage format of the non-volatile memory 380 is changed to the operating format, different ciphertexts will be stored in the non-volatile memory 380 in multiple system-on-a-chip architectures.

[0049] Furthermore, compared to existing system-on-a-chip (SoC) architectures, the SoC architecture 390 of this invention does not have an embedded flash memory to store the boot code; instead, the boot code is stored in the boot area of ​​an external non-volatile memory 380. In other words, the SoC architecture 390 of this invention is applicable to system-on-a-chip 300 that does not have a built-in embedded flash memory.

[0050] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A system-on-a-chip architecture, comprising: One non-volatile memory; as well as A system-on-a-chip (SoC) is connected to the non-volatile memory. The SoC includes: a central processing unit (CPU), a volatile memory, a system bus, an instant encryption / decryption circuit, a memory interface, a timer, and a key store. The central processing unit, the volatile memory, and the instant encryption / decryption circuit are connected to the system bus; the memory interface is connected between the instant encryption / decryption circuit and the non-volatile memory; the instant encryption / decryption circuit is connected to the key library to select multiple keys in the key library to perform an encryption or decryption operation. Wherein, after a power is turned on, when the timer is not disabled, the timer resets the central processing unit after a specific time, so that the central processing unit changes the storage format of the non-volatile memory from an initial format to an operating format; When the central processing unit is warm-reset, the central processing unit controls the instant encryption / decryption circuit to perform the decryption operation based on an initial key and the encryption operation based on a master key, and changes the storage format in the non-volatile memory from the initial format to the working format. The initial format of the non-volatile memory includes an initial boot code and encrypted data; the operating format of the non-volatile memory includes an encrypted boot code and an encrypted program code; the central processing unit executes the initial boot code, causing the instant encryption / decryption circuit to decrypt the encrypted data into plaintext according to the initial key, and the instant encryption / decryption circuit then encrypts the plaintext into the encrypted boot code and the encrypted program code according to the master key, and overwrites them to the non-volatile memory; When the timer is disabled, the instant encryption / decryption circuit performs the encryption and decryption actions based on the master key, and the central processing unit executes the encrypted boot code and the encrypted program code stored in the non-volatile memory.

2. A data protection method for a system-on-a-chip architecture, wherein the system-on-a-chip architecture includes: A non-volatile memory and a system-on-a-chip (SoC) are provided. The SoC is connected to the non-volatile memory. The SoC includes: a central processing unit (CPU), a volatile memory, a system bus, an instantaneous encryption / decryption circuit, a memory interface, a timer, and a key store. The CPU, the volatile memory, and the instantaneous encryption / decryption circuit are connected to the system bus. The memory interface is connected between the instantaneous encryption / decryption circuit and the non-volatile memory. The instantaneous encryption / decryption circuit is connected to the key store for selecting multiple keys from the key store to perform an encryption or decryption operation. The data protection method includes the following steps: (a) When a power source is turned on, the instant encryption / decryption circuit is in a normal mode; (b) The central processing unit executes an encrypted boot code in the non-volatile memory, wherein the encrypted boot code includes a disable instruction to disable the timer; (c) When the timer is disabled, the central processing unit executes an encrypted program code in the non-volatile memory, enabling the system single-chip architecture to operate normally; (d) When the timer is not disabled, after a specific time, change the instant encryption / decryption circuit to a transparent mode and reset the central processing unit; (e) After the central processing unit is reset, the central processing unit executes an initial boot code in the non-volatile memory, wherein the initial boot code includes the disable instruction to disable the timer; (f) If the timer is not disabled, return to step (d); (g) When the timer is disabled, the central processing unit copies the initial boot code in the non-volatile memory to the volatile memory and executes the initial boot code in the volatile memory; (h) The central processing unit changes the instant encryption / decryption circuit to a dual-key mode according to the initial power-on code in the volatile memory; (i) The central processing unit, based on the initial power-on code in the volatile memory, reads encrypted data from the non-volatile memory into the system chip, and then stores it back into the non-volatile memory; and (j) Perform a system reset.

3. The data protection method as described in claim 2, wherein when the instant encryption / decryption circuit is in the normal mode, the instant encryption / decryption circuit performs the encryption and decryption actions based on a master key of the key library.

4. The data protection method as described in claim 3, wherein when the instant encryption / decryption circuit is in the transparent mode, the instant encryption / decryption circuit does not perform the encryption and decryption operations.

5. The data protection method as described in claim 4, wherein when the instant encryption / decryption circuit is in the dual-key mode, the instant encryption / decryption circuit performs the encryption operation based on the master key of the key library, and performs the decryption operation based on an initial key of the key library.

6. The data protection method as described in claim 5, wherein, In step (i), the central processing unit executes the initial boot code, causing the instant encryption / decryption circuit to decrypt the encrypted data into plaintext according to the initial key, and the instant encryption / decryption circuit then encrypts the plaintext into the encrypted boot code and the encrypted program code according to the master key, and overwrites them to the non-volatile memory.

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