Strong physically unclonable function circuit based on closed-loop feedback voltage attenuator array

Abstract

The application discloses a strong physical unclonable function circuit based on a closed-loop feedback voltage attenuator array, which comprises a plurality of decoders, a voltage attenuation circuit, a choke amplification circuit and a buffer circuit, the voltage attenuation circuit is composed of a plurality of voltage attenuator arrays, and signal input ends of the decoders are electrically connected with a data bus; a gate output end of each decoder is electrically connected with a gate input end of a corresponding voltage attenuator array, and the number of voltage attenuators contained in each voltage attenuator array is 2 raised to the power of N. The circuit structure is cascaded by a plurality of voltage attenuator arrays, and the voltage attenuator circuit in a ring structure is formed by connecting the beginning and the end, and is output to the choke amplification circuit for signal preliminary quantization, and finally output to the buffer circuit as a random number sequence, so that a sequence with high randomness can be output, the overall power consumption is low, and the resistance to machine learning attacks is high.

Description

Technical Field

[0001] This invention relates to the technical field of integrated circuit hardware security, and in particular to a strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array. Background Technology

[0002] The purpose of True Random Number Generator (TRNG) circuit design is to generate truly random number sequences. These random number sequences are crucial for ensuring cryptographic security and the security of computer systems. Since random number sequences are the foundation of these applications, if the sequences are predictable or pseudo-random, they can be exploited by attackers to crack encryption algorithms or steal keys. This could allow attackers to crack ciphers by inferring patterns. If an attacker obtains the key, they can use it to decrypt encrypted data, thereby gaining access to sensitive information. Attackers can also use random numbers to forge digital signatures and authentication credentials, impersonating others and committing fraud. Cracked random numbers can also be used to attack protocols, causing system malfunctions. In short, if a random number generator is compromised, it will lead to system security problems and potentially serious consequences such as data breaches, identity theft, and cyberattacks. Therefore, when designing systems, it is essential to use sufficiently powerful and reliable random number generation methods to ensure system security.

[0003] A Physically Unclonable Function (PUF) circuit generates random numbers using physical processes or quantum phenomena. PUF structures can be used as true random number generators. Its principle is based on the randomness of the true circuit entropy source structure, thereby generating unpredictable sequences of random numbers. Therefore, the random numbers generated by a PUF circuit are difficult to predict, possessing true randomness and unpredictability.

[0004] In response to this, Physically Unclonable Functions (PUFs) have become a popular research area in hardware security due to their advantages such as low power consumption, low cost, and lightweight design. PUFs can be mainly divided into weak PUFs and strong PUFs, which are mainly used for key generation and device authentication, respectively, and both have broad research and application prospects in IoT hardware terminal security.

[0005] Achieving high-speed, highly reliable, and highly secure physically non-cloning function (PCF) circuits requires complex circuit designs, which increase area overhead. Furthermore, the complex circuit operations required to enhance randomness result in higher overall power consumption, increasing the cost of use. Therefore, PCF circuits in existing technologies suffer from high overall power consumption. Summary of the Invention

[0006] This invention provides a strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array, aiming to solve the problems of high overall power consumption and poor resistance to machine learning attacks in existing physically unclonable function circuits.

[0007] This invention discloses a strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array. The physically unclonable function circuit includes multiple decoders, a voltage attenuation circuit, a choke amplifier circuit, and a buffer circuit.

[0008] The voltage attenuation circuit consists of a ring formed by cascading multiple voltage attenuator arrays. The signal input terminals of the decoders are all electrically connected to the data bus. The gating output terminal of each decoder is electrically connected to the gating input terminal of a corresponding voltage attenuator.

[0009] The output terminal of the first voltage attenuator array is connected to the input terminal of the second voltage attenuator array; the input terminal of the first voltage attenuator array is connected to the output terminal of the last voltage attenuator array, and the connection point is electrically connected to the input terminal of the choke amplifier circuit.

[0010] The output terminal of the choke amplifier circuit is connected to the input terminal of the buffer circuit, and the output terminal of the buffer circuit is used to output a random number sequence.

[0011] Each voltage attenuator array consists of multiple voltage attenuators. The input terminals of the multiple voltage attenuators are connected and serve as the input terminal of the voltage attenuator array. The output terminals of the multiple voltage attenuators are connected and serve as the output terminal of the voltage attenuator array. The gating signal input terminal of each voltage attenuator is independently electrically connected to the gating output terminal of the decoder.

[0012] Each voltage attenuator array contains 2 to the power of N voltage attenuators, where N is a positive integer.

[0013] The strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array, wherein the voltage attenuator includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a first gating switch, a second gating switch, and a third gating switch;

[0014] The gate of the first MOS transistor is electrically connected to the gate of the third MOS transistor, and the connection point is connected to one end of the first gating switch. The other end of the first gating switch serves as the input terminal of the voltage attenuator.

[0015] The drain of the first MOSFET is electrically connected to the regulated power supply; the source of the first MOSFET is connected to the source of the second MOSFET; the gate of the second MOSFET is connected to the drain of the second MOSFET and the drain of the third MOSFET, and the connection point is connected to one end of the second selector switch, and the other end of the second selector switch serves as the output terminal of the voltage attenuator.

[0016] The source of the third MOS transistor is connected to one end of the third gating switch, and the other end of the third gating switch is connected to the ground terminal.

[0017] The control terminals of the first gating switch, the second gating switch, and the third gating switch are connected and serve as the gating signal input terminals of the voltage attenuator.

[0018] The strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array, wherein the first MOS transistor is a native MOS transistor.

[0019] The strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array, wherein the second MOS transistor is a low-voltage threshold P-MOS transistor, and the third MOS transistor is a high-voltage threshold N-MOS transistor.

[0020] The strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array, wherein the choke amplifier circuit is composed of multiple choke amplifiers connected in series;

[0021] The input terminal of the first choke amplifier is used as the input terminal of the choke amplifier circuit. The output terminal of the preceding choke amplifier circuit is connected to the input terminal of the following choke amplifier circuit. The output terminal of the last choke amplifier circuit is used as the output terminal of the choke amplifier circuit.

[0022] The strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array, wherein the choke amplifier includes a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor;

[0023] The gate of the fourth MOS transistor is connected to the gates of the fifth MOS transistor and the sixth MOS transistor, and the connection point serves as the input terminal of the choke amplifier.

[0024] The drain of the fourth MOS transistor is electrically connected to the regulated power supply, and the source of the fourth MOS transistor is electrically connected to the source of the fifth MOS transistor; the drain of the fifth MOS transistor is electrically connected to the drain of the sixth MOS transistor, and the connection point serves as the output terminal of the choke amplifier; the source of the sixth MOS transistor is connected to the ground terminal.

[0025] The strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array, wherein the fourth MOS transistor is a native MOS transistor.

[0026] The strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array, wherein the fifth MOS transistor is a low-voltage threshold P-MOS transistor and the sixth MOS transistor is a high-voltage threshold N-MOS transistor.

[0027] The circuit based on a closed-loop feedback voltage attenuator array with a strong physical non-cloning function, wherein the buffer circuit is a level shifter.

[0028] This application discloses a strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array. The circuit includes multiple decoders, a voltage attenuation circuit, a choke amplifier circuit, and a buffer circuit. The voltage attenuation circuit consists of a loop formed by cascading multiple voltage attenuator arrays. The signal input terminals of the decoders are all electrically connected to the data bus. The gating output terminal of each decoder is electrically connected to the gating input terminal of a corresponding voltage attenuator. Each voltage attenuator array contains 2^N voltage attenuators. In the above circuit structure, the voltage attenuation circuit, formed by cascading multiple voltage attenuator arrays and connecting them end-to-end to form a loop, outputs to the choke amplifier circuit for preliminary signal quantization. Finally, after passing through the buffer circuit, it outputs a random number sequence. This circuit can output a highly random sequence with low overall power consumption and strong resistance to machine learning attacks. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 The overall circuit diagram of the strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array provided in the embodiments of the present invention;

[0031] Figure 2 The circuit structure diagram of the voltage attenuator provided in the embodiment of the present invention;

[0032] Figure 3 The circuit structure diagram of the choke amplifier provided in the embodiment of the present invention;

[0033] Figure 4 The transmission characteristic diagram of the voltage attenuator provided in the embodiment of the present invention;

[0034] Figure 5 The transmission characteristic diagram of the choke amplifier provided in the embodiment of the present invention;

[0035] Figure 6 Application effect diagram of a circuit with a strong physical non-clonable function based on a closed-loop feedback voltage attenuator array;

[0036] Figure 7 This is another application effect diagram of the strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array provided in an embodiment of the present invention;

[0037] Figure 8 This is another application effect diagram of the strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array provided in the embodiments of the present invention;

[0038] Figure 9 This is another application effect diagram of the strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array provided in the embodiments of the present invention.

[0039] Figure 10 The diagram shows the effect of a strong physical non-cloning function circuit based on a closed-loop feedback voltage attenuator array provided in an embodiment of the present invention.

[0040] Reference numerals: Y, decoder; AS, voltage attenuation circuit; BS, choke amplifier circuit; Buffer, buffer circuit; A, voltage attenuator; B, choke amplifier; PI, basic inverter; M1, first MOSFET; M2, second MOSFET; M3, third MOSFET; K1, first gating switch; K2, second gating switch; K3, third gating switch; M5, fourth MOSFET; M5, fifth MOSFET; M6, sixth MOSFET. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0043] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0044] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0045] This invention discloses a strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array, such as... Figure 1 As shown, the circuit includes multiple decoders Y, a voltage attenuation circuit AS, a choke amplifier circuit BS, and a buffer circuit. The voltage attenuation circuit AS is composed of a ring formed by multiple voltage attenuator arrays. The signal input terminals of the decoders Y are all electrically connected to the data bus. The gating output terminal of each decoder Y is electrically connected to the gating input terminal of a corresponding voltage attenuator. The output terminal of the preceding voltage attenuator array is connected to the input terminal of the following voltage attenuator array. The input terminal of the first voltage attenuator array is connected to the output terminal of the last voltage attenuator array, and the connection point is electrically connected to the input terminal of the choke amplifier circuit BS. The input terminal of the choke amplifier circuit BS is connected to the input terminal of the buffer circuit Buffer, and the output terminal of the buffer circuit Buffer is used to output a random number sequence; each voltage attenuator array consists of multiple voltage attenuators A, the input terminals of the multiple voltage attenuators A are connected and serve as the input terminal of the voltage attenuator array, the output terminals of the multiple voltage attenuators A are connected and serve as the output terminal of the voltage attenuator array, and the gating signal input terminal of each voltage attenuator A is independently electrically connected to the gating output terminal of the decoder Y; each voltage attenuator array contains 2 to the power of N voltage attenuators A, where N is a positive integer.

[0046] Figure 1The circuit structure described herein is the overall architecture of the strong PUF circuit proposed in this application embodiment. It includes a ring-shaped voltage attenuation circuit with an n-stage (n is an even number) voltage attenuator array as an entropy source structure, as well as a cascaded multi-stage choke amplifier circuit, a digital buffer, and n decoders. Each voltage attenuator array contains m identically designed voltage attenuators, where m is 2 to the power of N and N is a positive integer.

[0047] The input excitation of this PUF circuit is output from an LFSR (Linear Feedback Shift Register) via a data bus to the signal input terminals of each decoder. The input contains a generated n×N bit sequence, with each group of N bits being input to n decoders. The gating signal output from the signal input terminals of the decoders can be selected from m voltage attenuators in each stage. Figure 1 Module A is used in the middle i_j (This is indicated by a strobe signal), thus selecting the appropriate voltage attenuator to connect to the circuit. The voltage attenuators connected in the cascaded circuit have an overall gain of less than 1 during circuit operation; therefore, the voltage at the output of each stage after cascading is close to V. trip The value of . Since the voltage at the output of the nth stage voltage attenuator array is fed back to the input of the first stage voltage attenuator array as feedback, each stage voltage attenuator in this cascaded attenuator loop can act as an entropy source. A change in any stage voltage attenuator will cause a change in the output voltage of the entire attenuator loop, and the gain will change with the change in the input voltage of that stage voltage attenuator. In addition, a choke amplifier circuit composed of three cascaded choke amplifiers with a gain greater than 1 (modules B1, B2 and B3 in the figure) is used to amplify the output of the nth stage in the above cascaded amplifier chain. Finally, after passing through a buffer circuit, a PUF response is obtained, that is, a random number sequence corresponding to the input excitation is generated.

[0048] Specifically, in the operation of a PUF circuit, when the input excitation changes, the basic unit of the stage access circuit in the attenuator loop corresponding to the decoder's output changes accordingly. For example, if the decoder input signal corresponding to stage x changes, this will cause a change in the gain of that stage's attenuator, and consequently, a change in the voltage V at its output. o,xThe magnitude of the voltage changes. Due to the feedback mechanism, the output voltage, after passing through the other n-1 stages of voltage attenuators, is fed back to the input of the x-th stage, further affecting the output of that stage until it reaches a steady state. This process is completed in a very short time, and the speed at which the circuit reaches equilibrium determines the throughput in the circuit performance. This feedback mechanism allows the later stages of the circuit to affect the earlier stages, further increasing the nonlinearity of the circuit and greatly increasing the complexity of machine learning attacks (ML attacks). The gain of the choke amplifier in this PUF circuit is greater than 1, and through design, the transistor size in the choke amplifier structure has the same proportion as the corresponding position of the voltage attenuator, and has the same V value as the voltage attenuator. trip The voltage value can be used to amplify the output voltage of the nth stage in the amplifier chain, and then it is preliminarily digitized through a buffer circuit to obtain the final PUF output.

[0049] In a more specific embodiment, such as Figure 2 As shown, the voltage attenuator A includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a first selector switch K1, a second selector switch K2, and a third selector switch K3. The gate of the first MOSFET M1 is electrically connected to the gate of the third MOSFET M3, and the connection point is connected to one end of the first selector switch K1. The other end of the first selector switch K1 serves as the input terminal of the voltage attenuator A. The drain of the first MOSFET M1 is electrically connected to a regulated power supply. The source of the first MOSFET M1 is connected to the source of the second MOSFET M2. The gate of MOSFET M2 is connected to the drain of the second MOSFET M2 and the drain of the third MOSFET M3, and the connection point is connected to one end of the second selector switch K2. The other end of the second selector switch K2 serves as the output terminal of the voltage attenuator A. The source of the third MOSFET M3 is connected to one end of the third selector switch K3, and the other end of the third selector switch K3 is connected to ground. The control terminals of the first selector switch K1, the second selector switch K2, and the third selector switch K3 are connected and serve as the selection signal input terminal of the voltage attenuator A. Specifically, the first MOSFET M1 is a native MOSFET. The second MOSFET M2 is a low-voltage threshold P-MOSFET, and the third MOSFET M3 is a high-voltage threshold N-MOSFET.

[0050] In a more specific embodiment, such as Figure 3As shown, the choke amplifier circuit BS consists of multiple choke amplifiers B connected in series. The input terminal of the first choke amplifier B serves as the input terminal of the choke amplifier circuit BS. The output terminal of the preceding choke amplifier circuit BS is connected to the input terminal of the following choke amplifier circuit BS, and the output terminal of the last choke amplifier circuit BS serves as the output terminal of the choke amplifier circuit BS. Specifically, the choke amplifier B includes a fourth MOSFET M5, a fifth MOSFET M5, and a sixth MOSFET M6. The gate of the fourth MOSFET M5 is connected to the gates of the fifth MOSFET M5 and the sixth MOSFET M6, and the connection point serves as the input terminal of the choke amplifier B. The drain of the fourth MOSFET M5 is electrically connected to a regulated power supply, and the source of the fourth MOSFET M5 is electrically connected to the source of the fifth MOSFET M5. The drain of the fifth MOSFET M5 is electrically connected to the drain of the sixth MOSFET M6, and the connection point serves as the output terminal of the choke amplifier B. The source of the sixth MOSFET M6 is connected to ground. The fourth MOS transistor M5 is a native MOS transistor. Furthermore, the fifth MOS transistor M5 is a low-voltage threshold P-MOS transistor, and the sixth MOS transistor M6 is a high-voltage threshold N-MOS transistor.

[0051] Figure 2 This is a basic unit structure diagram of a voltage attenuator. Figure 3 This is a basic unit structure diagram of a choke amplifier. The first and fourth MOSFETs, the second and fifth MOSFETs, and the third and sixth MOSFETs all have the same size proportions. Furthermore, the input and output of both the voltage attenuator and the choke amplifier are identical when connected in parallel, ensuring they have the same voltage rating. trip Voltage value. Specifically, as shown below... Figure 4 and Figure 5 As shown, Figure 4 The corresponding transfer characteristic diagram of the voltage attenuator. Figure 5 The graph shows the transfer characteristics of the choke amplifier. From the graph, we can see the voltage attenuator and the choke amplifier's V... out Curve and V inThe curves intersect at the same location. The first and fourth MOSFETs are intrinsic NVT NMOS transistors. By adjusting the MOSFET dimensions to operate in the subthreshold region, the current magnitude can be controlled, thereby reducing circuit power consumption. The second and fifth MOSFETs are low-threshold P-MOS transistors (LVT PMOS transistors), while the third and sixth MOSFETs are high-threshold N-MOS transistors (HVT PMOS transistors). Furthermore, the third and sixth MOSFETs (M3 and M6) can be controlled to operate in the subthreshold region, while the second and fifth MOSFETs (M2 and M5) operate in the saturation region. The superposition of these two nonlinear currents further enhances the circuit's resistance to power surges. The difference between the voltage attenuator and choke amplifier in the above structure is that the gate of the second MOSFET (M2) in the voltage attenuator is connected to the output voltage Vout, while the gate of the fifth MOSFET (M5) in the choke amplifier is connected to the input voltage Vin.

[0052] In a more specific embodiment, the buffer circuit is a level shifter. In this design, the buffer circuit uses a level shifter (LS). The level shifter is used to digitize the electrical signal output by the choke amplifier circuit BS to obtain the final output of the PUF circuit.

[0053] The voltage attenuation circuit has n stages, and each stage has N bits as input to the decoder. Therefore, the excitation can be defined as... In the above formula, the signal received at the input terminal of the k-th stage decoder is These signals are decoded to obtain a series of one-hot codes, where the output of the k-th level one-hot code is (Φ_k)→, which is an m×1 column vector used to select the amplifier in the circuit. Therefore, the control signal obtained after the decoder can be defined as matrix (1).

[0054]

[0055] Let the gain of the m basic amplifier units of the k-th stage be denoted as... Furthermore, since each stage of the amplifier is affected by the output voltage of the previous stage, a function f can be defined such that the gain of each basic unit can be denoted as g. k,m =f k,m (V o,(k-1) Therefore, the voltage obtained after amplification by the k-th stage amplifier can be expressed by formula (2):

[0056]

[0057] Since the cascaded amplifier chain circuit in this design introduces a feedback mechanism, the input voltage of each amplifier stage is affected by the gain of all n amplifier stages. Therefore, the output voltage expression of the nth stage can be expressed by formula (3):

[0058]

[0059] The matrix array representing the amplifier gain in the k-th stage can be represented by matrix (4):

[0060]

[0061] As can be seen from the above mathematical model analysis, the gain of each attenuator stage is related to the basic units of all other stages and varies with the input voltage. Therefore, when modeling each basic unit, in addition to considering its relationship with the input excitation, there are more complex multiplicative relationships. The modeling parameters increase exponentially with the number of stages in the amplifier chain, which can be specifically expressed as: K = n × m n In this design, n is 12 and m is 32. Substituting these values, we can obtain the modeling parameters as 13.8 × 10⁻⁶. 6 This also demonstrates the PUF's strong resistance to machine learning modeling attacks.

[0062] In this chip test, an Altera DE2 FPGA was used to generate the corresponding excitation signals and send them to the chip, while also receiving response signals from the PUF chip. The finished chip, after tape-out, will be packaged on a PCB board to enable interaction between the chip and the FPGA control signals. Performance testing and data processing analysis can be performed on the manufactured strong PUF, including layout and manufacturing process, power consumption, randomness, reliability, uniqueness, and attack resistance. The strong PUF based on a cascaded amplifier chain with feedback designed in this application also uses the UMC 65nm CMOS manufacturing process, with a standard operating voltage of 1.2V. In the chip structure diagram after tape-out using the above manufacturing process, the layout area of ​​the core array portion is 20439μm. 2 That is, 4.84 × 10 6 F 2 .

[0063] Reliability is generally expressed using the bit error rate (BER). During testing, the same stimulus input is applied to the same PUF chip under varying temperature or voltage conditions, and the resulting responses are compared. The Hamming distance between the stimuli under different conditions is calculated, and the ratio of this ratio to the number of bits in the response is used to represent reliability. Figure 6The diagram shows the temperature and voltage reliability of the strong PUF design proposed in this application. In this design, the bit error rate (BER) of 10 chips was tested, and the average value of the data from these 10 chips was taken to eliminate the influence of noise. When conducting the BER test, room temperature and pressure are typically used as the standard values ​​for comparison, i.e., 1.2V and 27℃. Figure 6 Figure (a) shows the bit error rate distribution as the operating voltage ranges from 0.9V to 1.5V. Figure 6 Figure (b) shows the bit error rate distribution from -40℃ to 120℃. The highest bit error rate in this range is 6.63%, at which point the operating temperature is 120℃ and the operating voltage is 1.2V. Therefore, it can be shown that the PUF can operate normally within this temperature and voltage range.

[0064] To verify the randomness of the strong PUF proposed in this application, the National Institute of Standards and Technology (NIST) Pub 800-22 test suite and autocorrelation function calculation were also used during data processing. Table 1 shows the results of the NIST Pub 800-22 test on the 1M response bits generated by the proposed strong PUF. As can be seen from the table, the p-value of each randomness test item is higher than 0.01, which proves that the response sequence generated by the PUF has sufficient randomness.

[0065] Table 1. Results of the randomness test in NIST Pub 800-22

[0066] NIST 800-22 test items Confidence level (P) Pass rate Frequency 0.350485 99 / 100 Block Frequency 0.924076 98 / 100 CumulativeSums(forward) 0.574903 98 / 100 CumulativeSums(reverse) 0.534146 99 / 100 Runs 0.304126 99 / 100 Longest Runs 0.275709 98 / 100 Rank 0.350485 99 / 100 FFT 0.474986 99 / 100 NonOverlapping Template 0.122325 99 / 100 Overlapping Template 0.213309 99 / 100 Approximate Entropy 0.657933 98 / 100 Serial (forward) 0.474986 98 / 100 Serial(reverse) 0.798139 99 / 100 Liner Complexity 0.759756 96 / 100

[0067] To further demonstrate the unpredictability of the PUF, ensure the stochastic relationship between the PUF chip's excitation and response, and guarantee non-correlation during basic unit reuse, autocorrelation detection (ACF) will be employed. Figure 7 The image shows the calculation of the autocorrelation function for the 200K response bits that passed the NIST test. After testing, the result shown is 0.0044 within a 95% confidence interval. Figure 7 As shown in Figure (a), the closer the result is to 0, the weaker the autocorrelation, thus demonstrating the good randomness of the design. Furthermore, to ensure the unpredictability of the PUF—a fundamental requirement of randomness—at least 50% of its output sequence must be composed of 0s and 1s.

[0068] In the test, 40K bits were extracted from the 200K response, and a scatter plot of the output was generated, as shown below. Figure 7As shown in Figure (b), white represents bits with an output of 0, and black represents bits with an output of 1. The scatter plot shows that the distribution of 0s and 1s in the output of this design is sufficiently uniform and random. Statistically, the percentage of outputs of 1 is 49.96%, and the percentage of outputs of 0 is 50.04%.

[0069] Uniqueness reflects the difference between chips and chip entities. The output of each PUF chip should be different from each other. When measuring the quality of uniqueness, the Hamming distance between the response sequences generated by the same input stimulus between different chips is usually used to characterize the differences between PUF chips. This index is also called inter-chip Hamming distance. The ideal value of this data is 50%. The closer it is to this value, the greater the difference between different PUFs.

[0070] Furthermore, the on-chip Hamming distance is determined by applying the same stimulus to the same chip at room temperature and pressure (i.e., 27°C and 1.2V) to obtain the corresponding response sequences. After repeating this process multiple times, the Hamming distance between these outputs is statistically calculated. The ideal value is 0; the closer the value is to this, the better the intrinsic stability of the PUF at room temperature and pressure. In the testing of the technical method in this application, 10 chips were randomly selected and tested at 27°C and a power supply voltage of 1.2V.

[0071] Figure 8 The intra-chip Hamming distance and inter-chip Hamming distance of this design are shown separately. The mean value of the intra-chip Hamming distance is 0.0073, and the standard deviation is 0.0012, demonstrating good stability under intrinsic conditions. Meanwhile, the mean value of the inter-chip Hamming distance is 0.5014, and the standard deviation is 0.0312, indicating that the PUF exhibits sufficiently large variations during manufacturing, thus demonstrating good uniqueness.

[0072] There are two metrics for measuring power consumption: one is power consumption, which is the overall power consumption of the circuit, typically measured in nW or μW; the other is energy efficiency ratio (EER), which represents the energy consumed by the PUF chip to generate one bit of output, measured in pJ / bit. In this design, the power consumption performance is statistically characterized by averaging the power consumption of 10 chips at different operating throughput rates. Figure 9 The results in the figure show the relationship between throughput, power consumption, and energy efficiency ratio.

[0073] from Figure 9As can be seen, within the throughput range of 1Kbps to 100Kbps, the overall power consumption of the circuit increases with the increase of throughput, while the energy efficiency ratio decreases. After weighing power consumption and energy efficiency ratio, 50Kbps was selected as the standard operating state. At this time, the power consumption is only 62.57nW, and the energy efficiency ratio is 1.25pJ / bit, demonstrating extremely low power consumption and a relatively low energy efficiency ratio.

[0074] The ability of a strong PUF to resist machine learning algorithm attacks has become crucial. After training by collecting known CRPs, the algorithm can use these CRPs to test and analyze the PUF, thereby fitting the parameters of each basic unit in the circuit and obtaining a mathematical model that is very similar to the original PUF. Therefore, it can predict and analyze unknown responses after obtaining stimuli not included in the training set, thereby breaking the unpredictability of the PUF and obtaining all CRPs, that is, the prediction accuracy reaches 100%.

[0075] Introducing sufficient nonlinear structures or partial protocols into the circuit can effectively reduce its prediction accuracy. The closer this metric is to 50%, the stronger the circuit's resistance to machine learning attacks. In the PUF circuit design proposed in this application, since each basic unit on the cascaded attenuator ring with feedback operates in the subthreshold or saturation region, the coupling and superposition of these two different transmission characteristics introduces nonlinear factors. Furthermore, through the above analysis, it can be seen that the transmission characteristics and gain of each stage are highly nonlinearly related to the output voltage of the previous stage, as well as the input excitation, process parameters, and other factors. Therefore, if a modeling attack is required on the circuit, a large number of modeling parameters need to be constructed, which significantly increases the modeling complexity, making modeling attacks on the circuit difficult to achieve and reducing the prediction accuracy.

[0076] Similarly, the prediction accuracy of 10M CRPs of this PUF was tested using Support Vector Machine (SVM), Linear Logistic Regression (LR), and the newly proposed CMA-ES algorithm. The results are as follows: Figure 10 As shown. The final data shows that the above algorithm achieves a prediction accuracy of 50.6% for this strong PUF circuit at 10M CRP, indicating that it can resist machine learning algorithm attacks without the need for additional protocols.

[0077] To further demonstrate the performance of the strong PUF circuit design based on closed-loop feedback voltage attenuator array in this application, a performance comparison will be made with other strong PUFs proposed by academic researchers in recent years. The comparison results are shown in Table 2. It can be seen that the PUF in this design can achieve a power consumption as low as 0.063μW while ensuring the operating voltage and temperature range, demonstrating excellent performance in terms of low power consumption and high energy efficiency.Among them, Comparison 1 is the test result published in the paper "Y.Cao, CQLiu and C.H.Chang. A Low Power Diode-Clamped Inverter-Based Strong Physical Unclonable Function for Robust and Lightweight Authentication. IEEE Transactions on Circuits and Systems I: Regular Papers, vol.65, no.11, Nov.2018, pp.3864-3873", Comparison 2 is the test result published in the paper "H.Zhuang, X.Xi, N.Sun and M.Orshansky. A Strand Subthreshold Current Array PUF Resilient to Machine Learning Attacks. in IEEE Transactions on Circuits and Systems I: Regular Papers, vol.67, no.1, pp.135-144, Jan.2020", and Comparison 3 is the test result published in the paper "A.Venkatesh, A.B. Venkatasubramaniyan, X.Xi and A.Sanyal. 0.3pJ / Bit". The test results published in the paper "Machine Learning Resistant Strong PUF Using Subthreshold Voltage Divider Array. IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 8, pp. 1394-1398, Aug. 2020" are compared with the test results published in the paper "J. Zhang et al. A4T / Cell Amplifier-Chain-Based XOR PUF With Strong Machine Learning Attack Resilience. IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 1, pp. 366-377, Jan. 2022, doi: 10.1109 / TCSI.2021.3114084".

[0078] Table 2

[0079]

[0080] This invention discloses a strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array. The circuit includes multiple decoders, a voltage attenuation circuit, a choke amplifier circuit, and a buffer circuit. The voltage attenuation circuit consists of a loop formed by cascading multiple voltage attenuator arrays. The signal input terminals of the decoders are all electrically connected to the data bus. The gating output terminal of each decoder is electrically connected to the gating input terminal of a corresponding voltage attenuator. Each voltage attenuator array contains 2^N voltage attenuators. In the above circuit structure, the voltage attenuation circuit, formed by cascading multiple voltage attenuator arrays and connecting them end-to-end to form a loop, outputs to the choke amplifier circuit for preliminary signal quantization. Finally, after passing through the buffer circuit, it outputs a random number sequence. This circuit can output a highly random sequence with low overall power consumption and strong resistance to machine learning attacks.

[0081] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A circuit with a strongly physically unclonable function based on a closed-loop feedback voltage attenuator array, characterized in that, The physically unclonable function circuit includes multiple decoders, voltage attenuation circuits, choke amplifier circuits, and buffer circuits. The voltage attenuation circuit is composed of a ring formed by cascading multiple voltage attenuator arrays. The signal input terminals of the decoders are all electrically connected to the data bus. The gating output terminal of each decoder is electrically connected to the gating input terminal of a corresponding voltage attenuator array. The output terminal of the first voltage attenuator array is connected to the input terminal of the second voltage attenuator array; the input terminal of the first voltage attenuator array is connected to the output terminal of the last voltage attenuator array, and the connection point is electrically connected to the input terminal of the choke amplifier circuit. The output terminal of the choke amplifier circuit is connected to the input terminal of the buffer circuit, and the output terminal of the buffer circuit is used to output a random number sequence. Each voltage attenuator array consists of multiple voltage attenuators. The input terminals of the multiple voltage attenuators are connected and serve as the input terminal of the voltage attenuator array. The output terminals of the multiple voltage attenuators are connected and serve as the output terminal of the voltage attenuator array. The gating signal input terminal of each voltage attenuator is independently electrically connected to the gating output terminal of the decoder. Each voltage attenuator array contains 2 to the power of N voltage attenuators, where N is a positive integer.

2. The strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array according to claim 1, characterized in that, The voltage attenuator includes a first MOSFET, a second MOSFET, a third MOSFET, a first gating switch, a second gating switch, and a third gating switch; The gate of the first MOS transistor is electrically connected to the gate of the third MOS transistor, and the connection point is connected to one end of the first gating switch. The other end of the first gating switch serves as the input terminal of the voltage attenuator. The drain of the first MOSFET is electrically connected to the regulated power supply; the source of the first MOSFET is connected to the source of the second MOSFET; the gate of the second MOSFET is connected to the drain of the second MOSFET and the drain of the third MOSFET, and the connection point is connected to one end of the second selector switch, and the other end of the second selector switch serves as the output terminal of the voltage attenuator. The source of the third MOS transistor is connected to one end of the third gating switch, and the other end of the third gating switch is connected to the ground terminal. The control terminals of the first gating switch, the second gating switch, and the third gating switch are connected and serve as the gating signal input terminals of the voltage attenuator.

3. The strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array according to claim 2, characterized in that, The first MOS transistor is a native MOS transistor.

4. The strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array according to claim 3, characterized in that, The second MOS transistor is a low-voltage threshold P-MOS transistor, and the third MOS transistor is a high-voltage threshold N-MOS transistor.

5. The strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array according to any one of claims 2-4, characterized in that, The choke amplifier circuit consists of multiple choke amplifiers connected in series; The input terminal of the first choke amplifier is used as the input terminal of the choke amplifier circuit. The output terminal of the preceding choke amplifier circuit is connected to the input terminal of the following choke amplifier circuit. The output terminal of the last choke amplifier circuit is used as the output terminal of the choke amplifier circuit.

6. The strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array according to claim 5, characterized in that, The choke amplifier includes a fourth MOSFET, a fifth MOSFET, and a sixth MOSFET; The gate of the fourth MOS transistor is connected to the gates of the fifth MOS transistor and the sixth MOS transistor, and the connection point serves as the input terminal of the choke amplifier. The drain of the fourth MOS transistor is electrically connected to the regulated power supply, and the source of the fourth MOS transistor is electrically connected to the source of the fifth MOS transistor; the drain of the fifth MOS transistor is electrically connected to the drain of the sixth MOS transistor, and the connection point serves as the output terminal of the choke amplifier; the source of the sixth MOS transistor is connected to the ground terminal.

7. The strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array according to claim 6, characterized in that, The fourth MOS transistor is a native MOS transistor.

8. The strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array according to claim 6, characterized in that, The fifth MOS transistor is a low-voltage threshold P-MOS transistor, and the sixth MOS transistor is a high-voltage threshold N-MOS transistor.

9. The strongly physically unclonable function circuit based on a closed-loop feedback voltage attenuator array according to any one of claims 1-4, characterized in that, The buffer circuit is a level converter.

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