Control device and control method thereof

Abstract

A control device and a control method thereof, wherein the device is used to drive a display device including a first channel and a second channel. The control device includes a first output device, a second output device, a first delay generator, a second delay generator, a first multiplexer, and a second multiplexer. The first output device outputs first transfer data according to an enable signal. The second output device outputs second transfer data according to the enable signal. The first delay generator generates a first trigger signal by counting a first delay time according to the enable signal. The second delay generator generates a second trigger signal by counting a second delay time according to the enable signal. The first multiplexer provides the first transfer data to the first channel according to the first trigger signal. The second multiplexer provides the second transfer data to the second channel according to the second trigger signal.

Description

Technical Field

[0001] This invention relates to a control device and control method for a display device, and more particularly to a control device and control method for time-division multiplexing display units of different channels to reduce resistance voltage drop. Background Technology

[0002] Backlight panels can be driven using various interface signals, with Bi-phase Mark Code (BMC) being one such signal interface. In backlight driving systems of different sizes, the resistive voltage drop (IR drop) of the supply voltage to the display device will affect the overall power consumption and image clarity. Therefore, it is necessary to optimize the backlight panel control method to reduce the IR drop of the display device's supply voltage. Summary of the Invention

[0003] This invention proposes a control device and control method for reducing the voltage drop of the supply voltage of a display device by time-division multiplexing the display units of different channels. By staggering the time when different channels of different display devices receive the preamble and adjusting the bit line width ratio of logic 0 to logic 1, the number of display units that are simultaneously turned on is reduced, thereby reducing the degree of voltage drop of the supply voltage of the display device.

[0004] In view of this, the present invention provides a control device for driving a display device, wherein the display device includes a first channel and a second channel. The control device includes a first output device, a second output device, a first delay generator, a second delay generator, a first multiplexer, and a second multiplexer. The first output device outputs first transfer data according to an enable signal. The second output device outputs second transfer data according to the enable signal. The first delay generator generates a first trigger signal by counting a first delay time according to the enable signal. The second delay generator generates a second trigger signal by counting a second delay time according to the enable signal. The first multiplexer provides the first transfer data to the first channel according to the first trigger signal. The second multiplexer provides the second transfer data to the second channel according to the second trigger signal.

[0005] According to an embodiment of the present invention, each of the first delay generator and the second delay generator includes a counter, a register, and a comparator. The counter counts a first time or a second time according to the enable signal and a clock signal. The register stores the first delay time or the second delay time. The comparator compares the first time and the first delay time to generate the first trigger signal, or compares the second time and the second delay time to generate the second trigger signal. When the first time equals the first delay time, the comparator generates the first trigger signal. When the second time equals the second delay time, the comparator generates the second trigger signal.

[0006] According to one embodiment of the present invention, the first delay time and the second delay time are different.

[0007] According to an embodiment of the present invention, either the first output device or the second output device further includes a bit line width controller, a bit line timing adjuster, and a data generator. The bit line width controller generates a control signal based on a bit line width ratio. The bit line timing adjuster generates an adjustment signal based on a clock signal, the enable signal, and the control signal. The data generator converts received data into transferred data based on the enable signal and the adjustment signal. The transferred data includes at least one first logic bit line and at least one second logic bit line, wherein the ratio of the bit line width of the first logic bit line to the bit line width of the second logic bit line is the bit line width ratio.

[0008] According to one embodiment of the present invention, the bit line width ratio of the first transfer data and the bit line width ratio of the second transfer data are different.

[0009] The present invention further proposes a control method for driving a display device, wherein the display device includes a first channel and a second channel. The control method includes outputting first transfer data and second transfer data according to an enable signal; generating a first trigger signal and a second trigger signal respectively by counting a first delay time and a second delay time according to the enable signal; providing the first transfer data to the first channel according to the first trigger signal; and providing the second transfer data to the second channel according to the second trigger signal.

[0010] According to an embodiment of the present invention, the step of generating the first trigger signal and the second trigger signal respectively by counting the first delay time and the second delay time according to the enable signal further includes storing the first delay time and the second delay time in a register; counting a first time and a second time according to the enable signal and a clock signal; generating the first trigger signal when the first time is equal to the first delay time; and generating the second trigger signal when the second time is equal to the second delay time.

[0011] According to one embodiment of the present invention, the first delay time is different from the second delay time.

[0012] According to an embodiment of the present invention, the step of outputting the first transfer data and the second transfer data according to the enable signal further includes generating a first adjustment signal according to a first bit line width ratio; generating a second adjustment signal according to a second bit line width ratio; generating a first control signal according to a clock signal, the enable signal, and the first adjustment signal; generating a second control signal according to the clock signal, the enable signal, and the second adjustment signal; converting a first received data into the first transfer data according to the enable signal and the first control signal; and converting a second received data into the second transfer data according to the enable signal and the second control signal.

[0013] According to an embodiment of the present invention, the first transfer data includes at least one first logic bit line and at least one second logic bit line, wherein the ratio of the bit line width of the first logic bit line to the bit line width of the second logic bit line is the first bit line width ratio, and the second transfer data includes at least one first logic bit line and at least one second logic bit line, wherein the ratio of the bit line width of the first logic bit line to the bit line width of the second logic bit line is the second bit line width ratio. Attached Figure Description

[0014] Figure 1 A block diagram of a control device according to an embodiment of the present invention is shown;

[0015] Figures 2A-2B A schematic diagram showing the transfer data according to an embodiment of the present invention;

[0016] Figure 3 A block diagram of a delay generator according to an embodiment of the present invention is shown;

[0017] Figure 4 A block diagram of an output device according to an embodiment of the present invention is shown;

[0018] Figure 5 This diagram illustrates the relationship between input data and transfer data according to an embodiment of the present invention.

[0019] Figures 6A-6B Displays a waveform diagram of the transfer data according to an embodiment of the present invention;

[0020] Figure 7 A schematic diagram showing the transfer data according to another embodiment of the present invention;

[0021] Figure 8 A block diagram of an output device according to another embodiment of the present invention is shown;

[0022] Figure 9 A block diagram of a preamble generator according to an embodiment of the present invention is shown;

[0023] Figure 10 A block diagram of an output device according to another embodiment of the present invention is shown;

[0024] Figure 11 A diagram showing the relationship between bitline codes and biphase marker codes according to an embodiment of the present invention; and

[0025] Figure 12 A flowchart of a control method according to an embodiment of the present invention is shown.

[0026] Attached icon number

[0027] 10: Display device

[0028] 100: Control device

[0029] 111: First output device

[0030] 112: Second output device

[0031] 11N: Nth output device

[0032] 121: First Delay Generator

[0033] 122: Second Delay Generator

[0034] 12N: Nth Delay Generator

[0035] 131: First Multiplexer

[0036] 132: Second Multiplexer

[0037] 13N: The Nth Multiplexer

[0038] 210,700: Transfer data

[0039] 220: Delayed data transfer

[0040] 300: Delay Generator

[0041] 310: Counter

[0042] 320: Temporary Register

[0043] 330: Comparator

[0044] 400: Output device

[0045] 410: Bit line width controller

[0046] 420: Bitline Time Adjuster

[0047] 430: Data Generator

[0048] 800, 1000: Output devices

[0049] 810, 900: Prefix generator

[0050] 820: Function Code Generator

[0051] 920: Prefix value temporary register

[0052] 930: Bit Line Counter

[0053] 940: Prefix Shift Register

[0054] 950: Bit Line Comparator

[0055] 1010: Function Code Generator

[0056] 1011: Function Code Count Register

[0057] 1012: Function Code Register

[0058] 1013: Function Code Counter

[0059] 1014: Function code shift register

[0060] 1015: Function Code Number Comparator

[0061] 1020: Lookup table temporary register

[0062] 1030: Lookup Table Comparator

[0063] 1040: Width Counter

[0064] 1050: Bit line width comparator

[0065] 1060: Bit Line Generator

[0066] 1200: Control Method

[0067] SC: Control Signal

[0068] SAD: Adjustment Signal

[0069] TM: predetermined time

[0070] CLK: Clock signal

[0071] PRE: Prefix

[0072] FNC: Function Code

[0073] DTC: Data Code

[0074] CC: Instruction Code

[0075] CC1: First instruction code

[0076] CC2: Second instruction code

[0077] CC3: Third instruction code

[0078] CC4: Fourth instruction code

[0079] D1: First Data

[0080] D2: Second Data

[0081] DM: Data of the Mth generation

[0082] EOP: End of Packet

[0083] Idle: Inactive

[0084] P1: Number of bit lines

[0085] P2: Number of function codes

[0086] PV: a predetermined value

[0087] ENPRE: Prefix Enable Signal

[0088] ENFC: Function Code Enable Signal

[0089] CV1: First count value

[0090] CV2: Second count value

[0091] SFT1: First shift signal

[0092] SFT2: Second shift signal

[0093] BTC: Bitline Code

[0094] BMC: Bidirectional Marker Code

[0095] CH1: First Channel

[0096] CH2: Second channel

[0097] CHN: Nth channel

[0098] CNT: Counting signal

[0099] HBP: Half-line pulse

[0100] FBP: Full-line pulse

[0101] LUT: Lookup Table

[0102] DI: Input Data

[0103] DI1: First input data

[0104] DI2: Second Input Data

[0105] DIN: Nth input data

[0106] DT: Transfer Data

[0107] DT1: First transfer data

[0108] DT2: Second Transfer Data

[0109] DTN: Nth transfer data

[0110] EN: Enable signal

[0111] DLY: Delay Time

[0112] DLY1: First delay time

[0113] DLY2: Second delay time

[0114] DLYN: Nth delay time Detailed Implementation

[0115] The following description is an embodiment of the present invention. Its purpose is to illustrate the general principles of the invention and should not be considered as a limitation thereof. The scope of the invention is defined by the claims.

[0116] It is understood that although terms such as "first," "second," and "third" may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or portions. Therefore, a first element, component, region, layer, and / or portion discussed below may be referred to as a second element, component, region, layer, and / or portion without departing from the teachings of some embodiments disclosed herein.

[0117] It is worth noting that the following disclosure provides multiple embodiments or examples for practicing different features of the invention. The specific examples and arrangements of elements described below are merely for briefly illustrating the spirit of the invention and are not intended to limit its scope. Furthermore, the same element symbols or words may be repeated in multiple examples in the following description. However, the purpose of repetition is only to provide a simplified and clear description and is not intended to limit the relationship between the various embodiments and / or configurations discussed below. Moreover, descriptions in the following description of a feature being connected to, coupled to, and / or formed on top of another feature may actually encompass multiple different embodiments, including those features being in direct contact, or those including additional features formed between those features, such that the features are not in direct contact.

[0118] Figure 1 A block diagram of a control device according to an embodiment of the present invention is shown. Figure 1 As shown, the control device 100 is coupled to the display device 10, wherein the display device 10 includes a first channel CH1, a second channel CH2, ... and an Nth channel CHN. According to some embodiments of the present invention, the first channel CH1, the second channel CH2, ... and the Nth channel CHN each include at least one display unit.

[0119] The control device 100 includes a first output device 111, a second output device 112, ..., an Nth output device 11N, a first delay generator 121, a second delay generator 122, ..., an Nth delay generator 12N, a first multiplexer 131, a second multiplexer 132, ..., and an Nth multiplexer 13N.

[0120] The first output device 111, the second output device 112, ..., and the Nth output device 11N convert the first input data DI1, the second input data DI2, ..., and the Nth input data DIN into first transfer data DT1, second transfer data DT2, ..., and Nth transfer data DTN, respectively, according to the enable signal EN. The first delay generator 121, the second delay generator 122, ..., and the Nth delay generator 12N count the first delay time DLY1, the second delay time DLY2, ..., and the Nth delay time DLYN, respectively, according to the enable signal EN, and generate the first trigger signal TR1, the second trigger signal TR2, ..., and the Nth trigger signal TRN accordingly.

[0121] According to an embodiment of the present invention, the first multiplexer 131, the second multiplexer 132, ... and the Nth multiplexer 13N respectively provide the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN to the corresponding first channel CH1, the second channel CH2, ... and the Nth channel CHN according to the first trigger signal TR1, the second trigger signal TR2, ... and the Nth trigger signal TRN, so as to form the first delayed transfer data DDT1, the second delayed transfer data DDT2, ... and the Nth delayed transfer data DDTN.

[0122] According to another embodiment of the present invention, when the first delay generator 121, the second delay generator 122, ... and the Nth delay generator 12N have not yet counted to the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN, the corresponding first trigger signal TR1, the second trigger signal TR2, ... and the Nth trigger signal TRN are not generated.

[0123] In other words, the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN are delayed by the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN, respectively, before being provided to the corresponding first channel CH1, second channel CH2, ... and Nth channel CHN.

[0124] According to one embodiment of the present invention, when any of the first delay generator 121, the second delay generator 122, ..., and the Nth delay generator 12N has not yet counted to the first delay time DLY1, the second delay time DLY2, ..., and the Nth delay time DLYN, the first multiplexer 131, the second multiplexer 132, ..., and the Nth multiplexer 13N will provide a preset logic level DL to any one of the corresponding channels CH1, CH2, ..., and CHN. According to one embodiment of the present invention, the preset logic level DL may be a high logic level. According to another embodiment of the present invention, the preset logic level DL may be a low logic level.

[0125] According to one embodiment of the present invention, the first delay generator 121, the second delay generator 122, ... and the Nth delay generator 12N are different from each other, and the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN are different from each other.

[0126] According to another embodiment of the present invention, at least two of the first delay generator 121, the second delay generator 122, ... and the Nth delay generator 12N are identical, and at least two of the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN are identical. In other words, a first predetermined number of output devices share the first delay time generated by the first delay generator, and a second predetermined number of output devices share the second delay time generated by the second delay generator. Figure 1 The illustrations are for illustrative purposes only and are not intended to limit the scope of this illustrations in any way.

[0127] Figures 2A-2B A schematic diagram showing the transfer data according to an embodiment of the present invention is shown. For example... Figure 2A As shown, the transfer data 210 includes a preamble PRE, first data D1, second data D2, ..., Mth data DM, and packet end EOP. According to an embodiment of the present invention, the transfer data 210 corresponds to... Figure 1 The first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN.

[0128] Prefix PRE is used to... Figure 1 The display units of the first channel CH1, the second channel CH2, ... and the Nth channel CHN of the display device 10 are initially set. The first data D1, the second data D2, ... and the Mth data DM are used to transmit control data for the corresponding display units. The packet end EOP is used to indicate the end of transmission.

[0129] According to one embodiment of the present invention, the transfer data 210 is in an idle state before the preamble PRE and after the end-of-packet EOP. Figures 2A-2B As shown in the embodiment, the data transfer 210 is at a high logic level when in the idle state. According to another embodiment of the present invention, the data transfer 210 may also be at a low logic level when in the idle state.

[0130] According to one embodiment of the present invention, when the idle state Idle is at a high logic level and the transfer data 210 transmits the least significant bit (LSB) first, the preamble PRE is 0xAA to facilitate the generation of the maximum number of logic transitions. According to another embodiment of the present invention, when the idle state Idle is at a high logic level and the transfer data 210 transmits the most significant bit (MSB) first, the preamble PRE is 0x55 to facilitate the generation of the maximum number of logic transitions.

[0131] According to another embodiment of the present invention, when the idle state Idle is at a low logic level and the transfer data 210 transmits the least significant bit (LSB) first, the preamble PRE is 0x55. According to another embodiment of the present invention, when the idle state Idle is at a low logic level and the transfer data 210 transmits the most significant bit (MSB) first, the preamble PRE is 0xAA.

[0132] like Figure 2B As shown, delayed transfer data 220 includes a delay time DLY more than transfer data 210. According to an embodiment of the present invention, delayed transfer data 220 corresponds to... Figure 1 The first delayed transfer data DDT1, the second delayed transfer data DDT2, ..., and the Nth delayed transfer data DDTN, where the delay time DLY corresponds to ... Figure 1 The first delay time is DLY1, the second delay time is DLY2, ..., and the Nth delay time is DLYN. In other words, the preamble PRE is provided by delaying the transfer data 220 by a delay time DLY compared to the transfer data 210.

[0133] In other words, such as Figure 1 In the illustrated embodiment, the first transfer data DT1, the second transfer data DT2, ..., and the Nth transfer data DTN are respectively delayed by the first delay time DLY1, the second delay time DLY2, ..., and the Nth delay time DLYN (corresponding to ... Figure 2B The delayed transfer data 220 is then provided to the corresponding first channel CH1, second channel CH2, ... and Nth channel CHN.

[0134] Figure 3 A block diagram of a delay generator according to an embodiment of the present invention is shown. Figure 3 As shown, the delay generator 300 includes a counter 310, a register 320, and a comparator 330. The counter 310 counts a predetermined time TM based on an enable signal EN and a clock signal CLK. The register 320 stores the delay time DLY. The comparator 330 compares the predetermined time TM with the delay time DLY. According to an embodiment of the present invention, when the predetermined time TM equals the delay time DLY, the comparator 330 generates a trigger signal TR.

[0135] According to one embodiment of the present invention, the delay generator 300 corresponds to... Figure 1 Any one of the first delay generator 121, the second delay generator 122, ... and the Nth delay generator 12N. Figure 1 as well as Figure 3As shown, the counters 310 of the first delay generator 121, the second delay generator 122, ... and the Nth delay generator 12N count a predetermined time TM according to the enable signal EN and the clock signal CLK. When the predetermined time TM counted by the first delay generator 121 is equal to the first delay time DLY1, the first delay generator 121 generates a first trigger signal TR1; when the predetermined time TM counted by the second delay generator 122 is equal to the second delay time DLY2, the second delay generator 122 generates a second trigger signal TR2, and so on.

[0136] According to another embodiment of the present invention, Figure 3 The temporary register 320 is used to store Figure 1 The first delay time is DLY1, the second delay time is DLY2, ... and the Nth delay time is DLYN. When the predetermined time TM counted by the counter 310 is equal to the first delay time DLY1, the comparator 330 generates a first trigger signal TR1; when the predetermined time TM counted by the counter 310 is equal to the second delay time DLY2, the comparator 330 generates a second trigger signal TR2, and so on.

[0137] Figure 4 A block diagram of an output device according to an embodiment of the present invention is shown. Figure 4 As shown, the output device 400 includes a bit line width controller 410, a bit line timing adjuster 420, and a data generator 430.

[0138] The bit line width controller 410 generates a control signal SC based on the bit line width ratio Q. The bit line timing adjuster 420 generates an adjustment signal SAD based on the clock signal CLK, the enable signal EN, and the control signal SC. The data generator 430 converts the input data DI into transfer data DT based on the enable signal EN and the adjustment signal SAD.

[0139] According to one embodiment of the present invention, the bit line width ratio Q is the ratio of the bit line width of the first logic bit line to the bit line width of the second logic bit line. According to one embodiment of the present invention, the first logic bit line is logic 0, and the second logic bit line is logic 1. According to some embodiments of the present invention, the output device 400 corresponds to... Figure 1 Any one of the first output device 111, the second output device 112, ... and the Nth output device 11N.

[0140] Figure 5 This displays a diagram showing the relationship between input data and transfer data according to an embodiment of the present invention. According to an embodiment of the present invention, Figure 5 The input data DI corresponds to Figure 4 Input data DI and Figure 1The first input data DI1, the second input data DI2, ... and the Nth input data DIN, and the transfer data DT correspond to... Figure 4 The transfer data DT, the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN.

[0141] like Figure 5 As shown, the input data DI is a combination of logic 0 and logic 1. When the input data DI is logic 0, the transition data DT does not change. When the input data DI is logic 1, the transition data DT changes when the input data DI changes from logic 0 to logic 1, and changes again at half a cycle. According to an embodiment of the present invention, the transition data DT is a bi-phase mark code (BMC).

[0142] Figures 6A-6B This displays a waveform diagram of the transferred data according to an embodiment of the present invention. For example... Figure 6A As shown, when the bit line width ratio Q is 1, it means that the bit line width ratio of logic 0 and logic 1 in the transfer data DT is 1:1. Therefore, the bit line width of logic 0 in the transfer data DT is the same as the bit line width of logic 1.

[0143] like Figure 6B As shown, when the bit line width ratio Q is 1.6, it means that the bit line width of logic 0 in the transfer data DT is 1.6 times that of logic 1. In other words, the bit line width of logic 0 in the transfer data DT is greater than the bit line width of logic 1.

[0144] like Figures 6A-6B As shown, the bit line width of logic 1 is fixed, and the bit line width ratio Q is used to adjust the bit line width of logic 0. According to one embodiment of the invention, the bit line width ratio Q is greater than 1 and less than 2. According to other embodiments of the invention, the bit line width of logic 0 can also be fixed, and the bit line width ratio Q can be used to adjust the bit line width of logic 1.

[0145] Back Figure 1 Because there are at least two different first delay times DLY1, second delay time DLY2, ... and Nth delay time DLYN, the turn-on times of the display units on the first channel CH1, second channel CH2, ... and Nth channel CHN are staggered. Furthermore, the bit line width ratio Q of the first transfer data DT1, second transfer data DT2, ... and Nth transfer data DTN is not 1, resulting in different conversion times for different transfer data. Therefore, the turn-on times of different display units are further staggered, thereby reducing the degree of voltage drop caused by the supply voltage of the display device.

[0146] Figure 7A schematic diagram showing the transfer of data according to another embodiment of the present invention is shown. For example... Figure 7 As shown, the transfer data 700 includes the preamble PRE, function code FNC, data code DTC, and end-of-packet EOP. The transfer data 700 is then compared with... Figure 2A Compared to transfer data 210, transfer data 700 includes function code FNC.

[0147] According to one embodiment of the present invention, the transferred data 700 corresponds to... Figure 1 The first transfer data DT1, the second transfer data DT2, ..., and the Nth transfer data DTN. The preamble PRE is used to... Figure 1 The display units of the first channel CH1, the second channel CH2, ... or the Nth channel CHN of the display device 10 are initially set.

[0148] The function code FNC includes a first instruction code CC1, a second instruction code CC2, a third instruction code CC3, and a fourth instruction code CC4. According to an embodiment of the present invention, the first instruction code CC1, the second instruction code CC2, the third instruction code CC3, and the fourth instruction code CC4 are used to set the synchronization format between the control device 100 and the display device 10.

[0149] The Data Code (DTC) includes first data D1, second data D2, ..., and the Mth data DM, where first data D1, second data D2, ..., and the Mth data DM are used to transmit control data for the corresponding display unit. The packet end (EOP) indicates the end of transmission.

[0150] According to one embodiment of the present invention, the transfer data 700 is in an idle state before the preamble PRE and after the end-of-packet EOP. Figure 7 As shown in the embodiment, the data transfer 700 is at a high logic level when in the idle state. According to another embodiment of the present invention, the data transfer 700 may also be at a low logic level when in the idle state.

[0151] Figure 8 A block diagram of an output device according to another embodiment of the present invention is shown. Figure 8 As shown, the output device 800 includes a preamble generator 810 and a function code generator 820. According to an embodiment of the present invention, the output device 800 corresponds to... Figure 1 The first output device 111, the second output device 112, ... and the Nth output device 11N.

[0152] Prefix generator 810 generates prefix PRE, and function code generator 820 generates function code FNC. Output device 800 converts input data DI into data code DTC, and sequentially outputs prefix PRE, function code FNC, data code DTC, and end-of-packet EOP as transfer data DT. According to an embodiment of the present invention, function code FNC, data code DTC, and end-of-packet EOP are biphase marker codes.

[0153] According to one embodiment of the present invention, Figure 8 The input data DI corresponds to Figure 1 The first input data DI1, the second input data DI2, ... and any one of the Nth input data DIN, Figure 8 The transfer data DT corresponds to Figure 1 The first transfer data DT1, the second transfer data DT2, ..., and the Nth transfer data DTN are all given below. The generation of the preamble PRE, the function code FNC, and the data code DTC will be explained in detail below.

[0154] Figure 9 This shows a block diagram of a preamble generator according to an embodiment of the present invention. Figure 9 As shown, the preamble generator 900 includes a preamble bit line count register 910, a preamble value register 920, a bit line counter 930, a preamble shift register 940, and a bit line count comparator 950.

[0155] A prefix bit line count register 910 is used to store the number of bit lines P1 of the prefix PRE, and a prefix value register 920 is used to store a predetermined value PV. According to some embodiments of the present invention, the prefix value register 920 stores the predetermined value PV corresponding to the number of bit lines P1. A bit line counter 930 counts according to an enable signal EN and a prefix enable signal ENPRE to generate a first count value CV1 and a first shift signal SFT1. According to one embodiment of the present invention, the enable signal EN is equivalent to... Figure 1 The enable signal EN.

[0156] According to one embodiment of the present invention, when the idle state Idle is at a high logic level and the preamble shift register 940 outputs the least significant bit (LSB) first, the predetermined value PV is 0xAA to facilitate the generation of the maximum number of logic transitions. According to another embodiment of the present invention, when the idle state Idle is at a high logic level and the preamble shift register 940 outputs the most significant bit (MSB) first, the predetermined value PV is 0x55 to facilitate the generation of the maximum number of logic transitions.

[0157] According to another embodiment of the present invention, when the idle state Idle is at a low logic level and the preamble shift register 940 outputs the least significant bit (LSB) first, the predetermined value PV is 0x55. According to another embodiment of the present invention, when the idle state Idle is at a low logic level and the preamble shift register 940 outputs the most significant bit (MSB) first, the predetermined value PV is 0xAA.

[0158] According to other embodiments of the present invention, the given value PV may also be other values. Here, 0x55 and 0xAA are used only for illustrative purposes and are not limited to them in any way.

[0159] Prefix shift register 940 shifts a predetermined value PV according to the first shift signal SFT1 and outputs a prefix PRE. Bit line comparator 950 compares the first count value CV1 with the bit line count P1 and generates a prefix enable signal ENPRE.

[0160] When the first count value CV1 is not greater than the number of bit lines P1, the preamble enable signal ENPRE is at the first logic level, enabling the preamble bit line counter 930 to continue counting. When the first count value CV1 is greater than the number of bit lines P1, the preamble enable signal ENPRE is at the second logic level and the preamble bit line counter 930 is disabled and stops counting.

[0161] For example, suppose the number of bit lines P1 is 32, representing Figure 7 The preamble PRE shown has 32 bits. The bit line counter 930 starts counting according to the enable signal EN and outputs a first count value CV1 and a first shift signal SFT1. The bit line comparator 950 compares the first count value CV1 with the bit line number P1.

[0162] When the first count value CV1 is not greater than the number of bit lines P1, the bit line comparator 950 uses the preamble enable signal ENPRE to control the bit line counter 930 to continue counting. The preamble shift register 940 outputs the most significant bit line or the least significant bit line of the predetermined value PV stored in the preamble value register 920 as the preamble PRE, based on the first shift signal SFT1 generated by the bit line counter 930.

[0163] When the first count value CV1 is greater than the number of bit lines P1 (in this embodiment, the first count value CV1 is 33 and the number of bit lines P1 is 32), the bit line comparator 950 uses the preamble enable signal ENPRE to control the bit line counter 930 to stop counting.

[0164] According to one embodiment of the present invention, since the preamble value register 920 stores a predetermined value PV corresponding to the number of bit lines P1, the preamble shift register 940 immediately stops outputting the preamble PRE after each bit line of the preamble value register 920 is output. According to another embodiment of the present invention, when the bit line counter 930 stops counting according to the preamble enable signal ENPRE, the bit line counter 930 simultaneously stops generating the first shift signal SFT1.

[0165] Figure 10 A block diagram of an output device according to an embodiment of the present invention is shown. Figure 10 As shown, the output device 1000 includes a function code generator 1010, a lookup table temporary register 1020, and a lookup table comparator 1030. According to some embodiments of the present invention, the output device 1000 incorporates... Figure 9 Prefix generator 900 corresponds to Figure 8 Output device 800 and Figure 1 Any one of the first output device 111, the second output device 112, ... and the Nth output device 11N.

[0166] like Figure 10 As shown, the function code generator 1010 includes a function code number register 1011, a function code register 1012, a function code counter 1013, a function code shift register 1014, and a function code number comparator 1015. The function code number register 1011 is used to store the function code number P2, and the function code register 1012 is used to store the instruction code CC of the function code number P2.

[0167] like Figure 7 As shown in the embodiment, the function code FNC includes four instruction codes, representing a function code number P2 of 4. Furthermore, the function code register 1012 is used to sequentially store the first instruction code CC1, the second instruction code CC2, the third instruction code CC3, and the fourth instruction code CC4. According to some embodiments of the present invention, when the function code FNC includes Y instruction codes, the function code number register 1011 stores a function code number P2 of Y, and the function code register 1012 sequentially stores Y function codes.

[0168] Back Figure 10 Function code counter 1013 according to Figure 9 The bit-line count comparator 950 generates a preamble enable signal ENPRE, and starts counting to generate a second count value CV2 and a second shift signal SFT2. The function code shift register 1014 outputs the instruction code CC stored in the function code register 1014 sequentially according to the second shift signal SFT2. The function code count comparator 1015 compares the second count value CV2 and the function code count P2, and generates a function code enable signal ENFC.

[0169] like Figure 7 As shown in the embodiment, when the second count value CV2 is 1, the function code shift register 1014 outputs the first instruction code CC1; when the second count value CV2 is 2, the function code shift register 1014 outputs the second instruction code CC2, and so on.

[0170] like Figure 10 As shown, the lookup table register 1020 is used to store the lookup table LUT. The lookup table comparator 1030 converts the instruction code CC and / or input data DI into the corresponding bit line code BTC according to the function code enable signal ENFC and the lookup table LUT.

[0171] According to an embodiment of the present invention, when the second count value CV2 is not greater than the number of function codes P2, the lookup table comparator 1030 operates in the first state according to the function code enable signal ENFC, so as to convert the instruction code CC into the corresponding bit line code BTC.

[0172] According to another embodiment of the present invention, when the second count value CV2 is greater than the number of function codes P2, the lookup table comparator 530 operates in the second state according to the function code enable signal ENFC, so as to convert the input data DI into the corresponding bit line code BTC.

[0173] like Figure 10 As shown, the output device 1000 further includes a width counter 1040, a bit line width comparator 1050, and a bit line generator 1060. The width counter 1040 generates a counting signal CNT based on the clock signal CLK. The bit line width comparator 1050 generates a half-bit line pulse HBP and a full-bit line pulse FBP based on the counting signal CNT. The bit line generator 1060 converts the bit line code BTC into a bidirectional marker code BMC.

[0174] According to one embodiment of the present invention, when the bit line code BTC is logic 1, the biphase marker code BMC switches once every half cycle; when the bit line code BTC is logic 0, the biphase marker code BMC switches once per cycle. According to another embodiment of the present invention, when the bit line code BTC is logic 0, the biphase marker code BMC switches once every half cycle; when the bit line code BTC is logic 1, the biphase marker code BMC switches once per cycle.

[0175] like Figure 8 Output device 800, Figure 9 Prefix generator 900 and Figure 10As shown in the output device 1000, the preamble generator 900 outputs a preamble PRE according to the enable signal EN. When the preamble PRE output is complete, the output device 900 is enabled to output the function code FNC by the preamble enable signal ENPRE. When the function code FNC output is complete, the output device 900 outputs the input data DI as the data code DTC according to the function code enable signal ENFC, where the function code FNC and the data code DTC are biphase marker codes BMC.

[0176] According to one embodiment of the present invention, when the data code DTC transmission is completed, the output device 900 further outputs the end-of-packet (EOP), wherein the end-of-packet (EOP) is a biphase marker code (BMC). In other words, apart from the preamble (PRE), the function code (FNC) of the transfer data DT, the data code DTC, and the end-of-packet (EOP) output by the output device 800 are all biphase marker codes (BMC).

[0177] Back Figure 10 When the designer provides an incorrect function code lookup table or needs to change the design, the requirements can be met by modifying the instruction code CC stored in function code register 1012 and the lookup table LUT stored in lookup table register 1020. Furthermore, users can also meet various different needs by modifying the function code number P2 stored in function code number register 1011, the instruction code CC stored in function code register 1012, and the lookup table LUT stored in lookup table register 1020.

[0178] Figure 11 This diagram illustrates the relationship between bitline codes and biphase marker codes according to an embodiment of the present invention. According to an embodiment of the present invention, Figure 11 The bit line code BTC corresponds to Figure 10 The bit line code BTC, the biphase marker code BMC corresponds to... Figure 5 The biphase marker code BMC.

[0179] like Figure 11 As shown, the bit line code BTC is a combination of logic 0 and logic 1. When the bit line code BTC is logic 0, the biphase marker code BMC changes once per cycle. When the bit line code BTC is logic 1, the biphase marker code BMC changes once every half cycle.

[0180] According to another embodiment of the present invention, when the bit line code BTC is logic 0, the biphase marker code BMC switches once every half cycle, and when the bit line code BTC is logic 1, the biphase marker code BMC switches once per cycle. Figures 6A-6B The embodiments shown are for illustrative purposes only and are not intended to limit the scope of the embodiments in any way.

[0181] Figure 12A flowchart of a control method according to an embodiment of the present invention is shown. The following is directed at... Figure 12 The description of control method 1200 will be combined with Figure 1 The control device 100 is described in detail below.

[0182] First, based on the enable signal EN, using Figure 1 The first output device 111, the second output device 112, ... and the Nth multiplexer 13N generate first transfer data DT1, second transfer data DT2, ... and Nth transfer data DTN (step S1210).

[0183] like Figure 4 As shown in the embodiment, according to the adjustment signal SAD, the data generator 430 converts the first input data DI1, the second input data DI2, ... and the Nth input data DIN into the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN, respectively. The bit line width ratio of any one of the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN to logic 0 and logic 1 is the bit line width ratio Q.

[0184] Next, based on the enable signal EN, using Figure 1 The first delay generator 121, the second delay generator 122, ... and the Nth delay generator 12N count the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN, and generate the first trigger signal TR1, the second trigger signal TR2, ... and the Nth trigger signal TRN respectively (step S1220).

[0185] like Figure 3 As shown in the embodiment, a predetermined time TM is counted, and when the predetermined time TM equals the delay time DLY (corresponding to... Figure 1 When the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN are reached, a trigger signal TR (corresponding to...) is generated. Figure 1 The first trigger signal TR1, the second trigger signal TR2, ... and the Nth trigger signal TRN).

[0186] Back Figure 12 Based on the first trigger signal TR1, the second trigger signal TR2, ... and the Nth trigger signal TRN, the first multiplexer 131, the second multiplexer 132, ... and the Nth multiplexer 13N respectively provide the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN to the corresponding first channel CH1, the second channel CH2, ... and the Nth channel CHN of the display device 10 (step S1230).

[0187] like Figure 1 As shown in the embodiment, since the first delay generator 121, the second delay generator 122, ... and the Nth delay generator 12N are used to count the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN and generate the first trigger signal TR1, the second trigger signal TR2, ... and the Nth trigger signal TRN respectively, the first multiplexer 131, the second multiplexer 132, ... and the Nth multiplexer 13N delay the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN respectively before providing the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN to the first channel CH1, the second channel CH2, ... and the Nth channel CHN.

[0188] This invention proposes a control device and control method for reducing the voltage drop of the supply voltage of a display device by time-division multiplexing the display units of different channels. By staggering the time when different channels of different display devices receive the preamble and adjusting the bit line width ratio of logic 0 to logic 1, the number of display units that are simultaneously turned on is reduced, thereby reducing the degree of voltage drop of the supply voltage of the display device.

[0189] While the embodiments and advantages of this disclosure have been disclosed above, it should be understood that any person skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps described in the specific embodiments of this specification. Any person skilled in the art can understand from the disclosure of some embodiments of this disclosure the current or future development of processes, machines, manufacturing, material composition, apparatus, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, and can be used according to some embodiments of this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claim scopes and embodiments.

Claims

1. A control device, characterized in that, For driving a display device, wherein the display device includes a first channel and a second channel, including: A first output device outputs first transfer data according to an enable signal; A second output device outputs a second transfer data according to the above-mentioned enable signal; A first delay generator generates a first trigger signal by counting a first delay time according to the above-mentioned enable signal; A second delay generator, based on the aforementioned enable signal, counts a second delay time to generate a second trigger signal; A first multiplexer, based on the aforementioned first trigger signal, provides the aforementioned first transfer data to the aforementioned first channel; and A second multiplexer provides the second transfer data to the second channel according to the second trigger signal. The aforementioned first output device and the aforementioned second output device further include: A one-bit linewidth controller generates a control signal based on the one-bit linewidth ratio; A one-bit time adjuster generates an adjustment signal based on a clock signal, the aforementioned enable signal, and the aforementioned control signal; and A data generator converts received data into transferred data according to the above-mentioned enable signal and the above-mentioned adjustment signal, wherein the transferred data includes at least one first logic bit line and at least one second logic bit line, wherein the ratio of the bit line width of the first logic bit line to the bit line width of the second logic bit line is the bit line width ratio. The bit line width ratio of the first transfer data and the bit line width ratio of the second transfer data are different.

2. The control device as described in claim 1, characterized in that, Both the first delay generator and the second delay generator described above include: A counter, based on the aforementioned enable signal and a clock signal, counts a first time or a second time. A temporary register for storing the first delay time or the second delay time; and A comparator generates the first trigger signal by comparing the first time and the first delay time, or generates the second trigger signal by comparing the second time and the second delay time, wherein the comparator generates the first trigger signal when the first time is equal to the first delay time, and the comparator generates the second trigger signal when the second time is equal to the second delay time.

3. The control device as described in claim 1, characterized in that, The first delay time and the second delay time mentioned above are different.

4. A control method, characterized in that, For driving a display device, wherein the display device includes a first channel and a second channel, wherein the control method includes: Based on an enable signal, output a first transfer data and a second transfer data; Based on the above enable signal, a first delay time and a second delay time are counted to generate a first trigger signal and a second trigger signal respectively; Based on the aforementioned first trigger signal, the aforementioned first transfer data is provided to the aforementioned first channel; and Based on the second trigger signal, the second transfer data is provided to the second channel. The step of outputting the first transfer data and the second transfer data according to the above-mentioned enable signal further includes: A first adjustment signal is generated based on a first bit line width ratio; A second adjustment signal is generated based on a second bit line width ratio; A first control signal is generated based on a clock signal, the aforementioned enable signal, and the aforementioned first adjustment signal; A second control signal is generated based on the aforementioned clock signal, the aforementioned enable signal, and the aforementioned second adjustment signal; Based on the aforementioned enable signal and the aforementioned first control signal, a first received data is converted into the aforementioned first transferred data; and Based on the above-mentioned enable signal and the above-mentioned second control signal, the second received data is converted into the above-mentioned second transferred data; The first transfer data includes at least one first logic bit line and at least one second logic bit line, wherein the ratio of the bit line width of the first logic bit line to the bit line width of the second logic bit line is the first bit line width ratio. The second transfer data includes at least one first logic bit line and at least one second logic bit line, wherein the ratio of the bit line width of the first logic bit line to the bit line width of the second logic bit line is the second bit line width ratio.

5. The control method as described in claim 4, characterized in that, The steps of generating the first trigger signal and the second trigger signal respectively by counting the first delay time and the second delay time according to the enable signal further include: A temporary register is used to store the first delay time and the second delay time. Based on the above enable signal and a clock signal, count a first time and a second time; When the first time equals the first delay time, the first trigger signal is generated; and When the second time is equal to the second delay time, the second trigger signal is generated.

6. The control method as described in claim 4, characterized in that, The first delay time mentioned above is different from the second delay time mentioned above.

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