Method of manufacturing memory elements having elongated active regions

Abstract

A method of fabricating a memory element is provided. The method includes providing a semiconductor substrate including an active region disposed on or in the semiconductor substrate; disposing a patterned photoresist layer on the semiconductor substrate; removing a first portion of the semiconductor substrate exposed by the patterned photoresist layer to form a first trench; removing the patterned photoresist layer; forming a first insulating component within the first trench; disposing an energy-decomposable mask on the semiconductor substrate and the first insulating component; irradiating a portion of the energy-decomposable mask with electromagnetic radiation; removing the portion of the energy-decomposable mask irradiated with electromagnetic radiation to form a patterned energy-decomposable mask; removing a second portion of the semiconductor substrate exposed by the patterned energy-decomposable mask to form a second trench; removing the patterned energy-decomposable mask; and forming a second insulating component within the second trench.

Description

[0001] Cross-referencing

[0002] This application claims priority to U.S. Patent Applications Nos. 17 / 737,722 and 17 / 737,703 (i.e., priority date "May 5, 2022"), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a method for fabricating a semiconductor device. In particular, it relates to a method for fabricating a memory device having an elongated active region (AA). Background Technology

[0004] Non-volatile memory elements retain data even when their power supply is cut off. One type of non-volatile memory element is a one-time programmable (OTP) memory element. With an OTP memory element, a user can only program the OTP memory element once and cannot modify the data stored in the OTP memory element. A signal is transmitted to a metal interconnect disposed above a semiconductor substrate.

[0005] However, this type of wiring in the metal interconnect presents an obstacle to increasing the wiring density of memory elements. Such wiring can result in a narrower process window and may lead to misalignment or leakage between multiple memory cells in the memory element, thus limiting the reduction of the minimum feature size. Therefore, it is desirable to develop improvements that address the relevant manufacturing challenges.

[0006] The description of the "prior art" above is only for background information and does not constitute an admission that the description of the "prior art" above discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the "prior art" above should be considered part of this disclosure. Summary of the Invention

[0007] One embodiment of this disclosure provides a method for fabricating a memory element. The method includes the steps of: providing a semiconductor substrate, the semiconductor substrate including an active region to which a patterned photoresist layer is disposed; the active region being disposed on the semiconductor substrate or on the semiconductor substrate, the patterned photoresist layer being disposed on the semiconductor substrate; removing a first portion of the semiconductor substrate exposed through the patterned photoresist layer to form a first trench; removing the patterned photoresist layer; forming a first insulating component within the first trench; disposing an energy-reducible mask on the semiconductor substrate and the first insulating component; irradiating a portion of the energy-reducible mask with electromagnetic radiation; removing the portion of the energy-reducible mask irradiated with the electromagnetic radiation to form a patterned energy-reducible mask; removing a second portion of the semiconductor substrate exposed through the patterned energy-reducible mask to form a second trench; removing the patterned energy-reducible mask; and forming a second insulating component within the second trench.

[0008] In some embodiments, the energy-decomposable shield is set after the first insulating component is formed.

[0009] In some embodiments, the energy-degradable shield is thermally degradable, light-degradable, or electron beam (e-beam) degradable.

[0010] In some embodiments, the energy-degradable shield includes a cross-linked compound having a functional group or a double bond.

[0011] In some embodiments, the energy-decomposable shield comprises a polymer, polyimide, resin, or epoxy resin.

[0012] In some embodiments, the electromagnetic radiation is directed vertically toward that portion of the energy-decomposable shield.

[0013] In some embodiments, the electromagnetic radiation is infrared, ultraviolet, or an electron beam (e-beam).

[0014] In some embodiments, the first insulating component and the second insulating component surround the active region of the semiconductor substrate.

[0015] In some embodiments, the first insulating component and the second insulating component comprise the same material.

[0016] In some embodiments, the first insulating component and the second insulating component are integrally formed to form a shallow trench isolation (STI).

[0017] In some embodiments, the formation of the first trench is performed before the formation of the second trench.

[0018] In some embodiments, the fabrication technique of the first insulating component includes disposing a first insulating material on the semiconductor substrate and within the first trench.

[0019] In some embodiments, the fabrication technique for the second insulating component includes disposing a second insulating material on the semiconductor substrate and within the second trench.

[0020] In some embodiments, the patterned photoresist layer and the patterned energy-degradable mask comprise different materials.

[0021] Another embodiment of this disclosure provides a method for fabricating a memory element. The method includes the steps of providing a semiconductor substrate, the semiconductor substrate including an active region and a first insulating component, the active region being disposed on or within the semiconductor substrate, and the first insulating component extending into the semiconductor substrate and disposed adjacent to the active region; disposing an energy-reducible mask on the semiconductor substrate and the first insulating component; irradiating a portion of the energy-reducible mask with electromagnetic radiation; removing the portion of the energy-reducible mask irradiated with electromagnetic radiation to form a patterned energy-reducible mask; removing a portion of the semiconductor substrate exposed by the patterned energy-reducible mask to form a trench; removing the patterned energy-reducible mask; and forming a second insulating component within the trench.

[0022] In some embodiments, the first insulating component is covered by the energy-decomposable shield.

[0023] In some embodiments, the length of the first insulating component is substantially greater than the length of the second insulating component.

[0024] In some embodiments, a depth of the first insulating component is approximately equal to a depth of the second insulating component.

[0025] In some embodiments, the first insulating component is covered by the patterned energy-degradable mask.

[0026] In some embodiments, the energy can decompose the portion of the mask and remove it by etching.

[0027] In some embodiments, the first insulating component and the second insulating component comprise oxides.

[0028] In some embodiments, the active region of the semiconductor substrate is surrounded by the first insulating component and the second insulating component.

[0029] In some embodiments, the electromagnetic radiation is disposed above the energy-decomposable shield.

[0030] In some embodiments, the depth of the trench is approximately equal to the depth of the first insulating component.

[0031] Another embodiment of this disclosure provides a method for fabricating a memory element. The method includes the steps of providing a semiconductor substrate including an active region disposed on or within the semiconductor substrate; disposing an energy-reducible mask on the semiconductor substrate; processing a portion of the energy-reducible mask; removing the portion of the energy-reducible mask to form a patterned energy-reducible mask; removing a portion of the semiconductor substrate exposed by the patterned energy-reducible mask to form a trench; removing the patterned energy-reducible mask; and forming an insulating component within the trench.

[0032] In some embodiments, the active area is located adjacent to the trench.

[0033] In some embodiments, the energy can decompose the portion of the shield into electromagnetic radiation.

[0034] In some embodiments, the electromagnetic radiation is infrared, ultraviolet, or an electron beam (e-beam).

[0035] In some embodiments, the electromagnetic radiation irradiates the energy-decomposable shield.

[0036] In some embodiments, the insulating component comprises an oxide.

[0037] In some embodiments, the energy-decomposable mask is provided by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0038] In some embodiments, the fabrication technique for the insulating component includes oxidation.

[0039] In some embodiments, the fabrication technique for the insulating component includes disposing an insulating material on the semiconductor substrate and within the trench.

[0040] In some embodiments, the insulating material above the trench is removed.

[0041] In some embodiments, the semiconductor substrate includes silicon.

[0042] In summary, because the active region of the semiconductor substrate is defined by disposing a patterned energy-reducible mask on the semiconductor substrate and then removing the semiconductor substrate to expose multiple predetermined portions through the patterned energy-reducible mask, the size of the active region can be kept to a minimum or not reduced during the removal process. Therefore, the process window for subsequent processes on the active region will not be further reduced. As a result, misalignment or leakage between multiple memory cells in the memory element can be avoided or minimized, and the overall performance of the memory element can be improved.

[0043] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, thereby enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0044] When with attachment Figure 1 When reading this document, the best understanding of all aspects of this disclosure can be obtained from the following detailed description. It should be understood that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features can be increased or decreased arbitrarily for clarity of discussion.

[0045] Figure 1 This is a cross-sectional top view schematic diagram illustrating memory elements of some embodiments of the present disclosure.

[0046] Figure 2 This is a schematic side view of the cross section, for example. Figure 1 A cross-section of a memory element along section line AA.

[0047] Figure 3 This is a schematic side view of the cross section, for example. Figure 1 A cross-section of a memory element along section line BB.

[0048] Figure 4 This is a flowchart illustrating methods for fabricating memory elements according to some embodiments of this disclosure.

[0049] Figures 5 to 28 This is a cross-sectional schematic diagram illustrating several intermediate stages in the fabrication of memory elements according to some embodiments of the present disclosure.

[0050] Explanation of reference numerals in the attached figures:

[0051] 100: Memory element

[0052] 101: Semiconductor substrate

[0053] 101a: Array area

[0054] 101b: Active Zone

[0055] 101c: First trench

[0056] 101d: Second trench

[0057] 101e: Depression

[0058] 102: First Insulation Component

[0059] 102': First insulating material

[0060] 103: Patterned photoresist layer

[0061] 103': Photoresist material

[0062] 104: Patterned Energy Decomposable Mask

[0063] 104': Energy-decomposable shield

[0064] 104a: Partial

[0065] 107: Second Insulation Component

[0066] 107': Second insulating material

[0067] 108: Insulation components

[0068] D1: Depth

[0069] D2: Depth

[0070] D3: Depth

[0071] D4: Depth

[0072] L1: Length

[0073] L2: Length

[0074] R: Electromagnetic radiation

[0075] S200: Preparation Method

[0076] S201: Steps

[0077] S202: Steps

[0078] S203: Steps

[0079] S204: Steps

[0080] S205: Steps

[0081] S206: Steps

[0082] S207: Steps

[0083] S208: Steps

[0084] S209: Steps

[0085] S210: Steps Detailed Implementation

[0086] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0087] Furthermore, the component numbers and / or letters may be repeated in various instances in this disclosure. Such repetition is for simplicity and clarity purposes and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed.

[0088] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figure and another (other) element or feature. These spatial relative terms are intended to encompass different orientations of the element in use or operation, in addition to those shown in the figure. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0089] Figure 1 This is a cross-sectional top view schematic diagram illustrating a memory element 100 of some embodiments of the present disclosure. Figure 2 This is a schematic side view of the cross section, for example. Figure 1 A cross-section of the memory element 100 along section line AA. Figure 3 This is a schematic side view of the cross section, for example. Figure 1 A cross-section of the memory element 100 along section line BB. In some embodiments, such as Figure 1 The memory element 100 shown may be part of an element. In some embodiments, the memory element 100 includes a plurality of cell units arranged along rows and columns.

[0090] In some embodiments, the memory element 100 includes a semiconductor substrate 101. In some embodiments, the semiconductor substrate 101 is inherently semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor wafer (e.g., a silicon wafer) or a silicon-on-insulator (SOI) wafer (e.g., a silicon-on-insulator wafer). In some embodiments, the semiconductor substrate 101 is a silicon substrate.

[0091] In some embodiments, a semiconductor substrate 101 defines a surrounding region (not shown) and an array region 101a. In some embodiments, the array region 101a is at least partially surrounded by the surrounding region. In some embodiments, the surrounding region is adjacent to a periphery of the semiconductor substrate 101, and the array region 101a is adjacent to a central region of the semiconductor substrate 101. In some embodiments, the array region 101a can be used to manufacture electronic components, such as capacitors, transistors, or the like. In some embodiments, a boundary is disposed between the surrounding region and the array region 101a.

[0092] In some embodiments, the semiconductor substrate 101 includes an active region 101b disposed on or within the semiconductor substrate 101. In some embodiments, the active region 101b is a doped region in the semiconductor substrate 101. In some embodiments, the active region 101b extends horizontally on or beneath the semiconductor substrate 101. In some embodiments, the dimension of an upper cross-section of each active region 101b may be the same as or different from that of the other active regions 101b. In some embodiments, the active region 101b is in the shape of a strip, an elongated shape, a rectangle, or a polygon.

[0093] In some embodiments, each active region 101b includes a dopant of the same type. In some embodiments, each active region 101b includes a dopant of a different type than the dopant types included in other active regions 101b. In some embodiments, each active region 101b has the same conductivity type. In some embodiments, the active region 101b includes an N-type dopant.

[0094] In some embodiments, the semiconductor substrate 101 includes a recess 101e extending into the semiconductor substrate 101 and surrounding the active region 101b. In some embodiments, the recess 101e is surrounded by one or more active regions 101b. The recess 101e extends away from the active region 101b and toward the semiconductor substrate 101.

[0095] In some embodiments, the memory element 100 includes an insulating component 108 surrounding an active region 101b of a semiconductor substrate 101. In some embodiments, the active regions 101b are surrounded by the insulating component 108 to separate and electrically insulate them from each other. In some embodiments, the active regions 101b are arranged along a row or column. In some embodiments, the active regions 101b are completely surrounded by the insulating component 108.

[0096] In some embodiments, the insulating component 108 is a shallow trench isolation (STI) or part of an STI. In some embodiments, the insulating component 108 defines a boundary of the active region 101b. In some embodiments, the insulating component 108 comprises an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof.

[0097] In some embodiments, the insulating component 108 is at least partially disposed within a recess 101e of the semiconductor substrate 101. In some embodiments, the recess 101e is completely filled by the insulating component 108. In some embodiments, a depth of the insulating component 108 is substantially greater than or equal to a depth of the active region 101b.

[0098] Figure 4 This is a flowchart illustrating a method S200 for fabricating a memory element 100 according to some embodiments of the present disclosure. Figures 5 to 28 This is a cross-sectional schematic diagram illustrating several intermediate stages in the fabrication of memory element 100 according to some embodiments of the present disclosure.

[0099] Figures 5 to 28 The stages shown are also schematically illustrated. Figure 4 In the flowchart in [the document]. In the following discussion, refer to [the document]. Figure 4 The processing steps shown are for discussion Figures 5 to 28 The manufacturing stages shown are described. Preparation method S200 includes multiple operations, and the description and explanation are not intended to limit the order of the steps. Preparation method S200 includes multiple steps (S201, S202, S203, S204, S205, S206, S207, S208, S209, and S210).

[0100] Please refer to Figures 5 to 7 ,in accordance with Figure 4 In step S201, a semiconductor substrate 101 is provided, wherein the semiconductor substrate 101 includes an active region 101b and a patterned photoresist layer 103, the active region 101b is disposed on or in the semiconductor substrate 101, and the patterned photoresist layer 103 is disposed on the semiconductor substrate 101.

[0101] In such Figure 5In some embodiments shown, a semiconductor substrate 101 is provided including an active region 101b disposed on or in the semiconductor substrate 101. In some embodiments, the semiconductor substrate 101 includes a semiconductor material. In some embodiments, the semiconductor substrate 101 is a silicon substrate. In some embodiments, the semiconductor substrate 101 defines a surrounding region (not shown) and an array region 101a, the array region 101a being at least partially surrounded by the surrounding region. In some embodiments, the array region 101a is disposed adjacent to a central region of the semiconductor substrate 101.

[0102] In some embodiments, the active region 101b is a doped region in the semiconductor substrate 101. In some embodiments, the active region 101b extends horizontally on an upper surface of the semiconductor substrate 101. In some embodiments, each active region 101b includes a dopant of the same type. In some embodiments, each active region 101b includes a dopant of a different type than the dopant types included in other active regions 101b. In some embodiments, each active region 101b has the same conductivity type. In some embodiments, the fabrication technique of the active region 101b includes an implantation process or an ion doping process.

[0103] In such Figure 6 and Figure 7 In some embodiments shown, a patterned photoresist layer 103 is formed on a semiconductor substrate 101. In some embodiments, the fabrication technique of the patterned photoresist layer 103 includes, for example, Figure 6 As shown, a photoresist material 103' is disposed on the semiconductor substrate, and as... Figure 7 The patterned photoresist material 103' is shown. Patterning the photoresist material 103' involves removing multiple portions of the photoresist material 103' by etching or any other suitable process. For example... Figure 7 As shown, the semiconductor substrate 101 is at least partially exposed via a patterned photoresist layer 103.

[0104] Please refer to Figure 8 ,in accordance with Figure 4 In step S202, a first portion of the semiconductor substrate 101 exposed via the patterned photoresist layer 103 is removed to form a first trench 101c. The first trench 101c extends through the semiconductor substrate 101. In some embodiments, the first portion of the semiconductor substrate 101 exposed via the patterned photoresist layer 103 is removed by etching or any other suitable process.

[0105] Please refer to Figure 9 and Figure 10 ,in accordance with Figure 4 In step S203, the patterned photoresist layer 103 is removed. Figure 9 It is along Figure 10 A cross-sectional view of section line CC in the diagram, and Figure 10 yes Figure 9 A top view schematic diagram. In some embodiments, the patterned photoresist layer 103 is removed by etching, stripping, or any other suitable process. Figure 10 As shown, after removing the patterned photoresist layer 103, the active region 101b of the semiconductor substrate 101 is exposed. In some embodiments, after forming such... Figure 9 and Figure 10 After the first trench 101c shown, it is formed in Figure 10 The top view diagram shows a strip-shaped pattern.

[0106] Please refer to Figures 11 to 13 ,in accordance with Figure 4 In step S204, a first insulating component 102 is formed in the first trench 101c. Figure 13 yes Figure 12 Top view diagram. Figure 12 It is along Figure 13 A cross-sectional view of the center section DD. In some embodiments, the fabrication technique for the first insulating component 102 includes disposing a first insulating material 102' on the semiconductor substrate 101 and within the first trench 101c, and then removing portions of the first insulating material 102' to form a structure as shown in the diagram. Figure 12 and Figure 13 The first insulating component 102 shown.

[0107] In some embodiments, the first trench 101c is filled with a first insulating material 102'. In some embodiments, portions of the insulating material 102' are removed by planarization, etching, or any other suitable process. In some embodiments, the first insulating component 102 is adjacent to or surrounds the active region 101b of the semiconductor substrate 101. In some embodiments, the first insulating component 102 comprises an oxide or the like. In some embodiments, the first insulating component 102 is part of an insulating component 108, which will be discussed later.

[0108] Please refer to Figures 14 to 15 ,in accordance with Figure 4 In step S205, an energy-decomposable mask 104' is disposed on the semiconductor substrate 101 and the first insulating component 102. Figure 15 yes Figure 14 Top view diagram. Figure 14 It is along Figure 15A cross-sectional view of the cross-section EE. In some embodiments, the first insulating component 102 is covered by an energy-degradable shield 104'. In some embodiments, the energy-degradable shield 104' is formed by deposition, chemical vapor deposition (CVD), physical vapor deposition (PVD), or any other suitable process. In some embodiments, the formation of the energy-degradable shield 104' is performed after the formation of the first insulating component 102.

[0109] In some embodiments, the energy-degradable mask 104' is thermally degradable, photodegradable, electron beam degradable, or the like. In some embodiments, the energy-degradable mask 104' can be degraded by any type of energy, such as heat, infrared (IR), ultraviolet (UV), electron beam, or the like. In some embodiments, the energy-degradable mask 104' includes a crosslinked compound having a functional group or a double bond. In some embodiments, the energy-degradable mask 104' includes a polymer, polyimide, resin, epoxy resin, or the like. In some embodiments, the photoresist material 103' and the energy-degradable mask 104' comprise different materials.

[0110] Please refer to Figure 16 and Figure 17 According to Figure 4 In step S206, an electromagnetic radiation R is used to irradiate a portion 104a of the shield 104', which can decompose the energy. Figure 17 yes Figure 16 Top view diagram. Figure 16 It is along Figure 17 A cross-sectional view of the cross section FF. In some embodiments, a portion 104a of the energy-decomposable shield 104' is treated with electromagnetic radiation R. In some embodiments, a portion 104a of the energy-decomposable shield 104' irradiated with electromagnetic radiation R is disposed on a semiconductor substrate 101. In some embodiments, a portion 104a of the energy-decomposable shield 104' irradiated with electromagnetic radiation R is disposed on an active region 101b of the semiconductor substrate 101.

[0111] In some embodiments, electromagnetic radiation R is directed perpendicularly toward a portion 104a of the energy-decomposable shield 104' to treat that portion 104a. Therefore, the portion 104a of the energy-decomposable shield 104' becomes easily removable. In some embodiments, the electromagnetic radiation R is infrared, ultraviolet, an electron beam, or the like. In some embodiments, the portion 104a of the energy-decomposable shield 104' has as... Figure 17 The image shows a top cross-section that is rectangular, circular, or polygonal in shape.

[0112] Please refer to Figure 18 and Figure 19As shown, based on Figure 4 In step S207, a portion 104a of the energy-decomposable mask 104' irradiated by electromagnetic radiation E is removed to form a patterned energy-decomposable mask 104. Figure 19 yes Figure 18 Top view diagram. Figure 18 It is along Figure 19 A cross-sectional view of the section line GG. In some embodiments, portion 104a of the energy-decomposable mask 104' is removed by etching or any other suitable process.

[0113] After removing portion 104a of the energy-removable mask 104', the active region 101b of the semiconductor substrate 101 is exposed via the patterned energy-removable mask 104. In some embodiments, the first insulating component 102 is covered by the patterned energy-removable mask 104. In some embodiments, the patterned photoresist layer and the patterned energy-removable mask 104 comprise different materials.

[0114] Please refer to Figure 20 and Figure 21 ,in accordance with Figure 4 In step S208, a second portion of the semiconductor substrate 101 exposed by the patterned energy-decomposable mask 104 is removed to form a second trench 101d. Figure 21 yes Figure 20 Top view diagram. Figure 20 It is along Figure 21 A cross-sectional view of the cross section HH. In some embodiments, the second portion of the semiconductor substrate 101 exposed via a patterned energy-decomposable mask 104 is removed by etching or any other suitable process. In some embodiments, the formation of the first trench 101c is performed prior to the formation of the second trench 101d.

[0115] In some embodiments, a depth D1 of the first trench 101c is approximately equal to a depth D2 of the second trench 101d. In some embodiments, the depth of the first trench 101c is approximately equal to a depth D3 of the first insulating component 102.

[0116] Please refer to Figure 22 ,in accordance with Figure 4 In step S209, the patterned energy-degradable mask 104 is removed. In some embodiments, the patterned energy-degradable mask 104 is removed by etching or any other suitable process. After the patterned energy-degradable mask 104 is removed, the first insulating component 102 is exposed.

[0117] Please refer to Figures 23 to 25 ,in accordance with Figure 4 In step S210, a second insulating component 107 is formed in the second trench 101d. Figure 25 yes Figure 24 Top view diagram. Figure 24 It is along Figure 25 A cross-sectional view of the cross-section JJ. In some embodiments, the fabrication technique of the second insulating component 107 includes disposing a second insulating material 107' on the semiconductor substrate 101 and the first insulating component 102, and on such... Figure 23 Within the second trench 101d shown, some portions of the second insulating material 107' are then removed to form a shape as shown. Figure 24 The second insulating component 107 is shown.

[0118] In some embodiments, the second trench 101d is filled with a second insulating material 107'. In some embodiments, some portions of the second insulating material 107' are removed by planarization, etching, or any other suitable process. In some embodiments, the second insulating material 107' above the second trench 101d is removed. In some embodiments, the first insulating component 102 and the second insulating component 107 surround the active region 101b of the semiconductor substrate 101. In some embodiments, the second insulating component 107 comprises an oxide or the like. In some embodiments, the first insulating component 102 and the second insulating component 107 comprise the same material.

[0119] In some embodiments, a length L1 of the first insulating component 102 is substantially greater than a length L2 of the second insulating component 107. In some embodiments, the first insulating component 102 (e.g., Figure 20 The depth D3 (as shown) is approximately equal to a depth D4 of the second insulating component 107.

[0120] In some embodiments, the first insulating component 102 and the second insulating component 107 are integrally formed to form an insulating component 108. In some embodiments, the insulating component 108 is a shallow trench isolation (STI). In some embodiments, such as Figures 26 to 28 form Figures 1 to 3 The memory element 100. In some embodiments, active regions 101b are surrounded by insulating components 108 to separate and electrically insulate the active regions 101b from each other. In some embodiments, the insulating components 108 define a boundary of the active regions 101b. In some embodiments, the insulating components 108 comprise oxides or the like.

[0121] In some embodiments, the size of a top cross-section of each active region 101b may be the same as or different from that of the other active regions 101b. In some embodiments, the active regions 101b are strip-shaped, elongated, rectangular, or polygonal. Since the fabrication technique of the active regions 101b of the semiconductor substrate 101 involves placing a patterned energy-reducible mask 104 on the semiconductor substrate 101 and then removing some predetermined portions of the semiconductor substrate 101 exposed via the patterned energy-reducible mask 104, the size of the active regions 101b can remain minimal or not reduced during removal. Therefore, a process window for subsequent processes on the active regions 101b will not be further reduced.

[0122] One embodiment of this disclosure provides a method for fabricating a memory element. The method includes the steps of: providing a semiconductor substrate, the semiconductor substrate including an active region to which a patterned photoresist layer is disposed; the active region being disposed on the semiconductor substrate or on the semiconductor substrate, the patterned photoresist layer being disposed on the semiconductor substrate; removing a first portion of the semiconductor substrate exposed through the patterned photoresist layer to form a first trench; removing the patterned photoresist layer; forming a first insulating component within the first trench; disposing an energy-reducible mask on the semiconductor substrate and the first insulating component; irradiating a portion of the energy-reducible mask with electromagnetic radiation; removing the portion of the energy-reducible mask irradiated with the electromagnetic radiation to form a patterned energy-reducible mask; removing a second portion of the semiconductor substrate exposed through the patterned energy-reducible mask to form a second trench; removing the patterned energy-reducible mask; and forming a second insulating component within the second trench.

[0123] Another embodiment of this disclosure provides a method for fabricating a memory element. The method includes the steps of providing a semiconductor substrate, the semiconductor substrate including an active region and a first insulating component, the active region being disposed on or within the semiconductor substrate, and the first insulating component extending into the semiconductor substrate and disposed adjacent to the active region; disposing an energy-reducible mask on the semiconductor substrate and the first insulating component; irradiating a portion of the energy-reducible mask with electromagnetic radiation; removing the portion of the energy-reducible mask irradiated with electromagnetic radiation to form a patterned energy-reducible mask; removing a portion of the semiconductor substrate exposed by the patterned energy-reducible mask to form a trench; removing the patterned energy-reducible mask; and forming a second insulating component within the trench.

[0124] Another embodiment of this disclosure provides a method for fabricating a memory element. The method includes the steps of providing a semiconductor substrate including an active region disposed on or within the semiconductor substrate; disposing an energy-reducible mask on the semiconductor substrate; processing a portion of the energy-reducible mask; removing the portion of the energy-reducible mask to form a patterned energy-reducible mask; removing a portion of the semiconductor substrate exposed by the patterned energy-reducible mask to form a trench; removing the patterned energy-reducible mask; and forming an insulating component within the trench.

[0125] In summary, because the active region of the semiconductor substrate is defined by disposing a patterned energy-reducible mask on the semiconductor substrate and then removing the semiconductor substrate to expose multiple predetermined portions through the patterned energy-reducible mask, the size of the active region can be kept to a minimum or not reduced during the removal process. Therefore, the process window for subsequent processes on the active region will not be further reduced. As a result, misalignment or leakage between multiple memory cells in the memory element can be avoided or minimized, and the overall performance of the memory element can be improved.

[0126] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0127] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A method for fabricating a memory element, comprising: A semiconductor substrate is provided, the semiconductor substrate including an active region and a first insulating component, the active region being disposed on or in the semiconductor substrate, and the first insulating component extending into the semiconductor substrate and disposed adjacent to the active region; An energy-decomposable shield is disposed on the semiconductor substrate and the first insulating component; Irradiating this energy with electromagnetic radiation can break down a portion of the shield. Remove the portion of the energy-decomposable shield that is irradiated by the electromagnetic radiation to form a patterned energy-decomposable shield; A portion of the semiconductor substrate exposed by the patterned energy-degradable mask is removed to form a trench; Removing the patterned energy decomposes the mask; as well as A second insulating component is formed in the trench, wherein a depth of the first insulating component is approximately equal to a depth of the second insulating component.

2. The method for fabricating a memory element as claimed in claim 1, wherein the first insulating component is covered by the energy-decomposable shield.

3. The method for fabricating a memory element as described in claim 1, wherein the length of the first insulating component is substantially greater than the length of the second insulating component.

4. The method for fabricating a memory element as claimed in claim 1, wherein the first insulating component is covered by the patterned energy-degradable mask.

5. The method for fabricating a memory element as claimed in claim 1, wherein the portion of the energy-decomposable mask is removed by etching.

6. The method for fabricating a memory element as claimed in claim 1, wherein the first insulating component and the second insulating component comprise oxides.

7. The method for fabricating a memory element as claimed in claim 1, wherein the active region of the semiconductor substrate is surrounded by the first insulating component and the second insulating component.

8. The method for fabricating a memory element as claimed in claim 1, wherein the electromagnetic radiation is disposed above the energy-decomposable shield.

9. The method for fabricating a memory element as claimed in claim 1, wherein the depth of the trench is approximately equal to the depth of the first insulating component.

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