Semiconductor structure and method of forming the same
By forming a first conductive layer as an etch stop layer before forming the trench structure, the contact between the trench and the gate structure is avoided, and the distance between the trench and the drift region is controlled, thus solving the problems of LDEMOS structure reliability and small process window and improving device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2022-04-29
- Publication Date
- 2026-06-26
AI Technical Summary
Laterally diffused enhanced metal-oxide-semiconductor (LDEMOS) structures have poor reliability and a small process window, which affects device performance.
Before forming the trench structure, a first conductive layer is formed. The first conductive layer serves as an etch stop layer in the trench structure to prevent the trench from continuing to etch downwards and contacting the gate structure. The trench structure extends from the second dielectric layer to the first dielectric layer from top to bottom, controlling the distance between the trench structure and the drift region.
This improved the reliability of the suspended plug within the trench structure, expanded the process window, and enhanced device performance.
Smart Images
Figure CN117012643B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor structure and a method for forming the same. Background Technology
[0002] Power semiconductor structures are widely used in many fields such as switching power supplies, automotive electronics, industrial control, wireless communication, and motor control. Two important indicators of power semiconductor structures are high breakdown voltage and low on-resistance. Laterally diffused metal-oxide-semiconductor (LDMOS) transistors are a type of power MOS structure, mainly used in power integrated circuits.
[0003] A laterally diffused metal-oxide-semiconductor (LDMOS) transistor structure includes: a first well region and a second well region located within a substrate, wherein the first well region and the second well region have different types of conductive ions; a gate structure located on the first well region and the second well region; a source doped layer and a drain doped layer located on opposite sides of the gate structure within the substrate, respectively, wherein the drain doped layer is located within the first well region and the source doped layer is located within the second well region, and both the source and drain doped layers contain source and drain ions with the same conductivity type as the well ions in the first well region. The second well region covered by the gate structure is the channel region, and the first well region between the drain doped layer and the channel region is the drift region of the LDMOS transistor. The drift region is used to change the electric field distribution of the LDMOS transistor and improve its breakdown voltage; however, for further miniaturized structures, its effect on improving the breakdown voltage is significantly limited.
[0004] Therefore, with the shrinking of semiconductor structure size, the Laterally Diffused Enhanced Metal Oxide Semiconductor (LDEMOS) transistor structure has been proposed. In LDEMOS, floating plugs are formed in the dielectric layer on the gate structure and drain doped layer, thereby reducing the hot carrier effect and improving the breakdown voltage of LDEMOS.
[0005] However, under current technology, the reliability of lateral diffusion enhanced metal oxide semiconductor (LDEMOS) structures is poor and the process window is small, which affects device performance. Summary of the Invention
[0006] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, which improves the reliability of the lateral diffusion enhanced metal oxide semiconductor (LDEMOS) structure, expands the process window, and enhances device performance.
[0007] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first well region and a drift region in the substrate, wherein the first well region and the drift region have opposite conductivity types; forming a gate structure, a source region located in the first well region, a drain region located in the drift region, and a first dielectric layer on the substrate, wherein the gate structure is located on a portion of the first well region and the drift region, the first dielectric layer is located on the sidewalls and top of the gate structure, and the projection pattern of the gate structure on the surface of the drift region is a first pattern; and forming a first conductive layer on the first dielectric layer. A second dielectric layer is located on the surface of the first dielectric layer and the first conductive layer, wherein the projection pattern of the first conductive layer on the surface of the drift region is a second pattern, and the first pattern is within the range of the second pattern; a trench structure is formed in the first dielectric layer and the second dielectric layer on the drift region, the trench structure including a first trench and a second trench that are interconnected, the first trench being located in the second dielectric layer, the second trench being located in the first dielectric layer, the first trench exposing a portion of the top surface of the first conductive layer, and the bottom of the second trench being higher than the surface of the drift region; a floating plug is formed within the trench structure.
[0008] Optionally, the method for forming the semiconductor structure further includes: forming an initial well region located within the substrate; the first well region and the drift region are located within the initial well region.
[0009] Optionally, the source region, drain region, and drift region have the same conductivity type.
[0010] Optionally, the drift region is doped with N-type conductive ions; the first well region is doped with P-type conductive ions.
[0011] Optionally, the method for forming the trench structure includes: forming a mask layer on the second dielectric layer, the mask layer having a mask opening, the projection pattern of the mask opening on the surface of the drift region being a third pattern, the third pattern partially overlapping with the second pattern; using the mask layer as a mask, etching the second dielectric layer until the top surface of the first conductive layer is exposed, forming a first trench on the first conductive layer; continuing to etch the second dielectric layer and the first dielectric layer below the first trench, forming a second trench below the first trench, the bottom of the second trench being higher than the surface of the drift region.
[0012] Optionally, the ratio of the depth of the second trench to the depth of the first trench is in the range of 1 / 5 to 1 / 2.
[0013] Optionally, the method for forming the semiconductor structure further includes: after forming the first dielectric layer and before forming the first conductive layer and the second dielectric layer, forming a source / drain contact layer located on the source region and the drain region.
[0014] Optionally, the method for forming the semiconductor structure further includes: forming a second conductive layer on the source / drain contact layer while forming the first conductive layer; and forming a via on the second conductive layer after forming the second dielectric layer.
[0015] Optionally, the through hole and the trench structure are formed simultaneously.
[0016] Optionally, before forming the first dielectric layer, the method for forming the semiconductor structure further includes forming an etch stop layer located on the substrate.
[0017] Optionally, after forming the gate structure, the method for forming the semiconductor structure further includes: forming a first sidewall and a second sidewall located on the sidewall of the gate structure, wherein the first sidewall is located on the surface of the first well region and the second sidewall is located on the surface of the drift region.
[0018] Optionally, the thickness of the first dielectric layer ranges from 5,000 angstroms to 8,000 angstroms; and the thickness of the second dielectric layer ranges from 7,000 angstroms to 10,000 angstroms.
[0019] Accordingly, the present invention also provides a semiconductor structure, comprising: a substrate; a first well region and a drift region located within the substrate, wherein the conductivity type of the first well region and the drift region are opposite; a gate structure, a source region located within the first well region, a drain region located within the drift region, and a first dielectric layer located on the substrate, wherein the gate structure is located on a portion of the first well region and the drift region, the first dielectric layer is located on the sidewalls and top of the gate structure, and the projection pattern of the gate structure on the surface of the drift region is a first pattern; a first conductive layer located on the first dielectric layer, and a second dielectric layer located on the surfaces of the first dielectric layer and the first conductive layer, wherein the projection pattern of the first conductive layer on the surface of the drift region is a second pattern, and the first pattern is within the range of the second pattern; a trench structure located within the first dielectric layer and the second dielectric layer, wherein the trench structure is located above the drift region, the trench structure includes a first trench and a second trench that are interconnected, the first trench being located within the second dielectric layer, the second trench being located within the first dielectric layer, the first trench exposing a portion of the top surface of the first conductive layer, and the bottom of the second trench being higher than the surface of the drift region; and a floating plug located within the trench structure.
[0020] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:
[0021] In the semiconductor structure formation method provided by the present invention, a first conductive layer is formed before forming the trench structure, and the projection pattern of the gate structure on the surface of the drift region is a first pattern, while the projection pattern of the first conductive layer on the surface of the drift region is a second pattern. Since the first pattern falls within the range of the second pattern, during the formation of the trench structure, the first conductive layer serves as an etching stop layer for the first trench in the trench structure, preventing the first trench from continuing to etch downwards and contacting the gate structure. Furthermore, the trench structure extends from the second dielectric layer to the first dielectric layer from top to bottom, thereby better controlling the distance between the bottom of the trench structure and the surface of the drift region, ensuring that the trench structure and the drift region are isolated from each other, thus improving the reliability of the floating plug within the trench structure, expanding the process window, and enhancing device performance.
[0022] In the semiconductor structure provided by the technical solution of the present invention, the presence of the first conductive layer avoids the possibility of the first trench contacting the gate structure. The trench structure extends from the second dielectric layer to the first dielectric layer from top to bottom, thereby enabling better control of the distance between the bottom of the trench structure and the surface of the drift region, ensuring that the trench structure and the drift region are isolated from each other, thereby improving the reliability of the floating plug in the trench structure, expanding the process window, and improving device performance. Attached Figure Description
[0023] Figures 1 to 3 This is a cross-sectional structural diagram illustrating the formation process of a semiconductor structure.
[0024] Figures 4 to 10 This is a cross-sectional structural schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention. Detailed Implementation
[0025] As described in the background section, under the existing technology, the reliability of the laterally diffused enhanced metal-oxide-semiconductor (LDEMOS) structure is poor, the process window is small, and the device performance is affected.
[0026] Figures 1 to 3 This is a cross-sectional schematic diagram of the formation process of a semiconductor structure.
[0027] Please refer to Figure 1 A substrate (not shown) is provided, the substrate including a base 100 and an initial well region 101 located on the base 100; a first well region 103 and a second well region 102 are formed in the initial well region 101, the first well region 103 and the second well region 102 having opposite conductivity types.
[0028] A gate 108 is formed on the substrate, a drain region 121 is formed in a first well region 103, a source region 122 is formed in a second well region 102, and a sidewall 107 is formed on the sidewall surface of the gate 108, wherein the gate 108 is located on a portion of the surface of the first well region 103 and the surface of the second well region 102.
[0029] In this embodiment, the semiconductor structure formation process further includes: forming a gate oxide layer 106 on the substrate surface, a metal contact layer (not shown) on the source region 122 and the drain region 121, and an etch stop layer 105 on the substrate surface.
[0030] Please refer to Figure 2 A first dielectric layer 109 is formed surrounding the gate 108; a source / drain contact layer 110 is formed on the surface of the source region 122 and the drain region 121; and a floating plug 130 is formed on the sidewall 107.
[0031] The method of forming the source / drain contact layer 110 and the floating plug 130 includes: etching the first dielectric layer 109 and the etching stop layer 105 on the source region 122 and the drain region 121 to form a first through-hole (not shown) on the source region 122 and the drain region 121, and a trench (not shown) on the sidewall 107, wherein the first through-hole exposes the metal contact layer; forming the source / drain contact layer 110 in the first through-hole, and forming the floating plug 130 in the trench.
[0032] Please refer to Figure 3 An electrical connection layer 111 is formed on the source / drain contact layer 110 and the floating plug 130; a second dielectric layer 112 is formed surrounding the electrical connection layer 111; and a conductive structure 113 is formed on the electrical connection layer 111.
[0033] The first through-hole located on the source region 122 and the drain region 121, and the trench located on the sidewall 107 are formed simultaneously. Because of the presence of a metal contact layer on the surfaces of the source region 122 and the drain region 121, during the etching of the etching stop layer 105 on the source region 122 and the drain region 121, the metal contact layer blocks the first through-hole from continuing to be etched downwards. However, during the formation of the trench, over-etching can easily occur, causing the etching stop layer 105 below the sidewall 107 to be etched through (e.g., ...). Figure 2 As shown at point A in the diagram, over-etching can easily cause the trench to contact the gate 108, leading to device failure. Therefore, the semiconductor structure formation method has a small process window, resulting in low reliability of the formed semiconductor structure.
[0034] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure. This method involves first forming a first conductive layer, followed by forming a trench structure. The trench structure includes a first trench and a second trench that are interconnected. The first trench is located above the first conductive layer, and the second trench is located below the first trench. The trench structure extends from a second dielectric layer into the first dielectric layer, and the bottom of the trench structure is higher than the surface of the drift region. The first conductive layer serves as an etch stop layer for the first trench, preventing the first trench from continuing to etch downwards and potentially contacting the gate structure. Furthermore, the trench structure extends from top to bottom from the second dielectric layer into the first dielectric layer, thereby allowing for better control of the distance between the bottom of the trench structure and the surface of the drift region. This ensures that the trench structure and the drift region are isolated from each other, thereby improving the reliability of the semiconductor structure, expanding the process window, and enhancing device performance.
[0035] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0036] Figures 4 to 10 This is a cross-sectional structural schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention.
[0037] Please refer to Figure 4 A substrate 200 is provided; an initial well region 201 is formed within the substrate 200; a first well region 202 and a drift region 203 are formed within the initial well region 201, wherein the first well region 202 and the drift region 203 have opposite conductivity types.
[0038] The substrate 200 is made of materials including silicon, silicon-germanium, silicon carbide, silicon-on-insulator (SOI), and germanium-on-insulator (GOI). Specifically, in this embodiment, the substrate 200 is made of silicon.
[0039] The drift region 203 is used to change the electric field distribution of the transistor to increase the breakdown voltage of the transistor and reduce leakage between the drain region, source region and gate structure formed subsequently.
[0040] Specifically, in this embodiment, the initial well region 201 is doped with N-type conductive ions; the drift region 203 is doped with N-type conductive ions; and the first well region 202 is doped with P-type conductive ions.
[0041] In this embodiment, the method for forming the initial well region 201 includes: forming a first patterned layer (not shown) on the substrate 200, wherein the first patterned layer exposes a portion of the surface of the substrate 200; and using the first patterned layer as a mask, performing N-type conductive ion implantation on the substrate 200 to form the initial well region 201 within the substrate 200.
[0042] Next, a gate structure, a source region in a first well region 202, a drain region in a drift region 203, and a first dielectric layer are formed on the substrate 200. The gate structure is located on a portion of the surface of the first well region 202 and the surface of the drift region 203, and the first dielectric layer is located on the sidewalls and top of the gate structure.
[0043] In this embodiment, the method for forming the gate structure, source region, drain region, and first dielectric layer is as follows: Figures 5 to 7 As shown.
[0044] Please refer to Figure 5 A gate dielectric layer 206 is formed on the substrate 200; a gate structure 208 is formed on the gate dielectric layer 206, the gate structure 208 being located on a portion of the first well region 202 and the drift region 203; a first sidewall 207 and a second sidewall 216 are formed on the sidewalls of the gate structure 208, the first sidewall 207 being located on the surface of the first well region 202 and the second sidewall 216 being located on the surface of the drift region 203.
[0045] The first sidewall 207 and the second sidewall 216 are used to protect the gate structure 208 and to ensure that there is a large spacing between the source region and the drain region formed subsequently.
[0046] In this embodiment, the material of the first sidewall 207 and the second sidewall 216 includes silicon nitride.
[0047] Since the materials of the first sidewall 207 and the second sidewall 216 include silicon nitride, while the material of the first dielectric layer is silicon oxide, in the subsequent process of forming the opening to accommodate the floating plug, i.e., the trench structure, by selecting a gas with a high selectivity ratio for etching silicon oxide and silicon nitride, the etching of the second sidewall 216 is reduced on the basis of etching the first dielectric layer, thereby reducing the probability that the subsequently formed floating plug is connected to the gate structure 208.
[0048] Please refer to Figure 6 A source region 222 is formed within the first well region 202, and a drain region 221 is formed within the drift region 203. The source region 222 and the drain region 221 are located on both sides of the first sidewall 207 and the second sidewall 216. A metal silicide layer (not shown) is formed on the surface of the source region 222 and the drain region 221. After forming the metal silicide layer, an etch stop layer 205 is formed on the substrate 200. The etch stop layer 205 covers the first well region 202, the drift region 203, and the initial well region 201.
[0049] In this embodiment, the first well region 202 covered by the gate structure 208 is the channel region of the transistor.
[0050] The function of the metal silicide layer is to reduce the contact resistance between the source / drain contact layer subsequently formed on the source region 222 and the drain region 221 and the source region 222 and the drain region 221.
[0051] Specifically, the material of the metal silicide layer includes NiSi, CoSi, or TiSi.
[0052] The function of the etching stop layer 205 is to protect the drift region 203 from damage during the subsequent formation of the trench structure located on the drift region 203.
[0053] Specifically, the material of the etch stop layer 205 includes silicon nitride.
[0054] In this embodiment, the source region 222, the drain region 221, and the drift region 203 have the same conductivity type.
[0055] Please refer to Figure 7 A first dielectric layer 209 is formed on the sidewalls and top of the gate structure 208; a source / drain contact layer 210 is formed within the first dielectric layer 209 on the source region 222 and the drain region 221.
[0056] The first dielectric layer 209 also covers the surfaces of the first sidewall 207, the second sidewall 216, and the etching stop layer 205.
[0057] In this embodiment, the source-drain contact layer 210 serves to electrically connect the source region 222, the drain region 221, and the subsequently formed second conductive layer.
[0058] Specifically, the method for forming the source / drain contact layer 210 includes: etching the first dielectric layer 209 and the etching stop layer 205; forming source / drain vias (not shown) in the first dielectric layer 209 that expose the surfaces of the source region 222 and the drain region 221 by a metal silicide layer; forming a source / drain contact material layer (not shown) in the source / drain vias; and planarizing the source / drain contact material layer until the surface of the first dielectric layer 209 is exposed to form the source / drain contact layer 210, wherein the source / drain contact layer 210 is connected to the source region 222 and the drain region 221 through the metal silicide layer.
[0059] During the etching of the first dielectric layer 209, the metal silicide layer also serves as an etching stop layer for the formation of the source and drain vias, thereby protecting the source region 222 and the drain region 221 from etching damage.
[0060] In this embodiment, the material of the first dielectric layer 209 includes silicon oxide.
[0061] In this embodiment, the thickness of the first dielectric layer 209 ranges from 5000 angstroms to 8000 angstroms.
[0062] In this embodiment, the source / drain contact layer 210 is made of tungsten.
[0063] Please refer to Figure 8 A first conductive layer 211 is formed on the first dielectric layer 209, and a second dielectric layer 213 is formed on the surfaces of the first dielectric layer 209 and the first conductive layer 211.
[0064] The projection pattern of the gate structure 208 on the surface of the drift region 203 is a first pattern, and the projection pattern of the first conductive layer 211 on the surface of the drift region 203 is a second pattern, with the first pattern falling within the range of the second pattern.
[0065] Because of the presence of the first conductive layer 211 and the fact that the first pattern is within the range of the second pattern, during the subsequent formation of the trench structure, the first conductive layer 211 serves as the etching stop layer for the first trench in the trench structure, preventing the first trench from continuing to be etched downwards and coming into contact with the gate structure 208. This protects the gate structure 208 from damage and prevents the subsequently formed floating plug from coming into contact with the gate structure 208, thus causing a short circuit in the transistor and improving the stability of the device.
[0066] In this embodiment, while forming the first conductive layer 211, a second conductive layer 212 is also formed on the source / drain contact layer 210.
[0067] The first conductive layer 211 and the second conductive layer 212 serve as electrical interconnect layers for semiconductor devices.
[0068] The first conductive layer 211 and the second conductive layer 212 are made of metal. Specifically, in this embodiment, the materials of the first conductive layer 211 and the second conductive layer 212 include copper.
[0069] In this embodiment, the first conductive layer 211 and the second conductive layer 212 are formed simultaneously. Specifically, the method for forming the first conductive layer 211 and the second conductive layer 212 includes: forming an initial conductive material layer (not shown) on the first dielectric layer 209 and the source / drain contact layer 210; and patterning the initial conductive material layer to form a second conductive layer 212 on each source / drain contact layer 210 and a first conductive layer 211 between each second conductive layer 212.
[0070] In this embodiment, after the first conductive layer 211 and the second conductive layer 212 are formed, a second dielectric layer 213 is formed on the surface of the first dielectric layer 209, the first conductive layer 211 and the second conductive layer 212.
[0071] The second dielectric layer 213 provides space for the subsequently formed source / drain upper plug and floating plug.
[0072] In this embodiment, the material of the second dielectric layer 213 is the same as that of the first dielectric layer 209, so that in the subsequent process of forming the trench structure, the second dielectric layer 213 and the first dielectric layer 209 can be continuously etched from top to bottom to form the trench structure.
[0073] Specifically, the material of the second dielectric layer 213 is silicon oxide. The thickness of the second dielectric layer 213 ranges from 7000 angstroms to 10000 angstroms.
[0074] Please refer to Figure 9 A trench structure 230 is formed in the first dielectric layer 209 and the second dielectric layer 213 on the drift region 203. The trench structure 230 includes a first trench 231 and a second trench 232 that are interconnected. The first trench 231 is located in the second dielectric layer 213 and the second trench 232 is located in the first dielectric layer 209. The first trench 231 exposes part of the top surface of the first conductive layer 211 and the bottom of the second trench 232 is higher than the surface of the drift region 203.
[0075] In this embodiment, the method for forming the trench structure 230 includes: forming a mask layer (not shown) on the second dielectric layer 213, the mask layer having a mask opening, the projection pattern of the mask opening on the surface of the drift region 203 being a third pattern, the third pattern partially overlapping with the second pattern; using the mask layer as a mask, etching the second dielectric layer 213 until the top surface of the first conductive layer 211 is exposed, forming a first trench 231 on the first conductive layer 211; continuing to etch the second dielectric layer 213 and the first dielectric layer 209 under the first trench 231, forming a second trench 232 under the first trench 231, the bottom of the second trench 232 being higher than the surface of the drift region 203.
[0076] During the etching of the second dielectric layer 213, the first conductive layer 211 serves as an etching stop layer, causing the etching process of the first trench 231 to stop on the first conductive layer 211. This avoids the possibility that the first trench 231 will continue to be etched downwards and come into contact with the gate structure 208, thus protecting the integrity of the gate structure 208.
[0077] After the first trench 231 is formed, the second dielectric layer 213 and the first dielectric layer 209 under the first trench 231 are etched using the over-etching stage of the etching process of the first trench 231 to form the second trench 232 located under the first trench 231. Since the first dielectric layer 209 and the second dielectric layer 213 are made of the same material, this over-etching stage can continue within the first dielectric layer 209 and the second dielectric layer 213 until the second trench 232 is formed.
[0078] In this embodiment, the bottom of the second trench 232 is higher than the surface of the etch stop layer 205. Since the trench structure 230 extends from the second dielectric layer 213 to the first dielectric layer 209 from top to bottom, the distance between the bottom of the trench structure 230 and the surface of the drift region 203 can be better controlled, ensuring that the trench structure 230 and the drift region 203 are isolated from each other. This avoids the subsequent connection between the floating plug formed in the second trench 232 and the drift region 203, thus expanding the process window and improving device performance.
[0079] In this embodiment, by adjusting the thickness of the first dielectric layer 209 and adjusting the etching rate of the etching process of the first trench 231, the amount of etching in the over-etching stage is controlled, so that the depth of the second trench 232 meets the design requirements.
[0080] In this embodiment, the ratio of the depth of the second trench 232 to the depth of the first trench 231 is in the range of 1 / 5 to 1 / 2.
[0081] In another embodiment, the second trench exposes the surface of the etch stop layer. Since the material of the first dielectric layer is different from the material of the etch stop layer, during the formation of the second trench, a gas with a high selectivity for both materials is selected, causing the etching process of the second trench to stop at the etch stop layer. This prevents the subsequent formation of a suspended plug within the second trench from connecting with the drift region.
[0082] In this embodiment, the etching process of the second dielectric layer 213 includes a dry etching process.
[0083] In this embodiment, while forming the trench structure 230, a through-hole 233 is formed within the second dielectric layer 213 on the second conductive layer 212 by etching the second dielectric layer 213. The through-hole 233 is used to accommodate the subsequently formed source / drain upper layer plugs.
[0084] Please refer to Figure 10 This forms a suspended plug 240 located within the trench structure 230 and a source / drain upper plug 241 located within the through hole 233.
[0085] The floating plug 240 and the source / drain upper plug 241 are used to connect the first conductive layer 211, the second conductive layer 212 and the upper electrical interconnect layer subsequently formed on the second dielectric layer 213, thereby connecting the transistor to other parts of the integrated circuit so that the transistor can function.
[0086] When a voltage is applied to the floating plug 240, a depletion region, i.e. a high-resistivity region, is formed in the drift region 203 at the bottom of the floating plug 240. The first well region 202 covered by the gate structure 208 is the channel region of the transistor. When a voltage is applied to the source-drain contact layer 210, the trajectory of the charge carriers is as follows: from the drain region 221 to the drift region 203, within the drift region 203, they need to bypass the space charge region to reach the channel region, and then reach the source region 222, thereby avoiding the hot carrier effect and increasing the breakdown voltage of the transistor.
[0087] Since the bottom of the trench structure 230 is higher than the surface of the drift region 203, it ensures that there is no contact between the floating plug 240 and the drift region 203. Consequently, when a voltage is applied to the floating plug 240, a depletion region can be formed in the drift region 203 at the bottom of the floating plug 240, thereby increasing the breakdown voltage of the transistor.
[0088] In this embodiment, the materials of the floating plug 240 and the source / drain upper plug 241 include tungsten. The formation process of the floating plug 240 and the source / drain upper plug 241 includes chemical vapor deposition or selective tungsten deposition.
[0089] The semiconductor structure formed in this embodiment can be applied to laterally diffused enhanced metal-oxide-semiconductor devices (LDEMOS).
[0090] Accordingly, embodiments of the present invention also provide a semiconductor structure formed using the above method.
[0091] Please continue to refer to this. Figure 10The semiconductor structure includes: a substrate 200; a first well region 202 and a drift region 203 located within the substrate 200, wherein the first well region 202 and the drift region 203 have opposite conductivity types; a gate structure 208 located on the substrate 200; a source region 222 located within the first well region 202; a drain region 221 located within the drift region 203; and a first dielectric layer 209, wherein the gate structure 208 is located on a portion of the first well region 202 and the drift region 203, and the first dielectric layer 209 is located on the gate... The sidewalls and top of the gate structure 208, the projection pattern of the gate structure 208 on the surface of the drift region 203 is a first pattern; the first conductive layer 211 located on the first dielectric layer 209, and the second dielectric layer 213 located on the surfaces of the first dielectric layer 209 and the first conductive layer 211, the projection pattern of the first conductive layer 211 on the surface of the drift region 203 is a second pattern, the first pattern is within the range of the second pattern; the trench structure 230 located in the first dielectric layer 209 and the second dielectric layer 213 (e.g., Figure 9 As shown, the trench structure 230 is located above the drift region 203. The trench structure 230 includes a first trench 231 and a second trench 232 that are interconnected. The first trench 231 is located within the second dielectric layer 213, and the second trench 232 is located within the first dielectric layer 209. The first trench 231 exposes part of the top surface of the first conductive layer 211, and the bottom of the second trench 232 is higher than the surface of the drift region 203. A floating plug 240 is located within the trench structure 230.
[0092] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A first well region and a drift region are formed within the substrate, wherein the first well region has the opposite conductivity type to the drift region; A gate structure, a source region located in a first well region, a drain region located in a drift region, and a first dielectric layer are formed on the substrate. The gate structure is located on a portion of the first well region and the drift region. The first dielectric layer is located on the sidewalls and top of the gate structure. The projection pattern of the gate structure on the surface of the drift region is a first pattern. A first conductive layer is formed on the first dielectric layer, and a second dielectric layer is formed on the surface of the first dielectric layer and the first conductive layer. The projection pattern of the first conductive layer on the surface of the drift region is the second pattern, and the first pattern is within the range of the second pattern. A trench structure is formed in the first dielectric layer and the second dielectric layer on the drift region. The trench structure includes a first trench and a second trench that are interconnected. The first trench is located in the second dielectric layer and the second trench is located in the first dielectric layer. The first trench exposes part of the top surface of the first conductive layer, and the bottom of the second trench is higher than the surface of the drift region. A suspended plug is formed within the trench structure.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: An initial well region is formed within the substrate; The first well region and the drift region are located within the initial well region.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The source region, drain region, and drift region have the same conductivity type.
4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The drift region is doped with N-type conductive ions; the first well region is doped with P-type conductive ions.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the trench structure includes: forming a mask layer on the second dielectric layer, the mask layer having a mask opening, the projection pattern of the mask opening on the surface of the drift region being a third pattern, the third pattern partially overlapping with the second pattern; using the mask layer as a mask, etching the second dielectric layer until the top surface of the first conductive layer is exposed, forming a first trench on the first conductive layer; continuing to etch the second dielectric layer and the first dielectric layer below the first trench, forming a second trench below the first trench, the bottom of the second trench being higher than the surface of the drift region.
6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The ratio of the depth of the second trench to the depth of the first trench is in the range of 1 / 5 to 1 / 2.
7. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: After the first dielectric layer is formed and before the first conductive layer and the second dielectric layer are formed, a source-drain contact layer is formed on the source region and the drain region.
8. The method for forming a semiconductor structure as described in claim 7, characterized in that, Also includes: While forming the first conductive layer, a second conductive layer is formed on the source / drain contact layer; After the second dielectric layer is formed, a via is formed on the second conductive layer.
9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The through hole and the groove structure are formed simultaneously.
10. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming the first dielectric layer, the method further includes forming an etch stop layer located on the substrate.
11. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the gate structure, the method further includes forming a first sidewall and a second sidewall located on the sidewall of the gate structure, wherein the first sidewall is located on the surface of the first well region and the second sidewall is located on the surface of the drift region.
12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the first dielectric layer ranges from 5,000 angstroms to 8,000 angstroms; the thickness of the second dielectric layer ranges from 7,000 angstroms to 10,000 angstroms.
13. A semiconductor structure, characterized in that, include: Substrate; A first well region and a drift region are located within the substrate, wherein the first well region has the opposite conductivity type to the drift region; The substrate includes a gate structure, a source region located in a first well region, a drain region located in a drift region, and a first dielectric layer. The gate structure is located on a portion of the first well region and the drift region. The first dielectric layer is located on the sidewalls and top of the gate structure. The projection pattern of the gate structure on the surface of the drift region is a first pattern. A first conductive layer located on the first dielectric layer, and a second dielectric layer located on the surface of the first dielectric layer and the first conductive layer, wherein the projection pattern of the first conductive layer on the surface of the drift region is the second pattern, and the first pattern is within the range of the second pattern; A trench structure located within the first dielectric layer and the second dielectric layer, the trench structure being located above the drift region, the trench structure including a first trench and a second trench that are interconnected, the first trench being located within the second dielectric layer, the second trench being located within the first dielectric layer, the first trench exposing a portion of the top surface of the first conductive layer, and the bottom of the second trench being higher than the surface of the drift region; A suspended plug located within the trench structure.