Method of manufacturing double-gate sgt semiconductor device

Abstract

The application discloses a manufacturing method of a double-gate SGT semiconductor device, which comprises the following steps: step one, forming one or more first grooves in a selected area of a semiconductor substrate, and forming a gate dielectric layer and a gate conductive material layer in the first grooves; step two, forming a body region; step three, forming a source region; step four, forming an interlayer film; and step five, forming a shielding gate, which comprises the following steps: step 51, etching the interlayer film and the semiconductor substrate in a forming area of a second groove in sequence to form the second groove, and the second groove is located on both sides of each first groove; the depth of the second groove in the semiconductor substrate is greater than the depth of the first groove; step 52, forming a shielding dielectric layer on the inner side surface of the second groove; and step 53, filling metal in the second groove to form a shielding gate field plate. The application can manufacture the double-gate SGT under the condition of good control of the number of masks and process simplification, and can reduce the process difficulty and increase the process controllability.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a method for manufacturing the inter-gate dielectric layer of a dual-gate shielded gate trench (SGT) semiconductor device. Background Technology

[0002] SGT MOSFET is a new type of power semiconductor device that not only has lower conduction losses than traditional deep trench MOSFETs, but also lower switching losses. It has a significant cost advantage in high-performance applications and is currently the most advanced core technology for medium and low voltage (less than 100V to 250V) MOSFETs.

[0003] SGT MOSFETs have two polysilicon gates. The lower gate, also known as the source polysilicon gate, is used to help deplete the charge in the breakdown region during reverse breakdown. The upper gate, also known as the conventional polysilicon gate, is used to control the switching of the device.

[0004] In SGT semiconductor devices such as SGT MOSFETs, the most crucial process step is the isolation between the two polysilicon gates in the gate trench—the polysilicon shield gate and the polysilicon gate itself. This isolation is typically achieved using an oxide layer, known as the inter-polysilicon oxide (IPO). The polysilicon shield gate connects to the source, which is composed of a front-side metal layer; hence, the polysilicon shield gate is also called the source polysilicon. The polysilicon gate connects to the gate, which is also composed of a front-side metal layer. The thickness and stability of the IPO not only affect the isolation effect between the gate and source but also the input capacitance, making it critical for the SGT process.

[0005] Currently, there are two main IPO production methods in the industry: thermal oxidation process for IPO formation and high-density plasma (HDP) chemical vapor deposition (CVD) process for IPO deposition.

[0006] In the thermal oxidation process for forming the IPO, after the bottom source polysilicon is formed, heavy ion implantation is performed to further create defects on the surface of the source polysilicon. Meanwhile, the semiconductor material, such as silicon, in the sidewall channel region of the gate trench (Mesa) remains in a relatively good single-crystal structure. Then, a thermal oxidation process is performed to form the IPO on top of the source polysilicon, while a gate oxide layer (GOX) is formed on the sidewall of the gate trench. Taking advantage of the numerous defects on the surface of the source polysilicon, the thickness of the IPO is made greater than the thickness of the gate oxide layer. This process is simple in steps but quite difficult. Furthermore, the IPO to GOX thickness ratio is fixed, limiting the adjustable thickness range and making it unsuitable for thin gate oxide products. Additionally, a significant thinning of the IPO is likely to occur at the polycorner of the source polysilicon.

[0007] In HDP CVD deposition of the IPO (Initial Gate Isolation), an oxide layer is formed to completely fill the gate trench using HDP CVD, and then the oxide layer is etched back to form the IPO of the desired thickness. This process allows for a wide adjustable range of IPO thickness, unaffected by the thickness of the gate oxide layer. However, the process is complex and costly. Furthermore, it is limited by the filling capacity of HDP, making it difficult to achieve an aspect ratio greater than 3. The IPO thickness depends on the oxide layer etch-back, resulting in significant fluctuations. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a method for manufacturing a dual-gate SGT semiconductor device, which can effectively control the number of photomask layers and fabricate dual-gate SGTs under simplified process conditions, thereby reducing process difficulty and increasing process controllability.

[0009] To solve the above-mentioned technical problems, the manufacturing method of the dual-gate SGT semiconductor device provided by the present invention includes the following steps:

[0010] Step 1: Form one or more first trenches with a first depth in a selected area of ​​a semiconductor substrate, form a gate dielectric layer on the inner surface of the first trench, and then fill the first trench with a gate conductive material layer; the gate dielectric layer and the gate conductive material layer filled in the first trench constitute a trench gate.

[0011] Step 2: Perform second conductivity type ion implantation in the selected area and advance to form a second conductivity type doped body region, through which the first trench passes.

[0012] Step 3: Implant heavily doped ions of the first conductivity type into the selected area and advance to form a source region, wherein the second side of the source region is self-aligned with the side of the first trench.

[0013] Step 4: Form an interlayer film that covers the surface of the semiconductor substrate on which the trench gate, the body region and the source region are formed.

[0014] Step 5: Forming the shielding barrier, including:

[0015] Step 51: Define the formation region of the second trench, and sequentially etch the interlayer film and the semiconductor substrate in the formation region of the second trench to form the second trench. The second trench is located on both sides of each of the first trenches. The depth of the second trench in the semiconductor substrate is the second depth, which is greater than the first depth.

[0016] Step 52: Form a shielding medium layer on the inner surface of the second trench.

[0017] Step 53: Fill the second trench with metal to form a shielding grid plate.

[0018] The shielding gate is composed of the shielding dielectric layer filled in the second trench and the shielding gate field plate; during reverse breakdown voltage, the shielding gate field plate is used to deplete the drift region of the first conductivity type doped in the semiconductor substrate between the shielding gate field plates to improve the device breakdown voltage.

[0019] A further improvement is to place step two before or after step one.

[0020] A further improvement is to place step three before or after step one, and step three before or after step two.

[0021] A further improvement is that, in step one, a first epitaxial layer doped with a first conductivity type is formed on the surface of the semiconductor substrate, the first trench and the second trench are both located in the first epitaxial layer, and the drift region is composed of the first epitaxial layer located at the bottom of the body region.

[0022] A further improvement is that the material of the shielding dielectric layer is an oxide layer.

[0023] A further improvement is that, in step 52, the shielding medium layer extends onto the surface of the interlayer film outside the second trench.

[0024] In step 53, the metal of the shielding grid plate extends further to the surface of the shielding medium layer outside the second trench.

[0025] Following that, it also includes:

[0026] Remove the metal from the shielding grid plate on the surface of the shielding medium layer outside the second trench and make the top surface of the shielding grid plate in the second trench region flush with the top surface of the shielding medium layer outside the second trench, while retaining the shielding medium layer outside the second trench.

[0027] A further improvement is made in step 51:

[0028] Before defining the formation region of the second trench, a protective layer is also formed on the surface of the interlayer film;

[0029] In the etching of the second trench, the protective layer is etched first, and then the interlayer film and the semiconductor substrate are etched.

[0030] The photoresist pattern formed by photolithography defines the formation area of ​​the second trench; the second trench is etched using the photoresist pattern as a mask, or the photoresist pattern is transferred into the protective layer and then the patterned protective layer is used as a mask to etch the second trench.

[0031] In step 52, the shielding medium layer extends further onto the surface of the protective layer outside the second trench; then, the shielding medium layer outside the second trench and the protective layer are removed.

[0032] In step 53, the metal of the shielding grid plate extends further to the surface of the interlayer membrane outside the second trench.

[0033] Following that, it also includes:

[0034] Remove the metal from the shielding grid plate outside the second trench and make the top surface of the shielding grid plate in the second trench region flush with the top surface of the interlayer membrane.

[0035] A further improvement is that the protective layer is a first nitride layer or a superposition of a first nitride layer and a second oxide layer.

[0036] A further improvement is that, in step 53, the metal material of the shielding grid plate includes W, Ti, TiN, or Al.

[0037] A further improvement is that, in step one, the gate dielectric layer is made of an oxide layer and formed using a thermal oxidation process.

[0038] A further improvement is that, in step one, the material of the gate conductive material layer is polycrystalline silicon.

[0039] A further improvement is that, after step five, it also includes:

[0040] Contact holes are formed in selected areas, the contact holes passing through the interlayer film, and corresponding contact holes are formed on top of the source region and the gate conductive material layer.

[0041] A front metal layer is formed, and the front metal layer is patterned and etched to form a source and a gate. The source region is connected to the source through the corresponding contact hole at the top, and the gate conductive material layer is connected to the gate through the corresponding contact hole at the top. The top of the shielding gate field plate is connected to the source.

[0042] Forming a contact pad.

[0043] Complete the back side process.

[0044] A further improvement is that the back-side process includes:

[0045] The semiconductor substrate is thinned on the back side.

[0046] The semiconductor substrate is heavily doped with a first conductivity type, and the thinned semiconductor substrate is directly used as the drain region of the first conductivity type heavy doping; or the thinned semiconductor substrate is implanted with a backside of the first conductivity type heavy doping to form the drain region.

[0047] A back metal layer is formed on the back side of the leak area.

[0048] A further improvement is that the semiconductor substrate comprises a silicon substrate.

[0049] A further improvement is that the process flow of the dual-gate SGT semiconductor device uses 7 photomasks, which are used to define the formation areas of the first trench, the body region, the source region, the second trench, the contact hole, the front metal layer pattern, and the contact pad.

[0050] A further improvement is that the dual-gate SGT semiconductor device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; or, the dual-gate SGT semiconductor device is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0051] Compared to existing SGT gate structures that use a stacked structure formed in the same gate trench, this invention separates the gate conductive material layer and the shielding gate field plate in the first and second trenches of the SGT. This simplifies the formation process of the entire SGT gate structure. Furthermore, this invention places the formation process of the second trench after the interlayer film formation. Thus, the metal from the back-end process (BEOL) after the interlayer film can be used to fill the second trench and serve as the shielding gate field plate. Compared to filling polysilicon as the shielding gate field plate in the front-end process, this invention further simplifies the formation process of the shielding gate field plate. Therefore, this invention simplifies the formation process of the SGT gate structure, namely the shielding gate and the trench gate, reduces process difficulty, and increases process controllability.

[0052] Although the first and second trenches of the present invention need to be defined by two photomasks, the present invention can control the overall number of photomask layers of the device, such as using 7 photomasks. Compared with the existing process of forming the polysilicon inter-oxide layer of SGT by using HDP oxide layer plus etch-back when using the same gate trench, the number of photomask layers of the present invention will not increase, which is beneficial to further control the process cost.

[0053] Since the SGT gate structure of the present invention is composed of a gate dielectric layer and a gate conductive material layer formed in the first trench and a shielding dielectric layer and a shielding gate field plate formed in the second trench, it is not necessary to set an isolation oxide layer between the gate conductive material layer and the shielding gate field plate. Therefore, the defect of increased process complexity caused by this is eliminated, thereby reducing process difficulty and increasing process controllability. Attached Figure Description

[0054] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0055] Figure 1 This is a flowchart of a method for manufacturing a dual-gate SGT semiconductor device according to an embodiment of the present invention;

[0056] Figure 2 This is a flowchart showing the manufacturing method of the dual-gate SGT semiconductor device according to the photomask sequence in an embodiment of the present invention;

[0057] Figures 3A-3F This is a schematic diagram of the cross-sectional structure of the device in each step of the manufacturing method of the dual-gate SGT semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0058] like Figure 1 The diagram shown is a flowchart of a method for manufacturing a dual-gate SGT semiconductor device according to an embodiment of the present invention; as shown Figures 3A to 3FThe diagram shown is a schematic cross-sectional view of the device structure in each step of the manufacturing method of the dual-gate SGT semiconductor device according to an embodiment of the present invention. The manufacturing method of the dual-gate SGT semiconductor device according to an embodiment of the present invention includes the following steps:

[0059] Step 1, such as Figure 3A As shown, one or more first trenches 103 with a first depth are formed in a selected area of ​​semiconductor substrate 101, a gate dielectric layer 104 is formed on the inner surface of the first trench 103, and then a gate conductive material layer 105 is filled in the first trench 103; the gate dielectric layer 104 and the gate conductive material layer 105 filled in the first trench 103 constitute a trench gate.

[0060] In this embodiment of the invention, a first epitaxial layer 102 doped with a first conductivity type is also formed on the surface of the semiconductor substrate 101. The first trench 103 and the second trench 110 are both located in the first epitaxial layer 102. The drift region is composed of the first epitaxial layer 102 located at the bottom of the body region 106.

[0061] The semiconductor substrate 101 includes a silicon substrate. The first epitaxial layer 102 includes a silicon epitaxial layer.

[0062] In this embodiment of the invention, the gate dielectric layer 104 is made of an oxide layer and is formed by a thermal oxidation process.

[0063] The gate conductive material layer 105 is made of polycrystalline silicon.

[0064] Step 2, as follows Figure 3A As shown, second conductivity type ion implantation is performed in a selected region to advance and form a second conductivity type doped body region 106, through which the first trench 103 passes.

[0065] In this embodiment of the invention, step two is placed after step one. In other embodiments, step two can also be placed before step one.

[0066] Step 3, as follows Figure 3A As shown, a first conductivity type of heavily doped ions are implanted in a selected region to advance and form a source region 107, wherein the second side of the source region 107 is self-aligned with the side of the first trench 103.

[0067] In this embodiment of the invention, step three is placed after step one and after step two; in other embodiments, step three may also be placed before step one and before step two; or, step three may be placed after step one and before step two.

[0068] In this embodiment of the invention, the method further includes the step of implanting heavily doped ions of a second conductivity type to form a body contact region 108, wherein the body contact region 108 is located outside the first side of the source region 107.

[0069] Step 4, as follows Figure 3B As shown, an interlayer film 109 is formed, which covers the surface of the semiconductor substrate 101 on which the trench gate, the body region 106 and the source region 107 are formed.

[0070] Step 5: Forming the shielding barrier, including:

[0071] Step 51, as follows Figure 3C As shown, the formation region of the second trench 110 is defined, and the interlayer film 109 and the semiconductor substrate 101 in the formation region of the second trench 110 are etched sequentially to form the second trench 110. The second trench 110 is located on both sides of each of the first trenches 103. The depth of the second trench 110 in the semiconductor substrate 101 is the second depth, which is greater than the first depth.

[0072] In this embodiment of the invention, in step 51:

[0073] like Figure 3B As shown, before defining the formation region of the second trench 110, a protective layer is also formed on the surface of the interlayer film 109. In some embodiments, the protective layer is a first nitride layer 201. In other embodiments, the protective layer may also be a superposition of a first nitride layer 201 and a second oxide layer (not shown).

[0074] like Figure 3C As shown, in the etching of the second trench 110, the protective layer is etched first, and then the interlayer film 109 and the semiconductor substrate 101 are etched.

[0075] In some embodiments, a photoresist pattern formed by photolithography defines the formation area of ​​the second trench 110; the photoresist pattern is used as a mask for etching (with PR) to form the second trench 110, and then the photoresist pattern is removed. In other embodiments, the photoresist pattern formed by photolithography defines the formation area of ​​the second trench 110, the photoresist pattern is then transferred to the protective layer, and then the patterned protective layer is used as a mask for etching (without PR) to form the second trench 110. Since the second depth is relatively deep, the protective layer needs to be relatively thick after removing the photoresist pattern. In this case, the protective layer needs to be a superposition of a first nitride layer 201 and a second oxide layer; after etching to form the second trench 110, the second oxide layer is removed.

[0076] Step 52, as follows Figure 3D As shown, a shielding medium layer 111 is formed on the inner surface of the second trench 110.

[0077] In this embodiment of the invention, the material of the shielding medium layer 111 is an oxide layer.

[0078] The shielding medium layer 111 extends beyond the surface of the protective layer outside the second trench 110, i.e., the surface of the first nitrided layer 201; then, the shielding medium layer 111 outside the second trench 110 and the protective layer are removed.

[0079] Step 53, as follows Figure 3E As shown, metal is filled in the second trench 110 to form a shielding grid plate 112.

[0080] In this embodiment of the invention, the metal of the shielding grid plate 112 further extends to the surface of the interlayer film 109 outside the second trench 110. Subsequently, it also includes:

[0081] Remove the metal from the shielding grid plate 112 outside the second trench 110 and make the top surface of the shielding grid plate 112 in the region of the second trench 110 flush with the top surface of the interlayer membrane 109.

[0082] The shielding gate is composed of the shielding dielectric layer 111 filled in the second trench 110 and the shielding gate field plate 112; during reverse breakdown voltage, the shielding gate field plate 112 is used to deplete the drift region formed in the semiconductor substrate 101 between the shielding gate field plates 112, which is doped with a first conductivity type, in order to improve the device breakdown voltage.

[0083] In this embodiment of the invention, the metal material of the shielding grid plate 112 includes W, Ti, TiN or Al, which can be achieved by subsequent processes.

[0084] In other embodiments, the protective layer may not be used in step 51.

[0085] In step 52, the shielding medium layer 111 extends further onto the surface of the interlayer film 109 outside the second trench 110.

[0086] In step 53, the metal of the shielding grid plate 112 further extends to the surface of the shielding dielectric layer 111 outside the second trench 110. This is followed by:

[0087] Remove the metal of the shielding grid plate 112 on the surface of the shielding medium layer 111 outside the second trench 110 and make the top surface of the shielding grid plate 112 in the region of the second trench 110 and the top surface of the shielding medium layer 111 outside the second trench 110 flat, while the shielding medium layer 111 outside the second trench 110 is retained.

[0088] In this embodiment of the invention, after step five, the method further includes:

[0089] like Figure 3F As shown, a contact hole 113 is formed in a selected area, the contact hole 113 passing through the interlayer film 109, and the corresponding contact hole 113 is formed on the top of the source region 107 and the gate conductive material layer 105.

[0090] A front metal layer 114 is formed, and the front metal layer 114 is patterned and etched to form a source and a gate. The source region 107 is connected to the source through the corresponding contact hole 113 at the top, and the gate conductive material layer 105 is connected to the gate through the corresponding contact hole 113 at the top. The top of the shielding gate field plate 112 is connected to the source.

[0091] Forming a contact pad.

[0092] Complete the back side process.

[0093] The back-side process includes:

[0094] The semiconductor substrate 101 is thinned on the back side.

[0095] The semiconductor substrate 101 is heavily doped with a first conductivity type, and the thinned semiconductor substrate 101 is directly used as the drain region of the first conductivity type heavy doping; or the thinned semiconductor substrate 101 is implanted with the back side of the first conductivity type heavy doping to form the drain region.

[0096] A back metal layer is formed on the back side of the leak area.

[0097] In this embodiment of the invention, the dual-gate SGT semiconductor device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type. In other embodiments, the dual-gate SGT semiconductor device can also be a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0098] Figure 3 shows a flowchart of the manufacturing method of the dual-gate SGT semiconductor device according to the photomask sequence in an embodiment of the present invention. In this embodiment, the process flow of the dual-gate SGT semiconductor device uses 7 photomasks, which are used to define the formation areas of the first trench 103, the body region 106, the source region 107, the second trench 110, the contact hole 113, the front metal layer 114 pattern, and the contact pad. The details are explained below according to the photomask layers:

[0099] The first photolithography process involves etching the gate trench to form a sacrificial oxide layer, a gate oxide layer, and a polysilicon gate. The gate trench is the first trench. This first photolithography process corresponds to step one.

[0100] The second photolithography process involves volume injection and drive. The second photomask process corresponds to step two.

[0101] The third photolithography process involves the injection and advancement of the source region. The third photomask process corresponds to step three.

[0102] The fourth photolithography process involves interlayer film deposition, second trench etching, deposition of the shielding dielectric layer and shielding gate plate, and etch-back. The fourth photomask process corresponds to step five.

[0103] The fifth photolithography process involves contact hole etching, body region implantation and push-in, and filling with tungsten pins. This fifth photomask process corresponds to the formation of contact hole 112. After the opening of contact hole 112 is opened, body region implantation is typically performed. For N-type devices, the body region implantation is P+ implantation, followed by push-in of the P+ implanted ions. Then, a metal layer is filled into the opening of contact hole 112 to form the contact hole 112. The filling metal layer is typically tungsten, hence the name tungsten pin.

[0104] The sixth photolithography process involves the deposition and etching of the front metal layer. This sixth photolithography process corresponds to the formation and patterning etching of the front metal layer 113.

[0105] The seventh layer of photolithography involves the deposition and etching of the contact pads (CP); the back side process.

[0106] Compared to existing SGT gate structures that use a stacked structure formed in the same gate trench, this embodiment of the invention separately forms the gate conductive material layer 105 and the shielding gate field plate 112 in the first trench 103 and the second trench 110. This simplifies the formation process of the entire SGT gate structure. Moreover, this embodiment places the formation process of the second trench 110 after the formation of the interlayer film 109. In this way, the metal of the back-end process (BEOL) after the interlayer film 109 can be used to fill the second trench 110 and serve as the shielding gate field plate 112. Compared to filling polysilicon as the shielding gate field plate 112 in the front-end process, this embodiment of the invention can further simplify the formation process of the shielding gate field plate 112. Therefore, this embodiment of the invention can simplify the formation process of the SGT gate structure, namely the shielding gate and the trench gate, reduce the process difficulty, and increase the process controllability.

[0107] Although the first trench 103 and the second trench 110 in this embodiment of the invention need to be defined by two photomasks, this embodiment of the invention can control the overall number of photomask layers of the device, such as using 7 photomasks. Compared with the existing process of forming the polysilicon inter-oxide layer of SGT by using HDP oxide layer plus etch-back when using the same gate trench, the number of photomask layers in this embodiment of the invention will not increase, which is beneficial to further control the process cost.

[0108] Since the SGT gate structure of this embodiment of the invention is composed of a gate dielectric layer 104 and a gate conductive material layer 105 formed in the first trench 103 and a shielding dielectric layer 111 and a shielding gate field plate 112 formed in the second trench 110, it is not necessary to provide an isolation oxide layer between the gate conductive material layer 105 and the shielding gate field plate 112. Therefore, the defect of increased process complexity caused by this is eliminated, thereby reducing process difficulty and increasing process controllability.

[0109] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing a dual-gate SGT semiconductor device, characterized in that, Includes the following steps: Step 1: Form one or more first trenches with a first depth in a selected area of ​​a semiconductor substrate, form a gate dielectric layer on the inner surface of the first trench, and then fill the first trench with a gate conductive material layer. A trench gate is formed by the gate dielectric layer and the gate conductive material layer filled in the first trench; Step 2: Perform second conductivity type ion implantation in the selected area and advance to form a second conductivity type doped body region, with the first trench passing through the body region; Step 3: Implant heavily doped ions of the first conductivity type into the selected area and advance to form a source region, wherein the second side of the source region is self-aligned with the side of the first trench; Step 4: Forming an interlayer film, wherein the interlayer film covers the surface of the semiconductor substrate on which the trench gate, the body region and the source region are formed; Step 5: Forming the shielding barrier, including: Step 51: Define the formation region of the second trench, and sequentially etch the interlayer film and the semiconductor substrate in the formation region of the second trench to form the second trench. The second trench is located on both sides of each of the first trenches. The depth of the second trench in the semiconductor substrate is the second depth, which is greater than the first depth. Step 52: Form a shielding dielectric layer on the inner surface of the second trench; Step 53: Fill the second trench with metal to form a shielding grid plate; The shielding gate is composed of the shielding dielectric layer filled in the second trench and the shielding gate field plate; during reverse breakdown voltage, the shielding gate field plate is used to deplete the drift region of the first conductivity type doped in the semiconductor substrate between the shielding gate field plates to improve the device breakdown voltage.

2. The method for manufacturing a dual-gate SGT semiconductor device as described in claim 1, characterized in that: Step 2 can be placed before or after Step 1.

3. The method for manufacturing a dual-gate SGT semiconductor device as described in claim 2, characterized in that: Step 3 can be placed before or after Step 1, or before or after Step 2.

4. The method for manufacturing a dual-gate SGT semiconductor device as described in claim 3, characterized in that: In step one, a first epitaxial layer doped with a first conductivity type is also formed on the surface of the semiconductor substrate. The first trench and the second trench are both located in the first epitaxial layer. The drift region is composed of the first epitaxial layer located at the bottom of the body region.

5. The method for manufacturing a dual-gate SGT semiconductor device as described in claim 1, characterized in that: The material of the shielding dielectric layer is an oxide layer.

6. The method for manufacturing a dual-gate SGT semiconductor device as described in claim 5, characterized in that: In step 52, the shielding dielectric layer also extends onto the surface of the interlayer film outside the second trench; In step 53, the metal of the shielding grid plate extends further to the surface of the shielding medium layer outside the second trench; Following that, it also includes: Remove the metal from the shielding grid plate on the surface of the shielding medium layer outside the second trench and make the top surface of the shielding grid plate in the second trench region flush with the top surface of the shielding medium layer outside the second trench, while retaining the shielding medium layer outside the second trench.

7. The method for manufacturing a dual-gate SGT semiconductor device as described in claim 5, characterized in that: In step 51: Before defining the formation region of the second trench, a protective layer is also formed on the surface of the interlayer film; In the etching of the second trench, the protective layer is etched first, and then the interlayer film and the semiconductor substrate are etched. The photoresist pattern formed by photolithography defines the formation area of ​​the second trench; The second trench can be etched using the photoresist pattern as a mask, or the photoresist pattern can be transferred into the protective layer and then the patterned protective layer can be used as a mask to etch the second trench. In step 52, the shielding medium layer extends further onto the surface of the protective layer outside the second trench; then, the shielding medium layer outside the second trench and the protective layer are removed. In step 53, the metal of the shielding grid plate also extends to the surface of the interlayer film outside the second trench; Following that, it also includes: Remove the metal from the shielding grid plate outside the second trench and make the top surface of the shielding grid plate in the second trench region flush with the top surface of the interlayer membrane.

8. The method for manufacturing a dual-gate SGT semiconductor device as described in claim 7, characterized in that: The protective layer is either a first nitrided layer or a superposition of a first nitrided layer and a second oxide layer.

9. The method for manufacturing a dual-gate SGT semiconductor device as described in claim 1, characterized in that: In step 53, the metal material of the shielding grid plate includes W, Ti, TiN or Al.

10. The method for manufacturing a dual-gate SGT semiconductor device as described in claim 1, characterized in that: In step one, the gate dielectric layer is made of an oxide layer and is formed using a thermal oxidation process.

11. The method for manufacturing a dual-gate SGT semiconductor device as described in claim 1, characterized in that: In step one, the material of the gate conductive material layer is polycrystalline silicon.

12. The method for manufacturing a dual-gate SGT semiconductor device as described in claim 1, characterized in that, After step five, the following also includes: A contact hole is formed in a selected area, the contact hole passing through the interlayer film, and corresponding contact holes are formed on top of the source region and the gate conductive material layer; A front metal layer is formed, and the front metal layer is patterned and etched to form a source and a gate. The source region is connected to the source through the corresponding contact hole at the top, and the gate conductive material layer is connected to the gate through the corresponding contact hole at the top. The top of the shielding gate field plate is connected to the source. Form a contact pad; Complete the back side process.

13. The method for manufacturing a dual-gate SGT semiconductor device as described in claim 12, characterized in that, The back-side process includes: The semiconductor substrate is thinned on the back side; The semiconductor substrate is heavily doped with the first conductivity type, and the thinned semiconductor substrate is directly used as the drain region of the first conductivity type; or the thinned semiconductor substrate is implanted with the back side of the first conductivity type to form the drain region. A back metal layer is formed on the back side of the leak area.

14. The method for manufacturing a dual-gate SGT semiconductor device as described in claim 1, characterized in that: The semiconductor substrate includes a silicon substrate.

15. The method for manufacturing a dual-gate SGT semiconductor device as described in claim 12, characterized in that: The process flow of the dual-gate SGT semiconductor device uses 7 photomasks, which are used to define the formation areas of the first trench, the body region, the source region, the second trench, the contact hole, the front metal layer pattern, and the contact pad.

16. The method for manufacturing a dual-gate SGT semiconductor device according to any one of claims 1 to 15, characterized in that: The dual-gate SGT semiconductor device is an N-type device with an N-type first conductivity type and a P-type second conductivity type; or, the dual-gate SGT semiconductor device is a P-type device with a P-type first conductivity type and an N-type second conductivity type.

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