Method of fabricating semiconductor device structure using nitrogen-containing pattern

Abstract

A method of fabricating a semiconductor device structure is provided. The method includes forming a nitrogen-containing pattern on a semiconductor substrate. The method also includes performing an energy treatment process to form a conversion portion in the semiconductor substrate and covered by the nitrogen-containing pattern. The method further includes etching the semiconductor substrate to surround the conversion portion with an opening structure.

Description

[0001] Cross-referencing

[0002] This application claims priority to U.S. Patent Application No. 17 / 735,284 (i.e., priority date "May 3, 2022"), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a method for fabricating a semiconductor device structure. In particular, it relates to a method for fabricating a semiconductor device structure using a nitrogen-containing pattern. Background Technology

[0004] Semiconductor components are indispensable for many modern applications. With advancements in electronic technology, semiconductor components have become increasingly smaller, while simultaneously offering superior functionality and incorporating a larger number of integrated circuits. Due to the miniaturization of semiconductor components, different forms and sizes of semiconductor components realizing different functions are integrated and packaged into a single module. Furthermore, numerous manufacturing steps are performed on the integration of these various forms of semiconductor components.

[0005] However, the fabrication and integration of these semiconductor devices involve many complex steps and operations. Integration within these semiconductor devices becomes increasingly complex. This increased complexity in the fabrication and integration of these semiconductor devices can lead to several defects. Therefore, there is a need for continuous improvement of the fabrication processes for these semiconductor devices in order to address these problems.

[0006] The description of the "prior art" above is only for background information and does not constitute an admission that the description of the "prior art" above discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the "prior art" above should be considered part of this disclosure. Summary of the Invention

[0007] One embodiment of this disclosure provides a method for fabricating a semiconductor device structure. The method includes forming a nitrogen-containing pattern on a semiconductor substrate. The method also includes performing an energy processing step to form a conversion portion on the semiconductor substrate and covered by the nitrogen-containing pattern. The method further includes etching the semiconductor substrate to surround the conversion portion with an opening structure.

[0008] In one embodiment, the fabrication method further includes removing the nitrogen-containing pattern after performing the energy processing. In one embodiment, the nitrogen-containing pattern is removed before etching the semiconductor substrate. In one embodiment, the conversion section is used as an etching mask to etch the semiconductor substrate. In one embodiment, the fabrication method further includes forming an insulating structure in the opening structure, wherein an active region in the semiconductor substrate is surrounded by the insulating structure.

[0009] In one embodiment, forming the insulating structure includes forming a dielectric material to cover the transition portion and the semiconductor substrate, wherein the opening structure is filled by the dielectric material. In another embodiment, forming the insulating structure further includes performing a planarization process on the dielectric material to remove a portion of the transition portion and the dielectric material.

[0010] Another embodiment of this disclosure provides a method for fabricating a semiconductor device structure. The method includes forming a nitrogen-containing pattern on a semiconductor substrate. The method also includes performing an energy processing step to replace a portion of the semiconductor substrate with a conversion section. The method further includes removing the nitrogen-containing pattern to expose the conversion section. Furthermore, the method includes using the conversion section as an etch mask to perform an etching process on the semiconductor substrate.

[0011] In one embodiment, the transition portion is covered by and in direct contact with the nitrogen-containing pattern before the nitrogen-containing pattern is removed. In one embodiment, the etching process is performed after the nitrogen-containing pattern is removed. In one embodiment, during the etching process, a portion of the semiconductor substrate exposed through the transition portion is removed to form an opening structure, and an interface between the transition portion and the semiconductor substrate is higher than a lower surface of the opening structure.

[0012] In one embodiment, the opening structure has an annular shape, and the transition portion has an island-shaped shape surrounded by the opening structure. In another embodiment, the fabrication method further includes: filling the opening structure with an insulating structure; and removing the transition portion to expose an active region surrounded by the insulating structure.

[0013] Another embodiment of this disclosure provides a method for fabricating a semiconductor device structure. The method includes forming a plurality of nitrogen-containing patterns on a semiconductor substrate. The method also includes performing an energy processing step to convert a plurality of portions of the semiconductor substrate into a plurality of transition sections. The method further includes removing the nitrogen-containing patterns after performing the energy processing step. Furthermore, the method includes using the transition sections as an etch mask to perform an etching process on the semiconductor substrate, such that each transition section is surrounded by an opening structure.

[0014] In one embodiment, forming the nitrogen-containing patterns includes: forming a nitrogen-containing layer on the semiconductor substrate; forming a patterned mask on the nitrogen-containing layer; and using the patterned mask as an etching mask to etch the nitrogen-containing layer. In one embodiment, the nitrogen-containing patterns are parallel to each other and spaced apart from each other. In one embodiment, the fabrication method further includes: forming an insulating structure in the opening structure; and removing the transition portions to expose a plurality of active regions in the semiconductor substrate.

[0015] In one embodiment, each active region has an island-shaped form surrounded by the insulating structure. In one embodiment, the energy processing includes a nitriding process. In one embodiment, prior to performing the etching process, an upper surface of the conversion portions is higher than an upper surface of the semiconductor substrate.

[0016] This disclosure provides several embodiments of a method for fabricating a semiconductor device structure. The method includes performing an energy processing step on a semiconductor substrate to form a transition region covered by a nitrogen-containing pattern. The method also includes using the transition region as an etch mask to etch the semiconductor substrate to form an opening structure. In some embodiments, an insulating structure is formed in the opening structure. Therefore, without increasing the size of an active region, a lower contact resistance can be obtained between the active region surrounded by the insulating structure and an overlay contact point. This reduces the manufacturing cost and time of the semiconductor device structure and enables greater design flexibility.

[0017] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, thereby enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0018] When with attachment Figure 1 When reading this document, the best understanding of all aspects of this disclosure can be obtained from the following detailed description. It should be understood that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features can be increased or decreased arbitrarily for clarity of discussion.

[0019] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device structure according to some embodiments of this disclosure.

[0020] Figure 2This is a top view schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure during the formation of a semiconductor device structure, in which a nitrogen-containing layer and a patterned mask are sequentially formed on a semiconductor substrate.

[0021] Figure 3 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 2 The section along line A-A'.

[0022] Figure 4 This is a top view schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure during the formation of a semiconductor device structure, in which the nitrogen-containing layer is etched to form multiple nitrogen-containing patterns.

[0023] Figure 5 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 4 The section along line A-A'.

[0024] Figure 6 This is a top view schematic diagram illustrating an intermediate stage during the formation of a semiconductor device structure in some embodiments of this disclosure, where the patterned mask is removed.

[0025] Figure 7 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 6 The section along line A-A'.

[0026] Figure 8 This is a top view schematic diagram illustrating an intermediate stage in which an energy processing process is performed during the formation of a semiconductor element structure to form multiple conversion sections in the semiconductor substrate, according to some embodiments of the present disclosure.

[0027] Figure 9 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 8 The section along line A-A'.

[0028] Figure 10 This is a top view schematic diagram illustrating an intermediate stage during the formation of a semiconductor device structure, in some embodiments of the present disclosure, of removing such nitrogen-containing patterns.

[0029] Figure 11 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 10 The section along line A-A'.

[0030] Figure 12 This is a top view schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure during the formation of a semiconductor element structure, in which such transition sections are used as etching masks to etch the semiconductor substrate to form an opening structure.

[0031] Figure 13 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 12The section along line A-A'.

[0032] Figure 14 This is a top view schematic diagram illustrating an intermediate stage in which, during the formation of a semiconductor element structure, a dielectric material is formed to cover the transition portions and fill the opening structure, according to some embodiments of the present disclosure.

[0033] Figure 15 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 14 The section along line A-A'.

[0034] Figure 16 This is a top view schematic diagram illustrating an intermediate stage in the opening structure during the planarization of the dielectric material to form an insulating structure in some embodiments of the present disclosure during the formation of a semiconductor element structure.

[0035] Figure 17 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 16 The section along line A-A'.

[0036] Figure 18 This is a cross-sectional schematic diagram illustrating an intermediate stage in which an energy processing process is performed during the formation of a semiconductor device structure to form multiple conversion sections in the semiconductor substrate, according to some embodiments of the present disclosure.

[0037] Figure 19 This is a cross-sectional schematic diagram illustrating an intermediate stage during the formation of a semiconductor device structure in some embodiments of the present disclosure, in which the nitrogen-containing patterns are removed.

[0038] Figure 20 This is a cross-sectional schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure during the formation of a semiconductor element structure, in which such transition sections are used as an etching mask to etch the semiconductor substrate to form an open structure.

[0039] Explanation of reference numerals in the attached figures: 10: Preparation method 100: Semiconductor Component Structure 101: Semiconductor substrate 103: Nitrogen-containing layer 105: Patterned Masking 110a: Open 110b: Open 110c: Open 110d: Opening 112a: Opening 112b: Opening 112c: Open 112d: Opening 115: Nitrogen-containing pattern 120a: Open 120b: Open 120c: Open 120d: Opening 122a: Opening 122b: Open 122c: Open 122d: Opening 125: Energy Processing Technology 127: Conversion Section 130a: Open 130b: Open 130c: Open 130d: Opening 132a: Opening 132b: Opening 132c: Open 132d: Opening 134: Open structure 135: Dielectric materials 137a: Insulation section 137b: Insulation section 137c: Insulation part 137d: Insulation part 139a: Insulation section 139b: Insulation section 139c: Insulation part 139d: Insulation section 141: Insulation Structure 151a: Active region 151b: Active Zone 151c: Active Zone 151d: Active region 151e: Active Zone 151f: Active Zone 151g: Active region 215: Nitrogen-containing patterns 225: Energy Processing Technology 227: Conversion Section 230a: Open 230b: Open 230c: Open 230d: Opening 234: Open structure S1: Interface S11: Steps S13: Steps S15: Steps S17: Steps S19: Steps S2: Lower surface S21: Steps S23: Steps S25: Steps S3: Upper surface S4: Upper surface S5: Interface S6: Lower surface Detailed Implementation

[0040] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0041] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0042] Figure 1 This is a flowchart illustrating a method 10 for fabricating a semiconductor device structure 100 according to some embodiments of this disclosure. The fabrication method 10 includes steps S11, S13, S15, S17, S19, S21, S23, and S25. A brief introduction follows. Figure 1 Steps S11~S25, then combined Figures 2-17 Please provide a detailed explanation. For example... Figure 1 As shown, preparation method 10 begins in step S11, wherein a nitrogen-containing layer is formed on a semiconductor substrate.

[0043] Next, in step S13, a patterned mask is formed on the nitrogen-containing layer, and in step S15, the nitrogen-containing layer is etched to form a plurality of nitrogen-containing patterns. In some embodiments, each nitrogen-containing pattern is arranged in parallel with each other. In step S17, an energy processing process is performed to form a plurality of conversion sections in the semiconductor substrate.

[0044] In some embodiments, the transition portions are covered by the nitrogen-containing patterns. In some embodiments, multiple portions of the semiconductor substrate covered by the nitrogen-containing patterns are converted into the transition portions. In some embodiments, the transition portions are aligned with the nitrogen-containing patterns.

[0045] Next, in step S19, the nitrogen-containing patterns are removed, and in step S21, an etching process is performed on the semiconductor substrate using the transition portions as an etching mask to form an opening structure. In some embodiments, each transition portion is surrounded by the opening structure. In some embodiments, the opening structure has an annular shape, and the transition portions have an island shape surrounded by the opening structure.

[0046] In step S23, a dielectric material is formed to cover the transition portions and fill the opening structure. Then, in step S25, a planarization process is performed on the dielectric material to form an insulating structure in the opening structure. In some embodiments, after the planarization process, the portions of the semiconductor structure covered by the transition portions are exposed and become a plurality of active regions (AA). In some embodiments, each active region has an island shape surrounded by the insulating structure.

[0047] Figures 2 to 17 These are top view and cross-sectional view diagrams, illustrating some embodiments of this disclosure. Figure 1 Preparation method 10: Preparation of semiconductor device structure 100 ( Figure 16 and Figure 17 Different stages of ) such as. Figure 2 and Figure 3 As shown, according to some embodiments, a nitrogen-containing layer 103 is formed on a semiconductor substrate 101, and a patterned mask 105 is formed on the nitrogen-containing layer 103. The various steps are illustrated in... Figure 1 Steps S11 to S13 in the preparation method 10 shown.

[0048] The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer. Additionally, the semiconductor substrate 101 may comprise elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP) and / or gallium arsenide phosphide (GaInAsP).

[0049] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator (SOI) substrate, which may include a substrate, a buried oxide layer, and a semiconductor layer, wherein the buried oxide layer is located on the substrate, the semiconductor layer is located on the buried oxide layer, and the SOI substrate is, for example, a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SOI substrate can be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and / or other applicable methods.

[0050] In some embodiments, the nitrogen-containing layer 103 includes a nitrogen-containing material, such as silicon nitride or silicon oxynitride. In some embodiments, the fabrication technique of the nitrogen-containing layer 103 includes a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, or other suitable methods.

[0051] In some embodiments, a patterned mask layer 105 having a plurality of openings 110a, 110b, 110c, 110d, 112a, 112b, 112c, 112d is formed on the nitrogen-containing layer 103. In some embodiments, the openings 110a, 110b, 110c, 110d are parallel to each other and are physically connected via the openings 112a, 112b, 112c, 112d. Furthermore, the nitrogen-containing layer 103 is exposed through the openings 110a, 110b, 110c, 110d, 112a, 112b, 112c, 112d. In some embodiments, the nitrogen-containing layer 103 and the patterned mask 105 comprise different materials so that different etching selectivity can be achieved in subsequent etching processes.

[0052] Next, as Figure 4 and Figure 5 As shown, according to some embodiments, an etching process is performed on the nitrogen-containing layer 103 using a patterned mask 105 as an etching process to form a plurality of nitrogen-containing patterns 115. The various steps are shown in... Figure 1 Step S15 of the fabrication method 10 shown. In some embodiments, a plurality of openings 120a, 120b, 120c, 120d, 122a, 122b, 122c, 122d are formed to penetrate the nitrogen-containing layer 103, so that the semiconductor substrate 101 is exposed through the openings 120a, 120b, 120c, 120d, 122a, 122b, 122c, 122d. The etching process may be a wet etching process, a dry etching process, or a combination thereof.

[0053] like Figure 6 and Figure 7 As shown, according to some embodiments, after the nitrogen-containing patterns 115 are formed on the semiconductor substrate 101, the patterned mask 105 is removed. In some embodiments, the patterned mask 105 is removed by a stripping process, an ashing process, an etching process, or other suitable processes.

[0054] Next, as Figure 8 and Figure 9 As shown, according to some embodiments, an energy processing process 125 is performed to form a plurality of conversion units 127 in a semiconductor substrate 101. The various steps are shown in... Figure 1Step S17 in the fabrication method 10 shown. In some embodiments, the semiconductor substrate 101 is covered by the nitrogen-containing patterns 115 and the portions of the nitrogen-containing patterns 115 that are in direct contact with the semiconductor substrate 101 are converted into the conversion portions 127, while the portions of the semiconductor substrate 101 exposed by the nitrogen-containing patterns 115 remain intact during the energy processing process 125.

[0055] In some embodiments, the energy processing process 125 includes a nitriding process. In some embodiments, each conversion section 127 has an island shape. Furthermore, according to some embodiments, the conversion sections 127 are parallel to each other.

[0056] like Figure 10 and Figure 11 As shown, according to some embodiments, after performing energy processing 125, the nitrogen-containing patterns 115 are removed. The various steps are shown in... Figure 1 Step S19 of the preparation method 10 shown. In some embodiments, the nitrogen-containing patterns 115 are removed to expose the conversion portions 127. In some embodiments, the nitrogen-containing patterns 115 are removed by a stripping process, an ashing process, an etching process or other suitable process.

[0057] Then, as Figure 12 and Figure 13 As shown, according to some embodiments, the conversion unit 127 is used as an etching mask to perform an etching process on the semiconductor substrate 101 to form an opening structure 134. The various steps are shown in... Figure 1 Step S21 in the preparation method 10 shown. The etching process can be a wet etching process, a dry etching process, or a combination thereof.

[0058] In some embodiments, portions of the semiconductor substrate 101 exposed by the transition sections 127 are partially removed to form an opening structure 134. In some embodiments, the opening structure 134 includes a plurality of openings 130a, 130b, 130c, 130d, 132a, 132b, 132c, and 132d. In some embodiments, the openings 130a, 130b, 130c, and 130d are parallel to each other and physically connected via the openings 132a, 132b, 132c, and 132d. Furthermore, according to some embodiments, an interface S1 between the transition sections 127 and the semiconductor substrate 101 is higher than a plurality of lower surfaces S2 of the opening structure 134.

[0059] Next, as Figure 14 and Figure 15 As shown, according to some embodiments, a dielectric material 135 is formed to cover the transition portions 127 and fill the opening structure 134. The various steps are shown in... Figure 1Step S23 of the preparation method 10 shown. In some embodiments, the dielectric material 135 includes silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a dielectric material with a low dielectric constant, or other suitable materials. The fabrication technique of the dielectric material 135 may include a deposition process, such as a CVD process, a PVD process, an ALD process, a spin coating process, or other suitable processes.

[0060] Next, as Figure 16 and Figure 17 As shown, according to some embodiments, a planarization process is performed on the dielectric material 135 to expose the semiconductor substrate 101, so that an insulating structure 141 is formed in the opening structure 134 (see reference). Figure 12 and Figure 13 The individual steps are shown in Figure 1 Step S25 of the preparation method 10 shown. In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process.

[0061] In some embodiments, the insulating structure 141 includes a plurality of insulating portions 137a, 137b, 137c, 137d, 139a, 139b, 139c, and 139d. In some embodiments, the insulating portions 137a, 137b, 137c, and 137d are parallel to each other and are physically connected via the insulating portions 139a, 139b, 139c, and 139d. In some embodiments, according to some embodiments, after the planarization process, the exposed semiconductor substrate 101 is exposed in the previous step (see reference). Figure 14 and Figure 15 The portions covered by the conversion section 127 of the ) become active regions 151a, 151b, 151c, 151d, 151e, 151f, and 151g.

[0062] In some embodiments, each active region 151a, 151b, 151c, 151d, 151e, 151f, 151g has an island-shaped form surrounded by an insulating structure 141. In some embodiments, the insulating structure 141 has a plurality of annular portions, and each active region 151a, 151b, 151c, 151d, 151e, 151f, 151g is surrounded by an annular portion of the insulating structure 141. After forming the insulating structure 141, a semiconductor device structure 100 is obtained.

[0063] In some embodiments, the method of fabricating the semiconductor device structure 100 includes forming a nitrogen-containing pattern 115 on a semiconductor substrate 101, and performing an energy processing process 125 on the semiconductor device 101 to form a conversion portion 127 between the semiconductor substrate 101 and the nitrogen-containing pattern 115. The method of fabricating the semiconductor device structure 100 also includes using the conversion portion 127 as an etching process to etch the semiconductor substrate 101 to form an opening structure 134. In some embodiments, an insulating structure 141 is formed in the opening structure 134. Therefore, a lower contact resistance can be obtained between the active regions 151a, 151b, 151c, 151d, 151e, 151f, 151g, which are surrounded by the insulating structure 141 and continue to form a covered contact, without increasing the size of the active regions 151a, 151b, 151c, 151d, 151e, 151f, 151g. As a result, the manufacturing cost and time of the semiconductor device structure 100 can be reduced, and greater design flexibility can be achieved.

[0064] Figures 18 to 20 This is a cross-sectional schematic diagram illustrating different stages of fabricating the semiconductor device structure 100 using another fabrication method according to some improved embodiments of this disclosure. It should be noted that... Figure 18 The steps preceding the structure shown are Figures 2 to 8 The steps shown are largely the same, and a detailed description of the relevant information can be found in the previous text, which will not be discussed again here.

[0065] like Figure 18 As shown, according to some embodiments, after removing the patterned mask 105 on the nitrogen-containing patterns 115, an energy processing process 225 is performed to form a plurality of transition portions 227 from a plurality of interfaces between the semiconductor substrate 101 and the nitrogen-containing patterns 115. After performing the energy processing process 225, the transition portions 227 are covered by a plurality of remaining portions of the plurality of nitrogen-containing patterns 215 and directly contact the remaining portions of the nitrogen-containing patterns 215.

[0066] In some embodiments, the energy processing process 225 includes a nitriding process. According to some embodiments, similar to... Figure 8 and Figure 9 The conversion sections 127, each conversion section 227 having an island shape, and the conversion sections 227 being parallel to each other.

[0067] like Figure 19As shown, according to some embodiments, the nitrogen-containing patterns 215 are removed after performing the energy processing process 225. In some embodiments, the nitrogen-containing patterns 215 are removed to expose the conversion portions 227. In some embodiments, the nitrogen-containing patterns 215 are removed by a stripping process, an ashing process, an etching process, or other suitable processes. Furthermore, according to some embodiments, the upper surfaces S3 of the conversion portions 227 are higher than the upper surface S4 of the semiconductor substrate 101.

[0068] Next, as Figure 20 As shown, according to some embodiments, the conversion unit 227 is used as an etching process to perform an etching process on the semiconductor substrate 101 to form an opening structure 234. The etching process may be a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the opening structure 234 includes a plurality of openings 230a, 230b, 230c, and 230d.

[0069] Some details of opening structure 234 are similar to or the same as those of opening structure 134 (see reference). Figure 12 and Figure 13 (This will not be repeated in the text.) For example, in a top view, openings 230a, 230b, 230c, and 230d are parallel to each other and are physically connected via multiple openings (not shown). Furthermore, according to some embodiments, multiple interfaces S5 between these transition sections 227 and the semiconductor substrate 101 are higher than the lower surface S6 of the opening structure 234.

[0070] Next, according to some embodiments, a dielectric material (not shown) is formed to cover the transition portions 227 and fill the opening structure 234, and a planarization process is performed on the dielectric material to form an insulating structure (not shown) in the opening structure 234. In some embodiments, the dielectric material includes silicon oxide, silicon nitride, silicon oxynitride, FSG, a low dielectric constant dielectric material, or other suitable materials, and the fabrication technique of the dielectric material may include a deposition process, such as a CVD process, a PVD process, an ALD process, a spin coating process, or other suitable processes. Furthermore, the planarization process includes a CMP process.

[0071] Although the steps of forming the dielectric material and planarizing the dielectric material to form the insulating structure are not shown, it should be understood that these steps are similar to those described above. Figures 14 to 17 The steps shown are not repeated herein. In some embodiments, each active region in the semiconductor substrate 101 has an island shape surrounded by the insulating structure. In some embodiments, the insulating structure has a plurality of annular portions, and each active region is surrounded by an annular portion of the insulating structure. After the insulating structure is formed, the semiconductor device structure is obtained.

[0072] This disclosure provides a method for fabricating a semiconductor device structure (e.g., semiconductor device structure 100). The method includes performing an energy processing process (e.g., energy processing process 125 or 225) on a semiconductor substrate (e.g., semiconductor substrate 101) to form a transition portion (e.g., transition portion 127 or 227) covered by a nitrogen-containing pattern (e.g., nitrogen-containing pattern 115 or 215). The method also includes using the transition portion as an etching mask to etch the semiconductor substrate to form an opening structure (e.g., opening structure 134 or 234). In some embodiments, an insulating structure (e.g., insulating structure 141) is formed in the opening structure. Therefore, a lower contact resistance between the active regions surrounded by the insulating structure 141 and continuing to form the covered contact can be obtained without increasing the size of the active regions (e.g., active regions 151a-g). As a result, the manufacturing cost and time of the semiconductor device structure can be reduced, and greater design flexibility can be achieved.

[0073] One embodiment of this disclosure provides a method for fabricating a semiconductor device structure. The method includes forming a nitrogen-containing pattern on a semiconductor substrate. The method also includes performing an energy processing step to form a conversion portion on the semiconductor substrate and covered by the nitrogen-containing pattern. The method further includes etching the semiconductor substrate to surround the conversion portion with an opening structure.

[0074] Another embodiment of this disclosure provides a method for fabricating a semiconductor device structure. The method includes forming a nitrogen-containing pattern on a semiconductor substrate. The method also includes performing an energy processing step to replace a portion of the semiconductor substrate with a conversion section. The method further includes removing the nitrogen-containing pattern to expose the conversion section. Furthermore, the method includes using the conversion section as an etch mask to perform an etch process on the semiconductor substrate.

[0075] Another embodiment of this disclosure provides a method for fabricating a semiconductor device structure. The method includes forming a plurality of nitrogen-containing patterns on a semiconductor substrate. The method also includes performing an energy processing step to convert a plurality of portions of the semiconductor substrate into a plurality of transition sections. The method further includes removing the nitrogen-containing patterns after performing the energy processing step. Furthermore, the method includes using the transition sections as an etch mask to perform an etching process on the semiconductor substrate, such that each transition section is surrounded by an opening structure.

[0076] The embodiments disclosed herein have several advantageous features. By forming the transition section and using it as an etching mask to etch the semiconductor substrate, a lower contact resistance can be obtained without increasing the size of the active region. As a result, the manufacturing cost and time of the semiconductor device structure can be reduced, and greater design flexibility can be achieved.

[0077] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0078] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A method for fabricating a semiconductor device structure, comprising: Forming a nitrogen-containing pattern on a semiconductor substrate; An energy processing process is performed to form a conversion section on the semiconductor substrate and covered by the nitrogen-containing pattern, wherein the energy processing process is a nitriding process, and the semiconductor substrate not covered by the nitrogen-containing pattern is not converted; as well as The semiconductor substrate is etched so that the conversion section is surrounded by an opening structure.

2. The preparation method as described in claim 1 further includes removing the nitrogen-containing pattern after performing the energy processing.

3. The preparation method according to claim 2, wherein the nitrogen-containing pattern is removed before etching the semiconductor substrate.

4. The fabrication method of claim 1, wherein the conversion unit is used as an etching mask to etch the semiconductor substrate.

5. The preparation method of claim 1 further includes forming an insulating structure in the opening structure, wherein an active region in the semiconductor substrate is surrounded by the insulating structure.

6. The preparation method of claim 5, wherein forming the insulating structure includes forming a dielectric material to cover the conversion portion and the semiconductor substrate, wherein the opening structure is filled with the dielectric material.

7. The preparation method of claim 6, wherein forming the insulating structure further includes performing a planarization process on the dielectric material to remove the transition portion and a portion of the dielectric material.

8. A method for fabricating a semiconductor element, comprising: Forming a nitrogen-containing pattern on a semiconductor substrate; An energy processing process is performed to replace a portion of the semiconductor substrate with a conversion section, wherein the energy processing process is a nitriding process, and the semiconductor substrate not covered by the nitrogen-containing pattern is not converted; Remove the nitrogen-containing pattern to expose the conversion section; as well as The conversion unit is used as an etching mask to perform an etching process on the semiconductor substrate.

9. The preparation method of claim 8, wherein before the nitrogen-containing pattern is removed, the conversion portion is covered by the nitrogen-containing pattern and directly contacts the nitrogen-containing pattern.

10. The preparation method of claim 8, wherein the etching process is performed after the nitrogen-containing pattern is removed.

11. The preparation method of claim 8, wherein during the etching process, a portion of the semiconductor substrate exposed through the conversion section is removed to form an opening structure, and an interface between the conversion section and the semiconductor substrate is higher than a lower surface of the opening structure.

12. The preparation method of claim 11, wherein the opening structure has an annular shape and the transition portion has an island shape surrounded by the opening structure.

13. The preparation method according to claim 11, further comprising: The opening structure is filled with an insulating structure; as well as Remove the transition section to expose an active area surrounded by the insulation structure.

14. A method for fabricating a semiconductor device structure, comprising: Multiple nitrogen-containing patterns are formed on a semiconductor substrate; An energy processing process is performed to convert multiple portions of the semiconductor substrate into multiple conversion sections, wherein the energy processing process is a nitriding process, and the semiconductor substrate not covered by the multiple nitrogen-containing patterns is not converted; After performing this energy processing, the multiple nitrogen-containing patterns are removed; as well as An etching process is performed on the semiconductor substrate using the multiple transition sections as an etching mask, such that each transition section is surrounded by an opening structure.

15. The preparation method of claim 14, wherein forming the plurality of nitrogen-containing patterns comprises: A nitrogen-containing layer is formed on the semiconductor substrate; A patterned mask is formed on the nitrogen-containing layer; as well as The nitrogen-containing layer was etched using a patterned mask as an etching mask.

16. The preparation method of claim 15, wherein the plurality of nitrogen-containing patterns are parallel to each other and separated from each other.

17. The preparation method according to claim 14, further comprising: An insulating structure is formed in the opening structure; as well as Remove the multiple conversion sections to expose multiple active regions in the semiconductor substrate.

18. The preparation method of claim 17, wherein each active region has an island shape surrounded by the insulating structure.

19. The preparation method of claim 14, wherein, prior to performing the etching process, an upper surface of the plurality of transition sections is higher than an upper surface of the semiconductor substrate.

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