Method of forming a semiconductor structure
By forming an etch stop layer and a second dielectric layer on the top surface of the gate structure and the source/drain contact layer, the problem of defects in the formation of the gate contact layer is solved, thereby improving the stability and performance of the semiconductor device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2022-04-27
- Publication Date
- 2026-07-21
AI Technical Summary
Defects can be easily introduced during the formation of the gate contact layer, leading to poor performance of semiconductor devices.
By forming a covering etch stop layer and a second dielectric layer on the top surface of the gate structure and source/drain contact layer, the etching process is ensured to stop on the etch stop layer, avoiding local over-etching and reducing structural damage.
It improves the stability and performance of the device, reduces structural defects, and improves RC delay.
Smart Images
Figure CN117012714B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for forming a semiconductor structure. Background Technology
[0002] With the development of semiconductor technology, the size of semiconductor devices continues to shrink, and the design of three-dimensional structures such as FinFETs has become a hot topic in this field. FinFETs generally have multiple fins extending vertically upward from the substrate, in which the channel of the FinFET is formed, the gate structure is formed on the fins, and the active region and drain region are formed in the fins on both sides of the gate structure.
[0003] In a finned field-effect transistor (FFET), the gate contact layer is located on the gate structure and is used to control the source-to-drain current. The gate contact layer is connected to the upper plug layer. Typically, the gate contact layer is located outside the effective region of the transistor, thus requiring additional space.
[0004] In recent years, the industry has used the COAG (Contact Over Active Gate) method to save a significant amount of operating space by placing the gate contact layer directly above the active area of the transistor.
[0005] However, in the existing technology, defects are easily introduced during the formation of the gate contact layer, resulting in poor device performance. Summary of the Invention
[0006] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure that reduces defects generated during the formation of the gate contact layer, thereby improving device performance.
[0007] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of gate structures, source / drain regions located on both sides of each gate structure, a plurality of source / drain contact layers located on the source / drain regions, and a first dielectric layer located on the substrate, wherein the first dielectric layer exposes the top surfaces of each gate structure and each source / drain contact layer, and the top surfaces of the source / drain contact layers are higher than the top surfaces of the gate structures; forming an etch stop layer covering the top surfaces of each gate structure and each source / drain contact layer, wherein the thickness of the etch stop layer on the gate structure is equal to the thickness of the source / drain contact layer on the source / drain region. The layers are of uniform thickness; a second dielectric layer is formed on the etch stop layer; the second dielectric layer is etched to form a connection via spanning a portion of the gate structure and a portion of the source / drain contact layer within the second dielectric layer. The connection via includes a first sub-via and a second sub-via that are interconnected. The first sub-via is located on a portion of the gate structure, and the second sub-via is located on a portion of the source / drain contact layer. The connection via exposes the surface of the etch stop layer; the etch stop layer under the connection via is etched until the top surface of the gate structure and the source / drain contact layer is exposed; a connection plug is formed within the connection via.
[0008] Optionally, the method for forming the semiconductor structure further includes: forming a gate via on a portion of the gate structure and a source / drain via on a portion of the source / drain contact layer within a second dielectric layer; forming a gate plug within the gate via and a source / drain plug within the source / drain via.
[0009] Optionally, the source / drain via, the gate via, and the connection via are formed simultaneously; the source / drain plug, the gate plug, and the connection plug are formed simultaneously.
[0010] Optionally, the method for forming the source / drain plug, gate plug, and connection plug includes: depositing a source / drain plug material layer, a gate plug material layer, and a connection plug material layer in the source / drain via, the gate via, and the connection via; and planarizing the source / drain plug material layer, the gate plug material layer, and the connection plug material layer to form the source / drain plug, the gate plug, and the connection plug.
[0011] Optionally, the deposition process of the source / drain plug material layer includes chemical vapor deposition; the deposition process of the gate plug material layer includes chemical vapor deposition; and the deposition process of the connection plug material layer includes chemical vapor deposition.
[0012] Optionally, the source / drain via is formed after the gate plug and the connection plug are formed.
[0013] Optionally, the method for forming the source / drain plug, gate plug, and connection plug includes: forming a gate via and a connection via in a second dielectric layer; depositing a gate plug material layer and a connection plug material layer in the gate via and the connection via; planarizing the gate plug material layer and the connection plug material layer to form the gate plug and the connection plug; after forming the gate plug and the connection plug, forming a source / drain via located in the second dielectric layer; depositing a source / drain plug material layer in the source / drain via; and planarizing the source / drain plug material layer to form the source / drain plug.
[0014] Optionally, the material of the source / drain plug material layer includes tungsten.
[0015] Optionally, the deposition process of the source / drain plug material layer includes a selective tungsten deposition process.
[0016] Optionally, the gate via is formed after the source / drain plugs and connection plugs are formed.
[0017] Optionally, the method for forming the gate structure, source / drain regions, source / drain contact layer, and first dielectric layer includes: forming a gate structure on the substrate, source / drain regions on both sides of the gate structure, and an initial first dielectric layer surrounding the gate structure; forming a source / drain contact layer on the surface of the source / drain regions within the initial first dielectric layer; and thinning the initial first dielectric layer until the top surfaces of the gate structure and the source / drain contact layer are exposed to form the first dielectric layer.
[0018] Optionally, the first dielectric layer is located between the gate structure and the source / drain contact layer, and the top surface of the first dielectric layer is lower than the top surface of the gate structure, thereby creating a gap on the first dielectric layer between the gate structure and the source / drain contact layer.
[0019] Optionally, after forming the etch stop layer, the gap is sealed to form a cavity layer between the gate structure and the source / drain contact layer.
[0020] Optionally, the thickness of the etching stop layer ranges from 100 angstroms to 200 angstroms.
[0021] Optionally, the material of the source / drain contact layer includes cobalt.
[0022] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:
[0023] In the semiconductor structure formation method provided by the present invention, since an etch stop layer and a second dielectric layer are formed covering the top surfaces of each gate structure and each source / drain contact layer, the etching process of the gate structure and the second dielectric layer on the source / drain contact layer can be stopped at the etch stop layer during the formation of the connection via spanning part of the gate structure and part of the source / drain contact layer. This results in a larger process window and avoids additional damage to the source / drain connection layer due to the height difference between the gate structure and the source / drain contact layer. Simultaneously, since the gate structure and the source / drain contact layer have the same structure, both consisting of an etch stop layer and a second dielectric layer, the etching process of the second dielectric layer on the gate structure and the source / drain contact layer can be more uniform during the subsequent formation of the connection via, reducing etching damage to the source / drain connection layer. Furthermore, since the thickness of the etch stop layer on the gate structure is the same as that on the source / drain contact layer, the etching degree of the etch stop layer on the gate structure and the source / drain contact layer can be ensured to be the same during the subsequent etching process. This avoids the problem of local over-etching, reduces damage to the source / drain contact layer, reduces structural defects, and thus improves device stability and device performance.
[0024] Furthermore, the method for forming the semiconductor structure further includes forming a cavity layer located between the gate structure and the source / drain contact layer. The cavity layer has a low dielectric constant; therefore, its location between the gate structure and the source / drain contact layer effectively reduces the parasitic capacitance between them, thereby improving RC delay. Attached Figure Description
[0025] Figures 1 to 3 This is a cross-sectional schematic diagram of the formation process of a semiconductor structure;
[0026] Figures 4 to 12 This is a schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention. Detailed Implementation
[0027] As described in the background section, in the prior art, defects are easily introduced during the formation of the gate contact layer, resulting in poor device performance.
[0028] Figures 1 to 3 This is a cross-sectional schematic diagram of the formation process of a semiconductor structure.
[0029] Please refer to Figure 1A substrate 100 is provided; a plurality of gate structures 101 are formed on the substrate 100, source / drain regions 102 are formed on both sides of each gate structure 101, a plurality of source / drain contact layers 104 are formed on the source / drain regions 102, and a first dielectric layer 103 is formed on the substrate 100; an etch stop layer 105 is formed on the top surface of the source / drain contact layer 104 and on the first dielectric layer 103; and a second dielectric layer 106 is formed on the etch stop layer 105.
[0030] The etching stop layer 105 is used to ensure that the etching of the vias on the source / drain contact layer 104 is stopped.
[0031] The source / drain contact layer 104 is made of cobalt.
[0032] Please refer to Figure 2 The second dielectric layer 106, the etching stop layer 105, and the first dielectric layer 103 are etched to form a gate via 111 located on a portion of the gate structure 101 and a connection via 110 spanning a portion of the gate structure 101 and a portion of the source / drain contact layer 104. The gate via 111 exposes the surface of the gate structure 101, and the connection via 110 exposes the surface of the gate structure 101 and the source / drain contact layer 104.
[0033] Please refer to Figure 3 A gate plug 121 and a connection plug 120 are formed in the gate through-hole 111 and the connection through-hole 110.
[0034] Because the source / drain contact layer 104 is higher than the gate structure 101, the thickness that needs to be etched on the surface of the source / drain contact layer 104 is less than the thickness that needs to be etched on the surface of the gate structure 101 during the simultaneous formation of the gate via 111 and the connection via 110. Furthermore, because the gate structure 101 is lower, the etch stop layer 105 needs to be completely etched through during the etching of the surface of the gate structure 101, resulting in the etch stop layer 105 on the surface of the source / drain contact layer 104 also being etched through. Consequently, the top surface of the source / drain contact layer 104 is easily damaged (e.g., ...). Figure 2 As shown at point A in the middle, this causes cobalt deficiency and cobalt contamination, thereby introducing defects and reducing device performance.
[0035] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure. This method involves forming an etch stop layer covering the top surfaces of each gate structure and each source / drain contact layer, and a second dielectric layer located on the etch stop layer. Therefore, during the subsequent formation of vias spanning a portion of the gate structure and a portion of the source / drain contact layer, even if the heights of the gate structure and the source / drain contact layer differ, the etching process of the second dielectric layer can still be relatively uniform, and the etching process of the second dielectric layer can be stopped at the etch stop layer. Furthermore, the thickness of the etch stop layer formed on the gate structure is the same as its thickness on the source / drain contact layer. Therefore, during subsequent etching of the etch stop layer, the problem of localized over-etching is avoided, thereby preventing additional damage to the source / drain contact layer, reducing structural defects, and thus improving device stability and performance.
[0036] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0037] Figures 4 to 12 This is a schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention.
[0038] Please refer to Figure 4 A substrate 200 is provided; a plurality of gate structures 202 are formed on the substrate 200, source and drain regions 201 are located on both sides of each gate structure 202, and an initial first dielectric layer 205 surrounds the gate structure 202.
[0039] The substrate 200 includes a base (not shown) and a plurality of fin structures (not shown) located on the base. Each of the gate structures 202 spans the top and part of the sidewall surface of the fin structure.
[0040] The substrate 200 is made of materials including silicon, silicon-germanium, silicon carbide, silicon-on-insulator (SOI), and germanium-on-insulator (GOI). Specifically, in this embodiment, the substrate 200 is made of silicon.
[0041] In this embodiment, the surface of the gate structure 202 also has a sidewall structure (not shown) for protecting the gate structure 202. The sidewall structure includes a first sidewall 203 and a second sidewall 204 located on the surface of the first sidewall 203. The second sidewall 204 is also located on the surface of the substrate 200.
[0042] Specifically, the material of the first sidewall 203 includes silicon oxide; the material of the second sidewall 204 includes silicon nitride.
[0043] In this embodiment, the method for forming the gate structure 202, source / drain regions 201, sidewall structure, and initial first dielectric layer 205 includes: forming a dummy gate (not shown) on the substrate 200; forming source / drain regions 201 in the substrate 200 on both sides of the dummy gate; forming a sidewall material layer (not shown) on the sidewall and top surface of the dummy gate; forming a first initial dielectric material layer (not shown) surrounding the dummy gate and the sidewall material layer on the substrate 200; removing the dummy gate to form a gate opening; depositing an initial gate (not shown) in the gate opening; planarizing the initial gate and the sidewall material layer to form the gate structure 202 and the sidewall structure; and depositing a second initial dielectric material layer (not shown) on the first initial dielectric material layer, wherein the first initial dielectric material layer and the second initial dielectric material layer constitute the initial first dielectric layer 205.
[0044] In this embodiment, the top surface of the initial first dielectric layer 205 is higher than the top surface of the gate structure 202.
[0045] In this embodiment, the material of the initial first dielectric layer 205 includes silicon oxide.
[0046] Please refer to Figure 5 A source / drain contact layer 207 is formed within the initial first dielectric layer 205, located on the surface of the source / drain region 201, and the top surface of the source / drain contact layer 207 is higher than the top surface of the gate structure 202.
[0047] The source / drain contact layer 207 enables electrical connection between the source / drain region 201 and the upper plug (not shown).
[0048] In this embodiment, the source / drain contact layer 207 has a contact sidewall 208 on its surface, which is used to control the height of the source / drain contact layer 207.
[0049] In this embodiment, the initial first dielectric layer 205, the source / drain contact layer 207, and the contact sidewall 208 have the same height.
[0050] Specifically, the method for forming the source / drain contact layer 207 and the contact sidewall 208 includes: forming a first through-hole (not shown) located within the initial first dielectric layer 205, the first through-hole exposing the surface of the source / drain region 201; depositing a sidewall material layer (not shown) on the sidewall of the first through-hole; depositing a source / drain contact material layer (not shown) within the first through-hole; and planarizing the sidewall material layer and the source / drain contact material layer until the surface of the initial first dielectric layer 205 is exposed, thereby forming the source / drain contact layer 207 and the contact sidewall 208.
[0051] In this embodiment, the material of the contact sidewall 208 includes silicon nitride.
[0052] In this embodiment, the material of the source / drain contact layer 207 includes cobalt.
[0053] Please refer to Figure 6 The initial first dielectric layer 205 is thinned until the top surfaces of the gate structure 202 and the source / drain contact layer 207 are exposed to form the first dielectric layer 206.
[0054] The purpose of thinning the initial first dielectric layer 205 is to expose the top of the gate structure 202 and the source / drain contact layer 207, thereby facilitating the subsequent formation of an etch stop layer on the surface of the gate structure 202 and the source / drain contact layer 207.
[0055] The first dielectric layer 206 is partially located between the gate structure 202 and the source / drain contact layer 207, and the top surface of the first dielectric layer 206 between the gate structure 202 and the source / drain contact layer 207 is lower than the top surface of the gate structure 202, thereby creating a gap 260 on the first dielectric layer 206 between the gate structure 202 and the source / drain contact layer 207. The gap 260 is formed during the thinning process of the initial first dielectric layer 205.
[0056] Since the gap 260 provides space for the cavity layer to be formed subsequently, it is beneficial to reduce the parasitic capacitance between the gate structure 202 and the source / drain contact layer 207.
[0057] In this embodiment, the process for thinning the initial first dielectric layer 205 includes a dry etching process.
[0058] Please refer to Figure 7 An etch stop layer 210 is formed covering the top surface of each gate structure 202 and each source / drain contact layer 207, wherein the thickness of the etch stop layer 210 on the gate structure 202 is the same as the thickness on the source / drain contact layer 207; and a second dielectric layer 220 is formed on the etch stop layer 210.
[0059] Because an etch stop layer 210 and a second dielectric layer 220 are formed covering the top surfaces of each gate structure 202 and each source / drain contact layer 207, the presence of the etch stop layer 210 allows the etching process of the gate structure 202 and the second dielectric layer 220 on the source / drain contact layer 207 to stop on the etch stop layer 210 during the subsequent formation of the connection vias spanning a portion of the gate structure 202 and a portion of the source / drain contact layer 207. This results in a larger process window, better etching uniformity, and avoids additional damage to the source / drain connection layer due to the difference in height between the gate structure 202 and the source / drain contact layer 207.
[0060] Furthermore, since the thickness of the etch stop layer 210 on the gate structure 202 is the same as the thickness on the source / drain contact layer 207, the etching degree of the etch stop layer 210 on the gate structure 202 and the source / drain contact layer 207 can be ensured to be the same during the subsequent etching process of the etch stop layer 210. This avoids the problem of local over-etching, reduces the damage to the source / drain contact layer 207, reduces structural defects, thereby improving device stability and device performance.
[0061] In this embodiment, the thickness of the etching stop layer 210 is in the range of 100 angstroms to 200 angstroms, thereby effectively protecting the source / drain contact layer 207 from damage during the subsequent formation of the interconnect via.
[0062] In addition, after forming the etch stop layer 210, the gap 260 is sealed to form a cavity layer 250 located between the gate structure 202 and the source / drain contact layer 207.
[0063] Because the cavity layer 250 is enclosed with air, its dielectric constant is relatively small. Therefore, it is located between the gate structure 202 and the source / drain contact layer 207, which can effectively reduce the parasitic capacitance between the gate structure 202 and the source / drain contact layer 207, thereby improving RC delay.
[0064] In this embodiment, the material of the etch stop layer 210 includes silicon nitride.
[0065] In this embodiment, the method for forming the etching stop layer 210 includes a non-orthographic projection deposition process. This non-orthographic projection deposition process can directly seal the voids 260 without filling them, thereby forming a cavity layer 250.
[0066] In this embodiment, the material of the second dielectric layer 220 includes silicon oxide.
[0067] Please refer to Figures 8 to 10 ,in, Figure 8 for Figure 10 A schematic diagram of the cross-sectional structure along the AA' direction. Figure 9 for Figure 10 A schematic diagram of the cross-sectional structure along the BB' direction. Figure 10 for Figure 8 , Figure 9 Top view along direction P.
[0068] After the second dielectric layer 220 is formed, the second dielectric layer 220 is etched to form a connecting via 221 that spans a portion of the gate structure 202 and a portion of the source / drain contact layer 207. The connecting via 221 includes a first sub-via (not shown) and a second sub-via (not shown) that are interconnected. The first sub-via is located on a portion of the gate structure 202, and the second sub-via is located on a portion of the source / drain contact layer 207. The connecting via 221 exposes the surface of the etch stop layer 210.
[0069] The connecting through hole 221 provides space for the subsequently formed connecting plug.
[0070] Because an etch stop layer 210 and a second dielectric layer 220 are formed covering the top surfaces of each gate structure 202 and each source / drain contact layer 207, the etching process of the second dielectric layer 220 on both the gate structure 202 and the source / drain contact layer 207 can be stopped at the etch stop layer 210 during the formation of the via 221 spanning a portion of the gate structure 202 and a portion of the source / drain contact layer 207. This results in a larger process window and avoids additional damage to the source / drain connection layer due to the difference in height between the gate structure 202 and the source / drain contact layer 207. Furthermore, since the gate structure 202 and the source / drain contact layer 207 have identical structures, both consisting of an etch stop layer 210 and a second dielectric layer 220, the etching process of the second dielectric layer 220 on both the gate structure 202 and the source / drain contact layer 207 can be more uniform during the subsequent formation of the via 221. This reduces etching damage to the source / drain connection layer, thereby reducing structural defects, improving device stability, and enhancing device performance.
[0071] In this embodiment, while forming the connection via 221, the method for forming the semiconductor structure further includes: forming a gate via 222 located on a portion of the gate structure 202 and a source / drain via 223 located on a portion of the source / drain contact layer 207 within the second dielectric layer 220. The gate via 222 and the source / drain via 223 provide space for the subsequently formed gate plug and source / drain plug.
[0072] It should be noted that, for ease of understanding, Figure 10 The second dielectric layer 220, the first dielectric layer 206, and the etch stop layer 210 are omitted. Only the coverage areas of the substrate 200, the gate structure 202, the source / drain contact layer 207, and the connection vias 221, the gate via 222, and the source / drain via 223 are shown.
[0073] Please continue to refer to this. Figure 10The substrate 200 includes a base 211 and a plurality of fin structures 212 located on the base 211. Each of the gate structures 202 spans the top and part of the sidewall surface of the fin structure 212.
[0074] In this embodiment, the layout of the connection via 221 and the gate via 222 adopts a COAG (Contact Over Active Gate) structure, that is, the connection via 221 and the gate via 222 are located directly above the gate structure 202 covered by the effective region of the transistor, thereby saving a lot of working area and improving the integration of the semiconductor device.
[0075] Specifically, the method for forming the connection via 221, gate via 222, and source / drain via 223 includes: forming a patterned layer (not shown) on the second dielectric layer 220, the patterned layer exposing a portion of the gate structure 202 and the surface of the source / drain contact layer 207; using the patterned layer as a mask, etching the second dielectric layer 220 until the surface of the etch stop layer 210 is exposed, to form the connection via 221, gate via 222, and source / drain via 223 located within the second dielectric layer 220.
[0076] In this embodiment, the etching process of the second dielectric layer 220 includes a dry etching process.
[0077] Please refer to Figure 11 and Figure 12 , Figure 11 and Figure 8 The view orientation is consistent. Figure 12 and Figure 9 The view orientation is consistent.
[0078] The etching stop layer 210 under the connection via 221, gate via 222 and source / drain via 223 is etched until the top surface of the gate structure 202 and the source / drain contact layer 207 is exposed; a connection plug 241 is formed in the connection via 221, a gate plug 242 is formed in the gate via 222 and a source / drain plug 243 is formed in the source / drain via 223.
[0079] Since the thickness of the etch stop layer 210 on the gate structure 202 is the same as the thickness on the source / drain contact layer 207, the etching degree of the etch stop layer 210 on the gate structure 202 and the source / drain contact layer 207 can be ensured to be the same during the etch of the etch stop layer 210 until the gate structure 202 and the source / drain contact layer 207 are exposed. This avoids the problem of local over-etching, reduces the damage to the source / drain contact layer 207, reduces structural defects, and thus improves device stability and device performance.
[0080] In this embodiment, the source / drain plug 243, the gate plug 242, and the connection plug 241 are formed simultaneously.
[0081] Specifically, the method for forming the source / drain plug 243, gate plug 242, and connection plug 241 includes: depositing a source / drain plug material layer (not shown), a gate plug material layer (not shown), and a connection plug material layer (not shown) in the source / drain via 223, the gate via 222, and the connection via 221; and planarizing the source / drain plug material layer, the gate plug material layer, and the connection plug material layer until the surface of the second dielectric layer 220 is exposed, thereby forming the source / drain plug 243, the gate plug 242, and the connection plug 241.
[0082] The source / drain plug 243 connects the source / drain contact layer 207 to the upper electrical interconnect structure (not shown); the gate plug 242 connects the gate structure 202 to the upper electrical interconnect structure; the connection plug 241 connects the gate structure 202 to the source / drain contact layer 207, so that the two have the same potential, and at the same time connect the two to the upper electrical interconnect structure.
[0083] In this embodiment, the deposition process of the source / drain plug material layer includes chemical vapor deposition; the deposition process of the gate plug material layer includes chemical vapor deposition; and the deposition process of the connection plug material layer includes chemical vapor deposition.
[0084] In this embodiment, the source / drain plug 243, gate plug 242, and connection plug 241 are made of tungsten.
[0085] In another embodiment, the source / drain via is formed after the gate plug and the connection plug are formed.
[0086] Specifically, the method for forming the connection via, gate via, source / drain via, source / drain plug, gate plug, and connection plug includes: forming a gate via and a connection via in a second dielectric layer; depositing a gate plug material layer and a connection plug material layer in the gate via and the connection via; planarizing the gate plug material layer and the connection plug material layer to form a gate plug and a connection plug; after forming the gate plug and the connection plug, forming a third dielectric layer on the gate plug and the connection plug; forming a source / drain via located in the third dielectric layer and the second dielectric layer, the source / drain via exposing the surface of the source / drain contact layer; depositing a source / drain plug material layer in the source / drain via; and planarizing the source / drain plug material layer to form a source / drain plug.
[0087] In other embodiments, a third dielectric layer may not be formed, and instead, after forming the gate plug and the connection plug, a source / drain via is directly formed within the second dielectric layer.
[0088] In this embodiment, the material of the source / drain plug material layer includes tungsten.
[0089] The deposition process for the source / drain plug material layer includes a selective tungsten deposition process. This selective tungsten deposition process improves the electrical contact between the formed source / drain plugs and other structures, thereby optimizing device performance.
[0090] In another embodiment, the gate via is formed after the source / drain plugs and connection plugs are formed.
[0091] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A plurality of gate structures, source / drain regions on both sides of each gate structure, a plurality of source / drain contact layers on the source / drain regions, and a first dielectric layer on the substrate are formed. The first dielectric layer exposes the top surfaces of each gate structure and each source / drain contact layer. The top surfaces of the source / drain contact layers are higher than the top surfaces of the gate structures. An etch stop layer is formed covering the top surface of each of the gate structures and each of the source and drain contact layers, wherein the thickness of the etch stop layer on the gate structure is the same as the thickness on the source and drain contact layer; A second dielectric layer is formed on the etching stop layer; The second dielectric layer is etched to form a connection via spanning a portion of the gate structure and a portion of the source / drain contact layer within the second dielectric layer. The connection via includes a first sub-via and a second sub-via that are interconnected. The first sub-via is located on a portion of the gate structure, and the second sub-via is located on a portion of the source / drain contact layer. The connection via exposes the surface of the etch stop layer. Etch the etch stop layer under the via until the top surface of the gate structure and the source / drain contact layer is exposed; A connecting plug is formed within the connecting through hole.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: A gate via and a source / drain via are formed in a portion of the gate structure within the second dielectric layer; a gate plug and a source / drain plug are formed within the gate via and the source / drain via, respectively.
3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The source / drain via, gate via, and connection via are formed simultaneously; the source / drain plug, gate plug, and connection plug are formed simultaneously.
4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The method for forming the source / drain plug, gate plug, and connection plug includes: depositing a source / drain plug material layer, a gate plug material layer, and a connection plug material layer in the source / drain via, the gate via, and the connection via; and planarizing the source / drain plug material layer, the gate plug material layer, and the connection plug material layer to form the source / drain plug, the gate plug, and the connection plug.
5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The deposition process of the source / drain plug material layer includes chemical vapor deposition; the deposition process of the gate plug material layer includes chemical vapor deposition; and the deposition process of the connection plug material layer includes chemical vapor deposition.
6. The method for forming a semiconductor structure as described in claim 2, characterized in that, After forming the gate plug and the connection plug, the source and drain vias are formed.
7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The method for forming the source / drain plug, gate plug, and connection plug includes: forming a gate via and a connection via in a second dielectric layer; depositing a gate plug material layer and a connection plug material layer in the gate via and the connection via; planarizing the gate plug material layer and the connection plug material layer to form the gate plug and the connection plug; after forming the gate plug and the connection plug, forming a source / drain via located in the second dielectric layer; depositing a source / drain plug material layer in the source / drain via; and planarizing the source / drain plug material layer to form the source / drain plug.
8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The material of the source / drain plug layer includes tungsten.
9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The deposition process of the source / drain plug material layer includes a selective tungsten deposition process.
10. The method for forming a semiconductor structure as described in claim 2, characterized in that, After forming the source / drain plugs and the connection plugs, the gate via is formed.
11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method of forming the gate structure, source / drain regions, source / drain contact layer, and first dielectric layer includes: forming a gate structure on the substrate, source / drain regions on both sides of the gate structure, and an initial first dielectric layer surrounding the gate structure; forming a source / drain contact layer on the surface of the source / drain regions within the initial first dielectric layer; and thinning the initial first dielectric layer until the top surfaces of the gate structure and the source / drain contact layer are exposed to form the first dielectric layer.
12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first dielectric layer is located between the gate structure and the source / drain contact layer, and the top surface of the first dielectric layer is lower than the top surface of the gate structure, thereby creating a gap on the first dielectric layer between the gate structure and the source / drain contact layer.
13. The method for forming a semiconductor structure as described in claim 12, characterized in that, After forming the etch stop layer, the gap is sealed to form a cavity layer between the gate structure and the source / drain contact layer.
14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the etching stop layer ranges from 100 angstroms to 200 angstroms.
15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the source / drain contact layer includes cobalt.