Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure comprises: providing a substrate comprising a first device region and a second device region; forming a gate material layer on the substrate, and forming a first initial mask material layer on the gate material layer; performing a modification treatment on the first initial mask material layer in the first device region or the second device region, and the first initial mask material layer after the modification treatment serves as a second initial mask material layer, the first initial mask material layer and the second initial mask material layer have an etching selectivity ratio; patterning the first initial mask material layer and the second initial mask material layer to form an initial mask layer; forming a side wall covering a side wall of the initial mask layer; removing the initial mask layer in the second device region, and retaining the side wall and the initial mask layer in the first device region as a first mask layer, and retaining the side wall in the second device region as a second mask layer; and patterning the gate material layer by taking the first mask layer and the second mask layer as masks. The method is beneficial to improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. Transistors, as one of the basic semiconductor devices, are currently widely used. Therefore, as the density and integration of semiconductor devices increase, the gate size of transistors is becoming shorter and shorter. The ability of traditional planar transistors to control channel current weakens, resulting in short-channel effects, which increase leakage current and ultimately affect the electrical performance of semiconductor devices.

[0003] To better adapt to the shrinking feature size, semiconductor processes have gradually transitioned from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. However, with further reductions in feature size, the size and shape accuracy of the gate still have a significant impact on transistor performance, making it difficult to further improve the performance of FinFETs. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a method for forming a semiconductor structure, thereby improving the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a gate material layer is formed on the substrate, and a first initial mask material layer covering the gate material layer is formed on the gate material layer; the substrate includes a first device region for forming a first transistor and a second device region for forming a second transistor, wherein the channel length of the first transistor is greater than the channel length of the second transistor; modifying the first initial mask material layer in the first device region or the second device region, wherein the modified first initial mask material layer serves as a second initial mask material layer, and the first initial mask material layer and the second initial mask material layer are connected... The mask material layers have an etching selectivity ratio; the first initial mask material layer and the second initial mask material layer are patterned to form initial mask layers discretely located in the first device region and the second device region; a sidewall is formed covering the sidewall of the initial mask layer; after forming the sidewall, the initial mask layer located in the second device region is removed, and the sidewall and the initial mask layer located in the first device region are retained as the first mask layer, and the sidewall located in the second device region is retained as the second mask layer; using the first mask layer and the second mask layer as masks, the gate material layer is patterned, and the gate material layer is patterned as a first gate layer and a second gate layer located on the substrates of the first device region and the second device region, respectively.

[0006] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0007] In the formation method provided by this embodiment of the invention, the first initial mask material layer in the first device region or the second device region is modified, and there is an etching selectivity ratio between the first initial mask material layer and the second initial mask material layer. In this embodiment of the invention, there is an etching selectivity ratio between the first initial mask material layer and the second initial mask material layer, and correspondingly, there is an etching selectivity ratio between the initial mask layer of the first device region and the initial mask layer of the second device region. This allows the initial mask layer of the first device region to be retained while the initial mask layer of the second device region is removed after the sidewalls are formed. This allows the sidewalls and the initial mask layer located in the first device region to be retained as the first mask layer, and the sidewalls located in the second device region to be retained as the second mask layer. This results in the width of the first mask layer being greater than the width of the second mask layer, and the width of the first gate layer being greater than the width of the second gate layer, satisfying the requirement that the channel length of the first transistor is greater than that of the second transistor. The invention addresses the channel length requirements of the transistor. Furthermore, the embodiments of the invention allow the use of the same photomask to form the initial mask layers for the first and second device regions, resulting in better height uniformity of the initial mask layer. Consequently, the height uniformity of the first and second mask layers is also better. This saves on process costs and facilitates better height uniformity of the first and second gate layers after patterning the gate material layer. Additionally, the embodiments of the invention allow for flexible selection of sidewall materials, making it easier to choose materials with similar etching selectivity to the initial mask layer of the first device region. This ensures similar etching selectivity between the first and second mask layers, reducing the probability of premature removal of either the first or second mask layer during the patterning of the gate material layer using the first and second mask layers as masks. This results in better height consistency between the first and second gate layers, which in turn improves the performance of the semiconductor structure. Attached Figure Description

[0008] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0009] Figures 6 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0010] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific semiconductor structure formation method as an example.

[0011] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] refer to Figure 1 A substrate 10 is provided, on which a gate material layer 20 is formed and a mask material layer 30 is formed. The substrate 10 includes a first device region 10L for forming a first transistor and a second device region 10S for forming a second transistor, wherein the channel length of the first transistor is greater than the channel length of the second transistor.

[0013] Continue to refer to Figure 1 A core material layer (not shown) is formed on the mask material layer 30; the core material layer is patterned to form a core layer 40 discrete in the second device region 10S; a sidewall 41 is formed on the sidewall of the core layer 40.

[0014] refer to Figure 2 After the sidewall 41 is formed, the core layer 40 is removed, and the sidewall 41 is retained as the second mask layer 52.

[0015] refer to Figure 3 A pattern material layer 50 is formed covering the first device region 10L and the second device region 10S, and the pattern material layer 50 also covers the second mask layer 52.

[0016] Since the pattern material layer 50 covering the second mask layer 52 needs to be removed subsequently, the pattern material layer 50 needs to be a material that is easy to remove and has a large etching selectivity ratio with the material of the second mask layer 52. Typically, the material of the pattern material layer 50 is spin-on carbon (SOC).

[0017] refer to Figure 4 The pattern material layer 50 is patterned to form a first mask layer 51 discretely located in the first device region 10L.

[0018] refer to Figure 5 Using the first mask layer 51 and the second mask layer 52 as masks, the mask material layer 30 and the gate material layer 20 are patterned sequentially. The mask material layer 30 is patterned as the gate mask layer 31, and the gate material 20 is patterned as the first gate layer 21 and the second gate layer 22 located on the substrate 10 of the first device region 10L and the second device region 10S, respectively.

[0019] Because the etching selectivity of the pattern material layer 50 and the second mask layer 52 is relatively large, the etching selectivity of the first mask layer 51 and the second mask layer 52 is also relatively large. Therefore, the etching rates of the first mask layer 51 and the second mask layer 52 differ significantly. Furthermore, since the materials of the first mask layer 51 and the second mask layer 52 are different, it is difficult to adjust the etching time of the first mask layer 51 and the second mask layer 52 by adjusting their heights. Thus, when using the first mask layer 51 and the second mask layer 52 as masks, the mask material layer 30 and the gate material layer 20 are patterned sequentially. During the process, it is easy for one of the first mask layer 51 and the second mask layer 52 to be removed first, resulting in poor height consistency between the first gate layer 21 and the second gate layer 22, which affects the performance of the semiconductor structure. Moreover, it is easy to cause over-etching of the gate mask layer 31, which is difficult to cover the top of the first gate layer 21 and the second gate layer 22. As a result, in the subsequent step of forming the source and drain doped layer, it is easy to form the top of the first gate layer 21 or the second gate layer 22 that is not completely covered by the gate mask layer 31, which affects the reliability of the device and may even damage the device.

[0020] Furthermore, since the first mask layer 51 is formed by patterning the pattern material layer 50, the material of the first mask layer 51 is limited by the second mask layer 52. Specifically, in order to facilitate the patterning of the pattern material layer 50 and reduce damage to the second mask layer 52, the pattern material layer 50 is usually made of an easily etchable material, which results in a lower etch resistance of the first mask layer 51. During the sequential patterning of the mask material layer 30 and the gate material layer 20, the etching rate of the first mask layer 51 is correspondingly faster (for example, if the material of the pattern material layer 50 is SOC, then the material of the first mask layer 51 is also SOC. SOC has lower hardness and is etched faster). Therefore, the first mask layer 51 is more likely to be removed earlier. To compensate for the difference in etching resistance between the first mask layer 51 and the second mask layer 52, the height of the first mask layer 51 can be increased. However, this can easily lead to SOC distortion. Moreover, during the etching process of the SOC, a large amount of polymer residue is easily generated, affecting subsequent process steps. At the same time, the linewidth roughness of the SOC is relatively large. Therefore, when etching the gate material layer 20 using the first mask layer 51 as a mask, the linewidth roughness of the first gate layer 21 is also likely to be relatively large. Furthermore, the channel length of the first device region 10L is relatively large. In device regions with large channel lengths, the length difference between different channels is usually large, which in turn leads to a large width difference between different first mask layers 51. This further results in poor dimensional accuracy of the first mask layer 51, and further leads to a large linewidth roughness of the first gate layer 21, affecting the dimensional and morphological accuracy of the first gate layer 21, and thus affecting the performance of the semiconductor structure.

[0021] In this embodiment of the invention, there is an etching selectivity ratio between the first initial mask material layer and the second initial mask material layer, and correspondingly, there is an etching selectivity ratio between the initial mask layer of the first device region and the initial mask layer of the second device region. This allows the initial mask layer of the first device region to be retained while the initial mask layer of the second device region is removed after the sidewalls are formed. This ensures that the sidewalls and initial mask layer located in the first device region are retained as the first mask layer, and the sidewalls located in the second device region are retained as the second mask layer. This results in the width of the first mask layer being greater than the width of the second mask layer, and consequently, the width of the first gate layer is greater than the width of the second gate layer. This satisfies the requirement that the channel length of the first transistor is greater than the channel length of the second transistor. Furthermore, this embodiment of the invention can use the same photomask to form both the first and second device regions. The initial mask layer of the region has good height uniformity, and correspondingly, the height uniformity of the first mask layer and the second mask layer is also good. This saves process costs and helps to ensure good height uniformity of the first gate layer and the second gate layer after patterning the gate material layer. At the same time, the embodiments of the present invention can flexibly select the sidewall material, and it is easy to select a material with an etching selectivity similar to that of the initial mask layer of the first device region, so that the etching selectivity of the first mask layer and the second mask layer is similar. Therefore, in the process of patterning the gate material layer using the first mask layer and the second mask layer as masks, it helps to reduce the probability of either the first mask layer or the second mask layer being removed prematurely, thereby making the height consistency of the first gate layer and the second gate layer better, which is beneficial to improving the performance of the semiconductor structure.

[0022] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] Figures 6 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0024] refer to Figure 6 A substrate (not shown) is provided, on which a gate material layer 200 is formed, and a first initial mask material layer 410 covering the gate material layer 200 is formed on the gate material layer 200. The substrate includes a first device region 100L for forming a first transistor and a second device region 100S for forming a second transistor, wherein the channel length of the first transistor is greater than the channel length of the second transistor.

[0025] The substrate provides the basis for the process operations of semiconductor structure formation. These semiconductor structures include fin field-effect transistors and gate-all-around (GAA) transistors.

[0026] The substrate includes a first device region 100L for forming a first transistor and a second device region 100S for forming a second transistor, wherein the channel length of the first transistor is greater than the channel length of the second transistor.

[0027] In this embodiment, taking a fin field-effect transistor as an example, the substrate includes a substrate 100 and a fin 110 protruding from the substrate 100, and the gate material layer 200 covers the fin 110.

[0028] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0029] Fin 110 is used to provide a channel for a fin field-effect transistor.

[0030] In this embodiment, the material of the fin 110 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials.

[0031] After the first gate layer and the second gate layer are subsequently formed on the substrate of the first device region 100L and the second device region 100S, the portion of the fin 110 covered by the first gate layer and the second gate layer serves as a channel. The channel length of the first transistor is greater than the channel length of the second transistor, and the width of the subsequently formed first gate layer is greater than the width of the second gate layer.

[0032] The gate material layer 200 is used for the subsequent formation of the first gate layer and the second gate layer.

[0033] In this embodiment, a gate material layer 200 is formed first, and then the gate material layer 200 is patterned. In the same step, multiple first gate layers and second gate layers are formed in the first device region 100L and the second device region 100S, which simplifies the process flow and improves the process efficiency.

[0034] In this embodiment, the gate material layer 200 includes a dummy gate material layer for subsequent formation of a first dummy gate layer and a second dummy gate layer.

[0035] The pseudo-gate material layer can be a single-layer structure or a stacked structure. The material of the pseudo-gate material layer includes one or both of amorphous silicon and polycrystalline silicon. Alternatively, the material of the pseudo-gate material layer can also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, or amorphous carbon.

[0036] It should be noted that, depending on the process requirements, a gate oxide layer (not shown in the figure) may also be formed between the dummy gate material layer and the fin 110. The material of the gate oxide layer can be silicon oxide.

[0037] In this embodiment, a gate mask material layer 300 is also formed on the gate material layer 200, and the first initial mask material layer 410 covers the gate mask material layer 300.

[0038] The gate mask material layer 300 is used for subsequent formation of the gate mask layer.

[0039] Specifically, the gate mask material layer 300 is made of one or more of silicon oxide and silicon nitride, meaning the gate mask material layer 300 can be a single-layer structure or a stacked structure. As an example, the gate mask material layer 300 is made of silicon oxide and silicon nitride, meaning the gate mask material layer 300 is a stacked structure, including a silicon nitride layer 310 and a silicon oxide layer 320 covering the silicon nitride layer 310.

[0040] The first initial mask material layer 410 is used to form the subsequent initial mask layer.

[0041] In this embodiment, the material of the first initial mask material layer 410 includes silicon or silicon carbide. As an example, in this embodiment, the material of the first initial mask material layer 410 is silicon.

[0042] Since the first initial mask material layer 410 of the first device region 100L or the second device region 100S needs to be modified by ion implantation, using silicon or silicon carbide as the first initial mask material layer 410 is beneficial to forming a second initial mask material layer with an etching selectivity ratio to the first initial mask material layer 410 through ion implantation.

[0043] Reference Figure 6 and Figure 7 The first initial mask material layer 410 in the first device region 100L or the second device region 100S is modified, and the modified first initial mask material layer 410 serves as the second initial mask material layer 420. There is an etching selectivity between the first initial mask material layer 410 and the second initial mask material layer 420.

[0044] In this embodiment, there is an etching selectivity between the first initial mask material layer 410 and the second initial mask material layer 420. Correspondingly, there is an etching selectivity between the initial mask layer of the first device region 100L and the initial mask layer of the second device region 100S. Subsequently, after the sidewalls are formed, the initial mask layer of the second device region 100S can be removed while the initial mask layer of the first device region 100L is retained. This allows the sidewalls and initial mask layer of the first device region 100L to be retained as the first mask layer, and the sidewalls of the second device region 100S to be retained as the second mask layer. This results in the width of the first mask layer being greater than that of the second mask layer. The width of the mask layer is such that the width of the first gate layer is greater than the width of the second gate layer, satisfying the requirement that the channel length of the first transistor is greater than the channel length of the second transistor. Moreover, this embodiment can use the same photomask to form the initial mask layers of the first device region 100L and the second device region 100S, thus the height uniformity of the initial mask layer is better, and the height uniformity of the first mask layer and the second mask layer is also better. While saving process costs, it is beneficial to make the height uniformity of the first gate layer and the second gate layer better after the patterned gate material layer is formed, which is beneficial to improving the performance of the semiconductor structure.

[0045] It should be noted that in this embodiment, the etching selectivity ratio of the first initial mask material layer 410 to the second initial mask material layer 420 should not be too small. If the etching selectivity ratio of the first initial mask material layer 410 to the second initial mask material layer 420 is too small, then the etching selectivity ratio of the initial mask layer 500 of the first device region 100L to the initial mask layer 500 of the second device region 100S will be too small. Subsequently, after the sidewalls are formed, when removing the initial mask layer 500 of the second device region 100S, it will be difficult to retain the initial mask layer 500 of the first device region 100L, thereby affecting the formation of the first and second mask layers, and consequently affecting the formation of the first gate layer and the second gate layer. Therefore, in this embodiment, the etching selectivity ratio of the first initial mask material layer 410 to the second initial mask material layer 420 is greater than 10:1.

[0046] In this embodiment, the modification treatment uses an ion implantation process.

[0047] Ion implantation is a process that involves injecting ions accelerated to a certain high energy into a solid material layer to change the physical and chemical properties of the solid material layer. It has the advantages of high efficiency and strong modified layer. Furthermore, ion implantation can precisely control the doping concentration and distribution of ions and has good control over the penetration depth of solid materials, which is conducive to achieving the modification treatment of the first initial mask material layer 410 in accordance with the process requirements.

[0048] In this embodiment, the implanted ions in the ion implantation process include one or more of B, As, P, and C.

[0049] In this embodiment, the material of the first initial mask material layer 410 is silicon. After implanting one or more ions of B, As, P and C into the silicon material, the properties of the silicon material can be changed, resulting in a larger etching selectivity between the silicon material and the ion-implanted silicon material. This allows the initial mask layer of the first device region 100L to be retained after the sidewalls are formed and the initial mask layer of the second device region 100S is removed. Thus, the sidewalls and the initial mask layer of the first device region 100L are retained as the first mask layer, and the sidewalls of the second device region 100S are retained as the second mask layer. This makes the width of the first mask layer greater than the width of the second mask layer, and the width of the first gate layer is greater than the width of the second gate layer, satisfying the requirement that the channel length of the first transistor is greater than the channel length of the second transistor.

[0050] It should be noted that the ion implantation dose in the ion implantation process should not be too large or too small. If the ion implantation dose is too high in the ion implantation process, the ion implantation range will be too large, making the process difficult to control. Consequently, implanted ions may diffuse into the first initial mask material layer 410 of the second device region 100S, affecting the etching selectivity between the initial mask layers of the first device region 100L and the second device region 100S, thus affecting the formation of the first gate layer and the second gate layer. If the ion implantation dose is too low in the ion implantation process, the ion implantation reaction time will be too long, reducing the efficiency of the process and failing to achieve the desired process effect. Furthermore, the etching resistance of the second mask material layer 420 and the first mask material layer 410 may be similar, making it difficult to form a large etching selectivity. Consequently, when removing the initial mask layer of the second device region 100S after the sidewalls are formed, the initial mask layer of the first device region 100L may be damaged, affecting the formation of the first mask layer and the second mask layer, and thus affecting the formation of the first gate layer and the second gate layer. Therefore, in this embodiment, the ion implantation dose in the ion implantation process is 1×10⁻⁶. 12 ions / cm 2 Up to 2×10 18 ions / cm 2 .

[0051] It should also be noted that the implantation energy in the ion implantation process should not be too high or too low. If the implantation energy is too high, the ion implantation range will be too large, making the process difficult to control; if the implantation energy is too low, the reaction time will be too long, reducing the efficiency of the process and affecting the formation of the second initial mask material layer 420. Therefore, in this embodiment, the implantation energy in the ion implantation process is between 1 keV and 600 keV.

[0052] Specifically, refer to Figure 6 The modification process includes forming a shielding layer 120 covering the first initial mask material layer 410 in either the first device region 100L or the second device region 100S, with the shielding layer 120 exposing the first initial mask material layer 410 in another region.

[0053] In this embodiment, the first initial mask material layer 410 in the first device region 100L is modified. Correspondingly, a shielding layer 120 covering the first initial mask material layer 410 is formed in the second device region 100S, and the shielding layer 120 exposes the first initial mask material layer 410 in the first device region 100L.

[0054] Specifically, the shielding layer 120 covers the first initial mask material layer 410 of the second device region 100S and exposes the first initial mask material layer 410 of the first device region 100L, in preparation for ion implantation of the first initial mask material layer 410 of the first device region 100L.

[0055] In this embodiment, the material of the shielding layer 120 includes photoresist, thus the operation of forming the shielding layer 120 is simple and easy.

[0056] It should be noted that in this embodiment, the shielding layer 120 only needs to shield the first initial mask material layer 410 of the first device region 100L. Therefore, the area covered by the shielding layer 120 is large, and the dimensional accuracy requirement of the shielding layer 120 is low. Thus, the shielding layer 120 can be formed using a first photomask with a lower accuracy requirement.

[0057] In other embodiments, the first initial mask material layer in the second device region may be modified. Correspondingly, a shielding layer covering the first initial mask material layer may be formed in the first device region, and the shielding layer exposes the first initial mask material layer in the second device region.

[0058] refer to Figure 7 The modification process also includes ion implantation of the first initial mask material layer 410 exposed by the shielding layer 120.

[0059] Ion implantation is used to create a large etching selectivity ratio between the second initial mask material layer 420 and the first initial mask material layer 410.

[0060] refer to Figure 8 After modification, it also includes: removing the masking layer 120.

[0061] Remove the masking layer 120 to prepare for the subsequent patterning of the first initial mask material layer 410 and the second initial mask material layer 420.

[0062] Reference Figure 9 and Figure 10 The first initial mask material layer 410 and the second initial mask material layer 420 are patterned to form an initial mask layer 500 discretely located in the first device region 100L and the second device region 100S.

[0063] This embodiment can use the same photomask to form the initial mask layer 500 of the first device region 100L and the second device region 100S. Therefore, the height uniformity of the initial mask layer 500 is better, and the height uniformity of the subsequently formed first mask layer and second mask layer is also better. While saving process costs, it is also beneficial to make the height uniformity of the first gate layer and the second gate layer better after the patterned gate material layer is formed, which is beneficial to improving the performance of the semiconductor structure.

[0064] The initial mask layer 500 is used to provide support for the subsequent formation of the sidewalls and together with the sidewalls constitutes the first mask layer.

[0065] Accordingly, in this embodiment, the initial mask layer 500 of the first device region 100L and the second device region 100S has an etching selectivity ratio.

[0066] Specifically, refer to Figure 9 The step of patterning the first initial mask material layer 410 and the second initial mask material layer 420 includes forming an etching mask 400 discretely distributed on the first device region 100L and the second device region 100S on the first initial mask material layer 410 and the second initial mask material layer 420.

[0067] The etching mask 400 is used as a mask for patterning the first initial mask material layer 410 and the second initial mask material layer 420.

[0068] It should be noted that since the etching mask 400 is used as a mask to form the initial mask layer 500, the position and size accuracy of the etching mask 400 are required to be high. Therefore, a second photomask with high precision is required to form the etching mask 400. Compared with the requirement to use two photomasks with high precision to form the initial mask layers of the first device area and the second device area respectively, in this embodiment, a first photomask with lower precision is used to form the shielding layer 120, and then a second photomask with higher precision is used to form the etching mask 400. This reduces the requirements for photomask fabrication and saves process costs accordingly.

[0069] refer to Figure 10 Pattern the first initial mask material layer 410 and the second initial mask material layer 420 along the etch mask 400.

[0070] By etching the mask 400 to transfer the pattern to the first initial mask material layer 410 and the second initial mask material layer 420, it is beneficial to improve the pattern accuracy of the initial mask layer 500.

[0071] In this embodiment, a dry etching process is used to pattern the first initial mask material layer 410 and the second initial mask material layer 420 along the etching mask 400.

[0072] Dry etching is an anisotropic etching process, with a longitudinal etching rate much greater than a transverse etching rate. Therefore, by selecting dry etching, it is beneficial to improve the pattern transfer accuracy from the etching mask 400 to the first initial mask material layer 410 and the second initial mask material layer 420. At the same time, dry etching is more directional, which is beneficial to improve the sidewall morphology quality and dimensional accuracy of the initial mask layer 500.

[0073] Reference Figure 11 and Figure 12 This forms a sidewall 610 that covers the sidewall of the initial mask layer 500.

[0074] The sidewall 610 is used as a second mask layer for the gate material layer 200 of the subsequent patterning of the second device region 100S, and also serves together with the initial mask layer 500 as a first mask layer for the gate material layer 200 of the subsequent patterning of the first device region 100L.

[0075] This embodiment allows for flexible selection of the material for the sidewall 610, making it easy to select a material with an etching selectivity similar to that of the initial mask layer 500 of the first device region 100L. This results in similar etching selectivity between the first and second mask layers. Consequently, during the patterning of the gate material layer 200 using the first and second mask layers as masks, it helps to reduce the probability of either the first or second mask layer being removed prematurely. This leads to better height consistency between the first and second gate layers, which in turn improves the performance of the semiconductor structure.

[0076] In this embodiment, the material of the sidewall 610 includes silicon nitride or silicon carbide.

[0077] Silicon nitride or silicon carbide can form an etch selectivity similar to that of the initial mask layer 500, thereby making the etch selectivity of the first mask layer and the second mask layer similar.

[0078] Specifically, refer to Figure 11 The step of forming the sidewall 610 of the initial mask layer 500 includes forming a sidewall material layer 600 covering the sidewalls and top of the initial mask layer 500 and the top of the gate material layer 200.

[0079] Specifically, the sidewall material layer 600 covers the top of the gate mask material layer 300.

[0080] The sidewall material layer 600 is used to directly form the sidewall 610, and the material of the sidewall material layer 600 includes silicon nitride or silicon carbide.

[0081] In this embodiment, the sidewall material layer 600 is formed using atomic layer deposition (ALD).

[0082] The sidewall material layer 600 formed by atomic layer deposition has good thickness uniformity and good step coverage capability, which enables the sidewall material layer 600 to cover the sidewalls and top of the initial mask layer 500 and the top of the gate material layer 200 in a good conformal manner.

[0083] refer to Figure 12 Remove the sidewall material layer 600 located on top of the initial mask layer 500 and the gate material layer 200, and retain the sidewall material layer 600 located on the sidewall of the initial mask layer 500 as the sidewall 610.

[0084] Specifically, the sidewall material layer 600 located on top of the gate mask material layer 300 is removed.

[0085] In this embodiment, a dry etching process is used to remove the sidewall material layer 600 located on top of the initial mask layer 500 and on top of the gate material layer 200.

[0086] Dry etching is an anisotropic etching process. Therefore, by selecting dry etching, it is beneficial to reduce damage to the initial mask layer 410 and the gate mask material layer 300. At the same time, dry etching is more directional, which is beneficial to improve the sidewall morphology quality and dimensional accuracy of the sidewall 610.

[0087] refer to Figure 13 After forming the sidewall 610, the initial mask layer 500 located in the second device region 100S is removed, and the sidewall 610 and the initial mask layer 500 located in the first device region 100L are retained as the first mask layer 710, and the sidewall 610 located in the second device region 100S is retained as the second mask layer 720.

[0088] The first mask layer 710 is used as an etching mask for patterning the gate material layer 200 located in the first device region 100L, and the second mask layer 720 is used as an etching mask for patterning the gate material layer 200 located in the second device region 100S.

[0089] In this embodiment, after the sidewall 610 is formed, the initial mask layer 500 located in the second device region 100S is removed by a wet etching process.

[0090] Wet etching has the characteristics of isotropic etching, which is beneficial for completely removing the initial mask layer 500 located in the second device region 100S. Moreover, wet etching has relatively low cost and simple operation steps, and can achieve a large etching selectivity, which helps to reduce damage to the sidewalls 610 and the initial mask layer 500 of the first device region 100L during the removal of the initial mask layer 500 located in the second device region 100S.

[0091] In this embodiment, the first initial mask material layer 410 in the first device region 100L is modified, and correspondingly, the etching solution of the wet etching process includes ammonia.

[0092] Ammonia water has strong etching properties for silicon materials and can produce a large etching selectivity for silicon materials and silicon materials after ion implantation. Therefore, using ammonia water for wet etching is beneficial to reduce damage to the sidewalls 610 and the initial mask layer 500 of the first device region 100L during the removal of the initial mask layer 500 located in the second device region 100S.

[0093] In other embodiments, the first initial mask material layer in the second device region is modified, and accordingly, the etching solution of the wet etching process includes an HNA solution.

[0094] It should be noted that the HNA solution is a mixture of hydrofluoric acid, nitric acid, and acetic acid.

[0095] Specifically, the initial mask layer of the second device region is silicon material after ion implantation, and the initial mask layer of the first device region is silicon material. The HNA solution has strong etching ability on silicon material after ion implantation and can produce a large etching selectivity ratio between silicon material and silicon material after ion implantation. Therefore, using HNA solution for wet etching is beneficial to reduce damage to the sidewalls and the initial mask layer of the first device region during the removal of the initial mask layer located in the second device region.

[0096] Specifically, in the HNA solution, the molar ratio of hydrofluoric acid, nitric acid, and acetic acid is 1:1:2, which enables a greater etching selectivity for both silicon materials and ion-implanted silicon materials.

[0097] refer to Figure 14 Using the first mask layer 710 and the second mask layer 720 as masks, the gate material layer 200 is patterned, and the gate material layer 200 is patterned into a first gate layer 210 and a second gate layer 220 respectively located on the substrates of the first device region 100L and the second device region 100S.

[0098] In this embodiment, the first gate layer 210 and the second gate layer 220 respectively span the fins 110 of the first device region 100L and the second device region 100S.

[0099] In this embodiment, the first gate layer 210 is used as the first pseudo gate layer 230, and the second gate layer 220 is used as the second pseudo gate layer 240.

[0100] The first pseudo-gate layer 230 and the second pseudo-gate layer 240 are used to occupy space for the subsequent formation of the gate structure.

[0101] Specifically, before patterning the gate material layer 200 using the first mask layer 710 and the second mask layer 720 as masks, the method further includes: patterning the gate mask material layer 300 using the first mask layer 710 and the second mask layer 720 as masks to form a gate mask 330.

[0102] The patterned gate mask material layer 300 passes the pattern downward through the gate mask 330 formed after patterning, which helps to improve the stability of the patterning process and the accuracy of pattern transfer, forming a first gate layer 210 and a second gate layer 220 with high dimensional accuracy.

[0103] Specifically, the gate mask material layer 300 includes a silicon nitride layer 310 and a silicon oxide layer 320 covering the silicon nitride layer 310. Therefore, the gate mask 330 includes a first gate mask 340 and a second gate mask 350 covering the first gate mask 340. The material of the first gate mask 340 is silicon nitride, and the material of the second gate mask 350 is silicon oxide.

[0104] Accordingly, in this embodiment, the gate material layer 200 is patterned using the gate mask 330 as a mask.

[0105] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which a gate material layer is formed, and a first initial mask material layer covering the gate material layer is formed on the gate material layer. The substrate includes a first device region for forming a first transistor and a second device region for forming a second transistor, wherein the channel length of the first transistor is greater than the channel length of the second transistor. The first initial mask material layer in the first device region or the second device region is modified, and the modified first initial mask material layer is used as the second initial mask material layer. There is an etching selectivity between the first initial mask material layer and the second initial mask material layer. The first initial mask material layer and the second initial mask material layer are graphically represented to form initial mask layers discretely located in the first device region and the second device region. A sidewall is formed that covers the sidewall of the initial mask layer; wherein the material selected for the sidewall is used to improve the consistency of the etching rate between the sidewall and the initial mask layer of the first device region; After the sidewalls are formed, the initial mask layer located in the second device region is removed, and the sidewalls and the initial mask layer located in the first device region are retained as the first mask layer, and the sidewalls located in the second device region are retained as the second mask layer. Using the first mask layer and the second mask layer as masks, the gate material layer is patterned, and the gate material layer is patterned as a first gate layer and a second gate layer located on the substrates of the first device region and the second device region, respectively.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The modification process includes ion implantation.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The implanted ions in the ion implantation process include one or more of B, As, P, and C.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The modification process includes: forming a shielding layer covering the first initial mask material layer in either the first device region or the second device region, wherein the shielding layer exposes the first initial mask material layer in another region; Ion implantation is performed on the first initial mask material layer exposed by the shielding layer; After the modification process, the method further includes removing the masking layer.

5. The method for forming a semiconductor structure as described in claim 2, characterized in that, The ion implantation process described above uses an implantation energy of 1 keV to 600 keV and an implantation dose of 1 × 10⁻⁶. 12 ions / cm 2 Up to 2×10 18 ions / cm 2 .

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first initial mask material layer includes silicon or silicon carbide.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The initial mask layer located in the second device region is removed using a wet etching process.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The first initial mask material layer in the first device region is modified. In the step of removing the initial mask layer located in the second device region using a wet etching process, the etching solution of the wet etching process includes ammonia. Alternatively, the first initial mask material layer in the second device region may be modified. In the step of removing the initial mask layer located in the second device region using a wet etching process, the etching solution of the wet etching process includes an HNA solution.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of patterning the first initial mask material layer and the second initial mask material layer includes: forming an etching mask discretely distributed between the first device region and the second device region on the first initial mask material layer and the second initial mask material layer; Pattern the first initial mask material layer and the second initial mask material layer along the etched mask.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The first initial mask material layer and the second initial mask material layer are patterned along the etched mask using a dry etching process.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a sidewall covering the sidewall of the initial mask layer includes: forming a sidewall material layer covering the top and sidewall of the initial mask layer and the top of the gate material layer; Remove the sidewall material layer located on top of the initial mask layer and on top of the gate material layer, and retain the sidewall material layer located on the sidewall of the initial mask layer as the sidewall.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, a gate mask material layer is further formed on the gate material layer, and the first initial mask material layer covers the gate mask material layer; Before patterning the gate material layer using the first mask layer and the second mask layer as masks, the method further includes: patterning the gate mask material layer using the first mask layer and the second mask layer as masks to form a gate mask; The step of patterning the gate material layer using the first mask layer and the second mask layer as masks includes: using the gate mask as a mask to pattern the gate material layer.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of modifying the first initial mask material layer in the first device region or the second device region, the first initial mask material layer and the second initial mask material layer are made to satisfy the following: the etching selectivity ratio of the first initial mask material layer to the second initial mask material layer is greater than 10:

1.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming a sidewall covering the sidewall of the initial mask layer, the material of the sidewall includes silicon nitride or silicon oxide.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The gate material layer includes a dummy gate material layer; In the step of patterning the gate material layer, the first gate layer is used as a first pseudo-gate layer, and the second gate layer is used as a second pseudo-gate layer.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing a substrate, the substrate includes a substrate and fins protruding from the substrate, and the gate material layer covers the fins; In the step of patterning the gate material layer, the first gate layer and the second gate layer respectively span the fins of the first device region and the second device region.

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