Structure of a chip package substrate and method of manufacturing the same

Abstract

The present application relates to chip packaging technical field, specifically a kind of structure and its manufacturing method of chip packaging substrate.It is a kind of structure of chip packaging substrate, including substrate, it is characterized in that:the chemical copper plating layer is provided on the two sides of the substrate respectively, the electroplated copper layer is provided on the outside of chemical copper plating layer, the mounting hole is provided on the chemical copper plating layer of substrate side or both sides, the silicon chip is provided in mounting hole, the dry film of solder mask is provided on the outside of substrate, the dry film of solder mask side is provided with a plurality of memory chips, the control chip is provided on the side of memory chip, the electroplated nickel gold layer is provided on the side or both sides of electroplated copper layer.Compared with prior art, structure and method process is simple, the thermal expansion coefficient of silicon chip is lower than green paint ink, fills in green paint, can reduce the CTE of substrate as a whole to some extent, to reduce the board warping.The solder mask process operation is convenient, twice green paint, twice solder mask film, vacuum extraction and vacuum extraction and pressure film operation process are same.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, specifically to a structure of a chip packaging substrate and its manufacturing method. Background Technology

[0002] Currently, ordinary substrates use many materials in the manufacturing process. Due to differences in material properties and coefficients of thermal expansion (copper's linear coefficient of thermal expansion is 17 × 10⁻⁶), these materials are used in various ways. -6 / ℃, the linear thermal expansion coefficient of insulating materials can be between 15×10 -6 / ℃~50×10 -6 (Between / ℃) This can cause uneven linear expansion of the substrate during heating, resulting in substrate warping. This can then lead to die cracks or delamination abnormalities during or after chip mounting. The internationally accepted standard for common packaging substrates, IPC-6012 Class II, requires warping to be less than 0.7%. However, due to the trend towards thinner, smaller, and denser products, many thin substrates now have increasingly stringent warping control requirements, with some customers even demanding a standard of 0.3%. Traditional manufacturing processes cannot meet these precision requirements.

[0003] Current substrate manufacturing processes offer numerous solutions to address board warping issues, including: ensuring consistent residual copper content on both sides, consistent residual green paint on both sides, using grids or dummy pads on strip edges to reduce stress, and improving the clamping methods of fixtures during production. While these improvements can partially reduce board warping, they cannot completely eliminate it. Summary of the Invention

[0004] To overcome the shortcomings of the prior art, this invention provides a structure of a chip packaging substrate and a method for manufacturing the same.

[0005] To achieve the above objectives, a chip packaging substrate structure is designed, comprising a substrate, characterized in that: chemically plated copper layers are respectively provided on both sides of the substrate, an electroplated copper layer is provided on the outer side of the chemically plated copper layers, mounting holes are provided on one or both sides of the chemically plated copper layers of the substrate, silicon wafers are provided in the mounting holes, a solder resist dry film is provided on the outer side of the substrate, a plurality of memory chips are provided on one side of the solder resist dry film, a control chip is provided on one side of the memory chips, and an electroplated nickel-gold layer is provided on one or both sides of the electroplated copper layers.

[0006] One end of the silicon wafer is connected to the substrate, and the other end of the silicon wafer is flush with the electroplated copper layer.

[0007] The silicon wafer and the substrate are connected by one of the following structures: mortise and tenon structure, slot structure, or chain structure.

[0008] The memory chip and control chip are encapsulated with a plastic layer on their outer side.

[0009] The aforementioned memory chips are arranged in a staggered, stepped pattern.

[0010] An adhesive layer is provided between the plurality of memory chips, between the memory chips and the solder resist dry film, and between the control chip and the solder resist dry film.

[0011] Several memory chips are electrically connected to each other via a gold wire one, and the memory chips are electrically connected to the electroplated nickel-gold layer via a gold wire two. The control chip is electrically connected to the electroplated nickel-gold layer via a gold wire three.

[0012] A tin ball is connected to one side of the electroplated nickel-gold layer.

[0013] A method for fabricating a chip packaging substrate includes the following steps: S1 provides a substrate; S2, Drill holes in the substrate; S3, remove adhesive residue and perform chemical copper plating on the hole walls of the substrate drilled holes; S4, chemical copper plating on the wall of the drilled hole in the substrate; S5, etching the electroplated copper layer to form conductive lines, fingers, and solder pads; S6, first anti-welding, filling holes and exposing green paint windows; S7, adhesive bonding, embedded silicon wafer; S8, secondary solder resist, the solder resist coating is applied to the silicon wafer and copper layer, and the bonding fingers and solder pads are exposed; S9, the surface treatment of the stringing fingers and solder pads is nickel-gold plated to form an electroplated nickel-gold layer; S10, embeds the memory chip and control chip, and forms an electrical connection; S11, plastic sealed; S12, shaping, appearance inspection, and packaging.

[0014] The specific methods for steps S6 to S9 are as follows: A1: Pre-treatment before soldering; A2: The first use involves applying a solder resist dry film with a thickness of 1 / 2 of the required thickness, and then pressing the film to fill the spaces between the circuits on the substrate and the vias of the substrate. A3: After exposure and development, solder mask openings are exposed at the edge of the substrate to form mounting holes, facilitating the placement of silicon wafers. The PET protective film on the solder mask surface is removed before development. A4: Apply a layer of colloid to the exposed weld shielding opening; A5, using a chip mounter to attach silicon wafers to one or both sides of the substrate; A6, after the silicon wafer is attached, it is cured and fixed by low-temperature baking in a nitrogen oven; A7: Second pre-welding treatment; A8, apply a second layer of solder resist dry film with half the required thickness, and press the film to make the solder resist thickness on the substrate reach the required solder resist thickness. A9, expose and develop to create nickel-gold plating windows, forming an electroplated nickel-gold layer; A10 was subjected to UV curing and post-curing respectively.

[0015] Compared with the prior art, the present invention has the following advantages: 1. The structure and process are simple. The coefficient of thermal expansion of silicon wafers is much lower than that of green paint ink. When filled under green paint, the CTE of the substrate can be reduced to a certain extent, thereby reducing board warping.

[0016] 2. The secondary green paint solder resist process is easy to operate. The process of applying solder resist film twice and vacuuming and pressing the film is the same as that of applying solder resist film once and vacuuming and pressing the film.

[0017] 3. Secondary solder resist can increase the flatness of the solder resist surface of the packaging substrate, improve the reliability of chip packaging products, and make the adhesion between the wafer and the substrate stronger.

[0018] 4. Secondary solder resist can reduce the risk of residual air bubbles in the vias of the packaging substrate and reduce the reliability risk of the package bursting due to high temperature. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of the present invention.

[0020] Figure 2 This is a flowchart of the present invention.

[0021] Figure 3 The following is a flowchart of steps S6 to S8 of the present invention.

[0022] Figure 4 This is a schematic diagram of the circuit board before the first solder resisting step S6 of the present invention.

[0023] Figure 5 This is a schematic diagram of the first anti-soldering step S6 of the present invention.

[0024] Figure 6 This is a schematic diagram of step S7 of the present invention, which involves embedding a silicon wafer.

[0025] Figure 7 This is a schematic diagram of the second anti-welding step S8 of the present invention.

[0026] Figure 8 This is a schematic diagram of step S9 of the present invention, which involves forming an electroplated nickel-gold layer.

[0027] Figure 9 This is a schematic diagram of the mortise and tenon connection between the substrate and the silicon wafer of the present invention.

[0028] Figure 10 This is a schematic diagram of the connection between the substrate and the silicon wafer slot of the present invention.

[0029] Figure 11 This is a schematic diagram of the structure connecting the substrate and the silicon wafer chain of the present invention.

[0030] Figure 12 This is a cross-sectional view of the connection between the substrate and the silicon wafer chain of the present invention. Detailed Implementation

[0031] The present invention will now be further described with reference to the accompanying drawings.

[0032] like Figure 1 As shown, a chemically plated copper layer 2 is provided on both sides of the substrate 1, and an electroplated copper layer 3 is provided on the outside of the chemically plated copper layer 2. Mounting holes 12 are provided on one or both sides of the chemically plated copper layer 2 of the substrate 1. A silicon wafer 5 is provided in the mounting holes 12. A solder resist dry film 4 is provided on the outside of the substrate 1. A plurality of memory chips 6 are provided on one side of the solder resist dry film 4. A control chip 11 is provided on one side of the memory chip 6. An electroplated nickel-gold layer 14 is provided on one or both sides of the electroplated copper layer 3.

[0033] One end of the silicon wafer 5 is connected to the substrate 1, and the other end of the silicon wafer 5 is flush with the electroplated copper layer 3.

[0034] like Figures 9 to 12 As shown, the silicon wafer 5 and the substrate 1 are connected by one of the following structures: mortise and tenon structure, slot structure, or chain structure.

[0035] The memory chip 6 and the control chip 11 are encapsulated in plastic layer 9.

[0036] Several memory chips 6 are arranged in a staggered, stepped pattern.

[0037] An adhesive layer 8 is provided between several memory chips 6, between memory chips 6 and solder resist dry film 4, and between control chip 11 and solder resist dry film 4.

[0038] Several memory chips 6 are electrically connected to each other via gold wire 71, memory chips 6 are electrically connected to the electroplated nickel-gold layer 14 via gold wire 72, and the control chip 11 is electrically connected to the electroplated nickel-gold layer 14 via gold wire 73.

[0039] A tin ball 10 is connected to one side of the electroplated nickel-gold layer 14, and an electrical connection is formed with the external structure through the tin ball 10.

[0040] Silicon wafer 5 has attracted attention due to its relatively low coefficient of thermal expansion and its status as an important insulating material. The linear coefficient of thermal expansion for monocrystalline silicon, specifically silicon wafers, is 2–2.8 × 10⁻⁶. -6 The thermal expansion coefficient of solder resist ink is 40-60×10 °C, which is much lower than that of solder resist ink. -6 / ℃. The manufacturing process of silicon wafers is relatively simple, and compared to epoxy resin-based solder resist materials, it is more environmentally friendly, renewable, and pollution-free. Therefore, this invention improves the warping problem of substrate 1 by embedding silicon wafer 5.

[0041] like Figure 2 As shown, the method for fabricating the chip packaging substrate structure in this embodiment includes the following steps: S1 provides a substrate; S2, Drill holes in the substrate; S3, remove adhesive residue and perform chemical copper plating on the hole walls of the substrate drilled holes; S4, chemical copper plating on the wall of the drilled hole in the substrate; S5, etching the electroplated copper layer to form conductive lines, fingers, and solder pads; S6, first anti-welding, filling holes and exposing green paint windows; S7, adhesive bonding, embedded silicon wafer; S8, secondary solder resist, the solder resist coating is applied to the silicon wafer and copper layer, and the bonding fingers and solder pads are exposed; S9, the surface treatment of the stringing fingers and solder pads is nickel-gold plated to form an electroplated nickel-gold layer 14; S10, embeds memory chip 6 and control chip 11, and forms an electrical connection; S11, plastic sealed; S12, shaping, appearance inspection, and packaging.

[0042] like Figures 3 to 8 As shown, the specific methods for steps S6 to S9 are as follows: A1: Pre-treatment before soldering; A2: The first use involves applying a solder resist dry film 4 with a thickness of 1 / 2 of the required thickness, and pressing the film to fill the spaces between the lines on the substrate 1 and the through holes 13 on the substrate 1. A3: After exposure and development, solder mask openings are exposed at the edge of substrate 1, forming mounting holes 12 to facilitate the placement of silicon wafer 5. The PET protective film on the solder mask surface is removed before development. A4: Apply a layer of colloid to the exposed weld shielding opening; A5, use a chip mounter to attach silicon wafers 5 to one or both sides of substrate 1; A6, after the silicon wafer 5 is attached, it is cured and fixed by low-temperature baking in a nitrogen oven; A7: Second pre-welding treatment; A8, a second time, 1 / 2 of the required thickness of solder resist dry film 4 is applied, and the film is pressed to make the solder resist thickness on the substrate 1 reach the required solder resist thickness. A9, expose and develop to create nickel-gold plating windows, forming an electroplated nickel-gold layer 14; A10 was subjected to UV curing and post-curing respectively.

[0043] This invention involves embedding a silicon wafer 5 into a substrate through two solder resist processes. The solder resist dry film fabrication process is divided into two steps. In the first solder resist dry film process, a solder resist dry film 4 of half the required thickness is applied, pressed, exposed, and developed. Simultaneously, the areas where the silicon wafer 5 needs to be embedded are opened through development. Silicon wafers 5 of different shapes are connected end to end using a pick-and-place machine. Finally, another solder resist dry film 4 of half the required thickness is applied, pressed, exposed, and developed to achieve the required solder resist thickness on the substrate. The second pressing process makes the solder resist layer surface smoother. After the first application of solder resist dry film 4, vacuuming, and pressing are divided into two steps, the surface smoothness of the solder resist on the substrate 1 is significantly better than that after the first application, vacuuming, and pressing. It is also easier to remove air bubbles from the vias 13 on the substrate 1 and fill them with solder resist.

[0044] This invention achieves the required flatness and thickness of the solder resist surface on the packaging substrate 1 through a two-step process of film application, lamination, exposure, and development. It also reduces the risk of residual air bubbles within the vias 13. Furthermore, the first step of applying, laminating, exposing, and developing the solder resist dry film 4 allows for the creation of solder resist openings to embed the silicon wafer 5. Different types of silicon wafers 5 are designed based on the required thickness and shape, ultimately resolving the substrate warping problem.

Claims

1. A structure for a chip packaging substrate, comprising a substrate, characterized in that: The substrate has electroless copper plating layers on both sides, and an electroplated copper layer on the outer side of the electroless copper plating layers. Mounting holes are provided on one or both sides of the electroless copper plating layers on the substrate, and silicon wafers are placed inside the mounting holes. A solder resist film is provided on the outer side of the substrate, and several memory chips are located on one side of the solder resist film. A control chip is located on one side of the memory chips. Electroplated nickel-gold layers are provided on one or both sides of the electroplated copper layers. One end of the silicon wafer is connected to the substrate, and the other end of the silicon wafer is flush with the electroplated copper layer. The silicon wafer and the substrate are connected by one of the following structures: mortise and tenon joint, slot structure, or chain structure. The method for fabricating the above-mentioned chip packaging substrate includes the following steps: S1 provides a substrate; S2, Drill holes in the substrate; S3, remove adhesive residue and perform chemical copper plating on the hole walls of the substrate drilled holes; S4, chemical copper plating on the wall of the drilled hole in the substrate; S5, etching the electroplated copper layer to form conductive lines, fingers, and solder pads; S6, first anti-welding, filling holes and exposing green paint windows; S7, adhesive bonding, embedded silicon wafer; S8, secondary solder resist, the solder resist coating is applied to the silicon wafer and copper layer, and the bonding fingers and solder pads are exposed; S9, the surface treatment of the stringing fingers and solder pads is nickel-gold plated to form an electroplated nickel-gold layer; S10, embeds the memory chip and control chip, and forms an electrical connection; S11, plastic sealed; S12, scooping, appearance inspection, packaging; The specific methods for steps S6 to S9 are as follows: A1: Pre-treatment before soldering; A2: The first use involves applying a solder resist dry film with a thickness of 1 / 2 of the required thickness, and then pressing the film to fill the spaces between the circuits on the substrate and the vias of the substrate. A3: After exposure and development, solder mask openings are exposed at the edge of the substrate to form mounting holes, facilitating the placement of silicon wafers. The PET protective film on the solder mask surface is removed before development. A4: Apply a layer of colloid to the exposed weld shielding opening; A5, using a chip mounter to attach silicon wafers to one or both sides of the substrate; A6, after the silicon wafer is attached, it is cured and fixed by low-temperature baking in a nitrogen oven; A7: Second pre-welding treatment; A8, apply a second layer of solder resist dry film with half the required thickness, and press the film to make the solder resist thickness on the substrate reach the required solder resist thickness. A9, expose and develop to create nickel-gold plating windows, forming an electroplated nickel-gold layer; A10 was subjected to UV curing and post-curing respectively.

2. The structure of a chip packaging substrate according to claim 1, characterized in that: The memory chip and control chip are encapsulated with a plastic layer on their outer side.

3. The structure of a chip packaging substrate according to claim 1, characterized in that: The aforementioned memory chips are arranged in a staggered, stepped pattern.

4. The structure of a chip packaging substrate according to claim 1 or 2, characterized in that: An adhesive layer is provided between the plurality of memory chips, between the memory chips and the solder resist dry film, and between the control chip and the solder resist dry film.

5. The structure of a chip packaging substrate according to claim 1, characterized in that: Several memory chips are electrically connected to each other via a gold wire one, and the memory chips are electrically connected to the electroplated nickel-gold layer via a gold wire two. The control chip is electrically connected to the electroplated nickel-gold layer via a gold wire three.

6. The structure of a chip packaging substrate according to claim 1, characterized in that: A tin ball is connected to one side of the electroplated nickel-gold layer.

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