Bipolar junction transistor with lateral and vertical conduction paths

Abstract

A bipolar junction transistor structure includes a semiconductor substrate and a doped layer having a first conductivity type, a doped well region having a second conductivity type, first and second heavily doped regions, third, fourth and fifth heavily doped regions having the first conductivity type, the doped well region formed in the doped layer, and the first to fifth heavily doped regions formed in the doped well region. The fifth heavily doped region is connected to a first contact, and the third and fourth heavily doped regions are connected to a second contact. Sixth and seventh heavily doped regions have the first conductivity type and are disposed in the doped layer, the sixth heavily doped region electrically coupled to the first heavily doped region, and the seventh heavily doped region electrically coupled to the second heavily doped region. The bipolar junction transistor structure can produce both lateral and vertical conduction paths when operated in either a positive or negative surge mode.

Description

Technical Field

[0001] This invention relates to a dual-subjunction transistor architecture, particularly a dual-subjunction transistor structure that combines the advantages of low circuit complexity and small circuit layout area, while simultaneously generating lateral and vertical conduction paths. Background Technology

[0002] A transient voltage suppressor (TVS) is an electronic component designed to react in real time to sudden or transient overvoltage conditions. One common type for achieving this protection is the TVS diode or Zener diode, designed to protect electronic devices from overvoltage. Generally, compared to other common overvoltage protection components (such as rheostats or gas discharge tubes), the operating characteristics of a transient voltage suppressor require it to respond much more quickly to overvoltage conditions. This makes transient voltage suppressors particularly useful for preventing transient and often destructive voltage pulses, as these rapidly generated overvoltage pulses are often caused by internal or external events (such as lightning or electric arcs) within the circuit architecture. Furthermore, transient voltage suppressors can be used for unidirectional or bidirectional electrostatic discharge (ESD) protection on data transmission or signal lines in electronic circuits. Generally, when equipment is rated for various applications, the energy level of transient overvoltages generated can be estimated by measuring energy in joules or by using current-related levels. These overvoltage pulses can be measured using specialized electronic instruments that can display power supply disturbances with amplitudes of several kilovolts lasting a few microseconds or less.

[0003] One known prior art is the US Patent Publication No. 6,707,110B2, which discloses a layout-configurable integrated circuit electrostatic discharge device. This device belongs to the category of electrostatic discharge devices whose holding voltage can be adjusted by changing the layout parameters in its circuit, thereby reducing the dependence of the holding voltage of its components on the current. However, it is worth noting that, according to this prior art, the bipolar junction transistor (BJT) in the device has a structure with an external base, and due to this characteristic, the gain of the transistor is significantly suppressed. In addition, another prior art patent, US2020 / 0035664 A1, discloses a vertical transient voltage suppressor. In this patent, to maintain a low holding voltage and low clamping voltage to enhance electrostatic discharge performance, the base of the vertical bijunction transistor (BJT) is floated. However, this requires a diode structure to be arranged in the epitaxial layer of the transistor and connected by an additional conductive trace. Furthermore, the two potential pins of the transient voltage suppressor must be located on opposite sides of the device. This means the prior art must employ the existing backside metallization process, which increases the number of process steps, manufacturing costs, and process complexity.

[0004] Furthermore, in the prior art, another US patent application with publication number US8,552,530B2 discloses a vertical transient voltage suppressor architecture suitable for protecting electronic devices. As can be seen from the references, the design purpose of this transient voltage suppressor is to form a vertical ESD transient protection suppressor architecture, aiming to provide effective electrostatic protection under both positive and negative pulse stress, reduce its breakdown voltage variation, and generate a symmetrical current-voltage characteristic curve. However, similar to the aforementioned prior art, the two potential pins of the device must also be arranged on opposite sides of the device. That is to say, in this prior art, it is unavoidable to simultaneously employ existing back-side metallization processes. In addition to this problem, the vertical NPN dual-carrier junction transistor structure formed in the device will have a large transistor gain, which, on the other hand, reduces its holding voltage; a result that is not desirable for circuit designers. In addition, as is well known, in the case of existing technologies that mostly adopt traditional transient voltage suppressor structures, the numerous internal circuit elements often interfere with each other, making it difficult to control the characteristics of the transistors and to accurately achieve the expected electrical design results.

[0005] Therefore, in view of the above, and considering the numerous problems listed above, it is essential to adopt a multi-faceted approach. Thus, the inventors of this invention, recognizing the potential for improvement in the aforementioned deficiencies and drawing upon years of experience in this field, have carefully observed and researched the subject, applying theoretical principles, and have proposed a novel design that effectively addresses these deficiencies. This invention provides a novel and innovative transistor device architecture. Through this practically innovative transistor architecture, not only can the long-standing deficiencies of the prior art be resolved, but also optimized electrical results in the device design can be achieved. Therefore, the circuit architecture and implementation methods specifically requested by this invention will be detailed below. Summary of the Invention

[0006] To address the problems existing in the prior art, the main objective of this invention is to provide a novel and highly innovative circuit architecture for a dual-subjunction transistor. According to the dual-subjunction transistor architecture proposed by this invention, the dual-subjunction transistor can simultaneously possess both lateral and vertical conduction paths without increasing circuit complexity or layout area.

[0007] Another object of the present invention is to provide a dual-subjunction transistor having lateral and vertical conduction paths, wherein when the lateral conduction path is formed, the dual-subjunction transistor is a dual-subjunction transistor with a floating base. Similarly, when the vertical conduction path is formed, the dual-subjunction transistor also has a floating base. Compared with the prior art, the present invention, through the further formed lateral conduction path, can provide another discharge path suitable for releasing transient surges, thereby reducing the on-resistance of the transistor and achieving better electrostatic discharge (ESD) protection.

[0008] Furthermore, another object of the present invention is to provide a dual-subjunction transistor capable of simultaneously forming a lateral conduction path and a vertical conduction path, wherein when the transistor operates in a forward surge mode, the vertical conduction path is formed, and the vertical conduction path includes a vertical npn dual-subjunction transistor structure and a forward bias diode connected in series with the vertical npn dual-subjunction transistor structure. By employing such a circuit arrangement, the present invention can effectively suppress the conventional latch-up effect. At the same time, the circuit layout adopted by the present invention also has better design flexibility, thus demonstrating that the process complexity of the present invention can not only be effectively reduced, but also easily controlled.

[0009] Therefore, in the following paragraphs, the present invention further provides various different embodiments and variations, which will be described in detail in the following embodiments, and these technical contents verify the effectiveness of the dual-carrier junction transistor with lateral conduction paths and vertical conduction paths provided by the present invention. Thus, it is evident that the present invention successfully solves many long-standing deficiencies of the prior art while maintaining its excellent electrical characteristics. Therefore, it can be further assured that the technical solution and technical means provided by the present invention not only have high competitiveness in the industry, but can also be widely applied in related IC and semiconductor industries.

[0010] In view of the numerous inventive objectives of the present invention disclosed above, these are aspects that cannot be achieved or applied by patents or papers that significantly improve upon existing technologies. Therefore, based on achieving the numerous inventive objectives mentioned above, the present invention aims to provide an innovative circuit architecture, which is a dual-carrier junction transistor with lateral and vertical conduction paths.

[0011] According to an embodiment of the present invention, the dual-carrier junction transistor includes: a semiconductor substrate having a first conductivity type; a doped layer having the first conductivity type; and a doped well region having a second conductivity type, wherein the first conductivity type and the second conductivity type are different conductivity types. The doped layer is disposed on the semiconductor substrate, and the doped well region is disposed within the doped layer having the first conductivity type.

[0012] In addition, a first heavily doped region having the second conductivity type, a second heavily doped region having the second conductivity type, a third heavily doped region having the first conductivity type, a fourth heavily doped region having the first conductivity type, and a fifth heavily doped region having the first conductivity type are further disposed in the doped well-shaped region having the second conductivity type. The fifth heavily doped region having the first conductivity type is electrically coupled to a first contact, and the third and fourth heavily doped regions having the first conductivity type are jointly electrically coupled to a second contact. Meanwhile, the first and second heavily doped regions having the second conductivity type are separated by the third, fourth, and fifth heavily doped regions having the first conductivity type.

[0013] In addition, a sixth doped region having the first conductivity type and a seventh doped region having the first conductivity type are further disposed in the doped layer having the first conductivity type. The sixth doped region having the first conductivity type and the seventh doped region having the first conductivity type are separated by doped well-shaped regions having the second conductivity type. Furthermore, the sixth doped region having the first conductivity type is electrically coupled to the first doped region having the second conductivity type, and the seventh doped region having the first conductivity type is electrically coupled to the second doped region having the second conductivity type.

[0014] According to a preferred embodiment of the present invention, when the first conductivity type is N-type semiconductor and the second conductivity type is P-type semiconductor, the first contact and the second contact are electrically coupled to a positive voltage level and a ground voltage level, respectively, thereby providing a positive surged operating mode.

[0015] When operating in the forward surge mode, the dual-sub-junction transistor provided by this invention forms a lateral conduction path, and the lateral conduction path includes at least one lateral npn dual-sub-junction transistor structure. Specifically, the at least one lateral npn dual-sub-junction transistor structure is composed of a fifth doped region having the first conductivity type, a doped well region having the second conductivity type, and a third doped region having the first conductivity type. Furthermore, the at least one lateral npn dual-sub-junction transistor structure also includes a fifth doped region having the first conductivity type, a doped well region having the second conductivity type, and a fourth doped region having the first conductivity type.

[0016] In addition, when operating in the forward surge mode, the dual-sub-junction transistor provided by this invention also forms a vertical conduction path, and the vertical conduction path includes at least one vertical npn dual-sub-junction transistor structure and at least one forward bias diode connected in series with the vertical npn dual-sub-junction transistor structure. The at least one vertical npn dual-sub-junction transistor structure is composed of a fifth doped region having the first conductivity type, a doped well region having the second conductivity type, a doped layer having the first conductivity type, and a sixth doped region having the first conductivity type. Furthermore, the at least one vertical npn dual-sub-junction transistor structure also includes a fifth doped region having the first conductivity type, a doped well region having the second conductivity type, a doped layer having the first conductivity type, and a seventh doped region having the first conductivity type. As for the at least one forward bias diode, it is composed of a sixth heavily doped region having the first conductivity type, a first heavily doped region having the second conductivity type, a doped well region having the second conductivity type, and a third heavily doped region having the first conductivity type. Furthermore, the at least one forward bias diode also includes a seventh heavily doped region having the first conductivity type, a second heavily doped region having the second conductivity type, a doped well region having the second conductivity type, and a fourth heavily doped region having the first conductivity type.

[0017] On the other hand, according to another optional embodiment of the present invention, when the first conductivity type is an N-type semiconductor and the second conductivity type is a P-type semiconductor, the first contact and the second contact can be electrically coupled to a negative voltage level and a ground voltage level, respectively, thereby providing a negative surge operating mode.

[0018] According to this alternative embodiment, when the dual-subjunction transistor provided by the present invention operates in the negative surge operation mode, a lateral conduction path is generated in the dual-subjunction transistor, and the lateral conduction path includes at least one lateral npn dual-subjunction transistor structure. According to an embodiment of the present invention, the at least one lateral npn dual-subjunction transistor structure comprises a third heavily doped region having the first conductivity type, a doped well region having the second conductivity type, and a fifth heavily doped region having the first conductivity type; furthermore, the at least one lateral npn dual-subjunction transistor structure also comprises a fourth heavily doped region having the first conductivity type, a doped well region having the second conductivity type, and a fifth heavily doped region having the first conductivity type.

[0019] Furthermore, the dual-substrate junction transistor provided by this invention may optionally further include an eighth doped region and a ninth doped region, wherein the eighth and ninth doped regions have the second conductivity type, and the eighth and ninth doped regions having the second conductivity type are jointly disposed in the doped layer having the first conductivity type. In this embodiment, the eighth, ninth, third, and fourth doped regions having the second conductivity type are electrically connected to each other, and are electrically coupled to the second contact. In this embodiment, when the first conductivity type is N-type semiconductor and the second conductivity type is P-type semiconductor, the first contact and the second contact can also be electrically coupled to a positive voltage level and a ground voltage level, respectively, thereby providing a positive surge operation mode. In this forward surge operation mode, the dual-subjunction transistor provided by this invention generates a lateral conduction path, and the lateral conduction path includes at least one lateral npn dual-subjunction transistor structure. In addition, when operating in this forward surge operation mode, the dual-subjunction transistor provided by this invention also simultaneously generates a vertical conduction path, and the vertical conduction path includes at least one vertical npn dual-subjunction transistor structure and at least one forward bias diode connected in series with the vertical npn dual-subjunction transistor structure.

[0020] On the other hand, in the structure of the present invention further configured with an eighth doped region and a ninth doped region of a second conductivity type, when the first conductivity type is an N-type semiconductor and the second conductivity type is a P-type semiconductor, the first contact and the second contact can optionally be electrically coupled to a negative voltage level and a ground voltage level, respectively, thereby providing a negative surge operation mode. In this negative surge operation mode, a lateral conduction path is generated in the dual-subjunction transistor provided by the present invention, and the lateral conduction path includes at least one lateral npn dual-subjunction transistor structure. According to this embodiment of the present invention, the formed at least one lateral npn dual-subjunction transistor structure comprises a third heavily doped region having a first conductivity type, a doped well region having a second conductivity type, and a fifth heavily doped region having a first conductivity type. Furthermore, the at least one lateral npn dual-subjunction transistor structure also comprises a fourth heavily doped region having the first conductivity type, a doped well region having the second conductivity type, and a fifth heavily doped region having the first conductivity type.

[0021] Of particular note is that, in the structure of the present invention further configured with an eighth and ninth doped region of a second conductivity type, when the dual-subjunction transistor operates in the negative surge operation mode, a vertical conduction path is generated in the dual-subjunction transistor provided by the present invention. The vertical conduction path includes: at least one silicon controlled rectifier transistor structure and two diode structures connected in parallel with the silicon controlled rectifier transistor structure, wherein the two diodes are connected in series and the silicon controlled rectifier transistor structure has diode-like characteristics. According to this embodiment of the present invention, the formed silicon controlled rectifier transistor structure is composed of an eighth doped region having the second conductivity type, a doped layer having the first conductivity type, a doped well region having the second conductivity type, and a fifth doped region having the first conductivity type. Furthermore, the silicon controlled rectifier transistor structure also includes a ninth doped region having the second conductivity type, a doped layer having the first conductivity type, a doped well region having the second conductivity type, and a fifth doped region having the first conductivity type.

[0022] In addition, in other alternative embodiments of the present invention, the first conductivity type and the second conductivity type disclosed above are not limited to the N-type semiconductor type and the P-type semiconductor type; in other words, in the alternative embodiments of the present invention that can be modified, the first conductivity type can be a P-type semiconductor type and the second conductivity type can be an N-type semiconductor type. In this alternative embodiment, the first contact and the second contact are electrically coupled to a low voltage level and a high voltage level, respectively, and the high voltage level of the second contact is greater than the low voltage level of the first contact.

[0023] In another alternative embodiment of the present invention, the disclosed bicarrier junction transistor may optionally be provided with an implanted buried layer having the first conductivity type, and the implanted buried layer is disposed between the semiconductor substrate having the first conductivity type and the doped layer having the first conductivity type.

[0024] In addition, according to another optional alternative embodiment of the present invention, the dual-carrier junction transistor disclosed in the present invention may also optionally be provided with a first well-shaped region and a second well-shaped region, wherein the first well-shaped region and the second well-shaped region have the first conductivity type, and the first well-shaped region and the second well-shaped region having the first conductivity type are formed in the doped layer having the first conductivity type, thereby such that in this embodiment, a sixth doped region having the first conductivity type is disposed in the first well-shaped region having the first conductivity type, and a seventh doped region having the first conductivity type is disposed in the second well-shaped region having the first conductivity type.

[0025] In the case of further configuring the first well-shaped region and the second well-shaped region, the aforementioned implanted buried layer disposed between the semiconductor substrate and the doped layer is optional, and the layout configuration provided by the present invention is obviously not limited thereto.

[0026] Therefore, it is worth noting that, based on the various embodiments and alternative embodiments provided above, the present invention is not limited to the disclosed embodiments. In other words, for those skilled in the art and those with ordinary knowledge and technical background of the present invention, modifications or alterations made to meet different circuit requirements without departing from the scope of the present invention, the modified embodiments and / or circuit implementations should still fall within the scope of the claims of the present invention.

[0027] Generally speaking, those skilled in the art and those with common knowledge can make appropriate modifications or changes to the technical content disclosed in this invention without departing from the spirit of the invention. However, this invention is certainly not limited to certain limited configurations and / or conductivity types disclosed in these embodiments. Therefore, it can be established that such modified or changed embodiments should still fall within the protection scope of this invention, and that such modified or changed embodiments are covered by this invention.

[0028] Therefore, in view of the above-mentioned technical solutions, the present invention aims to provide a dual-subjunction transistor structure that can have both lateral and vertical conduction paths. According to the transistor architecture provided by the present invention, not only can the shortcomings of the prior art be effectively solved, but also the first and second contacts connected to the transistor can be jointly disposed on the same surface of the dual-subjunction transistor with lateral and vertical conduction paths. In this way, through this technical feature, the present invention can effectively save the back-side metallization process that must be used in the prior art, thereby reducing the process steps and manufacturing complexity of the dual-subjunction transistor provided by the present invention, and realizing the optimized process efficiency of the present invention.

[0029] In summary, based on the technical solution provided by this invention, it is evident that this invention has undergone thorough and precise design, and discloses an innovative and improved dual-carrier junction transistor structure. By adopting the circuit architecture and operating mode disclosed in this invention, it is clear that this invention possesses numerous advantages. Therefore, it can be confidently asserted that the technical solution disclosed in this invention is beneficial, and compared with the prior art, it is extremely advantageous in overcoming its existing deficiencies.

[0030] The present invention will be further described in detail below with reference to specific embodiments and accompanying drawings, so that the purpose, technical content, features and effects of the present invention can be more easily understood. Attached Figure Description

[0031] Figure 1 A schematic diagram of a dual-subjunction transistor with lateral and vertical conduction paths according to an embodiment of the present invention is disclosed.

[0032] Figure 2 The present invention discloses a dual-subjunction transistor having lateral and vertical conduction paths in one embodiment, wherein the first conduction type and the second conduction type are respectively N-type semiconductor type and P-type semiconductor type.

[0033] Figure 3 public Figure 2 A schematic diagram of the structure of the dual-subjunction transistor in the embodiment operating in the forward surge mode.

[0034] Figure 4 Public basis Figure 3 The operating mode generates a structural diagram with a lateral conductive path.

[0035] Figure 5 Public basis Figure 3 The operating mode generates a structural diagram with a vertical conduction path.

[0036] Figure 6 public Figure 2 The embodiment of the dual-subjunction transistor operates in a negative surge operation mode and generates a structural schematic diagram with a lateral conduction path.

[0037] Figure 7 Public basis Figure 2 The embodiments further include schematic diagrams of an eighth and ninth doped region having a second conductivity type.

[0038] Figure 8 Disclosure based on the present invention Figure 2 A current-voltage diagram of a bipolar junction transistor shown in the embodiment.

[0039] Figure 9 Disclosure based on the present invention Figure 7 A current-voltage diagram of a bipolar junction transistor shown in the embodiment.

[0040] Figure 10 public Figure 7 The embodiment of the dual-subjunction transistor operates in a forward surge mode and produces a structural schematic diagram with a lateral conduction path.

[0041] Figure 11 public Figure 7 The embodiment of the dual-subjunction transistor operates in a forward surge mode and produces a structural schematic diagram with a vertical conduction path.

[0042] Figure 12 public Figure 7 The embodiment of the dual-subjunction transistor operates in a negative surge operation mode and generates a structural schematic diagram with a lateral conduction path.

[0043] Figure 13 public Figure 7 The embodiment of the dual-subjunction transistor operates in a negative surge operation mode and produces a structural schematic diagram with a vertical conduction path.

[0044] Figure 14 The present invention discloses a dual-subjunction transistor having lateral and vertical conduction paths in one embodiment, wherein the first conduction type and the second conduction type are respectively P-type semiconductor type and N-type semiconductor type.

[0045] Figure 15 Public basis Figure 14 The embodiments further include schematic diagrams of an eighth and ninth doped region having a second conductivity type.

[0046] Figure 16 The present invention is based on Figure 2 A further embodiment of the bicarrier junction transistor having lateral and vertical conduction paths includes a structural schematic diagram of an implanted embedded layer.

[0047] Figure 17 The present invention is based on Figure 14 A further embodiment of the bicarrier junction transistor having lateral and vertical conduction paths includes a structural schematic diagram of an implanted embedded layer.

[0048] Figure 18 The present invention is based on Figure 16 A further embodiment of the bipolar junction transistor having lateral and vertical conduction paths includes a structural schematic diagram of a first well-shaped region and a second well-shaped region.

[0049] Figure 19 The present invention is based on Figure 17 A further embodiment of the bipolar junction transistor having lateral and vertical conduction paths includes a structural schematic diagram of a first well-shaped region and a second well-shaped region.

[0050] Figure 20 The present invention is based on Figure 18 A schematic diagram of a bicarrier junction transistor with lateral and vertical conduction paths, wherein the embedded buried layer can be selectively removed.

[0051] Figure 21 The present invention is based on Figure 19 A schematic diagram of a bicarrier junction transistor with lateral and vertical conduction paths, wherein the embedded buried layer can be selectively removed.

[0052] Explanation of reference numerals in the figures: 1 - Dual-subjunction transistor with lateral and vertical conduction paths; 1A - Dual-subjunction transistor with lateral and vertical conduction paths; 1B - Dual-subjunction transistor with lateral and vertical conduction paths; 1C - Dual-subjunction transistor with lateral and vertical conduction paths; 1D - Dual-subjunction transistor with lateral and vertical conduction paths; 1E - Dual-subjunction transistor with lateral and vertical conduction paths; 1F - Dual-subjunction transistor with lateral and vertical conduction paths; 1G - Dual-subjunction transistor with lateral and vertical conduction paths; 1H - Dual-subjunction transistor with lateral and vertical conduction paths; 1I - Dual-subjunction transistor with lateral and vertical conduction paths; 1J - Dual-subjunction transistor with lateral and vertical conduction paths; 21 - First doped region; 22 - Second doped region; 23 - Third doped region; 24 - Fourth doped region; 25 - Fifth doped region. 26 - Sixth doped region; 27 - Seventh doped region; 28 - Eighth doped region; 29 - Ninth doped region; 100 - Semiconductor substrate; 102 - Doped layer; 104 - Doped well region; 110 - Embedded layer; 181 - First well region; 182 - Second well region; 21C - First doped region; 22C - Second doped region; 23C - Third doped region; 24C - Fourth doped region; 25C - Fifth doped region; 26C - Sixth doped region; 27C - Seventh doped region; 28C - Eighth doped region; 29C - Ninth doped region; 100C - Semiconductor substrate; 102C - Doped layer; 104C - Doped well region; 110C - Implanted buried layer; 181C - First well region; 182C - Second well region; P1 - First contact; P2 - Second contact; SCR1 - Current path; SCR2 - Current path; DS1 - Current path; DS2 - Current path. Detailed Implementation

[0053] The foregoing description of the present invention, along with the following embodiments, are intended to demonstrate and explain the spirit and principles of the invention, and to provide a further explanation of the claims. Please refer in detail to the preferred embodiments of the invention, examples of which are shown in the accompanying drawings. Where possible, the same reference numerals will be used in the drawings and description to refer to the same or similar elements. It should be understood that, for clarity and convenience, the invention may be enlarged in terms of shape and thickness in the drawings, and elements not specifically shown or described may take various forms known to those skilled in the art. Once disclosed in this disclosure, such alternatives and modifications will be readily apparent to those skilled in the art.

[0054] To illustrate the technical content and features of this invention and to enable those skilled in the art to understand, create, and use it, the invention is described below through numerous embodiments. However, it should be noted that these embodiments are not intended to limit the scope of the invention. Therefore, all equivalent modifications or variations made in accordance with the spirit of this invention should be included within the scope of protection of this invention.

[0055] Unless otherwise stated, certain conditional phrases or words, such as “may” or “possibly,” are generally used to express that embodiments of the invention “have,” but may also be interpreted as unnecessary features, elements, or steps. In other embodiments, these features, elements, or steps may not be required.

[0056] In the embodiments described in this specification, the reference to "one embodiment" or "in one embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, "one embodiment" or "in one embodiment" appearing in various places in this specification do not necessarily refer to the same embodiment.

[0057] In the embodiments and claims of this invention, specific terms are used to refer to specific elements. Those skilled in the art should understand that the same element can have different names. This invention does not distinguish between elements with different names but the same function. In this specification and claims, "comprising" is used in an open-ended manner and should therefore be interpreted as "including but not limited to". "Coupled with" is intended to cover any indirect or direct connection. In other words, if this invention provides a first device coupled to a second device, it means that the first device can be connected to the second device directly or indirectly through other intermediate devices or connection methods via electrical connection, wireless communication, optical communication, or other signal connections, with or without signal connections.

[0058] The present invention is described in detail through the following embodiments, which are merely illustrative examples. Those skilled in the art can readily make appropriate modifications and variations to the apparatus and methods while retaining the teachings of the present invention. Therefore, the following disclosure of the present invention should be interpreted as being limited only by the scope of the appended claims. Throughout the specification and claims, except where explicitly described, the terms "a" and "described" include "one or at least one" of an element or element. Furthermore, throughout the specification and claims, the singular includes descriptions of multiple elements or elements, except where the context clearly excludes multiples. Throughout the specification and claims, unless the meaning of certain words is explicitly defined, the term "wherein" includes "among" or "on top of". Generally, the meaning of each term used in the claims and specification of this invention refers to its common meaning known to those skilled in the art, unless otherwise noted. Some terms used to describe the invention and to guide those skilled in the art in understanding the invention may be discussed. Each illustrative example in this specification should not be used to limit the scope of the invention.

[0059] The terms “basically,” “approximately,” “about,” and “probably” can refer to a value within 20% of a given value or range, preferably within 10%. Furthermore, the quantities or figures provided in this invention can be approximate values, and unless otherwise specified, can be described using the terms described above. When a quantity, density, or other parameter includes a specified range, preferred range, or listed ideal value, its value can be considered as any number within that given range.

[0060] As described in the prior art paragraph, existing technologies often lack flexibility in circuit design and require significant circuit layout area and manufacturing costs. Therefore, this invention aims to address these shortcomings and proposes a novel and inventive transistor structure. The dual-subjunction transistor disclosed in this invention is characterized by its ability to simultaneously possess both lateral and vertical conduction paths. The specific architecture of the dual-subjunction transistor provided by this invention will be described in detail in the following sections through several variations.

[0061] First, please refer to Figure 1 As shown, it provides a structural schematic diagram of a dual-carrier junction transistor with lateral and vertical conduction paths according to an embodiment of the present invention, as follows. Figure 1As shown, the dual-carrier junction transistor 1 with lateral and vertical conduction paths disclosed in this invention includes a semiconductor substrate 100, a doped layer 102, a doped well region 104, a first heavily doped region 21, a second heavily doped region 22, a third heavily doped region 23, a fourth heavily doped region 24, a fifth heavily doped region 25, a sixth heavily doped region 26, and a seventh heavily doped region 27. According to an embodiment of the invention, the semiconductor substrate 100 has a first conductivity type. The doped layer 102 also has the first conductivity type, and is disposed on the semiconductor substrate 100. The doped well region 104 has a second conductivity type, wherein the second conductivity type is different from the first conductivity type. Furthermore, the doped well region 104 having the second conductivity type is disposed within the doped layer 102 having the first conductivity type.

[0062] According to an embodiment of the present invention, the first heavily doped region 21 and the second heavily doped region 22 have the second conductivity type described above. Conversely, the third heavily doped region 23, the fourth heavily doped region 24, and the fifth heavily doped region 25 have the first conductivity type described above. The first heavily doped region 21 and the second heavily doped region 22 having the second conductivity type, and the third heavily doped region 23, the fourth heavily doped region 24, and the fifth heavily doped region 25 having the first conductivity type, are disposed in the doped well-shaped region 104 having the second conductivity type. Figure 1 As shown, the fifth heavily doped region 25 with a first conductivity type is electrically coupled to a first contact P1, and the third heavily doped region 23 with a first conductivity type and the fourth heavily doped region 24 with a first conductivity type are electrically coupled to a second contact P2.

[0063] The sixth-doped region 26 and the seventh-doped region 27 have the aforementioned first conductivity type. Furthermore, the sixth-doped region 26 and the seventh-doped region 27, both having the first conductivity type, are disposed together in the doped layer 102 having the first conductivity type. Please refer to [link to relevant documentation]. Figure 1 As shown, it can be clearly seen that the sixth doped region 26 with the first conductivity type and the seventh doped region 27 with the first conductivity type are separated by the doped well region 104 with the second conductivity type. At the same time, in the doped well region 104 with the second conductivity type, the first doped region 21 with the second conductivity type and the second doped region 22 with the second conductivity type are separated by the third doped region 23 with the first conductivity type, the fourth doped region 24 with the first conductivity type, and the fifth doped region 25 with the first conductivity type.

[0064] like Figure 1As shown, the sixth heavily doped region 26 having the first conductivity type is electrically coupled to the first heavily doped region 21 having the second conductivity type, and the seventh heavily doped region 27 having the first conductivity type is electrically coupled to the second heavily doped region 22 having the second conductivity type.

[0065] In this invention Figure 1 In the disclosed technical solution, when the first conductivity type is an N-type semiconductor, the second conductivity type is a P-type semiconductor. Figure 2 This invention discloses a dual-carrier junction transistor 1A with lateral and vertical conduction paths according to an embodiment of the present invention, wherein the first conduction type and the second conduction type are respectively N-type semiconductor and P-type semiconductor structural schematic diagrams. In this embodiment, as... Figure 2 As shown, the semiconductor substrate 100 having the first conductivity type is an N-type semiconductor substrate, and is referred to as "N-type sub". The doped layer 102 located thereon and having the first conductivity type is an N-type semiconductor doped layer, and is referred to as "N-type layer".

[0066] When the second conductivity type is a P-type semiconductor, the doped well region 104 having the second conductivity type is a P-type semiconductor doped well region, and is denoted as "P-type well". Similarly, in Figure 2 In the first heavily doped region 21 having the second conductivity type, it is a P-type semiconductor heavily doped region and is denoted as "P+". The second heavily doped region 22 having the second conductivity type is also a P-type semiconductor heavily doped region and is denoted as "P+". As for the third heavily doped region 23, the fourth heavily doped region 24, and the fifth heavily doped region 25 having the first conductivity type, they are N-type semiconductor heavily doped regions and are denoted as "N+" respectively. Similarly, the sixth heavily doped region 26 and the seventh heavily doped region 27 disposed in the doped layer 102 ("N-type layer") having the first conductivity type also have the first conductivity type, they are N-type semiconductor heavily doped regions, and are both denoted as "N+".

[0067] However, it is worth noting that the present invention is not limited to such embodiments. In other words, according to other optional embodiments of the present invention, the first conductivity type can also be exemplified as a P-type semiconductor, and the second conductivity type can be exemplified as an N-type semiconductor. Generally speaking, those skilled in the art and with ordinary knowledge can naturally make optional variations and embodiments based on the actual needs of their circuits, within the spirit of the technical solutions taught in this invention. However, variations based on the technical content disclosed in this invention should still be covered within the protection scope of this invention.

[0068] Therefore, according to the present invention Figure 2 In the disclosed embodiment, when the first and second conductivity types are N-type semiconductor and P-type semiconductor, respectively, the first junction P1 and the second junction P2 of the bipolar junction transistor 1A with lateral and vertical conduction paths can be electrically coupled to a positive voltage level (+V) and a ground voltage level (GND), respectively. Figure 3 As shown, this provides a positive surge operation mode. In this case, the dual-carrier junction transistor 1A with lateral and vertical conduction paths, when operating in the positive surge operation mode, can simultaneously generate one lateral conduction path and one vertical conduction path. Please refer to further details. Figure 4 As shown in the diagram, the generated lateral conductive path is indicated by the direction of the arrow. (As per the present invention...) Figure 4 As shown, the lateral conduction path includes two lateral npn dual-substrate junction transistor structures. One lateral npn dual-substrate junction transistor structure consists of a fifth doped region 25 (N+) with the first conductivity type, a doped well region 104 (P-type well) with the second conductivity type, and a third doped region 23 (N+) with the first conductivity type. The other lateral npn dual-substrate junction transistor structure consists of a fifth doped region 25 (N+) with the first conductivity type, a doped well region 104 (P-type well) with the second conductivity type, and a fourth doped region 24 (N+) with the first conductivity type.

[0069] at the same time, Figure 5 This invention discloses a dual-subjunction transistor 1A with lateral and vertical conduction paths, illustrating the generation of one vertical conduction path when operating in the positive surge operation mode. Figure 5 Similarly, this invention uses an arrow-shaped diagram to indicate the generated vertical conduction path. Please refer to [link / reference]. Figure 5 As shown, it can be clearly seen that the vertical conduction path formed in this embodiment of the present invention includes: at least one vertical npn dual-subjunction transistor structure, and at least one forward bias diode connected in series with the vertical npn dual-subjunction transistor structure.

[0070] In detail, the at least one vertical npn dual-subjunction transistor structure formed in this embodiment includes: a fifth doped region 25 (N+) having the first conductivity type, a doped well region 104 (P-type well) having the second conductivity type, a doped layer 102 (N-type layer) having the first conductivity type, and a sixth doped region 26 (N+) having the first conductivity type (as shown in the left half of this figure). In addition, another vertical npn dual-subjunction transistor structure includes: a fifth doped region 25 (N+) having the first conductivity type, a doped well region 104 (P-type well) having the second conductivity type, a doped layer 102 (N-type layer) having the first conductivity type, and a seventh doped region 27 (N+) having the first conductivity type (as shown in the right half of this figure).

[0071] As for the at least one forward-biased diode connected in series with the vertical npn bipolar junction transistor structure, it is composed of a sixth heavily doped region 26 (N+) having the first conductivity type, a first heavily doped region 21 (P+) having the second conductivity type, a doped well region 104 (P-type well) having the second conductivity type, and a third heavily doped region 23 (N+) having the first conductivity type (as shown in the left half of this figure). Furthermore, another forward-biased diode connected in series with the vertical npn bipolar junction transistor structure is composed of a seventh heavily doped region 27 (N+) having the first conductivity type, a second heavily doped region 22 (P+) having the second conductivity type, a doped well region 104 (P-type well) having the second conductivity type, and a fourth heavily doped region 24 (N+) having the first conductivity type (as shown in the right half of this figure).

[0072] Therefore, according to the technical solution provided above by the present invention, it can be confirmed that when the dual-subjunction transistor disclosed in the present invention operates in the forward surge operation mode, the dual-subjunction transistor can simultaneously generate the lateral conduction path and the vertical conduction path.

[0073] On the other hand, the dual-subjunction transistor disclosed in this invention can also selectively operate in a negative surge operation mode. For a detailed description of this embodiment, please refer to the accompanying drawings of this invention. Figure 6 As shown. In Figure 6 The present invention discloses a schematic diagram of a dual-carrier junction transistor 1A with lateral and vertical conduction paths, wherein, when operating in the negative surge operation mode, one of the lateral conduction paths is generated. Figure 6 Similarly, this invention uses an arrow-shaped diagram to indicate the generated lateral conduction path. See also... Figure 6 As shown, it can be clearly seen that when the dual-substrate junction transistor 1A with lateral and vertical conduction paths operates in the negative surge operation mode, and its first conductivity type is N-type semiconductor and its second conductivity type is P-type semiconductor, then the first contact P1 and the second contact P2 are electrically coupled to a negative voltage level (-V) and a ground voltage level (GND) respectively, thereby providing the negative surge operation mode.

[0074] As shown by the arrows in the figure, the lateral conduction path formed in this embodiment includes two lateral npn dual-substrate junction transistor structures. One of the lateral npn dual-substrate junction transistor structures consists of a third doped region 23 (N+) with the first conductivity type, a doped well region 104 (P-type well) with the second conductivity type, and a fifth doped region 25 (N+) with the first conductivity type. The other lateral npn dual-substrate junction transistor structure consists of a fourth doped region 24 (N+) with the first conductivity type, a doped well region 104 (P-type well) with the second conductivity type, and a fifth doped region 25 (N+) with the first conductivity type.

[0075] Please refer to the accompanying drawings of this invention for further details. Figure 7 As shown, the invention is based on... Figure 2 An exemplary variation of the embodiment, wherein the provided dual-carrier junction transistor 1B with lateral and vertical conduction paths has a first conductivity type of N-type semiconductor and a second conductivity type of P-type semiconductor. Figure 2The embodiment differs in that, in addition to the semiconductor substrate 100 (N-type sub), doped layer 102 (N-type layer), third doped region 23 (N+), fourth doped region 24 (N+), fifth doped region 25 (N+), sixth doped region 26 (N+), and seventh doped region 27 (N+) having a first conductivity type, and the doped well region 104 (P-type well), first doped region 21 (P+), and second doped region 22 (P+) having a second conductivity type, the dual-carrier junction transistor 1B with lateral and vertical conduction paths further includes an eighth doped region 28 (P+) and a ninth doped region 29 (P+) having a second conductivity type. The eighth doped region 28 and the ninth doped region 29 are disposed within the doped layer 102 (N-type layer) having the first conductivity type. In this embodiment, it can be clearly seen that the eighth doped region 28 (P+) having the second conductivity type, the ninth doped region 29 (P+) having the second conductivity type, the third doped region 23 (N+) having the first conductivity type, and the fourth doped region 24 (N+) having the first conductivity type are electrically connected to each other and are electrically coupled to the second junction P2.

[0076] Figure 8 Disclosure based on the present invention Figure 2 The embodiment shows a current-voltage diagram of a dual-subjunction transistor. Figure 9 Disclosure based on the present invention Figure 7 A current-voltage schematic diagram of a dual-subjunction transistor shown in the embodiment. From Figure 8 The provided current-voltage curve shows that Figure 2 The bidirectional junction transistor 1A is a bidirectional device; however, by further providing an eighth doped region 28 (P+) and a ninth doped region 29 (P+) having a second conductivity type in the doped layer 102 (N-type layer) having a first conductivity type, the accompanying drawings of the present invention... Figure 7 The dual-subjunction transistor 1B provided herein can be successfully formed into a unidirectional element. It is evident that this invention can successfully fabricate a dual-subjunction transistor with unidirectional elements having both lateral and vertical conduction paths, while offering advantages in terms of lower process cost, circuit configuration loss, and process complexity.

[0077] And, here Figure 7In the provided embodiment, when its first and second conductivity types are N-type and P-type semiconductors respectively, its first contact P1 and second contact P2 can also be electrically coupled to a positive voltage level (+V) and a ground voltage level (GND) respectively, thereby providing a forward surge operation mode for this bipolar junction transistor 1B. For a related explanation of this forward surge operation mode, please refer to the following. Figure 10 and Figure 11 As shown.

[0078] First, such as Figure 10 As shown, when this dual-subjunction transistor 1B operates in the forward surge mode, a lateral conduction path is generated, and this lateral conduction path is illustrated in the accompanying drawings with arrows pointing in the direction of the arrows. Figure 10 The drawn lateral conduction path includes at least one lateral npn dual-subjunction transistor structure. One of the lateral npn dual-subjunction transistor structures consists of a fifth doped region 25 (N+) having the first conductivity type, a doped well region 104 (P-type well) having the second conductivity type, and a third doped region 23 (N+) having the first conductivity type. The other lateral npn dual-subjunction transistor structure consists of a fifth doped region 25 (N+) having the first conductivity type, a doped well region 104 (P-type well) having the second conductivity type, and a fourth doped region 24 (N+) having the first conductivity type.

[0079] Figure 11 This discloses a schematic diagram showing the vertical conduction path formed when the dual-subjunction transistor 1B is operated in the forward surge mode. The vertical conduction path is also represented in the accompanying drawings by arrows. Figure 11 The drawn vertical conduction path includes at least one vertical npn bipolar junction transistor structure and at least one forward bias diode connected in series with the vertical npn bipolar junction transistor structure.

[0080] In detail, the formed vertical npn dual-substrate junction transistor structure consists of a fifth doped region 25 (N+) with the first conductivity type, a doped well region 104 (P-type well) with the second conductivity type, a doped layer 102 (N-type layer) with the first conductivity type, and a sixth doped region 26 (N+) with the first conductivity type (as shown in the left half of the figure). Furthermore, another vertical npn dual-substrate junction transistor structure consists of a fifth doped region 25 (N+) with the first conductivity type, a doped well region 104 (P-type well) with the second conductivity type, a doped layer 102 (N-type layer) with the first conductivity type, and a seventh doped region 27 (N+) with the first conductivity type (as shown in the right half of the figure).

[0081] As for the at least one forward-biased diode connected in series with the vertical npn bipolar junction transistor structure, it is composed of a sixth heavily doped region 26 (N+) having the first conductivity type, a first heavily doped region 21 (P+) having the second conductivity type, a doped well region 104 (P-type well) having the second conductivity type, and a third heavily doped region 23 (N+) having the first conductivity type (as shown in the left half of this figure). Furthermore, another forward-biased diode connected in series with the vertical npn bipolar junction transistor structure is composed of a seventh heavily doped region 27 (N+) having the first conductivity type, a second heavily doped region 22 (P+) having the second conductivity type, a doped well region 104 (P-type well) having the second conductivity type, and a fourth heavily doped region 24 (N+) having the first conductivity type (as shown in the right half of this figure).

[0082] In view of the above, based on the accompanying drawings of the present invention Figure 10 and Figure 11 Based on the disclosed current path and technical description, it can be assured that when the dual-subjunction transistor 1B disclosed in this variant example of the present invention operates in the aforementioned forward surge operation mode, the dual-subjunction transistor 1B can also simultaneously generate the aforementioned lateral conduction path and vertical conduction path.

[0083] On the other hand, the dual-subjunction transistor 1B disclosed in this exemplary embodiment of the present invention can also selectively operate in a negative surge operation mode. For a detailed description of this embodiment, please refer further to the accompanying drawings of the present invention. Figure 12 and Figure 13 As shown. Among them, Figure 12This invention discloses a dual-subjunction transistor 1B with lateral and vertical conduction paths, illustrating the generation of one lateral conduction path when operating in the negative surge operation mode. Figure 12 Similarly, this invention uses an arrow-shaped diagram to indicate the generated lateral conduction path. See also... Figure 12 As shown, it can be clearly seen that when the dual-substrate junction transistor 1B with lateral and vertical conduction paths operates in the negative surge operation mode, and its first conductivity type is N-type semiconductor and its second conductivity type is P-type semiconductor, then the first contact P1 and the second contact P2 are electrically coupled to a negative voltage level (-V) and a ground voltage level (GND) respectively, thereby providing the negative surge operation mode.

[0084] As shown by the arrows in the figure, the lateral conduction path formed in this embodiment includes at least one lateral npn dual-substrate junction transistor structure. One of the lateral npn dual-substrate junction transistor structures consists of a third doped region 23 (N+) with the first conductivity type, a doped well region 104 (P-type well) with the second conductivity type, and a fifth doped region 25 (N+) with the first conductivity type. The other lateral npn dual-substrate junction transistor structure consists of a fourth doped region 24 (N+) with the first conductivity type, a doped well region 104 (P-type well) with the second conductivity type, and a fifth doped region 25 (N+) with the first conductivity type.

[0085] besides, Figure 13 This invention discloses a dual-subjunction transistor 1B with lateral and vertical conduction paths, illustrating the generation of one vertical conduction path when operating in the negative surge operation mode. Figure 13 Similarly, this invention uses an arrow-shaped diagram to indicate the generated vertical conduction path. See also... Figure 13As shown, it is evident that when the dual-carrier junction transistor 1B with lateral and vertical conduction paths operates in the negative surge operation mode, the formed vertical conduction path includes at least one silicon controlled rectifier (SCR) structure and two diodes connected in parallel with the SCR structure. The two diodes are connected in series, and the SCR structure exhibits diode-like characteristics. Specifically, the SCR structure formed in this embodiment is a PNPN SCR structure, comprising an eighth doped region 28 (P+) with the second conductivity type, a doped layer 102 (N-type layer) with the first conductivity type, a doped well region 104 (P-type well) with the second conductivity type, and a fifth doped region 25 (N+) with the first conductivity type. Meanwhile, another silicon-controlled rectifier transistor structure comprises a ninth doped region 29 (P+) having the second conductivity type, a doped layer 102 (N-type layer) having the first conductivity type, a doped well region 104 (P-type well) having the second conductivity type, and a fifth doped region 25 (N+) having the first conductivity type. Figure 13 In this invention, the current direction of the above-mentioned PNPN silicon controlled rectifier transistor structure is represented by the current paths "SCR1" and "SCR2", respectively, and the current of the two series-connected diodes is represented by the current paths "DS1" and "DS2", respectively.

[0086] In view of this, when the dual-subjunction transistor 1B in this embodiment operates in the negative surge operation mode, it not only successfully forms a unidirectional element while retaining its original BJT transistor characteristics, but also further generates the silicon controlled rectifier transistor structure and two diode structures connected in parallel with the silicon controlled rectifier transistor structure in the negative surge operation mode. Through this circuit configuration and design, the present invention can effectively achieve the inventive effect of the transistor having a lower clamping voltage and trigger voltage (Vt).

[0087] Furthermore, as stated above, in other alternative embodiments of the present invention, the first and second conductivity types used are not limited to the N-type and P-type semiconductor types provided in the above-described embodiments; in other words, in modifiable alternative embodiments of the present invention, the first conductivity type may optionally be a P-type semiconductor type, and the second conductivity type may optionally be an N-type semiconductor type. Those skilled in the art and those with ordinary knowledge in the art are permitted to make alternative variations and embodiments according to their actual circuit specifications and requirements. For example, Figure 14 Disclose a method according to the present invention Figure 2 The embodiment is an exemplary example of a modification, wherein the first conductivity type and the second conductivity type used are a P-type semiconductor and an N-type semiconductor, respectively. According to Figure 14 The disclosed embodiment, in an exemplary example of a modified version of the present invention, discloses a dual-carrier junction transistor 1C having lateral and vertical conduction paths, comprising a semiconductor substrate 100C having a first conductivity type (referred to as "P-type sub" in the figure), a doped layer 102C having a first conductivity type (referred to as "P-type layer" in the figure), and a doped well region 104C having a second conductivity type (referred to as "N-type well" in the figure).

[0088] exist Figure 14 In the embodiment, the first heavily doped region 21C having a second conductivity type is an N-type semiconductor heavily doped region, denoted as "N+". The second heavily doped region 22C having a second conductivity type is also an N-type semiconductor heavily doped region, denoted as "N+". As for the third heavily doped region 23C, the fourth heavily doped region 24C, and the fifth heavily doped region 25C having a first conductivity type, they are P-type semiconductor heavily doped regions, denoted as "P+" respectively. Similarly, the sixth heavily doped region 26C and the seventh heavily doped region 27C disposed in the doped layer 102C ("P-type layer") having the first conductivity type also have the first conductivity type, they are P-type semiconductor heavily doped regions, and are both denoted as "P+".

[0089] In this exemplary modification, when the first and second conductivity types are P-type and N-type semiconductors respectively, as shown in the figure, the first junction P1 of the transistor is electrically coupled to a low voltage level, indicated as "Low" in the figure; the second junction P2 is electrically coupled to a high voltage level, indicated as "High" in the figure, and the high voltage level of the second junction P2 is greater than the low voltage level of the first junction P1. In general, this invention covers modifications and equivalent embodiments based on the technical content disclosed herein, without being limited to their conductivity types. Furthermore, all variations based on the modifications of this invention are suitable for achieving the inventive objective of providing a dual-subjunction transistor with both lateral and vertical conduction paths.

[0090] To go further, please see Figure 15 As shown, the invention is based on... Figure 14 An exemplary variation of the embodiment, wherein the provided dual-carrier junction transistor 1D with lateral and vertical conduction paths has a first conductivity type of P-type semiconductor and a second conductivity type of N-type semiconductor. Figure 14 The difference in the embodiments is that, in Figure 15 In addition to a semiconductor substrate 100C (P-type sub), a doped layer 102C (P-type layer), a third doped region 23C (P+), a fourth doped region 24C (P+), a fifth doped region 25C (P+), a sixth doped region 26C (P+), and a seventh doped region 27C (P+) of a first conductivity type, and doped well regions 104C (N-type well), a first doped region 21C (N+), and a second doped region 22C (N+) of a second conductivity type, the dual-carrier junction transistor 1D with lateral and vertical conduction paths further includes an eighth doped region 28C (N+) and a ninth doped region 29C (N+) of a second conductivity type. The eighth doped region 28C and the ninth doped region 29C are disposed within the doped layer 102C (P-type layer) of the first conductivity type. In this embodiment, it can be clearly seen that the eighth doped region 28C(N+) with the second conductivity type, the ninth doped region 29C(N+) with the second conductivity type, the third doped region 23C(P+) with the first conductivity type, and the fourth doped region 24C(P+) with the first conductivity type are electrically connected to each other and are electrically coupled to the second junction P2, thereby forming a unidirectional bicarrier junction transistor structure.

[0091] On another note, please refer to Figure 16The figure shows a schematic diagram of a dual-subjunction transistor according to another embodiment of the present invention. As shown in the figure, in this embodiment, the dual-subjunction transistor 1E having lateral and vertical conduction paths further includes an implanted buried layer 110, which has the first conductivity type, and is disposed between a semiconductor substrate 100 having the first conductivity type and a doped layer 102 having the first conductivity type. Figure 16 As shown, based on the fact that the first conductivity type in this embodiment is an N-type semiconductor, the implanted embedded layer 110 in this embodiment can be an N-type implanted layer, and is implemented by placing it between the N-type sub 100 and the N-type layer 102, which is referred to as "NBL" in the accompanying drawings. (As previously disclosed...) Figure 2 Compared to the illustrated embodiment, the present invention can further reduce the equivalent resistance of the transistor by providing the implanted buried layer 110 in the dual-carrier junction transistor 1E. According to an embodiment of the present invention, the ion doping concentration of the implanted buried layer 110 can be set, for example, to 1E18–1E19 cm⁻¹. -3 .

[0092] Based on similar configuration concepts Figure 17 A schematic diagram of the structure of a dual-subjunction transistor according to another embodiment of the present invention is disclosed, which is consistent with the previous description. Figure 14 The difference between the embodiments shown is that, in Figure 17 The dual-carrier junction transistor 1F with lateral and vertical conduction paths disclosed herein may further include an implanted buried layer 110C, such that the implanted buried layer 110C has the first conductivity type, and the implanted buried layer 110C is disposed between the semiconductor substrate 100C having the first conductivity type and the doped layer 102C having the first conductivity type. Figure 17 As shown, based on the fact that the first conductivity type in this embodiment is a P-type semiconductor, the implanted embedded layer 110C in this embodiment can be a P-type implanted layer, and is implemented by placing it between the P-type sub 100C and the P-type layer 102C. This is referred to as "PBL" in the accompanying drawings. (As previously disclosed...) Figure 14 Compared to the illustrated embodiment, the present invention can also reduce the equivalent resistance of the transistor by further providing the aforementioned implanted buried layer 110C in the dual-carrier junction transistor 1F. According to an embodiment of the present invention, the ion doping concentration of the implanted buried layer 110C can, for example, be selected as 1E18 to 1E19 cm⁻¹. -3 .

[0093] Furthermore, to further reduce the equivalent resistance of the transistor, a first well-type region having a first conductivity type and a second well-type region having a first conductivity type can be further configured in the transistor structure. See also... Figure 18 As shown, the dual-carrier junction transistor 1G disclosed in this embodiment further includes a first well region 181 and a second well region 182 formed in a doped layer 102 of a first conductivity type. The first well region 181 and the second well region 182 have the same first conductivity type as the doped layer 102. Based on the fact that the first conductivity type in this embodiment is an N-type semiconductor type, the first well region 181 and the second well region 182 can be implemented as an N-type semiconductor well region in this embodiment, which is referred to as "N-type well" in the accompanying drawings. According to an embodiment of the present invention, a sixth doped region 26 (N+) having the first conductivity type is disposed in the first well region 181 (N-type well) having the first conductivity type, and a seventh doped region 27 (N+) having the first conductivity type is disposed in the second well region 182 (N-type well) having the first conductivity type.

[0094] Similarly, Figure 19 A schematic diagram of a dual-subjunction transistor 1H with lateral and vertical conduction paths according to another embodiment of the present invention is disclosed. In this embodiment, the dual-subjunction transistor 1H is... Figure 18 The example shown is a variation of the dual-subjunction transistor 1G; in Figure 19 In the disclosed embodiments, the first conductivity type is a P-type semiconductor. Therefore, the first well-type region 181C and the second well-type region 182C having the first conductivity type are implemented as a P-type semiconductor well-type region in this embodiment, which is referred to as "P-type well" in the accompanying drawings. According to this embodiment of the present invention, a sixth doped region 26C (P+) having the first conductivity type is disposed in the first well-type region 181C (P-type well) having the first conductivity type, and a seventh doped region 27C (P+) having the first conductivity type is disposed in the second well-type region 182C (P-type well) having the first conductivity type.

[0095] Furthermore, the present invention provides... Figure 20 and Figure 21 Two alternative implementation options are provided for reference. Figure 20 The disclosed embodiments are as follows Figure 18 A modification variation of the embodiment, wherein the implanted inner layer shown may be selectively removed or selectively provided. Figure 20In the dual-substrate junction transistor 1I disclosed herein, the first well region 181 and the second well region 182 (N-type well) can be directly configured without the presence of an implanted buried layer 110 (NBL). A sixth heavily doped region 26 (N+) having the first conductivity type is disposed in the first well region 181 (N-type well) having the first conductivity type, and a seventh heavily doped region 27 (N+) having the first conductivity type is disposed in the second well region 182 (N-type well) having the first conductivity type. This embodiment can also achieve the inventive objective of the present invention and significantly reduce the equivalent resistance of the transistor.

[0096] Based on the same design concept, Figure 21 The disclosed embodiments are as follows Figure 19 A modification variation of the embodiment, wherein the implanted inner layer shown may be selectively removed or selectively provided. Figure 21 In the dual-carrier junction transistor 1J disclosed herein, the first well region 181C and the second well region 182C (P-type well) can be directly disposed in the doped layer 102C (P-type layer) without the presence of an implanted buried layer 110C (PBL). A sixth doped region 26C (P+) having the first conductivity type is disposed in the first well region 181C (P-type well) having the first conductivity type, and a seventh doped region 27C (P+) having the first conductivity type is disposed in the second well region 182C (P-type well) having the first conductivity type. This embodiment can also achieve the inventive objective of the present invention and significantly reduce the equivalent resistance value of the transistor.

[0097] In view of the above, it is evident from the detailed technical solutions of the several embodiments provided in the preceding paragraphs that the dual-subjunction transistor structure disclosed in this invention is effective and simultaneously possesses both lateral and vertical conduction path characteristics. As disclosed in this invention, by placing the first contact P1 and the second contact P2 together on the same surface of the dual-subjunction transistor, the back-side metallization process required in the prior art is eliminated. Therefore, this invention not only optimizes the transistor's process steps and manufacturing costs but also maintains a low circuit layout complexity.

[0098] Therefore, in view of the above, this invention discloses several embodiments suitable for practical applications. Its advantages lie not only in providing excellent layout flexibility for circuit design, but also in offering several different circuit configuration designs. Accordingly, without departing from the spirit of this invention, those skilled in the art can make appropriate modifications or layout changes based on the technical content and methods disclosed in this invention, according to the necessary circuits, so that this invention is not limited to the specific configurations and / or circuit designs disclosed in the above embodiments. That is to say, any modifications or changes made based on the spirit of this invention should still fall within the scope of this invention, making this invention cover its modifications and equivalent embodiments.

[0099] It is evident that the present invention possesses numerous advantages over existing technologies. Therefore, in view of the above, the present invention not only possesses the necessary novelty and inventiveness, but also effectively addresses and avoids the shortcomings remaining in existing technologies. Therefore, in view of the above, compared with existing technologies, it is obvious that the embodiments and circuit architecture disclosed in the present invention can effectively solve many shortcomings remaining in existing technologies and present more efficient circuit performance. Furthermore, the technical solution provided by the present invention can be applied not only to common electronic components, but also widely to various electronic circuit components in the semiconductor industry, integrated circuit industry, or power electronics. It is evident that the technical solution claimed in this application has excellent industrial applicability and competitiveness. At the same time, the present invention also verifies, through various experimental and empirical data, that the technical features, methods, and effects achieved by the present invention are significantly different from existing solutions, and cannot be easily accomplished by those skilled in the art.

[0100] Therefore, in summary, based on the technical solutions taught by this invention, those skilled in the art can make modifications or variations according to the specifications and requirements of their actual circuits without departing from the spirit and intent of this invention. However, even with equivalent modifications, these modifications should still fall within the scope of this invention. In other words, this invention is not limited to the aforementioned exemplary examples.

[0101] The embodiments described above are merely illustrative of the technical ideas and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should still be covered within the protection scope of the present invention.

Claims

1. A dual-carrier junction transistor having lateral and vertical conduction paths, characterized in that, include: A semiconductor substrate having a first conductivity type; A doped layer having the first conductivity type, and the doped layer is disposed on the semiconductor substrate; A doped well region having a second conductivity type is disposed within a doped layer having a first conductivity type, wherein the first conductivity type and the second conductivity type are different conductivity types. The doped well region having the second conductivity type further comprises a first heavily doped region having the second conductivity type, a second heavily doped region having the second conductivity type, a third heavily doped region having the first conductivity type, a fourth heavily doped region having the first conductivity type, and a fifth heavily doped region having the first conductivity type. The fifth heavily doped region having the first conductivity type is electrically coupled to a first junction. The third heavily doped region having the first conductivity type and the fourth heavily doped region having the first conductivity type are jointly electrically coupled to a second junction. The first heavily doped region having the second conductivity type and the second heavily doped region having the second conductivity type are separated by the third heavily doped region having the first conductivity type, the fourth heavily doped region having the first conductivity type, and the fifth heavily doped region having the first conductivity type. A sixth doped region and a seventh doped region having the first conductivity type are disposed in the doped layer having the first conductivity type. The sixth doped region and the seventh doped region having the first conductivity type are separated by a doped well region having the second conductivity type. The sixth doped region having the first conductivity type is electrically coupled to the first doped region having the second conductivity type, and the seventh doped region having the first conductivity type is electrically coupled to the second doped region having the second conductivity type. The sixth doped region having the first conductivity type and the first doped region having the second conductivity type are electrically coupled and in a floating state, and the seventh doped region having the first conductivity type and the second doped region having the second conductivity type are electrically coupled and in a floating state. When the bipolar junction transistor with lateral and vertical conduction paths is operated, it has the characteristics of a bidirectional transistor.

2. The bipolar junction transistor having lateral and vertical conduction paths according to claim 1, wherein, When the first conductivity type is N-type semiconductor and the second conductivity type is P-type semiconductor, the first contact and the second contact are electrically coupled to a positive voltage level and a ground voltage level, respectively, thereby providing a positive surge operation mode.

3. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 2, characterized in that, When operating in the positive surge mode, a lateral conduction path is generated, and the lateral conduction path includes at least one lateral npn bipolar junction transistor structure.

4. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 3, characterized in that, The at least one lateral npn dual-subjunction transistor structure is composed of the fifth doped region having the first conductivity type, the doped well region having the second conductivity type, and the third doped region having the first conductivity type. Furthermore, the at least one lateral npn dual-subjunction transistor structure also includes a fifth doped region having the first conductivity type, the doped well region having the second conductivity type, and the fourth doped region having the first conductivity type.

5. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 2, characterized in that, When operating in the positive surge operation mode, a vertical conduction path is generated, and the vertical conduction path includes at least one vertical npn bipolar junction transistor structure and at least one forward bias diode connected in series with the vertical npn bipolar junction transistor structure.

6. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 5, characterized in that, The at least one vertical npn dual-subjunction transistor structure is composed of a fifth doped region having the first conductivity type, a doped well region having the second conductivity type, a doped layer having the first conductivity type, and a sixth doped region having the first conductivity type. Furthermore, the at least one vertical npn dual-subjunction transistor structure also includes a fifth doped region having the first conductivity type, a doped well region having the second conductivity type, a doped layer having the first conductivity type, and a seventh doped region having the first conductivity type.

7. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 5, characterized in that, The at least one forward bias diode is composed of a sixth heavily doped region having the first conductivity type, a first heavily doped region having the second conductivity type, a doped well region having the second conductivity type, and a third heavily doped region having the first conductivity type. Furthermore, the at least one forward bias diode also includes a seventh heavily doped region having the first conductivity type, a second heavily doped region having the second conductivity type, a doped well region having the second conductivity type, and a fourth heavily doped region having the first conductivity type.

8. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 1, characterized in that, When the first conductivity type is N-type semiconductor and the second conductivity type is P-type semiconductor, the first contact and the second contact are electrically coupled to a negative voltage level and a ground voltage level, respectively, thereby providing a negative surge operation mode.

9. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 8, characterized in that, When operating in the negative surge mode, a lateral conduction path is generated, and the lateral conduction path includes at least one lateral npn bipolar junction transistor structure.

10. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 9, characterized in that, The at least one lateral npn dual-subjunction transistor structure is composed of a third heavily doped region having the first conductivity type, a doped well region having the second conductivity type, and a fifth heavily doped region having the first conductivity type. Furthermore, the at least one lateral npn dual-subjunction transistor structure also includes a fourth heavily doped region having the first conductivity type, a doped well region having the second conductivity type, and a fifth heavily doped region having the first conductivity type.

11. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 1, characterized in that, It also includes an eighth doped region and a ninth doped region, wherein the eighth doped region and the ninth doped region have the second conductivity type, the eighth doped region having the second conductivity type and the ninth doped region having the second conductivity type are disposed in the doped layer having the first conductivity type, and the eighth doped region having the second conductivity type, the ninth doped region having the second conductivity type, the third doped region having the first conductivity type and the fourth doped region having the first conductivity type are electrically coupled to the second junction.

12. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 11, characterized in that, When the first conductivity type is N-type semiconductor and the second conductivity type is P-type semiconductor, the first contact and the second contact are electrically coupled to a positive voltage level and a ground voltage level, respectively, thereby providing a positive surge operation mode.

13. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 12, characterized in that, When operating in the positive surge mode, a lateral conduction path is generated, and the lateral conduction path includes at least one lateral npn bipolar junction transistor structure.

14. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 13, characterized in that, The at least one lateral npn dual-subjunction transistor structure is composed of the fifth doped region having the first conductivity type, the doped well region having the second conductivity type, and the third doped region having the first conductivity type. Furthermore, the at least one lateral npn dual-subjunction transistor structure also includes a fifth doped region having the first conductivity type, the doped well region having the second conductivity type, and the fourth doped region having the first conductivity type.

15. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 12, characterized in that, When operating in the positive surge operation mode, a vertical conduction path is generated, and the vertical conduction path includes at least one vertical npn bipolar junction transistor structure and at least one forward bias diode connected in series with the vertical npn bipolar junction transistor structure.

16. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 15, characterized in that, The at least one vertical npn dual-subjunction transistor structure is composed of a fifth doped region having the first conductivity type, a doped well region having the second conductivity type, a doped layer having the first conductivity type, and a sixth doped region having the first conductivity type. Furthermore, the at least one vertical npn dual-subjunction transistor structure also includes a fifth doped region having the first conductivity type, a doped well region having the second conductivity type, a doped layer having the first conductivity type, and a seventh doped region having the first conductivity type.

17. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 15, characterized in that, The at least one forward bias diode is composed of a sixth heavily doped region having the first conductivity type, a first heavily doped region having the second conductivity type, a doped well region having the second conductivity type, and a third heavily doped region having the first conductivity type. Furthermore, the at least one forward bias diode also includes a seventh heavily doped region having the first conductivity type, a second heavily doped region having the second conductivity type, a doped well region having the second conductivity type, and a fourth heavily doped region having the first conductivity type.

18. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 11, characterized in that, When the first conductivity type is N-type semiconductor and the second conductivity type is P-type semiconductor, the first contact and the second contact are electrically coupled to a negative voltage level and a ground voltage level, respectively, thereby providing a negative surge operation mode.

19. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 18, characterized in that, When operating in the negative surge mode, a lateral conduction path is generated, and the lateral conduction path includes at least one lateral npn bipolar junction transistor structure.

20. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 19, characterized in that, The at least one lateral npn dual-subjunction transistor structure is composed of a third heavily doped region having the first conductivity type, a doped well region having the second conductivity type, and a fifth heavily doped region having the first conductivity type. Furthermore, the at least one lateral npn dual-subjunction transistor structure also includes a fourth heavily doped region having the first conductivity type, a doped well region having the second conductivity type, and a fifth heavily doped region having the first conductivity type.

21. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 18, characterized in that, When operating in the negative surge mode, a vertical conduction path is generated, and the vertical conduction path includes at least one silicon controlled rectifier transistor structure and two diodes connected in parallel with the silicon controlled rectifier transistor structure, the two diodes being connected in series, and the silicon controlled rectifier transistor structure having diode characteristics.

22. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 21, characterized in that, The at least one silicon controlled rectifier transistor structure is composed of the eighth doped region having the second conductivity type, the doped layer having the first conductivity type, the doped well region having the second conductivity type, and the fifth doped region having the first conductivity type. Furthermore, the at least one silicon controlled rectifier transistor structure also includes a ninth doped region having the second conductivity type, the doped layer having the first conductivity type, the doped well region having the second conductivity type, and the fifth doped region having the first conductivity type.

23. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 1, characterized in that, When the first conductivity type is P-type semiconductor and the second conductivity type is N-type semiconductor, the first contact and the second contact are electrically coupled to a low voltage level and a high voltage level, respectively, and the high voltage level of the second contact is greater than the low voltage level of the first contact.

24. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 1, characterized in that, It also includes an implantable embedded layer having the first conductivity type, and the implantable embedded layer is disposed between the semiconductor substrate having the first conductivity type and the doped layer having the first conductivity type.

25. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 1, characterized in that, It also includes a first well-shaped region and a second well-shaped region, the first well-shaped region and the second well-shaped region having the first conductivity type, the first well-shaped region having the first conductivity type and the second well-shaped region having the first conductivity type being formed in the doped layer having the first conductivity type, and the sixth doped region having the first conductivity type being disposed in the first well-shaped region having the first conductivity type, and the seventh doped region having the first conductivity type being disposed in the second well-shaped region having the first conductivity type.

26. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 24, characterized in that, It also includes a first well-shaped region and a second well-shaped region, the first well-shaped region and the second well-shaped region having the first conductivity type, the first well-shaped region having the first conductivity type and the second well-shaped region having the first conductivity type being formed in the doped layer having the first conductivity type, and the sixth doped region having the first conductivity type being disposed in the first well-shaped region having the first conductivity type, and the seventh doped region having the first conductivity type being disposed in the second well-shaped region having the first conductivity type.

27. The dual-carrier junction transistor with lateral and vertical conduction paths as described in claim 1, characterized in that, The first contact and the second contact are both disposed on the same surface of the dual-subjunction transistor having lateral and vertical conduction paths.

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