A blocking junction double trench IGBT capable of assisted depletion and zero kickback

Abstract

The application discloses a blocking junction double-trench insulated bipolar transistor (SJBJ-IGBT) capable of realizing auxiliary depletion and zero back jump, and belongs to the technical field of power semiconductors. The application adds N columns and P columns in the P drift region and the N drift region of a traditional blocking junction insulated bipolar transistor (IPBJ-IGBT), and forms an auxiliary depletion drift region with a super-junction structure. In the forward blocking state of the device, the uniform electric field distribution in the device is realized due to the lateral auxiliary depletion effect of the internal super-junction, and there is no electric field peak, so that the withstand voltage of the device is greatly improved. In the open condition of the device, the reduction of the internal effective drift region area makes the internal blocking junction side of the P drift region more easily accumulate excess holes, so that the device is more easily turned on, and the back jump phenomenon of the traditional device is eliminated, the zero back jump voltage and the lower turn-on loss are realized.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and in particular to a blocking junction dual trench IGBT that can achieve assisted depletion and zero backflow. Background Technology

[0002] Insulated Gate Bipolar Transistor (IGBT) has become a core component in high-capacity power electronic systems due to its advantages such as high breakdown voltage and low conduction loss. It is widely used in new energy power generation, electrified transportation and smart grids. The vigorous development of these fields has also driven the continuous improvement of IGBT structure. Today, the development trend of IGBT is still to continue to improve reliability and reduce losses.

[0003] IGBT devices based on the superjunction (SJ) structure were first proposed in 2000. Compared with traditional IGBTs, superjunction IGBTs (SJ-IGBTs) exhibit better electrical performance. SJ-IGBT devices significantly increase the doping concentration in the drift region by incorporating sequentially arranged P-pillars and N-pillars, resulting in lower saturation on-state voltage drop at both room and high temperatures. Due to the higher doping concentration of the superjunction structure, the total number of charge carriers stored in the drift region of an SJ-IGBT device is less for the same on-current. Therefore, fewer minority carriers need to be extracted during device turn-off, allowing for faster turn-off and reduced turn-off energy.

[0004] Planar gate structure is a mature structure commonly used in high-voltage IGBTs, applied in environments with high reliability requirements such as power transmission and high-speed rail. However, due to its parasitic JFET resistance, planar gate IGBTs have a larger saturation voltage drop compared to slot gate structures, increasing dynamic losses. Slot gate IGBTs (TIGBTs), with their smaller cell spacing and higher current density, have become a commonly used structure for reducing conduction losses. However, TIGBTs exhibit electric field accumulation at the bottom of the slot gate, limiting the increase in blocking voltage. Furthermore, their short-circuit current is relatively large, resulting in weak short-circuit withstand capability. Introducing a P-Floating (FP) shielding layer at the bottom of the slot gate can reduce the peak electric field, but this introduces additional MOS resistance, increasing device losses. Simultaneously introducing a clamping diode in the P-base region between the slot and gate can improve both turn-off losses and on-state voltage drop (E). off -V CEsatA compromise needs to be struck between improving the short-circuit withstand capability of IGBTs and enhancing their short-circuit withstand capability, but existing solutions are mostly concentrated at the 1200V voltage level. Using a wide slot-gate spacing or a FP (Floating-P-body) region can reduce the device current density and significantly improve the short-circuit withstand capability of the IGBT. However, due to the negative gate capacitance effect, the FP-type slot-gate IGBT (FP-IGBT) experiences a short-circuit withstand capability through Miller capacitance C. GC Displacement current is generated at the gate, causing fluctuations in the gate voltage, reducing the gate control capability of the IGBT, and also causing EMI noise problems.

[0005] For IGBTs at voltage levels of 1700V and below, structures such as floating P-body regions, shielded trenches, and split P-body structures can improve EMI issues, but these require strict manufacturing precision. For IGBTs with voltage levels above 2500V, foreign IGBT manufacturers have launched 3300V-TIGBT products. Their basic structure uses a discrete floating P-body with a junction depth exceeding the trench gate depth to reduce the peak electric field at the trench gate bottom and enhance conductance modulation, thus improving EMI. off -V CEsat There is a trade-off, but the discrete floating FP region will affect the device's withstand voltage and on-state voltage drop; while connecting the discrete FP to ground through a fixed resistor provides some hole path, which can easily increase conduction loss, thus reducing the trade-off window of the design. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides a simple and reliable blocking junction dual-trench IGBT that can achieve auxiliary depletion and zero backflow.

[0007] The technical solution of this invention to solve the above problems is: a blocked junction dual-trench IGBT that can achieve assisted depletion and zero backflow, comprising a metal collector, a P+ collector region, and an FS cutoff region stacked sequentially from bottom to top. The FS cutoff region is provided with a first N-drift region, a first P-drift region, and a second N-drift region sequentially from left to right. A second P-drift region, a third N-drift region, and a third P-drift region are respectively disposed on the top layer of the first N-drift region, the first P-drift region, and the second N-drift region. Carrier storage regions are provided on the top layer of the second P-drift region, the middle region of the top layer of the third N-drift region, and the top layer of the third P-drift region. A P-body region is provided on the top layer of the two carrier storage regions located on the top layer of the second P-drift region and the top layer of the third P-drift region. A P+ floating P-body region is provided on the top layer of the carrier storage region located in the middle region of the top layer of the third N-drift region. The top layer of the body region is provided with a P+ base region and an N+ emitter region sequentially from the outside to the inside, and a metal emitter is provided on the top layer of the P+ base region and the N+ emitter region; an IGBT gate structure is provided between the two N+ emitter regions and the P+ floating P-body region; the IGBT gate structure includes a gate electrode and a gate dielectric layer, the gate dielectric layer spans the two N+ emitter regions and the P+ floating P-body region, and the lower part of the gate dielectric layer extends downward from the left and right sides of the P+ floating P-body region along the vertical direction of the device into the N-drift region to form two trenches, and the two gate electrodes are respectively set in the two trenches; the combination of the first N-drift region and the second P-drift region, and the combination of the third P-drift region and the second N-drift region, each form a blocking junction, and the third N-drift region and the first P-drift region each form an auxiliary depletion region; the blocking junction structure is located at the PN junction formed by the third N-drift region and the first P-drift region in the forward blocking state.

[0008] The aforementioned blocked junction dual-trench IGBT, which can achieve auxiliary depletion and zero backflow, has its outer side of the gate dielectric layer in contact with the N+ emitter region, P-body region, carrier storage region on the top layer of the second P-drift region or the third P-drift region, and the third N-drift region; and its inner side of the gate dielectric layer in contact with the carrier storage region in the middle region of the top layer of the P+ floating P-body region and the third N-drift region.

[0009] The above-mentioned blocking junction dual-trench IGBT can achieve auxiliary depletion and zero backflow, wherein the depth and width of the two gate electrodes of the IGBT gate structure are consistent.

[0010] The aforementioned blocking junction dual-trench IGBT, which can achieve auxiliary depletion and zero backflow, has the same depth and width in the first N-drift region, the second N-drift region, the second P-drift region, and the third P-drift region.

[0011] The aforementioned blocking junction dual-trench IGBT, which can achieve auxiliary depletion and zero backflow, has the same depth and width for the first P-drift region and the third N-drift region.

[0012] The aforementioned blocking junction dual-trench IGBT, which can achieve auxiliary depletion and zero backflow, has a sum of widths of the second P-drift region and the third P-drift region that is consistent with the width of the third N-drift region.

[0013] The aforementioned blocking junction dual-trench IGBT, which can achieve auxiliary depletion and zero backflow, has a sum of widths of the first N-drift region and the second N-drift region that is consistent with the width of the first P-drift region.

[0014] The aforementioned blocking junction dual-trench IGBT, which can achieve auxiliary depletion and zero backflow, has the depths of the first N-drift region, the second N-drift region, the second P-drift region, and the third P-drift region being consistent with the depth of the first P-drift region.

[0015] The aforementioned blocking junction dual-trench IGBT can achieve auxiliary depletion and zero backflow. The semiconductor materials used in the entire IGBT are silicon, silicon carbide, diamond, gallium oxide, or gallium nitride.

[0016] The beneficial effects of this invention are as follows:

[0017] 1. The present invention forms a blocking junction structure inside the device drift region. When the device is in forward turn-off, the blocking junction is reverse biased, and the electric field is mainly borne by the blocking junction. At the same time, the blocking junction contains a first P drift region and a third N drift region on both sides, which plays an auxiliary depletion role, reduces the peak electric field inside the device, makes the electric field uniformly distributed, and greatly improves the withstand voltage and reliability of the device.

[0018] 2. The third N-drift region and the first P-drift region of the present invention form an auxiliary depletion region. When the device is turned on, the reduction in the area of ​​the internal effective drift region makes it easier for the blocking junction side of the second P-drift region and the third P-drift region to accumulate excessive holes, making it easier for the device to be turned on and reducing the turn-on loss.

[0019] 3. When the device of the present invention is turned on, the PN junction formed by the first P drift region and the third N drift region is in a forward biased state, and there is an additional current path, which eliminates the bounce phenomenon of traditional blocking junction IGBT devices.

[0020] 4. The blocking junction structure with an auxiliary depletion drift region proposed in this invention is compatible with existing superjunction IGBT device fabrication processes. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a traditional dual-trench gate blocking junction IGBT device.

[0022] Figure 2 This is a schematic diagram of the structure of the present invention.

[0023] Figure 3 This is an equivalent circuit diagram of the IGBT structure (b) provided by the present invention and the traditional double trench gate blocking junction IGBT structure (a).

[0024] Figure 4 This is a comparison chart of the forward blocking voltage curves of the IGBT structure provided by this invention and the traditional double trench gate blocking junction IGBT structure.

[0025] Figure 5 This is a comparison chart of the output characteristic curves of the IGBT structure provided by this invention and the traditional double trench gate blocking junction IGBT structure.

[0026] Figure 6 This is a comparison diagram of the turn-on waveforms of the IGBT structure provided by this invention and the traditional double trench gate blocking junction IGBT structure. Detailed Implementation

[0027] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0028] like Figure 2As shown, a blocking junction dual-trench IGBT capable of assisted depletion and zero backflow includes a metal collector 13, a P+ collector region 12, and an FS cutoff region 11 stacked sequentially from bottom to top. The FS cutoff region 11 has a first N-drift region 8, a first P-drift region 9, and a second N-drift region 10 arranged sequentially from left to right. A second P-drift region 5 and a third N-drift region 6 are respectively disposed on the top layer of the first N-drift region 8, the first P-drift region 9, and the second N-drift region 10. The third P-drift region 7, the top layer of the second P-drift region 5, the middle region of the top layer of the third N-drift region 6, and the top layer of the third P-drift region 7 are all equipped with carrier storage regions 4. The top layers of the two carrier storage regions 4 located at the top layers of the second P-drift region 5 and the third P-drift region 7 are each equipped with a Pbody region 3. The top layer of the carrier storage region 4 located in the middle region of the top layer of the third N-drift region 6 is equipped with a P+ floating pbody region 16. The tops of the two pbody regions 3 are... Each layer has a P+ base region 1 and an N+ emitter region 2 arranged sequentially from the outside to the inside. A metal emitter 17 is provided on the top layer of the P+ base region 1 and the N+ emitter region 2. An IGBT gate structure is provided between the two N+ emitter regions 2 and the P+ floating pbody region 16. The IGBT gate structure includes a gate electrode 14 and a gate dielectric layer 15. The gate dielectric layer 15 spans the two N+ emitter regions 2 and the P+ floating pbody region 16. The lower part of the gate dielectric layer 15 extends downward from the left and right sides of the P+ floating pbody region 163 along the vertical direction of the device into the N-drift region to form two trenches. The two gate electrodes 14 are respectively disposed in the two trenches. The combination of the first N-drift region 8 and the second P-drift region 5, and the combination of the third P-drift region 7 and the second N-drift region 10, each form a blocking junction. The third N-drift region 6 and the first P-drift region 9 each form an auxiliary depletion region. The blocking junction structure is located at the PN junction formed by the third N-drift region 6 and the first P-drift region 9 in the forward blocking state.

[0029] The outer side of the gate dielectric layer 15 is in contact with the carrier storage region 4 and the third N-drift region 6 on the top layer of the N+ emitter region 2, Pbody region 3, second P-drift region 5 or third P-drift region 7; the inner side of the gate dielectric layer 15 is in contact with the carrier storage region 4 in the middle region of the top layer of the P+ floating pbody region 16 and the third N-drift region 6.

[0030] The semiconductor materials used in the entire IGBT can be silicon, silicon carbide, diamond, gallium oxide, or gallium nitride.

[0031] The blocking junction formed by the second P-drift region 5, the third P-drift region 7, the first N-drift region 8, and the second N-drift region 10, and the auxiliary depletion region structure formed by the third N-drift region 6 and the first P-drift region 9 in the drift region of the present invention must satisfy the following conditions:

[0032] 1) The second P-drift region 5, the third P-drift region 7, the first N-drift region 8, and the second N-drift region 10 must be located below the gate electrode 14 and the gate dielectric layer 15;

[0033] 2) The depth and width of the second P-drift zone 5, the third P-drift zone 7, the first N-drift zone 8, and the second N-drift zone 10 should be consistent;

[0034] 3) The blocking junction formed by the second P-drift region 5, the third P-drift region 7, the first N-drift region 8, and the second N-drift region 10 should be located in the middle of the device drift region;

[0035] 4) The auxiliary depletion region formed by the third N-drift region 6 and the first P-drift region 9 should be located inside the second P-drift region 5, the third P-drift region 7, the first N-drift region 8, and the second N-drift region 10;

[0036] 5) The depth of the auxiliary depletion zone formed by the third N-drift zone 6 and the first P-drift zone 9 should be consistent with the depth of the second P-drift zone 5, the third P-drift zone 7, the first N-drift zone 8, and the second N-drift zone 10;

[0037] 6) The depth and width of the first P-drift region 9 and the third N-drift region 6 are consistent; the sum of the widths of the second P-drift region 5 and the third P-drift region 7 is consistent with the width of the third N-drift region 6; the sum of the widths of the first N-drift region 8 and the second N-drift region 10 is consistent with the width of the first P-drift region 9.

[0038] 7) The depth and width of the two gate electrodes 14 of the IGBT gate structure are consistent.

[0039] 8) Except for the different doping types, the doping concentration should be consistent in each drift region.

[0040] like Figure 3 As shown, Figure 3 The left side shows the equivalent circuit of a traditional blocking junction IGBT, and the right side shows the equivalent circuit of this invention. A traditional blocking junction IGBT is equivalent to a MOSFET + SCR model. Because the thyristor requires a small voltage trigger to turn on, the traditional blocking junction IGBT exhibits a bounce phenomenon. The IGBT proposed in this invention is equivalent to a MOSFET + SCR + diode model. The diode connected in parallel with the thyristor plays an auxiliary turn-on role, eliminating the bounce phenomenon of the traditional blocking junction IGBT; and it plays an auxiliary depletion role during turn-off, reducing the peak value of the internal electric field of the device, thereby improving the breakdown voltage.

[0041] The principles of the present invention will be explained in detail below with reference to embodiments:

[0042] In the forward blocking state, the electric field of the proposed blocking junction dual-trench IGBT is almost entirely borne by the entire drift region, with no significant electric field peaks inside. Because the device uses alternating P-pillars and N-pillars instead of the traditional uniformly doped P-type and N-type drift regions, when the device is subjected to high voltage, the mutual depletion of the N-pillars and P-pillars generates a transverse electric field, making the electric field distribution flatter, improving the electric field spike phenomenon, reducing local electric field intensity, and thus increasing the voltage that the device can withstand during forward blocking.

[0043] During the turn-on process, the potential of the carrier storage region 4 is clamped by the electron channel. Electrons diffuse from the metal emitter 17 through the carrier storage region 4 to the second P-drift region 5 and the third P-drift region 7. Holes travel from the metal collector 13 through the FS cutoff region 11 to the first N-drift region 8 and the second N-drift region 10t. Due to the electric field modulation effect of the first P-drift region 9, holes can more easily cross the blocking junction to reach the second P-drift region 5 and the third P-drift region 7, meaning the device is easier to turn on. Therefore, there is no bounce phenomenon when the device is turned on. Consequently, the current rise time and conduction loss are significantly reduced during the device turn-on process.

[0044] During forward conduction, the drift region and P-pillars / N-pillars of this invention are filled with an excess of holes far exceeding the doping level of the drift region, thus having no additional impact on the forward characteristics of the device.

[0045] To verify the beneficial effects of this invention, taking a 650V dual-groove gate IGBT design as an example, TCAD software was used to... Figure 1 The traditional dual-trench gate blocking junction IGBT shown and Figure 2 The proposed blocking junction dual-trench IGBT device is simulated and compared, including the device's static parameters: forward blocking voltage, saturation on-state voltage drop, and threshold voltage, and dynamic parameters: turn-on loss Eon and turn-off loss Eoff. The comparison results are shown in Table 1.

[0046] Table 1

[0047] Forward blocking voltage (V) 813 718 Threshold voltage (V) 4.34 4.55 On-state voltage drop (V) 1.21 1.22 <![CDATA[Eon(mJ / cm 2 )]]> 1.607 3.011 <![CDATA[Eoff(mJ / cm 2 )]]> 3.376 3.225

[0048] As can be clearly seen from the table, the forward blocking voltage of the present invention is 813V, which is 11.7% higher than that of the traditional structure. The on-state voltage drop is comparable to that of the traditional structure, the turn-on loss is reduced by 46.7% compared to the traditional structure, and the turn-off loss is comparable to that of the traditional structure.

[0049] Figure 3The circuit equivalent diagram shows that a traditional blocking junction IGBT is equivalent to a MOSFET + thyristor (SCR) model. Because the SCR requires a small voltage trigger to turn on, the traditional blocking junction IGBT exhibits a bounce phenomenon. The IGBT proposed in this invention is equivalent to a MOSFET + SCR + diode model. The diode connected in parallel with the SCR plays an auxiliary turn-on role, eliminating the bounce phenomenon of the traditional blocking junction IGBT. Furthermore, it plays an auxiliary depletion role during blocking, reducing the peak electric field inside the device and thus improving the breakdown voltage.

[0050] Figure 4 The breakdown characteristics directly show that the breakdown voltage of the present invention is 11.7% higher than that of the conventional blocked junction IGBT.

[0051] Figure 5 The forward conduction characteristics show that the forward voltage drop of the present invention is not significantly different from that of the traditional blocking junction IGBT when conducting at high current, and they have the same on-resistance. Furthermore, the present invention exhibits no bounce phenomenon when conducting at low current.

[0052] Figure 6 The results of the turnaround curve directly indicate that, at V CE At 400V, the current rise time and turn-on loss of this invention are significantly improved compared to the conventional structure. This is because the effective drift region area of ​​this invention is smaller than that of the conventional structure, allowing externally injected carriers to fill the internal drift region more quickly. Therefore, during the turn-on process, the current rise time and Eon are significantly reduced, and carriers can be quickly injected into the channel to rapidly form a conduction channel, greatly accelerating the turn-on process.

[0053] It should be noted that this invention is not only applicable to the currently tested 650V dual-groove gate IGBT devices, but also to IGBT devices in the medium voltage range based on planar gates and slot gates. The blocking structure that achieves auxiliary depletion and zero bounce can also be applied to lateral power device structures.

Claims

1. A blocking junction dual-trench IGBT capable of achieving assisted depletion and zero backflow, comprising a metal collector, a P+ collector region, and an FS cutoff region stacked sequentially from bottom to top, characterized in that: The FS cutoff region is provided with a first N-drift region, a first P-drift region, and a second N-drift region from left to right. A second P-drift region, a third N-drift region, and a third P-drift region are respectively provided on the top layer of the first N-drift region, the first P-drift region, and the second N-drift region. Carrier storage regions are provided on the top layer of the second P-drift region, the middle region of the top layer of the third N-drift region, and the top layer of the third P-drift region. A P-body region is provided on the top layer of each of the two carrier storage regions located on the top layer of the second P-drift region and the top layer of the third P-drift region. A P+ floating P-body region is provided on the top layer of the carrier storage region located in the middle region of the top layer of the third N-drift region. A P+ base region and an N+ emitter region are provided sequentially from the outside to the inside of each of the two P-body regions. A metal emitter is provided on the top layer of the emitter region; an IGBT gate structure is provided between the two N+ emitter regions and the P+ floating P-body region; the IGBT gate structure includes a gate electrode and a gate dielectric layer, the gate dielectric layer spans the two N+ emitter regions and the P+ floating P-body region, and the lower part of the gate dielectric layer extends downward from the left and right sides of the P+ floating P-body region along the vertical direction of the device into the N-drift region to form two trenches, and the two gate electrodes are respectively disposed in the two trenches; the combination of the first N-drift region and the second P-drift region, and the combination of the third P-drift region and the second N-drift region, each form a blocking junction, and the third N-drift region and the first P-drift region each form an auxiliary depletion region; the blocking junction structure is located at the PN junction formed by the third N-drift region and the first P-drift region in the forward blocking state.

2. The blocking junction dual-trench IGBT with auxiliary depletion and zero backflow as described in claim 1, characterized in that: The outer side of the gate dielectric layer is in contact with the N+ emitter region, the P-body region, the carrier storage region on the top layer of the second P-drift region or the third P-drift region, and the third N-drift region; the inner side of the gate dielectric layer is in contact with the carrier storage region in the middle region of the top layer of the P+ floating P-body region and the third N-drift region.

3. The blocking junction dual-trench IGBT with auxiliary depletion and zero backflow as described in claim 1, characterized in that: The depth and width of the two gate electrodes of the IGBT gate structure are consistent.

4. The blocking junction dual-trench IGBT with auxiliary depletion and zero backflow as described in claim 1, characterized in that: The depth and width of the first N-drift region, the second N-drift region, the second P-drift region, and the third P-drift region are consistent.

5. The blocking junction dual-trench IGBT with auxiliary depletion and zero backflow as described in claim 1, characterized in that: The depth and width of the first P-drift region and the third N-drift region are consistent.

6. The blocking junction dual-trench IGBT capable of achieving auxiliary depletion and zero backflow according to claim 1, characterized in that: The sum of the widths of the second P-drift region and the third P-drift region is consistent with the width of the third N-drift region.

7. The blocking junction dual-trench IGBT capable of achieving auxiliary depletion and zero backflow according to claim 1, characterized in that: The sum of the widths of the first N-drift region and the second N-drift region is consistent with the width of the first P-drift region.

8. The blocking junction dual-trench IGBT with auxiliary depletion and zero backflow as described in claim 1, characterized in that: The depths of the first N-drift region, the second N-drift region, the second P-drift region, and the third P-drift region are consistent with the depth of the first P-drift region.

9. The blocking junction dual-trench IGBT with auxiliary depletion and zero backflow as described in claim 1, characterized in that: The semiconductor materials used in the entire IGBT are silicon, silicon carbide, diamond, gallium oxide, or gallium nitride.

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