A passive phase shifter based on all-pass networks and low-pass networks

Abstract

This invention discloses a passive phase shifter based on an all-pass network and a low-pass network. The invention includes a 90° phase shifting unit composed of a magnetically coupled all-pass network, an inter-unit matching network composed of on-chip inductors, a 45° phase shifting unit composed of a magnetically coupled all-pass network, a phase fine-tuning unit composed of a low-pass network, and an amplitude calibration unit composed of digital step attenuators. This invention uses an all-pass network structure to implement the 45° and 90° phase shifting units and a low-pass network structure to implement the phase fine-tuning unit. After fabrication, the phase shift degree can be calibrated and optimized by adjusting the control word of the on-chip variable capacitor, thereby improving the phase shift accuracy. The passive phase shifter disclosed in this invention can be manufactured using CMOS technology and has advantages such as zero power consumption, high linearity, bidirectional operation support, direct digital control, and high phase shift accuracy.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to a passive phase shifter based on an all-pass network and a low-pass network. Background Technology

[0002] In recent years, the application of wireless communication in the sub-6GHz band has become increasingly widespread, making the communication frequency bands below 6GHz gradually congested. Meanwhile, the radio frequency and millimeter wave bands above 6GHz have abundant bandwidth resources, suitable for broadband millimeter wave 5G communication and high-throughput low-Earth orbit satellite communication. However, with the increase in operating frequency, the path loss of signals increases during wireless transmission. To achieve long-distance transmission, phased array antenna technology improves the equivalent omnidirectional radiated power of the transmitter and the signal-to-noise ratio of the receiver through beamforming, compensating for the large path loss of high-frequency signals, while also enabling flexible signal coverage.

[0003] Beam scanning in a phased array system is achieved by controlling the phase of the received or transmitted signals in each element of the array. Therefore, the phase shifter module, which controls the signal phase, is one of the key modules of a phased array system. To achieve high-precision beam scanning, the phase shifter should have an omnidirectional 360° phase shift range, high phase shift accuracy, and low phase shift-related amplitude fluctuations. Compared to active phase shifters, passive phase shifters have zero DC power consumption, which helps reduce the overall power consumption of large-scale arrays. Furthermore, passive phase shifters support bidirectional operation and can be reused in transceiver channels, enabling compact RF transceiver front-end chips and saving production costs.

[0004] To reduce the design complexity of phase shifters, a 180° phase shift can be easily achieved by switching the polarity of an active amplifier, which reduces the phase shift range of passive phase shifters from 360° to 180°. Traditional passive phase shifters mainly adopt path gating or delay switching structures, which have the following problems: (1) Phase shifting units usually only have two fixed states, a phase shifting state and a reference state, and there is no method to calibrate the phase error. After the chip fabrication is completed, the phase shift degree of each unit cannot be adjusted; (2) Large phase shifting units, such as 45° phase shifting units and 90° phase shifting units, are prone to introducing large amplitude and phase errors. The above problems make it difficult for traditional passive phase shifters based on path gating or delay switching structures to achieve high precision. Summary of the Invention

[0005] The purpose of this invention is to provide a passive phase shifter based on an all-pass network and a low-pass network. This passive phase shifter can be implemented using CMOS technology and has the advantages of high linearity, zero DC power consumption, and bidirectional operation. It can achieve a phase shift range of 0 to 180° with direct digital control and a phase shift step of 5.625°, and has high phase shift accuracy.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0007] The present invention includes a 90° phase shifting unit composed of a magnetically coupled all-pass network, an inter-unit matching network composed of on-chip inductors, a 45° phase shifting unit composed of a magnetically coupled all-pass network, a phase fine-tuning unit composed of a low-pass network, and an amplitude calibration unit composed of a digital step attenuator.

[0008] The RF input differential signals IP and IN are phase-shifted by 0° or 90° using a 90° phase-shifting unit to generate the first set of differential signals V. IP1 and V IN1 The first group of differential signals V IP1 and V IN1 After passing through the inter-unit matching network, a second set of differential signals V is generated. IP2 and V IN2 The second group of differential signals V IP2 and V IN2 After undergoing 0° or 45° phase shifting by a 45° phase shifting unit, a third set of differential signals V is generated. IP3 and V IN3 The third group of differential signals V IP3 and V IN3 After phase shifting by 0°, 5.625°, 11.25°, 16.875°, 22.5°, 28.125°, 33.75°, or 39.375° by the phase fine-tuning unit, a fourth set of differential signals V is generated. IP4 and V IN4 The fourth group of differential signals V IP4 and V IN4 The amplitude calibration unit reduces amplitude fluctuations caused by phase switching during phase shifting and generates RF output differential signals OP and ON.

[0009] The beneficial effects of this invention are:

[0010] This invention employs an all-pass network structure to implement 45° and 90° phase shifting units, and a low-pass network structure to implement phase fine-tuning units. After chip fabrication, the phase shift degree can be calibrated and optimized by adjusting the control word of the on-chip variable capacitor, thereby improving the phase shift accuracy.

[0011] This invention uses a purely passive structure to achieve the phase shifting function, which has the advantages of high linearity and zero DC power consumption, thus greatly reducing the power consumption of phased array systems, especially large-scale phased array systems.

[0012] The phase shifter of this invention supports bidirectional operation, and the input and output can be interchanged while maintaining consistent phase shift performance. Therefore, it can be reused at the common terminal of the receiving channel and the transmitting channel, realizing a compact RF transceiver front-end chip and reducing production costs. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a structural block diagram of a passive phase shifter based on an all-pass network and a low-pass network according to the present invention;

[0015] Figure 2 This is a schematic diagram of the circuit structure of a passive phase shifter based on an all-pass network and a low-pass network according to the present invention;

[0016] Figure 3 This is a structural block diagram of an amplitude calibration unit according to the present invention;

[0017] Figure 4 This is a schematic diagram of an on-chip variable capacitor circuit structure according to the present invention;

[0018] Figure 5 The simulation results of phase shifting and phase shifting error are for a passive phase shifter based on an all-pass network and a low-pass network according to the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the present invention clearer, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Examples of these preferred embodiments are illustrated in the drawings. The embodiments of the present invention shown in and described with reference to the drawings are merely exemplary, and the present invention is not limited to these embodiments.

[0020] It should also be noted that, in order to avoid obscuring the invention with unnecessary details, only the structures and / or processing steps closely related to the solution according to the invention are shown in the accompanying drawings, while other details that are not closely related to the invention are omitted.

[0021] Furthermore, in the description of this invention, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used solely for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0022] Please see Figures 1 to 5 Examples of the present invention include:

[0023] like Figure 1 As shown, the passive phase shifter based on an all-pass network and a low-pass network provided by the present invention includes a 90° phase shifting unit composed of a magnetically coupled all-pass network, an inter-unit matching network composed of on-chip inductors, a 45° phase shifting unit composed of a magnetically coupled all-pass network, a phase fine-tuning unit composed of a low-pass network, and an amplitude calibration unit composed of a digital step attenuator, connected in sequence.

[0024] The 90° phase shifting unit adjusts the on-chip variable capacitor C. 11 C 12 C 13 The capacitance value allows for a 0° or 90° phase shift of the RF input differential signals IP and IN, generating the first set of differential signals V. IP1 and V IN1 .

[0025] The inter-unit matching network described above can optimize the impedance matching between the 45° phase-shifting unit and the 90° phase-shifting unit, and enable the first set of differential signals V IP1 and V IN1 After the on-chip inductor L 21 L 22 Generate a second set of differential signals V IP2 and V IN2 .

[0026] The 45° phase shifting unit is achieved by adjusting the on-chip variable capacitor C. 31 C 32 C 33 The capacitance value can make the second set of differential signals V IP2 and V IN2 Perform a 0° or 45° phase shift to generate a third set of differential signals V. IP3 and V IN3 .

[0027] The phase fine-tuning unit adjusts the on-chip variable capacitor C. 41 C 41 C 43 C 44 The capacitance value can make the third differential signal V IP3 and V IN3 Phase shifts of 0°, 5.625°, 11.25°, 16.875°, 22.5°, 28.125°, 33.75°, and 39.375° are performed to generate the fourth set of differential signals V. IP4 and V IN4 .

[0028] The amplitude calibration unit described above can enable the fourth group of differential signals V IP4 and V IN4The attenuation adjustment range is 0 to 3.75 dB, with an attenuation adjustment step of 0.25 dB, which reduces the amplitude fluctuation caused by phase switching during phase shift and generates RF output differential signals OP and ON.

[0029] like Figure 2 As shown, the 90° phase shift unit in this embodiment achieves a 90° phase shift of the RF input signals IP and IN; the 90° phase shift unit consists of an on-chip inductor L. 11 L 12 L 13 L 14 On-chip variable capacitor C 11 C 12 C 13 Composition; the on-chip inductor L 11 One end is connected to the on-chip variable capacitor C 11 One end is connected to the positive terminal IP of the RF input port, and the other end is connected to the on-chip inductor L. 12 One end and the on-chip variable capacitor C 13 One end is connected; the on-chip inductor L 12 One end is connected to the on-chip variable capacitor C 11 One end is connected to the positive terminal V of the first group of differential signals. IP1 The other end is connected to the on-chip inductor L. 11 One end and the on-chip variable capacitor C 13 One end is connected; the on-chip variable capacitor C 11 One end is connected to the on-chip inductor L 11 One end is connected to the positive terminal IP of the RF input port, and the other end is connected to the on-chip inductor L. 12 One end is connected to the positive terminal V of the first group of differential signals. IP1 The on-chip variable capacitor C 13 One end is connected to the on-chip inductor L 11 One end and the on-chip inductor L 12 One end is connected to the on-chip inductor L, and the other end is connected to the on-chip inductor L. 13 One end and the on-chip inductor L 14 One end is connected; the on-chip inductor L 13 One end is connected to the on-chip variable capacitor C 12 One end is connected to the negative terminal IN of the RF input port, and the other end is connected to the on-chip inductor L. 14 One end and the on-chip variable capacitor C 13 One end is connected; the on-chip inductor L 14 One end is connected to the on-chip variable capacitor C 12 One end is connected to the negative terminal V of the first group of differential signals. IN1 The other end is connected to the on-chip inductor L. 13 One end and the on-chip variable capacitor C13 One end is connected; the on-chip variable capacitor C 12 One end is connected to the on-chip inductor L 13 One end is connected to the negative terminal IP of the RF input port, and the other end is connected to the on-chip inductor L. 14 One end is connected to the negative terminal V of the first group of differential signals. IN1 The on-chip inductor L mentioned above 11 The end connected to the positive terminal IP of the RF input port and the on-chip inductor L 12 With on-chip variable capacitor C 13 The connected end is the same name terminal, and the coupling coefficient is k; the on-chip inductor L 13 The end connected to the negative terminal IN of the RF input port and the on-chip inductor L 14 With on-chip inductor L 13 The connected ends are of the same name, and the coupling coefficient is k.

[0030] Furthermore, the on-chip inductor L of the 90° phase-shifting unit 11 L 13 The on-chip inductors have the same inductance value, and the on-chip inductor L... 12 L 14 The on-chip inductors have the same inductance value, and the on-chip variable capacitor C... 11 C 12 The capacitor values ​​used are the same.

[0031] like Figure 2 As shown, the inter-cell matching network in this embodiment consists of an on-chip inductor L 21 L 22 Composition, on-chip inductor L 21 One end is connected to the positive terminal V of the first group of differential signals. IP1 One end is connected to the other end, and the other end is connected to the positive terminal V of the second set of differential signals. IP2 Connected; On-chip inductor L 22 One end is connected to the positive terminal V of the first group of differential signals. IIN1 One end is connected to the other end, and the other end is connected to the negative terminal V of the second set of differential signals. IN2 Phase connection. The inter-unit matching network can optimize the impedance matching between the 45° phase-shifting unit and the 90° phase-shifting unit, and generate a second set of differential signals V. IP2 and V IN2 .

[0032] Furthermore, the on-chip inductor L 21 L 22 The inductance values ​​of the on-chip inductors are the same.

[0033] like Figure 2 As shown, the 45° phase shifting unit in this embodiment has the same structure as the 90° phase shifting unit, realizing the processing of the second set of differential signals V. IP2 VIN2 A 45° phase shift.

[0034] like Figure 2 As shown, the phase fine-tuning unit in this embodiment is composed of an on-chip inductor L 41 L 42 L 43 L 44 L 45 L 46 On-chip variable capacitor C 41 C 42 C 43 C 44 composition.

[0035] On-chip variable capacitor C 41 One end is connected to the on-chip inductor L 41 One end is connected to the positive terminal V of the third group of differential signals. IP3 The other end is connected to the on-chip inductor L. 42 One end is connected to the negative terminal V of the third group of differential signals. IN3 On-chip inductor L 41 One end is connected to the on-chip variable capacitor C 41 One end is connected to the positive terminal V of the third group of differential signals. IP3 The other end is connected to the on-chip inductor L. 43 One end and the on-chip variable capacitor C 42 One end is connected; on-chip inductor L 42 One end is connected to the on-chip variable capacitor C 41 Connect to the negative terminal V of the third group of differential signals. IN3 The other end is connected to the on-chip inductor L. 44 One end and the on-chip variable capacitor C 42 Phase connection; on-chip variable capacitor C 42 One end is connected to the on-chip inductor L 41 One end and the on-chip inductor L 43 One end is connected to the on-chip inductor L, and the other end is connected to the on-chip inductor L. 42 One end and the on-chip inductor L 44 One end is connected; on-chip inductor L 43 One end is connected to the on-chip inductor L 41 One end and the on-chip variable capacitor C 42 One end is connected to the on-chip inductor L, and the other end is connected to the on-chip inductor L. 45 One end and the on-chip variable capacitor C 43 One end is connected; on-chip inductor L 44 One end is connected to the on-chip inductor L 42 One end and the on-chip variable capacitor C 42 One end is connected to the on-chip inductor L, and the other end is connected to the on-chip inductor L. 46 One end and the on-chip variable capacitor C43 One end is connected; on-chip variable capacitor C 43 One end is connected to the on-chip inductor L 43 One end and the on-chip inductor L 45 One end is connected to the on-chip inductor L, and the other end is connected to the on-chip inductor L. 44 One end and the on-chip inductor L 46 One end is connected; on-chip inductor L 45 One end is connected to the on-chip inductor L 43 One end and the on-chip variable capacitor C 43 One end is connected to the on-chip variable capacitor C, and the other end is connected to the on-chip variable capacitor C. 44 One end is connected to the positive terminal V of the fourth group of differential signals. IP4 On-chip inductor L 46 One end is connected to the on-chip inductor L 44 One end and the on-chip variable capacitor C 43 One end is connected to the on-chip variable capacitor C, and the other end is connected to the on-chip variable capacitor C. 44 One end is connected to the negative terminal V of the fourth group of differential signals. IN4 On-chip variable capacitor C 44 One end is connected to the on-chip inductor L 45 One end is connected to the positive terminal V of the fourth group of differential signals. IP4 The other end is connected to the on-chip inductor L. 46 One end is connected to the negative terminal V of the fourth group of differential signals. IN4 .

[0036] It should be noted that the on-chip inductor L... 41 L 42 L 43 L 44 L 45 L 46 The on-chip inductors have the same inductance value; the on-chip variable capacitor C 41 C 42 C 43 C 44 The selected capacitor values ​​are the same; this is achieved by controlling the on-chip variable capacitor C. 41 C 42 C 43 C 44 The capacitance value can achieve phase shifting of different phases of the signal, and can meet the phase shift step requirement of 5.625°.

[0037] like Figure 3As shown, the amplitude calibration unit in this embodiment consists of a 2dB attenuation unit, a 1dB attenuation unit, a 0.5dB attenuation unit, and a 0.25dB attenuation unit. The attenuation adjustment range is 0 to 3.75dB, and the attenuation adjustment step is 0.25dB. The amplitude calibration unit can reduce the amplitude fluctuation caused by phase switching during phase shift.

[0038] like Figure 4 As shown, the on-chip variable capacitor C is given. 11 C 12 C 13 C 31 C 32 C 33 C 41 C 42 C 43 C 44 Specific embodiments are described below. The on-chip variable capacitor is a capacitor array composed of several parallel switched capacitors. Different digital signals can control the switching of each capacitor, resulting in a total capacitance with a variable value. Any switched capacitor structure in the switched capacitor array includes a capacitor C with a constant capacitance value. 51 and capacitor C 52 The circuit consists of a switching transistor M1, an inverter I1, and bias resistors R1, R2, and R3; the drain of transistor M1 is connected to a capacitor C. 51 The source is connected to capacitor C. 52 The digital signal is connected to the bias resistor R2 after passing through the inverter I1, and then to the gate of transistor M1. The digital signal is then connected to the drain, gate, and source of transistor M1 via bias resistors R1, R2, and R3, respectively. When the digital signal is high, the gate of transistor M1 is low, and the source and drain are high, at which point transistor M1 is off, and the switched capacitor is closed. When the digital signal is low, the gate of transistor M1 is high, and the source and drain are low, at which point transistor M1 is on, and the switched capacitor is open.

[0039] Figure 5 The simulation results and error results of the phase shifter of this invention are shown. This phase shifter can achieve a phase shift range of 0–180° and a phase shift step of 5.625°. It also has the ability to optimize performance based on the operating frequency. Simulation results show that by adjusting the control word of the on-chip variable capacitor, the phase shifter achieves high phase accuracy in three adjacent frequency ranges (including 18–19 GHz, 19–20 GHz, and 20–21 GHz), with no overlap between phase states and a root mean square (RMS) phase error of less than 2.6°.

[0040] Furthermore, it should be noted that in this specification, "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0041] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A passive phase shifter based on an all-pass network and a low-pass network, characterized in that: It includes a 90° phase-shifting unit composed of a magnetically coupled full-pass network, an inter-unit matching network composed of on-chip inductors, a 45° phase-shifting unit composed of a magnetically coupled full-pass network, a phase fine-tuning unit composed of a low-pass network, and an amplitude calibration unit composed of a digital step attenuator. The RF input differential signals IP and IN are phase-shifted by 0° or 90° using a 90° phase-shifting unit to generate the first set of differential signals V. IP1 and V IN1 The first group of differential signals V IP1 and V IN1 After passing through the inter-unit matching network, a second set of differential signals V is generated. IP2 and V IN2 The second group of differential signals V IP2 and V IN2 After undergoing 0° or 45° phase shifting by a 45° phase shifting unit, a third set of differential signals V is generated. IP3 and V IN3 The third group of differential signals V IP3 and V IN3 After phase shifting by 0°, 5.625°, 11.25°, 16.875°, 22.5°, 28.125°, 33.75°, or 39.375° by the phase fine-tuning unit, a fourth set of differential signals V is generated. IP4 and V IN4 The fourth group of differential signals V IP4 and V IN4 After passing through the amplitude calibration unit, the amplitude fluctuation caused by phase switching during phase shift is reduced, and RF output differential signals OP and ON are generated; The 90° phase-shifting unit consists of an on-chip inductor L 11 L 12 L 13 L 14 On-chip variable capacitor C 11 C 12 C 13 composition; On-chip inductor L 11 One end is connected to the on-chip variable capacitor C 11 One end is connected to the positive terminal IP of the RF input port, and the other end is connected to the on-chip inductor L. 12 One end and the on-chip variable capacitor C 13 One end is connected; on-chip inductor L 12 The other end is connected to the on-chip variable capacitor C 11 The other end is connected as the positive terminal V of the first set of differential signals. IP1 ; On-chip variable capacitor C 13 The other end is connected to the on-chip inductor L 13 One end and the on-chip inductor L 14 One end is connected; on-chip inductor L 13 The other end is connected to the on-chip variable capacitor C 12 One end is connected to the negative terminal IN of the RF input port; on-chip inductor L 14 The other end is connected to the on-chip variable capacitor C 12 The other end is connected as the negative terminal V of the first set of differential signals. IN1 ; The 45° phase shifting unit has the same structure as the 90° phase shifting unit, and its input is the positive terminal V of the second set of differential signals. IP2 The negative terminal V of the second group of differential signals IN2 The output is the positive terminal V of the third group of differential signals. IP3 The negative terminal V of the third group of differential signals IN3 .

2. A passive phase shifter based on an all-pass network and a low-pass network according to claim 1, characterized in that: The on-chip inductor L of the 90° phase shift unit 11 L 13 The on-chip inductors have the same inductance value, and the on-chip inductor L... 12 L 14 The on-chip inductors have the same inductance value, and the on-chip variable capacitor C... 11 C 12 The capacitor values ​​used are the same.

3. A passive phase shifter based on an all-pass network and a low-pass network according to claim 1, characterized in that: The inter-cell matching network consists of an on-chip inductor L 21 L 22 Composition; On-chip inductor L 21 One end is connected to the positive terminal V of the first group of differential signals. IP1 Connect one end to the other, which serves as the positive terminal V of the second set of differential signals. IP2 On-chip inductor L 22 One end is connected to the negative end V of the first group of differential signals. IN1 Connect one end to the other, which serves as the negative terminal V of the second set of differential signals. IN2 .

4. A passive phase shifter based on an all-pass network and a low-pass network according to claim 3, characterized in that: The on-chip inductor L 21 L 22 The inductance values ​​of the on-chip inductors are the same.

5. A passive phase shifter based on an all-pass network and a low-pass network according to claim 1, characterized in that: The input to the phase fine-tuning unit is the positive terminal V of the third group of differential signals. IP3 The negative terminal V of the third group of differential signals IN3 The output is the positive terminal V of the fourth group of differential signals. IP4 The negative terminal V of the fourth group of differential signals IN4 The phase fine-tuning unit consists of an on-chip inductor L. 41 L 42 L 43 L 44 L 45 L 46 On-chip variable capacitor C 41 C 42 C 43 C 44 Composition; On-chip inductor L 41 L 43 L 45 Connected in series, on-chip inductor L 42 L 44 L 46 Connected in series, with the on-chip variable capacitor C 41 One end is connected to the positive terminal V of the third group of differential signals. IP3 The other end is connected to the negative terminal V of the third set of differential signals. IN3 On-chip variable capacitor C 42 One end is connected to the on-chip inductor L 41 and on-chip inductor L 43 Between them, the other end is connected to the on-chip inductor L. 42 and on-chip inductor L 44 Between; On-chip variable capacitor C 43 One end is connected to the on-chip inductor L 43 and on-chip inductor L 45 Between them, the other end is connected to the on-chip inductor L. 44 and on-chip inductor L 46 Between; On-chip variable capacitor C 44 One end is connected to the positive terminal V of the fourth group of differential signals. IP4 The other end is connected to the negative terminal V of the fourth group of differential signals. IN4 .

6. A passive phase shifter based on an all-pass network and a low-pass network according to claim 5, characterized in that: The on-chip inductor L 41 L 42 L 43 L 44 L 45 L 46 The on-chip inductor has the same inductance value; the on-chip variable capacitor C 41 C 42 C 43 C 44 The capacitor values ​​used are the same.

7. A passive phase shifter based on an all-pass network and a low-pass network according to claim 1, characterized in that: The amplitude calibration unit consists of four attenuation modules: a 2 dB attenuation unit, a 1 dB attenuation unit, a 0.5 dB attenuation unit, and a 0.25 dB attenuation unit. These four attenuation modules are connected in sequence, with an attenuation adjustment range of 0 to 3.75 dB and an attenuation adjustment step of 0.25 dB.

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