Semiconductor optical amplifier and method of manufacturing the same

Abstract

The application relates to the technical field of communication, and provides a semiconductor optical amplifier and a manufacturing method thereof. The semiconductor optical amplifier comprises a substrate and a mesa structure etched from an epitaxial structure grown on the substrate; the mesa structure is divided into at least one light-free region and at least one light-emitting region; a current conduction structure is grown above the mesa of the light-emitting region and is used for conducting current to the mesa structure; and a first current blocking structure is grown above the light-free region and is used for blocking the current in the upper layer from reaching the mesa structure. The application increases the maximum power threshold of the output, thereby prolonging the service life. The light-free region does not emit light, thereby reducing the overall heat generation of the chip, increasing the heat conduction path, improving the heat conduction effect, and further improving the reliability of the chip.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a semiconductor optical amplifier and its manufacturing method. Background Technology

[0002] Semiconductor optical amplifiers (SOAs) are characterized by multiple functions, small size, low power consumption, and easy monolithic integration with other semiconductor devices. They play a unique and important role in optical signal amplification, optical signal processing, and optical switching applications, and are one of the key components of fiber optic communication networks.

[0003] As is well known, reliability is a crucial indicator of semiconductor chip quality. Reliability refers to the probability that a product will perform its intended function under specified conditions and within a specified time. With the development of science and technology, semiconductor chips have been widely applied in cutting-edge fields of defense and science and technology. Therefore, the requirements for the stability and reliability of semiconductor chips are becoming increasingly stringent. In actual production and R&D processes, life testing is typically used to evaluate the reliability level of chips, and quality feedback is used to improve the reliability level to ensure chip quality. A lower failure rate during life testing demonstrates stronger chip reliability. Therefore, reducing the failure rate during life testing has become a key research area. This can usually be achieved through chip design or manufacturing. To achieve this, it is necessary to consider the main aspects of chip production, taking corresponding measures from raw materials, chip design, equipment, process optimization design, and the environment. However, chip design plays a crucial and overarching role.

[0004] In existing technologies, when a chip emits light, its internal temperature rises. When the internal temperature of the chip and its surrounding environment are too high, the chip's failure rate increases significantly, thereby reducing the chip's reliability and lifespan.

[0005] Furthermore, in existing technologies, SOA (Self-Oriented Aperture Assemblies) often employ buried heterojunction structures. Because the active layer thickness (~0.15 μm) is smaller than its width (~2 μm), its far-field vertical divergence angle perpendicular to the junction plane is typically larger than its horizontal divergence angle, resulting in an elliptical light spot. However, the mode field of single-mode fiber conforms to a Bessel function distribution, exhibiting a circularly symmetrical light spot. This severe mode field mismatch leads to low coupling efficiency, which directly affects the desired high gain and low noise figure of the optical signal. Therefore, mode field matching between the single-mode fiber and the SOA is crucial for effectively coupling the input and output light into a circularly symmetrical single-mode fiber with a core diameter of only 8–9 μm.

[0006] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0007] The technical problem to be solved by this invention is that the high internal temperature of the chip in the prior art affects the reliability and service life of the chip.

[0008] The present invention adopts the following technical solution:

[0009] In a first aspect, the present invention provides a semiconductor optical amplifier, including a substrate 1 and a mesa structure 21 formed by etching an epitaxial structure 2 grown on the substrate 1;

[0010] The tabletop structure 21 is divided into at least one dark area 210 and at least one light-emitting area 211;

[0011] A current-conducting structure 3 is grown above the mesa of the light-emitting area 211 to conduct current to the mesa structure 21.

[0012] A first current blocking structure 4 is grown above the light-free area 210 to block the current from the upper layer from reaching the platform structure 21.

[0013] Preferably, the first current blocking structure 4 includes a first semiconductor layer 41 and a second semiconductor layer 42 grown on the first semiconductor layer 41; wherein the first semiconductor layer 41 is a P-type material and the second semiconductor layer 42 is an N-type material.

[0014] Preferably, the current-conducting structure 3 includes one or more semiconductor layers, and the one or more semiconductor layers have the same doping type.

[0015] Preferably, the portion of the platform structure 21 near both ends of the optical amplifier is divided into a light-free region 210, and the portion of the platform structure 21 near the center of the optical amplifier is divided into a light-emitting region 211.

[0016] Preferably, based on the distance from both ends of the optical amplifier, the portion of the platform structure 21 near both ends of the optical amplifier is divided into a first region 212, and the portion of the platform structure 21 near the middle of the optical amplifier is divided into a second region 213.

[0017] The difference between the tabletop width of the tabletop structure 21 in the first region 212 and the tabletop width in the second region 213 is greater than a first preset difference.

[0018] Furthermore, at the connection point between the first region 212 and the second region 213, the width of the tabletop structure 21 increases or decreases sequentially to achieve a smooth connection between the first region 212 and the second region 213 of the tabletop structure 21.

[0019] A second current blocking structure 5 is also grown on both sides of the light-emitting area 211 to block the current from the upper layer from reaching both sides of the mesa structure 21. The second current blocking structure 5 is obtained by etching away the part of the first current blocking structure 4 located above the mesa of the light-emitting area 211 after growing the first current blocking structure 4 above the light-emitting area 211.

[0020] Preferably, the epitaxial structure 2 includes at least one of a buffer layer 22, a lower cladding layer 23, an active layer 24, and a first upper cladding layer 25.

[0021] Secondly, the present invention also provides a method for fabricating a semiconductor optical amplifier, comprising growing an epitaxial structure 2 on a substrate 1, including:

[0022] A protective film 6 with a preset pattern is grown on the epitaxial structure 2, and the surface of the epitaxial structure 2 on which the protective film 6 is grown is etched to obtain a mesa structure 21 covered with the protective film 6.

[0023] The protective film 6 in the dark region 210 is etched away, and multiple semiconductor layers are grown on the surface of the mesa structure 21. After growing the corresponding semiconductor layers, the protective film 6 in the light-emitting region 211 is etched away, and subsequent semiconductor layers are grown to obtain the current-conducting structure 3 in the dark region 210 and the first current-blocking structure 4 in the light-emitting region 211.

[0024] Preferably, the step of growing multiple semiconductor layers on the surface of the mesa structure 21, and etching away the protective film 6 in the light-emitting region 211 after growing the corresponding semiconductor layers, to perform subsequent semiconductor layer growth, specifically includes:

[0025] A first semiconductor layer 41 and a second semiconductor layer 42 are grown on the surface of the mesa structure 21. After growing the second semiconductor layer 42, the protective film 6 in the light-emitting region 211 is etched away, and a third semiconductor layer 43 is grown to obtain the first current blocking structure 4 in the dark region 210 and the current conducting structure 3 in the light-emitting region 211.

[0026] Preferably, the second difference between the table width of the preset graphic in the first region 212 and the table width in the second region 213 is greater than the preset difference;

[0027] Furthermore, at the connection point between the first region 212 and the second region 213, the width of the platform of the preset graphic increases or decreases sequentially.

[0028] This invention establishes a non-light-emitting region and a light-emitting region. The non-light-emitting region incorporates a current-blocking structure, preventing it from emitting light and allowing it to function solely as a transmission channel for the optical waveguide. When light passes through this region, its optical mode field expands, the cavity surface power density decreases, the critical power for optical catastrophe increases, and the maximum power threshold that the device can output increases, thereby extending its operational lifespan. Furthermore, by partially preventing light emission, the overall heat generation of the chip is reduced, increasing heat transfer pathways and improving heat transfer efficiency, thus further enhancing the chip's reliability. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a partial perspective view of a semiconductor optical amplifier provided in an embodiment of the present invention;

[0031] Figure 2 This is a side view schematic diagram of an epitaxial structure in a semiconductor optical amplifier provided in an embodiment of the present invention;

[0032] Figure 3 This is a cross-sectional schematic diagram of the light-free region in a semiconductor optical amplifier provided by an embodiment of the present invention;

[0033] Figure 4 This is a cross-sectional schematic diagram of the light-emitting region in a semiconductor optical amplifier provided by an embodiment of the present invention;

[0034] Figure 5 This is a cross-sectional schematic diagram of the light-emitting region in another semiconductor optical amplifier provided by an embodiment of the present invention;

[0035] Figure 6 This is a cross-sectional schematic diagram of the light-free region in another semiconductor optical amplifier provided by an embodiment of the present invention;

[0036] Figure 7 This is a top view schematic diagram of a mesa structure in a semiconductor optical amplifier provided in an embodiment of the present invention;

[0037] Figure 8 This is a top view schematic diagram of a mesa structure in another semiconductor optical amplifier provided in an embodiment of the present invention;

[0038] Figure 9 This is a top view schematic diagram of a mesa structure in another semiconductor optical amplifier provided in an embodiment of the present invention;

[0039] Figure 10 This is a schematic diagram of a method for fabricating a semiconductor optical amplifier according to an embodiment of the present invention;

[0040] Figure 11 This is a schematic diagram of the structure in a method for fabricating a semiconductor optical amplifier provided in an embodiment of the present invention;

[0041] Figure 12 This is a schematic diagram of the structure in another method for manufacturing a semiconductor optical amplifier provided in an embodiment of the present invention;

[0042] Figure 13 This is a cross-sectional schematic diagram of the light-free region in another semiconductor optical amplifier provided in an embodiment of the present invention;

[0043] Figure 14 This is a cross-sectional schematic diagram of the light-emitting region in another semiconductor optical amplifier provided in an embodiment of the present invention;

[0044] Figure 15 This is a partial perspective view of another semiconductor optical amplifier provided in an embodiment of the present invention.

[0045] In all the accompanying drawings, the same reference numerals are used to denote the same elements or structures, wherein:

[0046] 1. Substrate; 2. Epitaxial structure; 21. Mesa structure; 210. Dark region; 211. Light-emitting region; 212. First region; 213. Second region; 22. Buffer layer; 23. Lower cladding layer; 24. Active layer; 25. First upper cladding layer; 3. Current-conducting structure; 4. First current-blocking structure; 41. First semiconductor layer; 42. Second semiconductor layer; 43. Third semiconductor layer; 5. Second current-blocking structure; 6. Protective film. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0048] In the description of this invention, the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and do not require that this invention must be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0049] In this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0050] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0051] Example 1:

[0052] In existing technologies, high internal temperatures within chips affect their reliability and lifespan. To address this issue, Embodiment 1 of this invention provides a semiconductor optical amplifier, such as... Figure 1 and Figure 2 As shown, it includes a substrate 1 and a mesa structure 21 formed by etching an epitaxial structure 2 grown on the substrate 1; the mesa structure 21 forms the waveguide of the semiconductor optical amplifier.

[0053] The platform structure 21 is divided into at least one dark region 210 and at least one light-emitting region 211. A current-conducting structure 3 is grown above the platform of the light-emitting region 211 to conduct current to the platform structure 21. A first current-blocking structure 4 is grown above the dark region 210 to block current from reaching the platform structure 21. Structurally, the platform structure 21 can be divided into a platform and side surfaces. The current-conducting structure 4 is grown above the platform, and the first current-blocking structure 4 is grown above the platform and side surfaces, covering the dark region 210.

[0054] It should be noted here that... Figure 2 The extended structure 2 shown can be understood as a structural schematic diagram during the fabrication of the platform structure 21. Figure 2 The structure shown is formed after the corresponding etching operation. Figure 1 The mesa structure 21 shown, after etching, is identical to the epitaxial structure 2. In subsequent embodiment 2, the epitaxial structure 2 is also used as an alternative representation of the mesa structure 21. Figure 2 As shown, the epitaxial structure 2 includes at least one of a buffer layer 22, a lower cladding layer 23, an active layer 24, and a first upper cladding layer 25.

[0055] Figure 1 This can be understood as a schematic diagram obtained by viewing a portion of the structure of a semiconductor optical amplifier, in which the mesa structure 21 is visible in all cross-sections of the semiconductor optical amplifier. Figure 1Only two cross-sections of the dark region 210 and one cross-section of the light-emitting region 211 are selected to represent the mesa structure 21. A schematic diagram of the cross-section of the semiconductor optical amplifier corresponding to the dark region 210 is shown below. Figure 3 As shown, a schematic cross-sectional view of the semiconductor optical amplifier corresponding to the light-emitting region 211 is shown below. Figure 4 As shown.

[0056] The current-conducting structure 3 grown above the light-emitting region 211 can be grown directly above the mesa structure 21, or it can be grown after other semiconductor layers are grown on the mesa structure 21. In a preferred embodiment, such as... Figure 5 As shown, second current-blocking structures 5 are also grown on both sides of the light-emitting region 211 to block the current from the upper layer from reaching the sides of the mesa structure 21. This ensures that the current is transmitted downwards from directly above the mesa structure 21, rather than from the sides. The second current-blocking structure 5 is obtained by growing a first current-blocking structure 4 above the light-emitting region 211 and then etching away the portion of the first current-blocking structure 4 located above the mesa of the light-emitting region 211.

[0057] In practical applications, the substrate 1 is made of InP, and the epitaxial structure 2 sequentially comprises: an InP buffer layer 22 of N-type material, an InP lower cladding layer 23 of N-type material, an active layer 24 of InGaAsP material, and a first upper cladding layer 25 of P-type material. The active layer 24 can be a buried heterojunction structure or a ridge waveguide structure. The buried heterojunction structure can be a planar active layer 24 buried heterojunction structure, such as an etched mesa buried structure, a double-groove planar buried structure, or a strip-shaped buried heterojunction, or a non-planar active layer 24 buried heterojunction structure, such as a V-groove substrate 1 or channel substrate 1 buried structure, a mesa substrate 1 buried heterojunction structure, or a buried crescent structure. The epitaxial structure 2 can be obtained through one or more MOCVD (metal organic chemical vapor deposition) techniques.

[0058] This embodiment sets up a light-free region 210 and a light-emitting region 211. The light-free region 210 is equipped with a first current-blocking structure 4, so that this region does not emit light and only serves as a transmission channel for the optical waveguide. When light passes through this region, its optical mode field expands, the cavity surface power density decreases, the critical power for optical catastrophe increases, and the maximum power threshold that the device can output increases, thereby increasing the operating life. Furthermore, the fact that some areas do not emit light also reduces the overall heat generation of the chip, increases the heat transfer path, improves the heat transfer effect, and further improves the reliability of the chip.

[0059] In practical applications, the probability of optical catastrophes occurring near the ends of the optical amplifier is higher, while the probability of optical catastrophes occurring near the center of the optical amplifier is lower. Therefore, in the preferred embodiment, such as... Figure 1 As shown, the portion of the mesa structure 21 near both ends of the optical amplifier is divided into a light-free region 210, and the portion of the mesa structure 21 near the center of the optical amplifier is divided into a light-emitting region 211. This reduces heat generation at both ends of the amplifier, thereby further reducing the possibility of optical catastrophic events. In an optional embodiment, the length of the light-free region 210 can be 20–100 μm, and the length of the light-emitting region 211 can be 300–1300 μm.

[0060] The first current blocking structure 4 can be a plurality of alternatingly stacked first semiconductor layers 41 and a plurality of second semiconductor layers 42, wherein the first semiconductor layers 41 and the second semiconductor layers 42 have different doping types. Figure 6 As shown, another embodiment exists where the first current-blocking structure 4 includes a first semiconductor layer 41 and a second semiconductor layer 42 grown on the first semiconductor layer 41; wherein the first semiconductor layer 41 is a P-type material and the second semiconductor layer 42 is an N-type material. When current reaches the second semiconductor layer 42, since the second semiconductor layer 42 is an N-type material and the lower first semiconductor layer 41 is a P-type material, a PN junction is formed. Due to the unidirectional conductivity of the PN junction, current cannot be transmitted from the upper N-type material to the lower P-type material, thus blocking the current. Therefore, the light-free region 210 does not emit light.

[0061] The current-conducting structure 3 includes one or more semiconductor layers, all of which have the same doping type. Specifically, all semiconductor layers can be N-type or P-type materials, or the lower semiconductor layer can be N-type and the upper semiconductor layer can be P-type. This forms a unidirectional conductive PN junction, allowing current to flow from the upper P-type material to the lower N-type material, thus achieving current conduction. After growing the first current-blocking structure 4, the top region of the mesa structure 21 is etched away to form the second current-blocking structure 5 located on both sides of the light-emitting region 211. Then, the current-conducting structure 3 is grown, resulting in a complete semiconductor optical amplifier with the first current-blocking structure 4, the second current-blocking structure 5, and the current-conducting structure. In this implementation, the second current-blocking structure 5 includes a first semiconductor layer 41 and a second semiconductor layer 42 grown on the first semiconductor layer 41, such as... Figure 14 As shown.

[0062] In practical applications, current reaching the mesa structure 21 mainly refers to current reaching the active layer 24 within the mesa structure 21. In an optional embodiment, a first upper cladding layer 25 of P-type material is grown above the active layer 24. In this embodiment, the current conducting structure 3 includes one or more semiconductor layers of P-type material, and the first current blocking structure 4 may contain only one semiconductor layer of N-type material, which, together with the first upper cladding layer 25, serves to block current from reaching the active layer 24.

[0063] This embodiment also provides a preferred implementation method, such as... Figure 7 , Figure 8 or Figure 9 As shown, it includes: dividing the portion of the platform structure 21 near the two ends of the optical amplifier into a first region 212 based on the distance from both ends of the optical amplifier, and dividing the portion of the platform structure 21 near the middle of the optical amplifier into a second region 213.

[0064] The difference between the tabletop width in the first region 212 and the tabletop width in the second region 213 of the tabletop structure 21 is greater than a first preset difference; wherein, the first preset difference is obtained by those skilled in the art based on the gain and noise requirements of the optical amplifier.

[0065] Furthermore, at the connection point between the first region 212 and the second region 213, the width of the tabletop structure 21 increases or decreases sequentially to achieve a smooth connection between the first region 212 and the second region 213 of the tabletop structure 21.

[0066] In practical application scenarios, there are such Figure 7 , Figure 8 and Figure 9 The three implementations are shown. When using Figure 7 When the mesa structure 21 is shown, the waveguide width near both ends of the optical amplifier gradually increases. At this point, the light distribution can be well confined within the active layer 24, resulting in a larger light field distribution, a larger spot size, and a smaller far-field divergence angle. When using... Figure 8 When the platform structure 21 is shown, the waveguide width near both ends of the optical amplifier gradually decreases, and part of its optical field will penetrate into the outer cladding, thereby increasing the near-field output spot size of the SOA and decreasing the far-field divergence angle, making it close to the mode spot size in the optical fiber. By increasing the spot size, the far-field divergence angle is reduced, thereby improving the coupling efficiency between the SOA chip and the optical fiber, and giving the chip higher gain and lower noise figure.

[0067] It should be noted that the division of the light-emitting region 211 and the dark region 210 can be done in the same way as the division of the first region 212 and the second region 213. For example, the first region 212 can be regarded as the dark region 210 and the second region 213 can be regarded as the light-emitting region 211. Different division methods can also be used, and the present invention does not limit this.

[0068] When the first region 212 is used as the light-free region 210 and the second region 213 is used as the light-emitting region 211, combined with the various embodiments in this example, the semiconductor amplifier generated in a real-world scenario includes: a multilayer epitaxial structure 2 sequentially grown on a semiconductor InP substrate 1, comprising an N-type InP buffer layer 222, an N-type InP lower cladding layer 233, an InGaAsP active layer 244, and a P-type InP first upper cladding layer 25; the epitaxial structure 2 is etched to obtain... Figure 1 The mesa structure 21 shown has the following characteristics: the length of the first region 212 is 20–100 μm, and the length of the second region 213 is 300–1300 μm; the width of the mesa structure 21 in the first region 212 is 0.5–2 μm or 2–4 μm, and the width of the mesa structure 21 in the second region 213 is 1–3 μm; in the first region 212, a P-type P-InP first barrier layer, an N-type N-InP second barrier layer, a P-type P-InP second upper cladding layer, and a P-type highly doped P-InGaAs ohmic contact layer are sequentially grown on top of the mesa structure 21; in the second region 213, a P-type P-InP second upper cladding layer and a P-type highly doped P-InGaAs ohmic contact layer are sequentially grown on top of the mesa structure 21.

[0069] It should be noted that in this embodiment and in subsequent embodiments, in Figure 1 and Figure 15 In the diagram, each dashed line represents a corresponding structure from a perspective view. In other accompanying drawings, the dashed lines do not represent actual structures but are used to mark the division of corresponding areas, such as... Figure 7 , Figure 8 and Figure 9 In the diagram, dashed lines are used to represent the division of the first region 212 and the second region 213.

[0070] The terms "light-free area 210", "light-emitting area 211", "first area 212" and "second area 213" do not represent dividing the tabletop structure 21 into four areas. Rather, they refer to dividing the entire tabletop structure 21 into a light-free area 210 and a light-emitting area 211 according to one classification standard, and then dividing the entire tabletop structure 21 into a first area 212 and a second area 213 according to another classification standard. Both classifications refer to the entire tabletop structure.

[0071] Example 2:

[0072] This invention provides a method for fabricating a semiconductor optical amplifier, which can be used to fabricate the semiconductor optical amplifier described in Embodiment 1. It should be noted that this invention focuses on the method process output related to substantially differentiating features; other processes, such as electrode fabrication, are not within the scope of this invention and are conventional prior art, therefore they will not be described in detail later in this invention. The method for fabricating the semiconductor optical amplifier described in this embodiment includes growing an epitaxial structure 2 on a substrate 1, such as... Figure 10 As shown, it includes:

[0073] In step 201, a protective film 6 with a preset pattern is grown on the epitaxial structure 2 to obtain the following: Figure 11 The structure shown is obtained by etching the surface of the epitaxial structure 2 on which the protective film 6 is grown to obtain a mesa structure 21 covered with the protective film 6; thus, the structure is obtained as shown. Figure 12 The structure shown. The protective film 6 can be SiO2. X The membrane, wherein the value of X is obtained by those skilled in the art based on experience, and typically X is 2, and the protective membrane 6 is a SiO2 membrane.

[0074] In step 202, the protective film 6 in the dark region 210 is etched away, and multiple semiconductor layers are grown on the surface of the mesa structure 21. After growing the corresponding semiconductor layers, the protective film 6 in the light-emitting region 211 is etched away, and subsequent semiconductor layers are grown to obtain the current-conducting structure 3 in the dark region 210 and the first current-blocking structure 4 in the light-emitting region 211. When the protective film 6 in the light-emitting region 211 is etched away, the semiconductor layers already grown in the light-emitting region 211 are also etched away along with the protective film 6. At the same time, since the etched protective film 6 only covers the top area of ​​the mesa structure, and the two sides of the mesa structure 21 are not covered, a second current-blocking structure 5 is generated on both sides of the mesa structure 21. This causes the current to be transmitted downward from directly above the mesa structure 21, instead of downward from the two sides of the mesa structure 21.

[0075] The process of growing multiple semiconductor layers on the surface of the mesa structure 21, and etching away the protective film 6 in the light-emitting region 211 after growing the corresponding semiconductor layers, to grow subsequent semiconductor layers, specifically includes:

[0076] A first semiconductor layer 41 and a second semiconductor layer 42 are grown on the surface of the mesa structure 21. After growing the second semiconductor layer 42, the protective film 6 in the light-emitting region 211 is etched away, and a third semiconductor layer 43 is grown to obtain the first current-blocking structure 4 in the dark region 210 and the current-conducting structure 3 in the light-emitting region 211. The dark region 210 is as follows: Figure 13As shown, the light-emitting area 211 is as follows Figure 14 As shown.

[0077] The first semiconductor layer 41 is a P-type material, the second semiconductor layer 42 is an N-type material, the first semiconductor layer 41 and the second semiconductor layer 42 form the first current blocking structure 4, and the third semiconductor layer 43 is a P-type material, forming the current conducting structure 3.

[0078] In a preferred embodiment, the difference between the table width of the preset graphic in the first region 212 and the table width in the second region 213 is greater than a second preset difference;

[0079] Furthermore, at the connection point between the first region 212 and the second region 213, the mesa width of the preset pattern increases or decreases sequentially. The second preset difference is obtained by those skilled in the art based on the gain and noise requirements of the optical amplifier. By controlling the preset pattern, the mesa structure 21 obtained by etching is controlled, so that the difference between the mesa width in the first region 212 and the mesa width in the second region 213 is greater than the first preset difference, thereby reducing the divergence angle, improving the coupling efficiency between the SOA chip and the optical fiber, and giving the chip higher gain and lower noise figure.

[0080] Based on this structure, a SiO2 insulating layer was grown using PECVD (plasma-enhanced chemical vapor deposition), and current injection windows were opened on the ridges using photolithography and etching techniques. Then, SiO2 was deposited and grown on the chip surface. X or SiN X The dielectric film on the ridges is removed by photolithography and etching, and electrode windows are etched out. Then, the upper and lower metal electrodes are fabricated by evaporation and sputtering. The electrode materials are one or more of Ti, Pt, or Au. After chip disassembly, optical films are usually deposited on the front and rear light-emitting surfaces to reduce end-face reflection.

[0081] The following example uses a buried heterojunction SOA with an active layer of 24 to illustrate the specific fabrication method of this chip. Figure 2The present invention discloses an epitaxial structure 2 for an SOA (Self-Oriented Aspect-Oriented Architecture), comprising a multilayer epitaxial structure 2 sequentially grown on a semiconductor InP substrate 1, including an N-type InP buffer layer 22, an N-type InP lower cladding layer 23, an InGaAsP active layer 24, and a P-type InP first upper cladding layer 25. The specific fabrication process of this SOA epitaxial structure 2 involves sequentially growing the lower cladding layer 23, the active layer 24, and the first upper cladding layer 25 on the semiconductor substrate 1. The active layer 244 can be, but is not limited to, a buried heterojunction structure or a ridge waveguide structure, and the corresponding epitaxial structure 2 can be obtained through one or more MOCVD (Metal-Oxide-CVD) techniques.

[0082] exist Figure 2 On epitaxial structure 2, SiO2 with a thickness of approximately 2000 Å is grown by PECVD. X A film is formed, and then techniques such as photolithography and etching are used to fabricate films such as... Figure 11 The partially retained SiO shown X Membrane. Retains a portion of SiO₂. X A top view of the membrane SOA chip is shown below. Figure 7 , Figure 8 or Figure 9 As shown, based on the retained SiO X The chip is divided into a first region 212 and a second region 213 by different membrane widths. The length of the second region 213 is defined as L1, and the lengths of the first region 212 are defined as L2 and L3 respectively, depending on their proximity to the semiconductor amplifier. Figure 15 As shown, the length of L1 ranges from 300 to 1300 μm, while the lengths of L2 and L3 range from 20 to 100 μm.

[0083] As can be seen from the figure, the SiO2 retained in the second region 213 and the first region 212 X The widths of the films are different; the width of the oxide film in the second region 213 is either greater than or less than the width of the oxide film in the first region 212. When the width of the oxide film in the second region 213 is greater than the width of the oxide film in the first region 212, ... Figure 7 As shown, when the oxide film width of the second region 213 is smaller than the oxide film width of the first region 212, as... Figure 8 As shown, the first region 212 has SiO at different ends. X The membrane width can be the same or different, such as Figure 9 As shown, the oxide film width of the first region 212 at one end is greater than the oxide film width of the first region 212, and the oxide film width of the first region 212 at the other end is less than the oxide film width of the first region 212.

[0084] Regardless of whether it is the second region 213 or the first region 212, its SiO X The film widths all ranged from 2 to 5 μm. Then, ICP etching was performed to remove SiO₂.X The epitaxial layer outside the film-covered area was etched to a depth of approximately 0.5 μm. Subsequently, wet etching was performed using a Br2-containing etchant, achieving a total etching depth of approximately 1.0 μm. The side view of the etched chip is shown below. Figure 12 As shown, due to the SiO in the second region 213 and the first region 212 X Because the film width is different, the width of the active region after etching is also different, i.e., Figure 15 The sizes of W1, W2, and W3 shown are different, but they are all graded waveguides in the active region, meaning the width of the active layer 24 changes gradually from the second region 213 to the first region 212. It should be noted that the widths W1, W2, and W3 of the active layer 24 in the second region 213 and the first region 212 are not the same value and are also graded. The overall width of W1 is greater than or less than W2 and W3. W2 and W3 can be graded waveguides of the same width or graded waveguides of different widths; their width depends on the SiO2 content. X The width of the film and the etching and corrosion depth. The range of W1 is 1 to 3 μm, and the ranges of W2 and W3 are 0.5 to 2 μm or 2 to 4 μm.

[0085] The SiO2 covering the first region 212 was removed by photolithography and etching. X The membrane retains only the SiO2 in the second region 213. X The next step is to grow a P-type first barrier layer, specifically P-InP, using MOCVD. Then, an N-type second barrier layer, specifically N-InP, is grown. Finally, wet etching is used to remove the SiO2 in the second region 213. X The film can be removed using BOE (Buffered Oxide Etch). The N-type second barrier layer in region 213 is due to the previous SiO... X The presence of the film on the SiO in the second region 213 X The film was removed during etching and did not cover the active layer 24 above the mesa structure 21. The N-type second barrier layer in the first region 212 was removed due to the previous removal of SiO. X A film is formed, which constitutes a continuous N-type second barrier layer. A P-type second upper cladding layer, specifically P-InP, is then grown on this structure, followed by the growth of a P-type ohmic contact layer, specifically highly doped P-InGaAs. The entire epitaxial structure 2 is as follows: Figure 15 As shown. Figure 13As shown, the active layer 24 of the first region 212 has a PNP structure from top to bottom. When current is applied to the chip, the current flows from the second semiconductor layer 42 to the first semiconductor layer 41 from N to P, acting as a current barrier and preventing the current from reaching the active region. Therefore, the active layer 24 does not emit light. In contrast, the active layer 24 of the second region 213 has a P-type first upper cladding layer 25 and a P-type second upper cladding layer (i.e., the third semiconductor layer 43). When current is applied to the chip, the current can be injected into the active layer 24 to emit light. In this structure, the first region 212 only serves as a light channel and does not produce an electro-optic effect.

[0086] Based on this epitaxial structure 2, a SiO2 insulating layer is grown using PECVD, and current injection windows are opened on the ridges using photolithography and etching. Then, SiO2 is deposited and grown on the chip surface. X or SiN X The dielectric film on the ridges is removed using photolithography and etching methods, and electrode windows are etched out. Then, upper and lower metal electrodes are fabricated using evaporation and sputtering methods. The electrode materials are Ti, Pt, and Au. After chip disassembly, optical films are usually deposited on the front and rear light-emitting surfaces to reduce end-face reflection.

[0087] This embodiment achieves local electro-optic conversion of the active layer 24 of the chip by fabricating a light-emitting region 211 and a dark region 210, further reducing chip heat generation and improving chip lifespan. Simultaneously, the change in the optical waveguide size optimizes the far-field divergence angle of the chip.

[0088] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A semiconductor optical amplifier, characterized in that, It includes a substrate (1) and a mesa structure (21) formed by etching an epitaxial structure (2) grown on the substrate (1). The table structure (21) is divided into at least one dark area (210) and at least one light-emitting area (211). A current-conducting structure (3) is grown above the mesa of the light-emitting area (211) to conduct current to the mesa structure (21). A first current blocking structure (4) is grown above the light-free region (210) to block the current from the upper layer from reaching the mesa structure (21), so that the region does not emit light and only serves as a transmission channel for the optical waveguide. Based on the distance from both ends of the optical amplifier, the portion of the platform structure (21) near both ends of the optical amplifier is divided into a first region (212), and the portion of the platform structure (21) near the middle of the optical amplifier is divided into a second region (213); the first region (212) is designated as a light-free region (210), and the second region (213) is designated as a light-emitting region (211). The difference between the tabletop width in the first region (212) and the tabletop width in the second region (213) of the tabletop structure (21) is greater than a first preset difference; and at the connection position between the first region (212) and the second region (213), the tabletop width of the tabletop structure (21) increases or decreases sequentially to achieve a smooth connection between the first region (212) and the second region (213) of the tabletop structure (21).

2. The semiconductor optical amplifier according to claim 1, characterized in that, The first current blocking structure (4) includes a first semiconductor layer (41) and a second semiconductor layer (42) grown on the first semiconductor layer (41); wherein the first semiconductor layer (41) is a P-type material and the second semiconductor layer (42) is an N-type material.

3. The semiconductor optical amplifier according to claim 1, characterized in that, The current-conducting structure (3) includes one or more semiconductor layers, wherein the one or more semiconductor layers have the same doping type.

4. The semiconductor optical amplifier according to any one of claims 1-3, characterized in that, A second current blocking structure (5) is also grown on both sides of the light-emitting area (211) to block the current from the upper layer from reaching both sides of the mesa structure (21); wherein, the second current blocking structure (5) is obtained by etching away part of the structure of the first current blocking structure (4) located above the mesa of the light-emitting area (211) after growing the first current blocking structure (4) above the light-emitting area (211).

5. The semiconductor optical amplifier according to any one of claims 1-3, characterized in that, The epitaxial structure (2) includes at least one of a buffer layer (22), a lower cladding layer (23), an active layer (24), and a first upper cladding layer (25).

6. A method for manufacturing a semiconductor optical amplifier, used to manufacture the semiconductor optical amplifier as described in any one of claims 1-5, characterized in that, An epitaxial structure (2) is grown on a substrate (1), comprising: A protective film (6) is grown on the epitaxial structure (2), and the protective film (6) is etched to obtain a preset pattern. The surface of the epitaxial structure (2) on which the protective film (6) is grown is etched to obtain a mesa structure (21) covered with the protective film (6). The protective film (6) in the dark region (210) is etched away, and multiple semiconductor layers are grown on the surface of the mesa structure (21). After growing the corresponding semiconductor layers, the protective film (6) in the light-emitting region (211) is etched away, and subsequent semiconductor layers are grown to obtain the first current blocking structure (4) in the dark region (210) and the current conducting structure (3) in the light-emitting region (211).

7. The method for fabricating a semiconductor optical amplifier according to claim 6, characterized in that, The process of growing multiple semiconductor layers on the surface of the mesa structure (21), and etching away the protective film (6) in the light-emitting area (211) after growing the corresponding semiconductor layers, and then growing subsequent semiconductor layers, specifically includes: A first semiconductor layer (41) and a second semiconductor layer (42) are grown on the surface of the mesa structure (21). After growing the second semiconductor layer (42), the protective film (6) in the light-emitting region (211) is etched away, and a third semiconductor layer (43) is grown to obtain a first current blocking structure (4) in the light-free region (210) and a current conducting structure (3) in the light-emitting region (211).

8. The method for fabricating a semiconductor optical amplifier according to claim 6, characterized in that, The second difference between the table width in the first region (212) and the table width in the second region (213) of the preset graphic is greater than the preset difference; Furthermore, at the connection point between the first region (212) and the second region (213), the width of the platform of the preset graphic increases or decreases sequentially.

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