A resonant gate drive circuit suitable for SiC MOSFET series connection

Abstract

The application discloses a resonant gate drive circuit suitable for SiC MOSFET series connection, which comprises a drive circuit, a protection circuit, a level conversion and auxiliary power supply circuit and a power circuit, wherein the drive circuit is composed of a drive chip, a resonant inductor and a diode; the protection circuit is composed of a diode; the level conversion and auxiliary power supply circuit is composed of a level conversion circuit and an auxiliary power supply circuit; and the power circuit is composed of a SiC MOSFET / IGBT series connection circuit. The application can control the turn-on and turn-off of the power semiconductor device when working in series connection, realize the electrical isolation between the signal input side and the drive output side, reduce the energy loss of the device drive circuit, realize the voltage sharing of the series connection circuit, expand to multiple series connection, expand the working voltage and improve the circuit efficiency.

Description

Technical Field

[0001] This invention relates to the fields of power semiconductor device drive design and performance testing technology, specifically a resonant gate drive circuit suitable for SiC MOSFET series connection. Background Technology

[0002] With the widespread application of power semiconductor devices, SiC MOSFETs are more suitable for high-frequency applications compared to Si IGBTs. However, in high-frequency environments, the losses in the drive circuit also increase accordingly. Traditional gate drive circuits designed with drive resistors are energy-consuming circuits, further increasing losses. Currently, the maximum operating voltage of SiC MOSFETs produced by mainstream manufacturers is 1700V, which cannot meet the application conditions of higher bus voltages. Therefore, it is necessary to connect the devices in series to meet both high-frequency and high-voltage application environments. However, when devices are connected in series, uneven voltage distribution is often caused by inconsistent parasitic parameters in the power circuit. In addition, power semiconductor devices under high-frequency conditions will experience higher overvoltage and overcurrent phenomena, which can lead to mis-conduction and failure of the devices in severe cases, causing irreversible damage to the devices and applications. Summary of the Invention

[0003] This invention addresses the shortcomings of existing technologies by proposing a resonant gate drive circuit suitable for SiC MOSFET series connection. This circuit aims to achieve efficient and reliable conduction of power semiconductor devices operating at high frequencies. Furthermore, under series connection conditions, it enables complementary balancing of the gate drive current, synchronizing the gate drive signals and achieving reasonable voltage equalization of the output voltage of the series-connected devices. The resonant drive circuit also allows for energy recovery and can be extended to accommodate a sufficient number of series lines, thereby meeting the application requirements of higher bus voltages in external circuits.

[0004] To achieve the above-mentioned objectives, the present invention adopts the following technical solution:

[0005] The present invention provides a resonant gate drive circuit suitable for SiC MOSFET series connection, characterized in that it includes: a drive circuit, a protection circuit, a level conversion and auxiliary power supply circuit, and a power circuit.

[0006] The driving circuit consists of driving chip U1, driving chip U2, resonant inductor L1, resonant inductor L2, and diodes D1, D2, D3, D4, D7, D8, D9, and D10.

[0007] The input VIN pin of the driver chip U1 is connected to the input voltage Vs1. The input IN+ and IN- pins of the driver chip U1 receive the PWM signal sent by the external DSP, respectively. The input 4-GND1 pin of the driver chip U1 is grounded.

[0008] The output VCC pin of the driver chip U1 is connected to the cathode of diode D3, and the connection point is connected to the output voltage VCC1 of the auxiliary power supply. The output GND2 pin of the driver chip U1 is connected to the anode of diode D4, and the connection point is connected to the output voltage VEE1 of the auxiliary power supply. The output OUT+ pin of the driver chip U1 is connected to the anode of diode D1, and the output OUT- pin of the driver chip U1 is connected to the cathode of diode D2.

[0009] The cathode of diode D1 is connected to the anode of diode D2, and the connection point between the two is connected to one end of resonant inductor L1.

[0010] The anode of diode D3 is connected to the cathode of diode D4, and the connection point of the two is connected to the other end of resonant inductor L1 and the gate of metal-oxide-semiconductor field-effect transistor MOSFET1, respectively.

[0011] The input VIN pin of the driver chip U2 is connected to the input voltage Vs2. The input IN+ and IN- pins of the driver chip U2 receive the PWM signals sent by the external DSP, respectively. The input GND1 pin of the driver chip U2 is grounded.

[0012] The output VCC pin of the driver chip U2 is connected to the cathode of diode D9, and the connection point is connected to the output voltage VCC2 of the auxiliary power supply. The output GND2 pin of the driver chip U2 is connected to the anode of diode D10, and the connection point is connected to the output voltage VEE2 of the auxiliary power supply. The output OUT+ pin of the driver chip U2 is connected to the anode of diode D7, and the output OUT- pin of the driver chip U2 is connected to the cathode of diode D8.

[0013] The cathode of diode D7 is connected to the anode of diode D8, and the connection point between the two is connected to one end of resonant inductor L2.

[0014] The anode of diode D9 is connected to the cathode of diode D10, and the connection point of the two is connected to the other end of resonant inductor L2 and the gate of metal-oxide-semiconductor field-effect transistor MOSFET2, respectively.

[0015] The protection circuit consists of diodes D5, D6, D11, and D12.

[0016] The anode of diode D5 is connected to the gate of metal-oxide-semiconductor field-effect transistor MOSFET1, and the cathode is connected to the anode of diode D6.

[0017] The cathode of diode D6 is connected to the drain of metal-oxide-semiconductor field-effect transistor MOSFET1;

[0018] The anode of diode D11 is connected to the gate of metal-oxide-semiconductor field-effect transistor MOSFET2, and the cathode of diode D11 is connected to the anode of diode D12.

[0019] The cathode of the diode D12 is connected to the drain of the metal-oxide-semiconductor field-effect transistor MOSFET2;

[0020] The level conversion and auxiliary power supply circuit consists of a level conversion circuit and an auxiliary power supply circuit.

[0021] The level conversion circuit consists of level conversion chip U3, level conversion chip U5, capacitor C1, capacitor C2, capacitor C8, and capacitor C9;

[0022] The IN pin of chip U3 is connected to the input voltage Vin, the OUT pin of chip U3 is connected to the output voltage Vs1, and the GND pin of chip U3 is grounded.

[0023] The two ends of capacitor C1 are connected to the IN pin and GND pin of chip U3, respectively; the two ends of capacitor C2 are connected to the OUT pin and GND pin of chip U3, respectively.

[0024] The IN pin of chip U5 is connected to the input voltage Vin, the OUT pin of chip U5 is connected to the output voltage Vs2, and the GND pin of chip U3 is grounded.

[0025] The two ends of capacitor C8 are connected to the IN pin and GND pin of chip U5, respectively; the two ends of capacitor C9 are connected to the OUT pin and GND pin of chip U5, respectively.

[0026] The auxiliary power supply circuit consists of an isolated DC / DC chip U4, an isolated DC / DC chip U6, capacitors C3, C4, C5, C6, C7, C10, C11, C12, C13, and C14.

[0027] The VIN pin of chip U4 is connected to the input voltage Vin, the GND pin of chip U4 is grounded, the V+ pin of chip U4 is connected to the output voltage VCC1, the 0V pin of chip U4 is connected to the output potential Vc1, and the V- pin of chip U4 is connected to the output voltage VEE1.

[0028] The two ends of capacitor C3 are connected to the VIN pin and GND pin of chip U4, respectively; capacitor C4 and capacitor C5 are connected in parallel, and their two ends are connected to the V+ pin and 0V pin of chip U4, respectively; capacitor C6 and capacitor C7 are connected in parallel, and their two ends are connected to the 0V pin and V- pin of chip U4, respectively.

[0029] The VIN pin of chip U6 is connected to the input voltage Vin, the GND pin of chip U6 is grounded, the V+ pin of chip U6 is connected to the output voltage VCC2, the 0V pin of chip U6 is connected to the output potential Vc2, and the V- pin of chip U6 is connected to the output voltage VEE2.

[0030] The two ends of capacitor C10 are connected to the VIN pin and GND pin of chip U6, respectively; capacitor C11 and capacitor C12 are connected in parallel, and their two ends are connected to the V+ pin and 0V pin of chip U6, respectively; capacitor C13 and capacitor C14 are connected in parallel, and their two ends are connected to the 0V pin and V- pin of chip U6, respectively.

[0031] The power circuit consists of a metal-oxide-semiconductor field-effect transistor MOSFET1 and a metal-oxide-semiconductor field-effect transistor MOSFET2;

[0032] The drain of the metal-oxide-semiconductor field-effect transistor MOSFET1 is connected to an external circuit, the gate is connected to the connection point between diodes D3 and D4 in the driving circuit, and the source is connected to the 0V pin of chip U4 in the auxiliary power supply circuit.

[0033] The drain of the metal-oxide-semiconductor field-effect transistor MOSFET2 is connected to the source of the metal-oxide-semiconductor field-effect transistor MOSFET1, the gate is connected to the connection point between diodes D9 and D10 in the driving circuit, and the source is connected to the 0V pin of chip U6 in the auxiliary power supply circuit.

[0034] The resonant gate drive circuit for SiC MOSFETs in series, as described in this invention, is also characterized by:

[0035] The driving chip U1 is composed of a P-type semiconductor device P1 and an N-type semiconductor device N1;

[0036] The gate of the P-type semiconductor device P1 receives the PWM signal, the source is connected to the VCC pin of the chip U1, and the drain is connected to the OUT+ pin of the chip U1.

[0037] The gate of the N-type semiconductor device N1 receives the PWM signal, the source is connected to the GND2 pin of the chip U1, and the drain is connected to the OUT- pin of the chip U1.

[0038] The first resonant circuit of the driving circuit is composed of diodes D1, D2, D3, D4, D5, D6 and resonant inductor L1;

[0039] When the P-type semiconductor device P1 is turned on and the N-type semiconductor device N1 is turned off, the connection point potential between diodes D1 and D2 is the driving positive voltage VCC1. The driving positive voltage VCC1 charges the internal capacitor of MOSFET1 through P1, diode D1, and resonant inductor L1. When the current in resonant inductor L1 rises to its peak value, the voltage of diode D3 is reverse-biased to prevent the current from continuing to increase and clamps the output gate voltage at its maximum positive value. The metal-oxide-semiconductor field-effect transistor MOSFET1 is turned on, and the current returns to VCC1 through resonant inductor L1 and diode D3, thereby realizing energy recovery and utilization.

[0040] When the P-type semiconductor device P1 is turned off and the N-type semiconductor device N1 is turned on, the connection point potential between diodes D1 and D2 is the driving negative voltage VEE1. The internal capacitor of MOSFET1 discharges to VEE1 through resonant inductor L1, diode D2, and N1. When the current of resonant inductor L1 rises in reverse to its peak value, the voltage of diode D4 is reverse-biased to prevent the current from increasing further and to clamp the output gate voltage at its maximum negative value. When the metal-oxide-semiconductor field-effect transistor MOSFET1 is turned off, the current returns to VEE1 through diode D4 and resonant inductor L1, thereby realizing energy recovery and utilization.

[0041] The diodes D3 and D4 clamp the gate voltage output by the first resonant circuit between VEE1 and VCC1 to eliminate overvoltage oscillation caused by LC resonance.

[0042] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0043] 1. This invention uses an RGD (Resonant Gate Driver) circuit to turn SiC MOSFETs on and off. During the driving process, some current energy is recovered, reducing the driving losses of power semiconductor devices and improving the operating efficiency of the driver chip. Furthermore, the diodes in the driver circuit can effectively clamp the driving voltage, preventing excessive driving voltage from damaging the driver circuit during the resonance process. Therefore, this invention enables power semiconductor devices to operate more efficiently, reliably, and with reduced power consumption.

[0044] 2. This invention couples the resonant inductors in parallel drive circuits, enabling the inductors to not only function as resonators in the circuit but also to provide complementary current balancing for the parallel circuits. This allows the drive circuits to be turned on and off synchronously, solving the dynamic and static voltage imbalance problems caused by differences in parameters such as threshold voltage, on-resistance, inter-electrode capacitance, and transconductance of power semiconductor devices. It balances the voltage of multiple series-connected devices, achieving voltage equalization in series-connected power circuits. Therefore, this invention can achieve safe and reliable voltage equalization for multiple devices connected in series in a power circuit.

[0045] 3. This invention addresses the design of the gate drive circuit without involving the design of the drive resistor. Due to the effects of the coupling inductor and resonant circuit, a drive resistor is unnecessary to eliminate gate oscillation, reducing energy loss caused by the presence of a drive resistor. Therefore, this invention can eliminate the need for a gate drive resistor to achieve voltage equalization in series devices and reduce energy loss.

[0046] 4. This invention uses a Zener diode to detect the drain-source voltage of a metal-oxide-semiconductor field-effect transistor (MOSFET), preventing excessive drain-source voltage from damaging the device. When an excessive drain-source voltage is generated during the MOSFET's turn-off process due to parasitic parameters or a short circuit, potentially damaging the device, the Zener diode breaks down. The power circuit current then flows to the MOSFET's internal capacitor to charge it, reducing the turn-off rate, minimizing voltage overshoot, and protecting the device.

[0047] 5. This invention reserves multiple test points in the overall control circuit design, providing conditions for subsequent experiments. This enables better performance of SiC MOSFET double-pulse experiments, SiC MOSFET series double-pulse experiments, SiC MOSFET series applications, and other related tests. Furthermore, subsequent experiments can verify the beneficial effects of RGD control on semiconductor devices. Therefore, this invention can meet the needs of various experiments, achieving high adaptability. Attached Figure Description

[0048] Figure 1 This is a driving circuit diagram in an embodiment of the present invention;

[0049] Figure 2This is a circuit diagram of level conversion and auxiliary power supply in an embodiment of the present invention;

[0050] Figure 3 This is an overall drive control flowchart in an embodiment of the present invention;

[0051] Figure 4 This is an extended circuit diagram in an embodiment of the present invention. Detailed Implementation

[0052] The technical solution of the present invention will now be clearly and completely described in conjunction with the accompanying drawings.

[0053] In this embodiment, a resonant gate drive circuit suitable for SiC MOSFET series connection includes: a drive circuit, a protection circuit, a level conversion and auxiliary power supply circuit, and a power circuit.

[0054] like Figure 1 As shown, the driving circuit consists of driving chip U1, driving chip U2, resonant inductor L1, resonant inductor L2, and diodes D1, D2, D3, D4, D7, D8, D9, and D10.

[0055] The driver chip U1 has 8 pins, namely the input side pins 1-VIN, 2-IN+, 3-IN-, 4-GND1, and the output side pins 5-VCC, 6-OUT+, 7-OUT-, 8-GND2;

[0056] The input side VIN pin 1 of the driver chip U1 is connected to the input voltage Vs1. The input side IN+ pin 2 and IN- pin 3 of the driver chip U1 receive the PWM signal sent by the external DSP, respectively. The input side GND1 pin 4 of the driver chip U1 is grounded.

[0057] The output VCC pin 5 of the driver chip U1 is connected to the cathode of diode D3, and the connection point is connected to the output voltage VCC1 of the auxiliary power supply. The output GND2 pin 8 of the driver chip U1 is connected to the anode of diode D4, and the connection point is connected to the output voltage VEE1 of the auxiliary power supply. The output OUT+ pin 6 of the driver chip U1 is connected to the anode of diode D1, and the output OUT- pin 7 of the driver chip U1 is connected to the cathode of diode D2.

[0058] The driver chip U1 is internally composed of a P-type semiconductor device P1 and an N-type semiconductor device N1;

[0059] The gate of the P-type semiconductor device P1 receives the PWM signal, the source is connected to the VCC pin 5 of the chip U1, and the drain is connected to the OUT+ pin 6 of the chip U1.

[0060] The gate of the N-type semiconductor device N1 receives the PWM signal, the source is connected to pin 8-GND2 of chip U1, and the drain is connected to pin 7-OUT of chip U1.

[0061] The same applies to the driver chip U2.

[0062] The cathode of diode D1 is connected to the anode of diode D2, and the connection point between the two is connected to one end of resonant inductor L1.

[0063] The anode of diode D3 is connected to the cathode of diode D4, and the connection point of the two is connected to the other end of resonant inductor L1 and the gate of metal-oxide-semiconductor field-effect transistor MOSFET1, respectively.

[0064] The driver chip U2 has 8 pins: 1-VIN, 2-IN+, 3-IN-, 4-GND1 for the input side, and 5-VCC, 6-OUT+, 7-OUT-, 8-GND2 for the output side.

[0065] The input side VIN pin 1 of the driver chip U2 is connected to the input voltage Vs2. The input side IN+ pin 2 and IN- pin 3 of the driver chip U2 receive the PWM signal sent by the external DSP, respectively. The input side GND1 pin 4 of the driver chip U2 is grounded.

[0066] The output VCC pin 5 of the driver chip U2 is connected to the cathode of diode D9, and the connection point is connected to the output voltage VCC2 of the auxiliary power supply. The output GND2 pin 8 of the driver chip U2 is connected to the anode of diode D10, and the connection point is connected to the output voltage VEE2 of the auxiliary power supply. The output OUT+ pin 6 of the driver chip U2 is connected to the anode of diode D7, and the output OUT- pin 7 of the driver chip U2 is connected to the cathode of diode D8.

[0067] The cathode of diode D7 is connected to the anode of diode D8, and the connection point is connected to one end of resonant inductor L2.

[0068] The anode of diode D9 is connected to the cathode of diode D10, and the connection point of the two is connected to the other end of resonant inductor L2 and the gate of metal-oxide-semiconductor field-effect transistor MOSFET2, respectively.

[0069] The diodes D1, D2, D7, and D8 used are to reduce reverse recovery and make the driving voltage more stable. However, due to their presence, the generated driving voltage is slightly higher than the potentials VCC and VEE generated by the auxiliary power supply circuit.

[0070] Resonant inductors L1 and L2 are positively coupled by a magnetic ring to transfer energy between the first and second resonant circuits and to achieve complementary balancing of the gate current, thereby achieving voltage equalization.

[0071] The first resonant circuit of the drive circuit is composed of diodes D1, D2, D3, D4, D5, D6 and resonant inductor L1;

[0072] When the P-type semiconductor device P1 is turned on and the N-type semiconductor device N1 is turned off, the connection point potential between diodes D1 and D2 is the driving positive voltage VCC1. The driving positive voltage VCC1 charges the internal capacitor of MOSFET1 through P1, diode D1, and resonant inductor L1. When the current in resonant inductor L1 rises to its peak value, the voltage of diode D3 is reverse-biased to prevent the current from continuing to increase and clamps the output gate voltage at its maximum positive value. The metal-oxide-semiconductor field-effect transistor MOSFET1 is turned on, and the current returns to VCC1 through resonant inductor L1 and diode D3, thereby realizing energy recovery and utilization.

[0073] When the P-type semiconductor device P1 is turned off and the N-type semiconductor device N1 is turned on, the connection point potential between diodes D1 and D2 is the driving negative voltage VEE1. The internal capacitor of MOSFET1 discharges to VEE1 through resonant inductor L1, diode D2, and N1. When the current of resonant inductor L1 rises in reverse to its peak value, the voltage of diode D4 is reverse-biased to prevent the current from increasing further and to clamp the output gate voltage at its maximum negative value. When the metal-oxide-semiconductor field-effect transistor MOSFET1 is turned off, the current returns to VEE1 through diode D4 and resonant inductor L1, thereby realizing energy recovery and utilization.

[0074] Diodes D3 and D4 clamp the gate voltage output from the first resonant circuit between VEE1 and VCC1 to eliminate overvoltage oscillation caused by LC resonance.

[0075] The same applies to the second resonant circuit.

[0076] The protection circuit consists of diodes D5, D6, D11, and D12.

[0077] The anode of diode D5 is connected to the gate of metal-oxide-semiconductor field-effect transistor MOSFET1, and the cathode is connected to the anode of diode D6;

[0078] The cathode of diode D6 is connected to the drain of metal-oxide-semiconductor field-effect transistor MOSFET1;

[0079] The anode of diode D11 is connected to the gate of metal-oxide-semiconductor field-effect transistor MOSFET2, and the cathode of diode D11 is connected to the anode of diode D12.

[0080] The cathode of diode D12 is connected to the drain of metal-oxide-semiconductor field-effect transistor MOSFET2;

[0081] When MOSFET1 experiences excessive drain-source voltage overshoot during turn-off due to parasitic parameters or short circuits, potentially damaging the device, Zener diode D6 or D12 breaks down. The excessively high dv / dt of the power circuit generates current through the MOSFET's internal capacitance to charge the gate capacitance, reducing the turn-off rate, minimizing voltage overshoot, and protecting the device.

[0082] The power circuit consists of a metal-oxide-semiconductor field-effect transistor (MOSFET1) and a metal-oxide-semiconductor field-effect transistor (MOSFET2);

[0083] The drain of the metal-oxide-semiconductor field-effect transistor MOSFET1 is connected to the external circuit, the gate is connected to the connection point between diodes D3 and D4 in the driving circuit, and the source is connected to the 4-0V pin of chip U4 in the auxiliary power supply circuit.

[0084] The drain of the metal-oxide-semiconductor field-effect transistor MOSFET2 is connected to the source of the metal-oxide-semiconductor field-effect transistor MOSFET1, the gate is connected to the connection point between diodes D9 and D10 in the driving circuit, and the source is connected to the 4-0V pin of chip U6 in the auxiliary power supply circuit.

[0085] like Figure 2 As shown, the level conversion and auxiliary power supply circuit consists of a level conversion circuit and an auxiliary power supply circuit;

[0086] The level conversion circuit consists of level conversion chip U3, level conversion chip U5, capacitor C1, capacitor C2, capacitor C8, and capacitor C9;

[0087] Chip U3 has 3 pins: 1-IN, 2-OUT, 3-GND;

[0088] The IN pin 1 of chip U3 is connected to the input voltage Vin, the OUT pin 2 of chip U3 is connected to the output voltage Vs1, and the GND pin 3 of chip U3 is grounded.

[0089] The two ends of capacitor C1 are connected to the IN pin 1 and GND pin 3 of chip U3, respectively; the two ends of capacitor C2 are connected to the OUT pin 2 and GND pin 3 of chip U3, respectively.

[0090] Chip U5 has 3 pins: 1-IN, 2-OUT, 3-GND;

[0091] The IN pin 1 of chip U5 is connected to the input voltage Vin, the OUT pin 2 of chip U5 is connected to the output voltage Vs2, and the GND pin 3 of chip U3 is grounded.

[0092] The two ends of capacitor C8 are connected to the IN pin 1 and GND pin 3 of chip U5, respectively; the two ends of capacitor C9 are connected to the OUT pin 2 and GND pin 3 of chip U5, respectively.

[0093] The auxiliary power supply circuit consists of isolated DC / DC chip U4, isolated DC / DC chip U6, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C10, capacitor C11, capacitor C12, capacitor C13, and capacitor C14.

[0094] Chip U4 has 5 pins: 1-VIN, 2-GND, 3-V+, 4-0V, 5-V-;

[0095] The VIN pin 1 of chip U4 is connected to the input voltage Vin, the GND pin 2 of chip U4 is grounded, the V+ pin 3 of chip U4 is connected to the output voltage VCC1, the 0V pin 4 of chip U4 is connected to the output potential Vc1, and the V- pin 5 of chip U4 is connected to the output voltage VEE1.

[0096] The two ends of capacitor C3 are connected to the VIN pin 1 and GND pin 2 of chip U4, respectively; after capacitors C4 and C5 are connected in parallel, their two ends are connected to the V+ pin 3 and 0V pin 4 of chip U4, respectively; after capacitors C6 and C7 are connected in parallel, their two ends are connected to the 0V pin 4 and V- pin 5 of chip U4, respectively.

[0097] Chip U6 has 5 pins: 1-VIN, 2-GND, 3-V+, 4-0V, 5-V-;

[0098] The VIN pin 1 of chip U6 is connected to the input voltage Vin, the GND pin 2 of chip U6 is grounded, the V+ pin 3 of chip U6 is connected to the output voltage VCC2, the 0V pin 4 of chip U6 is connected to the output potential Vc2, and the V- pin 5 of chip U6 is connected to the output voltage VEE2.

[0099] The two ends of capacitor C10 are connected to the VIN pin 1 and GND pin 2 of chip U6, respectively; capacitors C11 and C12 are connected in parallel, and their two ends are connected to the V+ pin 3 and 0V pin 4 of chip U6, respectively; capacitors C13 and C14 are connected in parallel, and their two ends are connected to the 0V pin 4 and V- pin 5 of chip U6, respectively.

[0100] like Figure 3 As shown, an external power supply provides a voltage Vin, which is converted to a voltage Vs by a level conversion circuit. An auxiliary power supply then converts Vin into isolated positive voltage VCC and negative voltage VEE. The converted Vs is used to power the input side of the driver chip, while the isolated positive voltage VCC and negative voltage VEE are used to provide potential to the output side of the driver chip.

[0101] The PWM signal generated by the DSP is used to control the driver chip. The driver chip outputs a square wave voltage with an amplitude between VEE and VCC to power the gate and source of the MOSFET, thereby controlling its turn-on and turn-off.

[0102] The two devices connected in series have the same driving circuit, and their driving processes are independent of each other. They rely solely on the resonant inductor for coupling to transfer energy, balance the gate current, and thus achieve voltage equalization.

[0103] like Figure 4 As shown, this extended circuit is a half-bridge power structure, with both the upper and lower half-bridges consisting of two MOSFETs connected in series to increase the operating voltage level. The two upper devices are controlled by the same PWM1 signal, while the two lower devices are controlled by a separate PWM2 signal. The drive circuits for the two upper MOSFETs are... Figure 2 and Figure 3 The circuit described is consistent, and the voltage of each component is equalized in series through the coupling of the resonant inductor, so that the voltage of the components during operation is kept as balanced as possible.

[0104] As can be seen from the above embodiments, the circuit of the present invention can realize resonant driving and series connection of power semiconductor devices.

Claims

1. A resonant gate drive circuit suitable for SiC MOSFETs in series, characterized in that, include: Drive circuit, protection circuit, level conversion and auxiliary power supply circuit, and power circuit; The driving circuit consists of driving chip U1, driving chip U2, resonant inductor L1, resonant inductor L2, and diodes D1, D2, D3, D4, D7, D8, D9, and D10. The input VIN pin of the driver chip U1 is connected to the input voltage Vs1. The input IN+ and IN- pins of the driver chip U1 receive the PWM signal sent by the external DSP, respectively. The input 4-GND1 pin of the driver chip U1 is grounded. The output VCC pin of the driver chip U1 is connected to the cathode of diode D3, and the connection point is connected to the output voltage VCC1 of the auxiliary power supply. The output GND2 pin of the driver chip U1 is connected to the anode of diode D4, and the connection point is connected to the output voltage VEE1 of the auxiliary power supply. The output OUT+ pin of the driver chip U1 is connected to the anode of diode D1, and the output OUT- pin of the driver chip U1 is connected to the cathode of diode D2. The cathode of diode D1 is connected to the anode of diode D2, and the connection point between the two is connected to one end of resonant inductor L1. The anode of diode D3 is connected to the cathode of diode D4, and the connection point of the two is connected to the other end of resonant inductor L1 and the gate of metal-oxide-semiconductor field-effect transistor MOSFET1, respectively. The input VIN pin of the driver chip U2 is connected to the input voltage Vs2. The input IN+ and IN- pins of the driver chip U2 receive the PWM signal sent by the external DSP, respectively. The input GND1 pin of the driver chip U2 is grounded. The output VCC pin of the driver chip U2 is connected to the cathode of diode D9, and the connection point is connected to the output voltage VCC2 of the auxiliary power supply. The output GND2 pin of the driver chip U2 is connected to the anode of diode D10, and the connection point is connected to the output voltage VEE2 of the auxiliary power supply. The output OUT+ pin of the driver chip U2 is connected to the anode of diode D7, and the output OUT- pin of the driver chip U2 is connected to the cathode of diode D8. The cathode of diode D7 is connected to the anode of diode D8, and the connection point between the two is connected to one end of resonant inductor L2. The anode of diode D9 is connected to the cathode of diode D10, and the connection point of the two is connected to the other end of resonant inductor L2 and the gate of metal-oxide-semiconductor field-effect transistor MOSFET2, respectively. Resonant inductors L1 and L2 are positively coupled using a magnetic ring; The protection circuit consists of diodes D5, D6, D11, and D12. The anode of diode D5 is connected to the gate of metal-oxide-semiconductor field-effect transistor MOSFET1, and the cathode is connected to the anode of diode D6. The cathode of diode D6 is connected to the drain of metal-oxide-semiconductor field-effect transistor MOSFET1; The anode of diode D11 is connected to the gate of metal-oxide-semiconductor field-effect transistor MOSFET2, and the cathode of diode D11 is connected to the anode of diode D12. The cathode of the diode D12 is connected to the drain of the metal-oxide-semiconductor field-effect transistor MOSFET2; The level conversion and auxiliary power supply circuit consists of a level conversion circuit and an auxiliary power supply circuit. The level conversion circuit consists of level conversion chip U3, level conversion chip U5, capacitor C1, capacitor C2, capacitor C8, and capacitor C9; The IN pin of chip U3 is connected to the input voltage Vin, the OUT pin of chip U3 is connected to the output voltage Vs1, and the GND pin of chip U3 is grounded. The two ends of capacitor C1 are connected to the IN pin and GND pin of chip U3, respectively; the two ends of capacitor C2 are connected to the OUT pin and GND pin of chip U3, respectively. The IN pin of chip U5 is connected to the input voltage Vin, the OUT pin of chip U5 is connected to the output voltage Vs2, and the GND pin of chip U3 is grounded. The two ends of capacitor C8 are connected to the IN pin and GND pin of chip U5, respectively; the two ends of capacitor C9 are connected to the OUT pin and GND pin of chip U5, respectively. The auxiliary power supply circuit consists of an isolated DC / DC chip U4, an isolated DC / DC chip U6, capacitors C3, C4, C5, C6, C7, C10, C11, C12, C13, and C14. The VIN pin of chip U4 is connected to the input voltage Vin, the GND pin of chip U4 is grounded, the V+ pin of chip U4 is connected to the output voltage VCC1, the 0V pin of chip U4 is connected to the output potential Vc1, and the V- pin of chip U4 is connected to the output voltage VEE1. The two ends of capacitor C3 are connected to the VIN pin and GND pin of chip U4, respectively; capacitor C4 and capacitor C5 are connected in parallel, and their two ends are connected to the V+ pin and 0V pin of chip U4, respectively; capacitor C6 and capacitor C7 are connected in parallel, and their two ends are connected to the 0V pin and V- pin of chip U4, respectively. The VIN pin of chip U6 is connected to the input voltage Vin, the GND pin of chip U6 is grounded, the V+ pin of chip U6 is connected to the output voltage VCC2, the 0V pin of chip U6 is connected to the output potential Vc2, and the V- pin of chip U6 is connected to the output voltage VEE2. The two ends of capacitor C10 are connected to the VIN pin and GND pin of chip U6, respectively; capacitor C11 and capacitor C12 are connected in parallel, and their two ends are connected to the V+ pin and 0V pin of chip U6, respectively; capacitor C13 and capacitor C14 are connected in parallel, and their two ends are connected to the 0V pin and V- pin of chip U6, respectively. The power circuit consists of a metal-oxide-semiconductor field-effect transistor MOSFET1 and a metal-oxide-semiconductor field-effect transistor MOSFET2; The drain of the metal-oxide-semiconductor field-effect transistor MOSFET1 is connected to an external circuit, the gate is connected to the connection point between diodes D3 and D4 in the driving circuit, and the source is connected to the 0V pin of chip U4 in the auxiliary power supply circuit. The drain of the metal-oxide-semiconductor field-effect transistor MOSFET2 is connected to the source of the metal-oxide-semiconductor field-effect transistor MOSFET1, the gate is connected to the connection point between diodes D9 and D10 in the driving circuit, and the source is connected to the 0V pin of chip U6 in the auxiliary power supply circuit.

2. The resonant gate drive circuit suitable for SiC MOSFET series connection according to claim 1, characterized in that, The driving chip U1 is composed of a P-type semiconductor device P1 and an N-type semiconductor device N1; The gate of the P-type semiconductor device P1 receives the PWM signal, the source is connected to the VCC pin of the chip U1, and the drain is connected to the OUT+ pin of the chip U1. The gate of the N-type semiconductor device N1 receives the PWM signal, the source is connected to the GND2 pin of the chip U1, and the drain is connected to the OUT- pin of the chip U1.

3. The resonant gate drive circuit suitable for SiC MOSFET series connection according to claim 2, characterized in that: The first resonant circuit of the driving circuit is composed of diodes D1, D2, D3, D4, D5, D6 and resonant inductor L1; When the P-type semiconductor device P1 is turned on and the N-type semiconductor device N1 is turned off, the connection point potential between diodes D1 and D2 is the driving positive voltage VCC1. The driving positive voltage VCC1 charges the internal capacitor of MOSFET1 through P1, diode D1, and resonant inductor L1. When the current in resonant inductor L1 rises to its peak value, the voltage of diode D3 is reverse-biased to prevent the current from continuing to increase and clamps the output gate voltage at its maximum positive value. The metal-oxide-semiconductor field-effect transistor MOSFET1 is turned on, and the current returns to VCC1 through resonant inductor L1 and diode D3, thereby realizing energy recovery and utilization. When the P-type semiconductor device P1 is turned off and the N-type semiconductor device N1 is turned on, the connection point potential between diodes D1 and D2 is the driving negative voltage VEE1. The internal capacitor of MOSFET1 discharges to VEE1 through resonant inductor L1, diode D2, and N1. When the current of resonant inductor L1 rises in reverse to its peak value, the voltage of diode D4 is reverse-biased to prevent the current from increasing further and to clamp the output gate voltage at its maximum negative value. When the metal-oxide-semiconductor field-effect transistor MOSFET1 is turned off, the current returns to VEE1 through diode D4 and resonant inductor L1, thereby realizing energy recovery and utilization. The diodes D3 and D4 clamp the gate voltage output by the first resonant circuit between VEE1 and VCC1 to eliminate overvoltage oscillation caused by LC resonance.

Images