High voltage bootstrap capacitor floating half bridge gate drive circuit and apparatus

Abstract

The application discloses a high-voltage self-boosting capacitor floating half-bridge gate drive circuit and equipment, a first end of a high-voltage pulse latch level converter is connected with DVDD, a second end is connected with a control signal, a third end is connected with GND, a fourth end, a fifth end and a sixth end are connected with the second end of C BOOT , a seventh end is connected with the first end of a high-side gate drive unit, an eighth end and a ninth end are connected with the second end of D1, the first end of D1 is connected with DVDD, the first end of C BOOT is connected with the second end of D1; the second end and the third end of the high-side gate drive unit are connected with the first end of L1, the fourth end is connected with the gate of SW1, the fifth end and the sixth end are connected with the second end of D1, the second end of L1 outputs a voltage, the first end of C out is connected with the voltage, the second end of C out is connected with GND; the first end of a low-side gate drive unit is connected with the control signal, the second end and the third end are connected with GND, the fourth end is connected with the gate of SW2, the fifth end and the sixth end are connected with DVDD; the source electrode of SW1 is connected with the drain electrode of SW2, the drain electrode is connected with an input voltage VIN, and the source electrode of SW2 is connected with GND.

Description

Technical Field

[0001] This invention belongs to the field of circuit technology, specifically relating to a high-voltage bootstrap capacitor floating half-bridge gate drive circuit and device. Background Technology

[0002] A switching power supply maintains a stable output voltage by controlling the on- and off-time ratio of a switching transistor, offering advantages such as small size and high efficiency. Most power supply applications use gallium nitride (GaN) field-effect transistors (FETs) or N-channel metal-oxide-semiconductor (MOSFETs) as the main power supply due to their low cost, faster speed, and lower on-resistance. However, using GaN FETs or N-channel MOSFETs as high-side switches requires a gate drive circuit referenced to the source of the GaN FET or N-channel MOSFET. The driver must be able to withstand the dramatic voltage swings during switching and drive the gate of the GaN FET or N-channel MOSFET above the positive power rail. In most cases, however, the gate drive voltage must be higher than the highest DC potential supplied in the circuit. This makes high-side driver design a challenging task.

[0003] When the voltage level of the gate drive circuit is lower than the voltage level of the GaN FET or N-channel MOSFET power transistor, the principle of bootstrap gate drive technology is considered. This method utilizes a gate drive and an accompanying bias circuit, both of which use the source of the master GaN FET or N-channel MOSFET transistor as a reference. Both the driver and the bias circuit oscillate between the two input voltage rails and the device source.

[0004] However, in traditional bootstrap half-bridge gate-driven high-voltage drivers, the driver and ground reference control signals are connected by a level shifting circuit, which must withstand the high voltage difference between the floating high-side and ground reference low-side circuits and the large capacitor switching current, resulting in poor circuit performance. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a high-voltage bootstrap capacitor-type floating half-bridge gate drive circuit and device. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] In a first aspect, the present invention provides a high-voltage bootstrap capacitor floating half-bridge gate drive circuit, comprising: a high-voltage pulse latch-up level converter, a high-side gate drive unit, and a low-side gate drive unit.

[0007] The first terminal of the high-voltage pulse latch-up level converter is connected to the power supply DVDD, the second terminal is the control signal input terminal, the third terminal is connected to ground GND, and the fourth, fifth, and sixth terminals are connected to capacitor C. BOOT The second and seventh terminals are connected to the first terminal of the high-side gate drive unit. The eighth and ninth terminals are connected to the second terminal of diode D1. The first terminal of diode D1 is connected to the power supply DVDD. Capacitor C BOOT The first terminal is connected to the second terminal of diode D1;

[0008] The second and third terminals of the high-side gate drive unit are connected to the first terminal of inductor L1, the fourth terminal is connected to the gate of switch SW1, the fifth and sixth terminals are connected to the second terminal of diode D1, the second terminal of inductor L1 is the voltage output terminal, and the second terminal of inductor L1 is connected to the output capacitor C. out The first terminal, the output capacitor C out The second end is connected to ground (GND);

[0009] The first terminal of the low-side gate drive unit is the control signal input terminal, the second and third terminals are connected to ground GND, the fourth terminal is connected to the gate of the switching transistor SW2, and the fifth and sixth terminals are connected to the power supply DVDD.

[0010] The source of switch SW1 is connected to the drain of switch SW2, the drain of switch SW1 is connected to the input voltage VIN, and the source of switch SW2 is connected to ground GND.

[0011] The high-voltage pulse latch-up level converter is used to convert the input level of the second terminal of the high-voltage pulse latch-up level converter to a high-low level, so that the output of the seventh terminal of the high-voltage pulse latch-up level converter is a logic opposite to the input level. When the seventh terminal of the high-voltage pulse latch-up level converter outputs a high level, the voltage value is DVDD+VIN, and when the seventh terminal of the high-voltage pulse latch-up level converter outputs a low level, the voltage value is VIN.

[0012] The high-side gate drive unit is used to output a low level at the fourth terminal when the input level of the first terminal of the high-side gate drive unit is high, so that the gate drive signal of the switch SW1 is low; and to output a high level at the fourth terminal when the input level of the first terminal of the high-side gate drive unit is low, so that the gate drive signal of the switch SW1 is high.

[0013] The low-side gate drive unit is used to output a low level at the fourth terminal when the input level of the first terminal of the low-side gate drive unit is high, so that the gate drive signal of the switch SW2 is low; and to output a high level at the fourth terminal when the input level of the first terminal of the low-side gate drive unit is low, so that the gate drive signal of the switch SW2 is high.

[0014] Optional, the high-voltage pulse latch-up level converter includes:

[0015] The high-voltage pulse latch-up level converter includes an inverter INV1, high-voltage PMOS transistors DPMOS1, DPMOS2, DPMOS3, and DPMOS4, low-voltage NMOS transistors MN1 and MN2, and high-voltage NMOS transistors DNMOS1 and DNMOS2.

[0016] The positive terminal of inverter INV1 is the first terminal of the high-voltage pulse latch-up level converter, which is connected to the power supply DVDD. The negative terminal is the third terminal of the high-voltage pulse latch-up level converter, which is connected to ground GND. The input terminal is the second terminal of the high-voltage pulse latch-up level converter, which is connected to the control signal PWM, the first terminal of the low-side gate drive unit, and the gate of the high-voltage NMOS transistor DNMOS2. The output terminal is connected to the gate of the high-voltage NMOS transistor DNMOS1.

[0017] The drain of high-voltage NMOS transistor DNMOS1 is connected to the drain of high-voltage PMOS transistor DPMOS1 and the drain of high-voltage PMOS transistor DPMOS3. The source of high-voltage NMOS transistor DNMOS1 is connected to the negative terminal of inverter INV1, the source of high-voltage NMOS transistor DNMOS2, the second and third terminals of the low-side gate drive unit, the source of switch transistor SW2, and the output capacitor C. out The second end is connected to ground (GND);

[0018] The drain of the high-voltage NMOS transistor DNMOS2 is connected to the drain of the high-voltage PMOS transistor DPMOS2 and the drain of the high-voltage PMOS transistor DPMOS4.

[0019] The source of the high-voltage PMOS transistor DPMOS1 is connected to the second terminal of the diode D1. The gate of the high-voltage PMOS transistor DPMOS1 is connected to the gate of the low-voltage NMOS transistor MN1, the drain of the low-voltage NMOS transistor MN2, the source of the high-voltage PMOS transistor DPMOS4, and the first terminal of the high-side gate drive unit.

[0020] The source of the high-voltage PMOS transistor DPMOS2 is connected to the second terminal of the diode D1, and the gate of the high-voltage PMOS transistor DPMOS2 is connected to the gate of the low-voltage NMOS transistor MN2, the drain of the low-voltage NMOS transistor MN1, and the source of the high-voltage PMOS transistor DPMOS3.

[0021] The gate and capacitor C of the high-voltage PMOS transistor DPMOS3 BOOT The second terminal, the source of low-voltage NMOS transistor MN1, the source of low-voltage NMOS transistor MN2, the gate of high-voltage PMOS transistor DPMOS4, the source of switching transistor SW1, and the first terminal of inductor L1 are connected.

[0022] Optionally, the high-side gate drive unit includes:

[0023] Inverters INV2, INV3, INV4, INV5, INV6, INV7; NAND gates NAND1, NAND2; low-voltage NMOS transistor MN3; low-voltage PMOS transistor MP1.

[0024] The input terminal of inverter INV2 is the first terminal of the high-side gate drive unit, and the output terminal of inverter INV2 is connected to the input terminal of inverter INV6 and the first input terminal of NAND gate NAND1.

[0025] The output of inverter INV6 is connected to the second input of NAND gate NAND2;

[0026] The first input terminal of the NAND gate NAND2 is connected to the output terminal of the inverter INV5 and the gate of the low-voltage PMOS transistor MP1, and the output terminal of the NAND gate NAND2 is connected to the input terminal of the inverter INV7.

[0027] The output of inverter INV7 is connected to the input of inverter INV3 and the gate of low-voltage NMOS transistor MN3;

[0028] The source of NMOS transistor MN3 is the third terminal of the high-side gate drive unit, and the drain of low-voltage NMOS transistor MN3 is the fourth terminal of the high-side gate drive unit. The drain of NMOS transistor MN3 is connected to the drain of low-voltage PMOS transistor MP1 and the gate of switching transistor SW1.

[0029] The source of the low-voltage PMOS transistor MP1 is the fifth terminal of the high-side gate drive unit;

[0030] The output of inverter INV4 is connected to the input of inverter INV5, and the input of inverter INV4 is connected to the output of NAND gate NAND1.

[0031] The second input terminal of the NOT gate NAND1 is connected to the output terminal of the inverter INV3;

[0032] The second terminal of the high-side gate driving unit is the ground terminal of all logic gates in the high-side gate driving unit;

[0033] The sixth terminal of the high-side gate drive unit is the power supply terminal for all logic gates in the high-side gate drive unit.

[0034] Optionally, the low-side gate drive unit includes:

[0035] Inverters INV8, INV9, INV10, INV11, INV12, INV13; NAND gates NAND3, NAND4; low-voltage NMOS transistor MN4; low-voltage PMOS transistor MP2.

[0036] The input terminal of inverter INV11 is the first terminal of the low-side gate drive unit, and the output terminal of inverter INV11 is connected to the input terminal of inverter INV12 and the first input terminal of NAND gate NAND3.

[0037] The output of inverter INV12 is connected to the second input of NAND gate NAND4;

[0038] The first input terminal of NAND gate NAND4 is connected to the output terminal of inverter INV10 and the gate of low-voltage PMOS transistor MP2, and the output terminal of NAND gate NAND4 is connected to the input terminal of inverter INV13.

[0039] The output of inverter INV13 is connected to the input of inverter INV8 and the gate of low-voltage NMOS transistor MN4;

[0040] The source of the low-voltage NMOS transistor MN4 is the third terminal of the low-side gate drive unit, and the drain of the low-voltage NMOS transistor MN4 is the fourth terminal of the low-side gate drive unit. The drain of the low-voltage NMOS transistor MN4 is connected to the drain of the low-voltage PMOS transistor MP2 and the gate of the switching transistor SW2.

[0041] The source of the low-voltage PMOS transistor MP2 is the fifth terminal of the low-side gate drive unit;

[0042] The output of inverter INV9 is connected to the input of inverter INV8, and the input of inverter INV9 is connected to the output of NAND gate NAND3.

[0043] The second input terminal of the NOT gate NAND3 is connected to the output terminal of the inverter INV8;

[0044] The second terminal of the low-side gate driving unit is the ground terminal of all logic gates in the high-side gate driving unit;

[0045] The sixth terminal of the low-side gate drive unit is the power supply terminal for all logic gates in the high-side gate drive unit.

[0046] Optionally, diode D1 can be multiple diodes connected in series.

[0047] Optionally, the switching transistor SW1 is a GaN FET device or an N-channel MOSFET.

[0048] Optionally, the switching transistor SW2 can be a GaN FET device or an N-channel MOSFET.

[0049] Optional, capacitor C BOOT It is a polarized capacitor, and the capacitance C is... BOOT The first terminal is the positive terminal, and the capacitor C BOOT The second end is the negative electrode.

[0050] Optional, output capacitor C out It is a polarized capacitor, and the capacitance C is... out The first terminal is the positive terminal, and the capacitor C out The second end is the negative electrode.

[0051] In a second aspect, the present invention also provides an electronic device comprising: a high-voltage bootstrap capacitor floating half-bridge gate drive circuit as described in the first aspect and its alternatives.

[0052] The beneficial effects of this invention are:

[0053] The high-voltage bootstrap capacitor-type floating half-bridge gate drive circuit and device provided by this invention are applicable to various high-voltage BCD (Bipolar-CMOS-DMOS) processes, exhibiting better applicability. By controlling the turn-off of the CMOS transistor through a pulse-locked level converter, the high-side level transition of the floating half-bridge is achieved. This not only eliminates quiescent current but also significantly reduces power consumption and improves the efficiency of the switching power supply. It can withstand the severe voltage swings that occur during switching transitions and drives the gate of the GaN FET or N-channel MOSFET above the positive power rail, resulting in high circuit performance.

[0054] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0055] Figure 1 A schematic diagram of a bootstrap capacitor floating half-bridge gate drive circuit provided by the present invention.

[0056] Figure 2 A schematic diagram of a high-voltage bootstrap capacitor floating half-bridge gate drive circuit provided by the present invention.

[0057] Figure 3 This is a schematic diagram of a voltage level waveform provided by the present invention.

[0058] The accompanying drawings have illustrated specific embodiments of the invention, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the invention in any way, but rather to illustrate the concept of the invention to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0059] A switching power supply maintains a stable output voltage by controlling the on- and off-time ratio of a switching transistor, offering advantages such as small size and high efficiency. Most power supply applications use GaN FETs or N-channel MOSFETs as the main power source due to their low cost, faster speed, and lower on-resistance. Using GaN FETs or N-channel MOSFETs as high-side switches requires a gate drive circuit referenced to the source of the GaN FET or N-channel MOSFET. The driver must be able to withstand the dramatic voltage swings during switching and drive the gate of the GaN FET or N-channel MOSFET above the positive power rail. In most cases, the gate drive voltage must be higher than the highest DC potential supplied in the circuit. All these challenges make high-side driver design a highly challenging task.

[0060] When the voltage level of the gate drive circuit is lower than the voltage level of the GaN FET or N-channel MOSFET power transistor, the principle of bootstrap gate drive technology is considered. This method utilizes a gate drive and an accompanying bias circuit, both of which use the source of the master GaN FET or N-channel MOSFET transistor as a reference. Both the driver and the bias circuit oscillate between the two input voltage rails and the device source.

[0061] Figure 1 This is a schematic diagram of a bootstrap capacitor floating half-bridge gate drive circuit provided by the present invention. This structure is a typical bootstrap capacitor floating half-bridge gate drive circuit. In the diagram, D1 is a bootstrap diode, C1 is a bootstrap capacitor, C2 is the output capacitor, HS is the high-side gate drive, LS is the low-side gate drive, L is an inductor, VIN is the main power supply of the switching power supply, VDD is the power supply for the gate drive, and GND is ground.

[0062] like Figure 1 As shown, when the control logic is high, the bootstrap capacitor C1 charges through the bootstrap diode D1. The capacitor voltage drop across switch Q1 causes the source of Q1 to rise to VIN, and diode D1 is reverse biased. The voltage at the positive terminal of bootstrap capacitor C1 thus rises above VIN to provide the additional voltage required to keep Q1 on.

[0063] However, as Figure 1 The driver and floating bias shown are implemented using low-voltage circuit elements. The driver and ground reference control signals are connected by a level shifting circuit, which must withstand the high voltage difference between the floating high side and the ground reference low side circuits and the large capacitor switching current, resulting in poor circuit performance.

[0064] Figure 2 A schematic diagram of a high-voltage bootstrap capacitor floating half-bridge gate drive circuit provided by the present invention is shown below. Figure 2As shown, the circuit includes: a high-voltage pulse latch-up level converter 21, a high-side gate drive unit 22, and a low-side gate drive unit 23.

[0065] The first terminal of the high-voltage pulse latch-up level converter 21 is connected to the power supply DVDD, the second terminal is the control signal input terminal (optional, the control signal is a PWM signal), the third terminal is connected to ground GND, and the fourth, fifth, and sixth terminals are connected to capacitor C. BOOT The second and seventh terminals are connected to the first terminal of the high-side gate drive unit, and the eighth and ninth terminals are connected to the second terminal of diode D1. The first terminal of diode D1 is connected to the power supply DVDD. Capacitor C BOOT The first end is connected to the second end of diode D1.

[0066] The second and third terminals of the high-side gate drive unit 22 are connected to the first terminal of inductor L1, the fourth terminal is connected to the gate of switch SW1, and the fifth and sixth terminals are connected to the second terminal of diode D1. The second terminal of inductor L1 is the voltage output terminal, and the second terminal of inductor L1 is connected to the output capacitor C. out The first terminal. Output capacitor C out The second end is connected to ground (GND).

[0067] The first terminal of the low-side gate drive unit 23 is the control signal input terminal, the second and third terminals are connected to ground GND, the fourth terminal is connected to the gate of the switching transistor SW2, and the fifth and sixth terminals are connected to the power supply DVDD.

[0068] The source of switch SW1 is connected to the drain of switch SW2, the drain of switch SW1 is connected to the input voltage VIN, and the source of switch SW2 is connected to ground GND.

[0069] The high-voltage pulse latch-up level converter is used to convert the input level of the second terminal of the high-voltage pulse latch-up level converter to a high-low level, so that the output of the seventh terminal of the high-voltage pulse latch-up level converter is a logic opposite to the input level. When the seventh terminal of the high-voltage pulse latch-up level converter outputs a high level, the voltage value is DVDD+VIN, and when the seventh terminal of the high-voltage pulse latch-up level converter outputs a low level, the voltage value is VIN.

[0070] The high-side gate drive unit is used to output a low level at the fourth terminal when the input level of the first terminal of the high-side gate drive unit is high, so that the gate drive signal of the switch SW1 is low, and output a high level at the fourth terminal when the input level of the first terminal of the high-side gate drive unit is low, so that the gate drive signal of the switch SW1 is high.

[0071] The low-side gate drive unit is used to output a low level at the fourth terminal when the input level of the first terminal of the low-side gate drive unit is high, so that the gate drive signal of the switch SW2 is low, and output a high level at the fourth terminal when the input level of the first terminal of the low-side gate drive unit is low, so that the gate drive signal of the switch SW2 is high.

[0072] Optional, capacitor C BOOT It is a polarized capacitor, and the capacitance C is... BOOT The first terminal is the positive terminal, and the capacitor C BOOT The second end is the negative electrode.

[0073] Optional, output capacitor C out It is a polarized capacitor, and the capacitance C is... out The first terminal is the positive terminal, and the capacitor C out The second end is the negative electrode.

[0074] See Figure 2 When switch SW1 is off and switch SW2 is on, the bootstrap capacitor C BOOT The second terminal is pulled down to ground. Bootstrap capacitor C BOOT The bootstrap capacitor C is charged through diode D1, which is connected to the internal digital power supply (DVDD power supply). When switch SW1 is on and switch SW2 is off, the bootstrap capacitor C... BOOT The second terminal is pulled up to the switching transistor power supply voltage VIN. Then, diode D1 is reverse biased and blocks the rail voltage of the internal digital power supply DVDD because the bootstrap capacitor C is at this time. BOOT Since the first terminal of the capacitor is left floating and the voltage across the capacitor cannot change abruptly, the bootstrap capacitor C... BOOT The voltage value at the first terminal is DVDD+VIN.

[0075] The high-voltage bootstrap capacitor floating half-bridge gate drive circuit provided by this invention is applicable to various high-voltage BCD (Bipolar-CMOS-DMOS) processes, exhibiting better applicability. By controlling the turn-off of the CMOS transistor through a pulse-locked level converter, the high-side level transition of the floating half-bridge is achieved. This not only eliminates quiescent current but also significantly reduces power consumption and improves the efficiency of the switching power supply. It can withstand the severe voltage swings that occur during switching transitions and drives the gate of the GaN FET or N-channel MOSFET above the positive power rail, resulting in high circuit performance.

[0076] Optionally, the high-voltage pulse latch-up level converter includes: an inverter INV1, high-voltage PMOS transistors DPMOS1, DPMOS2, DPMOS3, and DPMOS4, low-voltage NMOS transistors MN1 and MN2, and high-voltage NMOS transistors DNMOS1 and DNMOS2.

[0077] The positive terminal of inverter INV1 is the first terminal of high voltage pulse latch-up level converter 21, which is connected to power supply DVDD. The negative terminal is the third terminal of high voltage pulse latch-up level converter 21, which is connected to ground GND. The input terminal is the second terminal of high voltage pulse latch-up level converter 21, which is connected to control signal PWM, the first terminal of low-side gate drive unit 23, and the gate of high voltage NMOS transistor DNMOS2. The output terminal is connected to the gate of high voltage NMOS transistor DNMOS1.

[0078] The drain of high-voltage NMOS transistor DNMOS1 is connected to the drain of high-voltage PMOS transistor DPMOS1 and the drain of high-voltage PMOS transistor DPMOS3. The source of high-voltage NMOS transistor DNMOS1 is connected to the negative terminal of inverter INV1, the source of high-voltage NMOS transistor DNMOS2, the second and third terminals of low-side gate drive unit 23, the source of switch transistor SW2, and the output capacitor C. out The second end is connected to ground (GND).

[0079] The drain of the high-voltage NMOS transistor DNMOS2 is connected to the drain of the high-voltage PMOS transistor DPMOS2 and the drain of the high-voltage PMOS transistor DPMOS4.

[0080] The source of the high-voltage PMOS transistor DPMOS1 is connected to the second terminal of the diode D1. The gate of the high-voltage PMOS transistor DPMOS1 is connected to the gate of the low-voltage NMOS transistor MN1, the drain of the low-voltage NMOS transistor MN2, the source of the high-voltage PMOS transistor DPMOS4, and the first terminal of the high-side gate driving unit 22.

[0081] The source of the high-voltage PMOS transistor DPMOS2 is connected to the second terminal of diode D1, and the gate of the high-voltage PMOS transistor DPMOS2 is connected to the gate of the low-voltage NMOS transistor MN2, the drain of the low-voltage NMOS transistor MN1, and the source of the high-voltage PMOS transistor DPMOS3.

[0082] The gate and capacitor C of the high-voltage PMOS transistor DPMOS3 BOOT The second terminal, the source of low-voltage NMOS transistor MN1, the source of low-voltage NMOS transistor MN2, the gate of high-voltage PMOS transistor DPMOS4, the source of switching transistor SW1, and the first terminal of inductor L1 are connected.

[0083] See Figure 2When the control signal at the input of inverter INV1 is high (potential voltage equal to DVDD), high-voltage NMOS transistor DNMOS1 is off, high-voltage NMOS transistor DNMOS2 is on, high-voltage PMOS transistor DPMOS1 is on, high-voltage PMOS transistor DPMOS2 is off, high-voltage PMOS transistor DPMOS3 is on, high-voltage PMOS transistor DPMOS4 is off, low-voltage NMOS transistor MN1 is off, and low-voltage NMOS transistor MN2 is on. At this time, the output of the pulse latch-up level converter is low (potential voltage equal to SW).

[0084] When the input of inverter INV1 is at a low level (potential voltage equal to GND), high-voltage NMOS transistor DNMOS1 is turned on, high-voltage NMOS transistor DNMOS2 is turned off, high-voltage PMOS transistor DPMOS1 is turned off, high-voltage PMOS transistor DPMOS2 is turned on, high-voltage PMOS transistor DPMOS3 is turned off, high-voltage PMOS transistor DPMOS4 is turned on, low-voltage NMOS transistor MN1 is turned on, and low-voltage NMOS transistor MN2 is turned off. At this time, the pulse latch-up level converter output is high (potential voltage equal to BOOST).

[0085] This circuit enables floating-ground level digital logic conversion without static current, greatly reducing power consumption. It uses fewer components to achieve floating-ground level digital logic conversion, improving the integration of high-voltage BCD process high-voltage half-bridge gate driver chips.

[0086] Optionally, the high-side gate drive unit 22 includes: inverters INV2, INV3, INV4, INV5, INV6, and INV7; NAND gates NAND1 and NAND2; low-voltage NMOS transistor MN3; and low-voltage PMOS transistor MP1.

[0087] The input terminal of inverter INV2 is the first terminal of the high-side gate drive unit 22, and the output terminal of inverter INV2 is connected to the input terminal of inverter INV6 and the first input terminal of NAND gate NAND1.

[0088] The output of inverter INV6 is connected to the second input of NAND gate NAND2.

[0089] The first input terminal of the NAND gate NAND2 is connected to the output terminal of the inverter INV5 shown and the gate of the low-voltage PMOS transistor MP1. The output terminal of the NAND gate NAND2 is connected to the input terminal of the inverter INV7.

[0090] The output of inverter INV7 is connected to the input of inverter INV3 and the gate of low-voltage NMOS transistor MN3.

[0091] The source of NMOS transistor MN3 is the third terminal of the high-side gate driving unit 22, and the drain of low-voltage NMOS transistor MN3 is the fourth terminal of the high-side gate driving unit 22. The drain of NMOS transistor MN3 is connected to the drain of low-voltage PMOS transistor MP1 and the gate of switching transistor SW1.

[0092] The source of the low-voltage PMOS transistor MP1 is the fifth terminal of the high-side gate drive unit 22.

[0093] The output of inverter INV4 is connected to the input of inverter INV5, and the input of inverter INV4 is connected to the output of NAND gate NAND1.

[0094] The second input of the NOT gate NAND1 is connected to the output of the inverter INV3.

[0095] The second terminal of the high-side gate driving unit 22 is the ground terminal of all logic gates in the high-side gate driving unit 22.

[0096] The sixth terminal of the high-side gate driving unit 22 is the power supply terminal for all logic gates in the high-side gate driving unit 22.

[0097] See Figure 2 When the input of inverter INV2 is at a high level (potential voltage equal to BOOST), it is inverted by inverter INV2 to a low level (potential voltage equal to SW). According to the logic of NAND gates, the output of NAND gate NAND1 is at a high level, and the gate drive signal of low-voltage PMOS transistor MP1 is at a high level, so low-voltage PMOS transistor MP1 is turned off. At this time, the first and second input signals of NAND gate NAND2 are both at high levels, so the output signal of NAND gate NAND2 is at a low level. Therefore, the gate drive signal of low-voltage NMOS transistor MN3 is at a high level, and low-voltage NMOS transistor MN3 is turned on. That is, the gate drive signal of switching transistor SW1 is at a low level.

[0098] When the input of inverter INV2 is a low-level transmission signal (voltage equal to SW), it is inverted by inverter INV2 to a high-level signal (voltage equal to BOOST). According to the logic of NAND gates, the output transmission signal of NAND gate NAND2 is high, and the gate drive signal of low-voltage NMOS transistor MN3 is low, so low-voltage NMOS transistor MN3 is off. At this time, the first and second input signals of NAND gate NAND1 are both high, so the output signal of NAND gate NAND1 is low, and the gate drive signal of low-voltage PMOS transistor MP1 is low, so low-voltage PMOS transistor MP1 is on. That is, the gate drive signal of switching transistor SW1 is high.

[0099] This circuit structure ensures that the low-voltage PMOS transistor MP1 and the low-voltage NMOS transistor MN3 will not be turned on simultaneously, preventing the chip from burning out; it also enables digital logic conversion between floating power supply and ground, and can turn the switching transistor SW1 on and off without static power consumption current.

[0100] Optionally, the low-side gate drive unit 23 includes: inverters INV8, INV9, INV10, INV11, INV12, and INV13; NAND gates NAND3 and NAND4; low-voltage NMOS transistor MN4; and low-voltage PMOS transistor MP2.

[0101] The input terminal of inverter INV11 is the first terminal of low-side gate drive unit 23, and the output terminal of inverter INV11 is connected to the input terminal of inverter INV12 and the first input terminal of NAND gate NAND3.

[0102] The output of inverter INV12 is connected to the second input of NAND gate NAND4.

[0103] The first input terminal of NAND gate NAND4 is connected to the output terminal of inverter INV10 and the gate of low-voltage PMOS transistor MP2, and the output terminal of NAND gate NAND4 is connected to the input terminal of inverter INV13.

[0104] The output of inverter INV13 is connected to the input of inverter INV8 and the gate of low-voltage NMOS transistor MN4.

[0105] The source of the low-voltage NMOS transistor MN4 is the third terminal of the low-side gate drive unit 23, and the drain of the low-voltage NMOS transistor MN4 is the fourth terminal of the low-side gate drive unit 23. The drain of the low-voltage NMOS transistor MN4 is connected to the drain of the low-voltage PMOS transistor MP2 and the gate of the switching transistor SW2.

[0106] The source of the low-voltage PMOS transistor MP2 is the fifth terminal of the low-side gate drive unit 23.

[0107] The output of inverter INV9 is connected to the input of inverter INV8, and the input of inverter INV9 is connected to the output of NAND gate NAND3.

[0108] The second input of the NOT gate NAND3 is connected to the output of the inverter INV8.

[0109] The second terminal of the low-side gate driving unit 23 is the ground terminal of all logic gates in the high-side gate driving unit 22.

[0110] The sixth terminal of the low-side gate driving unit 23 is the power supply terminal for all logic gates in the high-side gate driving unit 22.

[0111] See Figure 2When the input of inverter INV11 is a high-level transmission signal (potential voltage equal to BOOST), it is inverted by INV11 to a low-level signal (potential voltage equal to SW). According to the logic of NAND gates, the output transmission signal of NAND gate NAND3 is high, and the gate drive signal of low-voltage PMOS transistor MP2 is high, so low-voltage PMOS transistor MP2 is turned off. At this time, the first and second input signals of NAND gate NAND4 are both high, so the output signal of NAND gate NAND4 is low, and the gate drive signal of low-voltage NMOS transistor MN4 is high, so low-voltage NMOS transistor MN4 is turned on. That is, the gate drive signal of switching transistor SW2 is low.

[0112] When the input of inverter INV11 is a low-level transmission signal (potential voltage equal to SW), it is inverted by inverter INV11 to a high-level signal (potential voltage equal to BOOST). According to the logic of NAND gates, the output transmission signal of NAND gate NAND4 is high, and the gate drive signal of low-voltage NMOS transistor MN4 is low, so low-voltage NMOS transistor MN4 is turned off. At this time, the first and second input signals of NAND gate NAND3 are both high, so the output signal of NAND gate NAND3 is low, and the gate drive signal of low-voltage PMOS transistor MP2 is low, so low-voltage PMOS transistor MP2 is turned on. That is, the gate drive signal of switching transistor SW2 is high.

[0113] This circuit structure ensures that the low-voltage PMOS transistor MP2 and the low-voltage NMOS transistor MN4 will not be turned on simultaneously, preventing the chip from burning out; and it can turn the switching transistor SW2 on and off without static power consumption current.

[0114] Optionally, diode D1 can be multiple diodes connected in series.

[0115] Optionally, the switching transistor SW1 is a GaN FET device or an N-channel MOSFET.

[0116] Optionally, the switching transistor SW2 can be a GaN FET device or an N-channel MOSFET.

[0117] The circuit provided by this invention will be described below with reference to waveform diagrams. Figure 3 A schematic diagram of a level waveform provided by the present invention is shown below. Figure 3 and Figure 2Assume the drain transmission signal of high-voltage NMOS transistor DNMOS1 is CLK1, the drain transmission signal of high-voltage NMOS transistor DNMOS2 is CLK2, the gate transmission signal of high-voltage PMOS transistor DPMOS1 is CLK3, the gate transmission signal of high-voltage PMOS transistor DPMOS2 is CLK4, the gate transmission signal of switching transistor SW1 is CLK5, the voltage at the first terminal of the bootstrap capacitor is BOOST (internal floating power supply signal), and the voltage at the second terminal of the bootstrap capacitor is SW (internal floating ground signal). The references for the high and low bits of signals CLK1 and CLK2 are the voltage BOOST (internal floating power supply signal) and GND; the references for the high and low bits of signals CLK3, CLK4, and CLK5 are the voltage BOOST (internal floating power supply signal) and SW (internal floating ground signal); and the references for the high and low bits of signal CLK6 are the internal digital power supply voltage DVDD and GND. t1 is the time of the first rising edge of the PWM input signal within a complete cycle, t2 is the time of the first falling edge of the PWM input signal within a complete cycle, and t3 is the time of the second rising edge of the PWM input signal within a complete cycle.

[0118] At times t1 to t2, the input PWM signal is the high level of the internal digital power supply DVDD. The high-voltage NMOS transistor DNMOS1 is off, the high-voltage NMOS transistor DNMOS2 is on, the high-voltage PMOS transistor DPMOS1 is on, the high-voltage PMOS transistor DPMOS2 is off, the high-voltage PMOS transistor DPMOS3 is on, the high-voltage PMOS transistor DPMOS4 is off, the low-voltage NMOS transistor MN1 is off, and the low-voltage NMOS transistor MN2 is on.

[0119] At this time, the voltage BOOST is at the DVDD+VIN potential; the voltage SW is at the VIN potential; the transmission signal CLK1 is high at DVDD+VIN; the transmission signal CLK2 is low at GND; the transmission signal CLK3 is low at VIN; the transmission signal CLK4 is high at DVDD+VIN; the transmission signal CLK5 is high at DVDD+VIN; and the transmission signal CLK6 is low at GND. This causes switch SW1 to be fully turned on and switch SW2 to be fully turned off.

[0120] At times t2 to t3, the input PWM signal is the low level of the internal digital power supply DVDD. The high-voltage NMOS transistor DNMOS1 is turned on, the high-voltage NMOS transistor DNMOS2 is turned off, the high-voltage PMOS transistor DPMOS1 is turned off, the high-voltage PMOS transistor DPMOS2 is turned on, the high-voltage PMOS transistor DPMOS3 is turned off, the high-voltage PMOS transistor DPMOS4 is turned on, the low-voltage NMOS transistor MN1 is turned on, and the low-voltage NMOS transistor MN2 is turned off.

[0121] At this time, BOOST voltage is at DVDD potential; SW voltage is at GND potential; transmission signal CLK1 is GND low; transmission signal CLK2 is DVDD high; transmission signal CLK3 is DVDD high; transmission signal CLK4 is GND low; transmission signal CLK5 is GND low; and transmission signal CLK6 is DVDD high. This completely turns off switch SW1 and fully turns on switch SW2.

[0122] The present invention also provides an electronic device, comprising: any of the high-voltage bootstrap capacitor floating half-bridge gate drive circuits provided in the above embodiments.

[0123] In this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0124] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0125] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0126] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus (devices), or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects, all of which are collectively referred to herein as "modules" or "systems." Furthermore, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The computer program may be stored / distributed in a suitable medium, provided with or as part of other hardware, or may take other distribution forms, such as via the Internet or other wired or wireless telecommunications systems.

[0127] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing device, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0128] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0129] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0130] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-voltage bootstrap capacitor-type floating half-bridge gate drive circuit, characterized in that, include: High-voltage pulse latch-up level converter, high-side gate drive unit, and low-side gate drive unit; The first terminal of the high-voltage pulse latch-up level converter is connected to the power supply DVDD, the second terminal is the control signal input terminal, the third terminal is connected to ground GND, the fourth, fifth and sixth terminals are connected to the second terminal of the capacitor CBOOT, the seventh terminal is connected to the first terminal of the high-side gate drive unit, and the eighth and ninth terminals are connected to the second terminal of the diode D1. The first terminal of the diode D1 is connected to the power supply DVDD, and the first terminal of the capacitor CBOOT is connected to the second terminal of the diode D1. The second and third terminals of the high-side gate driving unit are connected to the first terminal of inductor L1, the fourth terminal is connected to the gate of switch SW1, the fifth and sixth terminals are connected to the second terminal of diode D1, the second terminal of inductor L1 is the voltage output terminal, the second terminal of inductor L1 is connected to the first terminal of output capacitor Cout, and the second terminal of output capacitor Cout is connected to ground GND. The first terminal of the low-side gate drive unit is a control signal input terminal, the second and third terminals are connected to ground GND, the fourth terminal is connected to the gate of the switching transistor SW2, and the fifth and sixth terminals are connected to the power supply DVDD. The source of the switching transistor SW1 is connected to the drain of the switching transistor SW2, the drain of the switching transistor SW1 is connected to the input voltage VIN, and the source of the switching transistor SW2 is connected to ground GND. The high-side gate driving unit is configured to output a low level at its fourth terminal when the input level at the first terminal of the high-side gate driving unit is high, so that the gate driving signal of the switching transistor SW1 is low, and output a high level at its fourth terminal when the input level at the first terminal of the high-side gate driving unit is low, so that the gate driving signal of the switching transistor SW1 is high. The low-side gate driving unit is configured to output a low level at its fourth terminal when the input level at the first terminal of the low-side gate driving unit is high, so that the gate driving signal of the switching transistor SW2 is low, and output a high level at its fourth terminal when the input level at the first terminal of the low-side gate driving unit is low, so that the gate driving signal of the switching transistor SW2 is high. The high-voltage pulse latch-up level converter includes an inverter INV1, high-voltage PMOS transistors DPMOS1, DPMOS2, DPMOS3, and DPMOS4, low-voltage NMOS transistors MN1 and MN2, and high-voltage NMOS transistors DNMOS1 and DNMOS2. The positive terminal of the inverter INV1 is the first terminal of the high-voltage pulse latch-up level converter, which is connected to the power supply DVDD. The negative terminal is the third terminal of the high-voltage pulse latch-up level converter, which is connected to ground GND. The input terminal is the second terminal of the high-voltage pulse latch-up level converter, which is connected to the control signal PWM, the first terminal of the low-side gate drive unit, and the gate of the high-voltage NMOS transistor DNMOS2. The output terminal is connected to the gate of the high-voltage NMOS transistor DNMOS1. The drain of the high-voltage NMOS transistor DNMOS1 is connected to the drain of the high-voltage PMOS transistor DPMOS1 and the drain of the high-voltage PMOS transistor DPMOS3. The source of the high-voltage NMOS transistor DNMOS1 is connected to the negative terminal of the inverter INV1, the source of the high-voltage NMOS transistor DNMOS2, the second and third terminals of the low-side gate drive unit, the source of the switch transistor SW1, the second terminal of the output capacitor Cout, and the ground GND. The drain of the high-voltage NMOS transistor DNMOS2 is connected to the drain of the high-voltage PMOS transistor DPMOS2 and the drain of the high-voltage PMOS transistor DPMOS4. The source of the high-voltage PMOS transistor DPMOS1 is connected to the second terminal of the diode D1, and the gate of the high-voltage PMOS transistor DPMOS1 is connected to the gate of the low-voltage NMOS transistor MN1, the drain of the low-voltage NMOS transistor MN2, the source of the high-voltage PMOS transistor DPMOS4, and the first terminal of the high-side gate driving unit. The source of the high-voltage PMOS transistor DPMOS2 is connected to the second terminal of the diode D1, and the gate of the high-voltage PMOS transistor DPMOS2 is connected to the gate of the low-voltage NMOS transistor MN2, the drain of the low-voltage NMOS transistor MN1, and the source of the high-voltage PMOS transistor DPMOS3. The gate of the high-voltage PMOS transistor DPMOS3 is connected to the second terminal of the capacitor CBOOT, the source of the low-voltage NMOS transistor MN1, the source of the low-voltage NMOS transistor MN2, the gate of the high-voltage PMOS transistor DPMOS4, the source of the switch transistor SW1, and the first terminal of the inductor L1.

2. The circuit according to claim 1, characterized in that, The high-side gate driving unit includes: Inverters INV2, INV3, INV4, INV5, INV6, INV7; NAND gates NAND1, NAND2; low-voltage NMOS transistor MN3; low-voltage PMOS transistor MP1. The input terminal of the inverter INV2 is the first terminal of the high-side gate driving unit, and the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV6 and the first input terminal of the NAND gate NAND1. The output of the inverter INV6 is connected to the second input of the NAND gate NAND2; The first input terminal of the NAND gate NAND2 is connected to the output terminal of the inverter INV5 and the gate of the low-voltage PMOS transistor MP1, and the output terminal of the NAND gate NAND2 is connected to the input terminal of the inverter INV7. The output terminal of inverter INV7 is connected to the input terminal of inverter INV3 and the gate of low-voltage NMOS transistor MN3; The source of the NMOS transistor MN3 is the third terminal of the high-side gate driving unit, and the drain of the low-voltage NMOS transistor MN3 is the fourth terminal of the high-side gate driving unit. The drain of the NMOS transistor MN3 is connected to the drain of the low-voltage PMOS transistor MP1 and the gate of the switching transistor SW1. The source of the low-voltage PMOS transistor MP1 is the fifth terminal of the high-side gate drive unit; The output terminal of inverter INV4 is connected to the input terminal of inverter INV5, and the input terminal of inverter INV4 is connected to the output terminal of NAND gate NAND1. The second input terminal of the NAND gate NAND1 is connected to the output terminal of the inverter INV3; The second end of the high-side gate driving unit is the ground terminal of all logic gates in the high-side gate driving unit; The sixth terminal of the high-side gate driving unit is the power supply terminal for all logic gates in the high-side gate driving unit.

3. The circuit according to claim 2, characterized in that, The low-side gate driving unit includes: Inverters INV8, INV9, INV10, INV11, INV12, INV13; NAND gates NAND3, NAND4; low-voltage NMOS transistor MN4; low-voltage PMOS transistor MP2. The input terminal of the inverter INV11 is the first terminal of the low-side gate driving unit, and the output terminal of the inverter INV11 is connected to the input terminal of the inverter INV12 and the first input terminal of the NAND gate NAND3. The output of the inverter INV12 is connected to the second input of the NAND gate NAND4; The first input terminal of the NAND gate NAND4 is connected to the output terminal of the inverter INV10 and the gate of the low-voltage PMOS transistor MP2, and the output terminal of the NAND gate NAND4 is connected to the input terminal of the inverter INV13. The output terminal of inverter INV13 is connected to the input terminal of inverter INV8 and the gate of low-voltage NMOS transistor MN4; The source of the low-voltage NMOS transistor MN4 is the third terminal of the low-side gate driving unit, the drain of the low-voltage NMOS transistor MN4 is the fourth terminal of the low-side gate driving unit, and the drain of the low-voltage NMOS transistor MN4 is connected to the drain of the low-voltage PMOS transistor MP2 and the gate of the switching transistor SW2. The source of the low-voltage PMOS transistor MP2 is the fifth terminal of the low-side gate drive unit; The output terminal of inverter INV9 is connected to the input terminal of inverter INV10, and the input terminal of inverter INV9 is connected to the output terminal of NAND gate NAND3. The second input terminal of the NAND gate NAND3 is connected to the output terminal of the inverter INV8; The second end of the low-side gate driving unit is the ground terminal of all logic gates in the low-side gate driving unit; The sixth terminal of the low-side gate driving unit is the power supply terminal for all logic gates in the low-side gate driving unit.

4. The circuit according to claim 2, characterized in that, The diode D1 consists of multiple diodes connected in series.

5. The circuit according to claim 1 or 4, characterized in that, The switching transistor SW1 is a GaNFET device or an N-channel MOSFET.

6. The circuit according to claim 5, characterized in that, The switching transistor SW2 is a GaNFET device or an N-channel MOSFET.

7. The circuit according to claim 1 or 4, characterized in that, The capacitor CBOOT is a polarized capacitor, with its first terminal being positive and its second terminal being negative.

8. The circuit according to claim 7, characterized in that, The output capacitor Cout is a polarized capacitor, with the first terminal of Cout being positive and the second terminal being negative.

9. An electronic device, characterized in that, include: The high-voltage bootstrap capacitor floating half-bridge gate drive circuit as described in any one of claims 1-8.

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