Circuit device, physical quantity measuring device, electronic device, and mobile body

Abstract

Circuit device, physical quantity measuring device, electronic device, and mobile body. The circuit device includes code data generating circuit that generates code data, and A / D conversion circuit that performs code shift based on the code data, and A / D converts an input signal, the A / D conversion circuit having a first D / A conversion circuit that D / A converts the code data and outputs a code signal, the code data generating circuit generating error data having a shaping characteristic in frequency characteristic, and converting the error data into the code data according to a conversion characteristic of the first D / A conversion circuit.

Description

[0001] This application is a divisional application of the invention patent application filed on March 8, 2018, with application number 201810191011.0 and entitled "Circuit Device, Physical Quantity Measuring Device, Electronic Device and Moving Body". Technical Field

[0002] This invention relates to circuit devices, physical quantity measuring devices, electronic devices, and moving bodies. Background Technology

[0003] Conventionally, successive approximation type A / D conversion circuits are known to perform A / D conversion on sampled input signals through successive comparison operations. In such A / D conversion circuits, methods are known to improve differential nonlinearity (DNL) and integral nonlinearity (INL) by using time-varying code data for code shifting. For example, Patent Document 1 discloses an A / D conversion circuit comprising: a comparison circuit; a successive comparison register that updates its value based on the comparison result; a first D / A conversion circuit that performs D / A conversion on the register value; a code data generation circuit that generates time-varying code data; and a second D / A conversion circuit that performs D / A conversion on the code data.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2010-263399

[0005] In the aforementioned A / D conversion circuit, if the D / A conversion circuit performing the D / A conversion on the code data exhibits nonlinearity, errors caused by this nonlinearity may enter the A / D converted data. The code data is generated, for example, through a linear feedback shift register (LFSR). Therefore, the code data becomes periodic due to the cycle of one code rotation of the LFSR. Consequently, the periodicity of the code data causes periodic errors in the A / D conversion data, potentially becoming noise components at the characteristic frequency. These noise components at the characteristic frequency may affect the Allan variance characteristics of the A / D conversion circuit (e.g., a relatively long τ characteristic). Summary of the Invention

[0006] The present invention was made to solve at least a part of the above-mentioned problems and can be implemented in the following ways or forms.

[0007] One aspect of the present invention relates to a circuit apparatus comprising: a code data generation circuit that generates time-varying code data; and a successive approximation type A / D conversion circuit that performs code shifting based on the code data to perform A / D conversion on an input signal, wherein the code data generation circuit generates error data with frequency characteristics having shaping properties and converts the error data into the code data.

[0008] According to one aspect of the present invention, error data with a frequency response exhibiting shaping characteristics is generated, the error data is converted into code data, and a code shift based on the code data is performed to conduct an A / D conversion on the input signal. Thus, the error in the A / D conversion data caused by the code shift becomes the error corresponding to the error data, and the error in the A / D conversion data exhibits shaping characteristics. Because the error in the A / D conversion data caused by the code shift has shaping characteristics, the possibility of code shift affecting the Allan variance characteristic can be reduced in successive approximation A / D conversion circuits.

[0009] Furthermore, in one embodiment of the present invention, the code data generation circuit may convert the error data into code data by converting the code data into the inverse function of the error data.

[0010] In this way, by appropriately setting the function that converts code data into error data, the frequency characteristics of the A / D conversion error can be made to be the same (or approximately the same) as the frequency characteristics of the error data. Therefore, the error of the A / D conversion data can be given an integer characteristic.

[0011] Furthermore, in one embodiment of the present invention, the A / D conversion circuit may have a code data D / A conversion circuit for performing D / A conversion on the code data, and the function is a function based on the conversion characteristics of the code data D / A conversion circuit.

[0012] The inverse function of the function that converts code data to error data is the function that converts error data back to code data. By setting the function for converting code data to error data based on the conversion characteristics of the D / A conversion circuit, the error transfer function of the system can be made approximately 1 (or a constant). Therefore, the error in the A / D conversion data caused by code shift has the same (approximately the same) frequency characteristics as the error data.

[0013] Furthermore, in one embodiment of the present invention, when the code data is CS, the specified values ​​corresponding to the range of the code data are CM and CA, the error data is ERR, and the function is f, the following condition is met:

[0014] When CS > 0, ERR = f(CS) = (CM - CS) / CA

[0015] When CS = 0, ERR = f(CS) = 0

[0016] When CS < 0, ERR = f(CS) = -(CM + CS) / CA.

[0017] By employing such a function f, it is possible to define a function f that corresponds to the nonlinearity of the D / A conversion circuit used for code data. That is, it is possible to define a function f based on the conversion characteristics of the D / A conversion circuit used for code data.

[0018] Furthermore, in one embodiment of the invention, the code data generation circuit may include: a data generation circuit; a modulation circuit that modulates the generated data from the data generation circuit to generate the error data; and a conversion circuit that converts the error data into the code data.

[0019] Thus, since the code data generation circuit includes a modulation circuit, it is able to generate error data with frequency characteristics that have shaping properties. Furthermore, since the code data generation circuit includes a conversion circuit, it is able to convert the error data into code data.

[0020] Furthermore, in one aspect of the invention, the modulation circuit may generate the error data by performing ΔΣ modulation n times (n is an integer greater than or equal to 1) on the generated data.

[0021] In this way, by performing n-fold ΔΣ modulation on the generated data, error data with shaping characteristics can be generated. Moreover, the shaping characteristics of this error data can be used to impart shaping characteristics to the errors in A / D conversion data caused by code shifting.

[0022] Furthermore, in one embodiment of the present invention, the data generation circuit may generate pseudo-random number data as the generated data.

[0023] In this way, code data is generated by modulating pseudo-random number data. Because pseudo-random number data is used, the periodicity of the code data can be reduced; however, periodicity may still remain in the code data due to the operating cycle of the data generation circuit. In this embodiment, by modulating the pseudo-random number data, the impact of the periodicity of the code data on the Allan variance characteristics of the A / D conversion data can be reduced.

[0024] Furthermore, in one embodiment of the present invention, the data generation circuit may output the generated data based on the pseudo-random number data and the second random number data.

[0025] This allows for the generation of data with higher randomness. For example, if the frequency of occurrence of each code in the generated data is uneven, it can make that frequency more uniform.

[0026] Furthermore, in one embodiment of the present invention, the A / D conversion circuit may include: a comparison circuit; a control circuit having a successive comparison register that outputs successive comparison data, the register value of which is set according to a comparison result signal from the comparison circuit; a successive comparison data D / A conversion circuit that performs D / A conversion on the successive comparison data from the control circuit and outputs a D / A output signal corresponding to the successive comparison data; and a code data D / A conversion circuit that performs D / A conversion on the code data and outputs a code signal corresponding to the code data. The comparison circuit performs processing by comparing a sampled signal of the input signal and a signal obtained by adding the code signal to the D / A output signal, or by comparing a signal obtained by adding the D / A output signal and the code signal to the sampled signal. The control circuit outputs output data calculated based on the successive comparison result data of the successive comparison register and the code data as A / D conversion data of the input signal.

[0027] In cases where the successive comparison data D / A conversion circuit exhibits nonlinearity, this nonlinearity can become the cause of nonlinearity in the A / D conversion characteristics. According to one aspect of the invention, by using code data that varies over time, it is possible to change the successive comparison result data relative to the input signal. Thus, the nonlinearity is dispersed over time, improving the characteristics of the A / D conversion circuit as observed in a time-averaged manner. For example, it is possible to disperse the codes that generate missing codes over time.

[0028] Furthermore, in one embodiment of the invention, it may include: a driving circuit that drives a physical quantity transducer; and a detection circuit that receives a detection signal from the physical quantity transducer and detects a physical quantity signal corresponding to the physical quantity, the detection circuit having an A / D conversion circuit for performing A / D conversion on the input signal based on the detection signal.

[0029] This enables code shifting based on code data to perform A / D conversion on an input signal based on a detection signal. The code data is generated from error data with shaping characteristics. Consequently, by improving the Allan variance characteristics of the A / D conversion circuit, physical quantity signals can be detected with high precision.

[0030] Furthermore, other aspects of the present invention relate to a physical quantity measuring device that includes the aforementioned circuitry and the physical quantity transducer.

[0031] Furthermore, another aspect of the present invention relates to electronic devices including any of the circuit devices described above.

[0032] Furthermore, another aspect of the present invention relates to a mobile body comprising the circuitry described in any of the foregoing. Attached Figure Description

[0033] Figure 1 This is a comparative example of a circuit device.

[0034] Figure 2 This is an example of the integral nonlinearity characteristic of D / A conversion circuits used for code data.

[0035] Figure 3 This is a diagram illustrating the time variation of the error in A / D conversion data caused by code shift.

[0036] Figure 4 This is an example of the frequency characteristics of the error in A / D conversion data caused by code shift in the comparative example.

[0037] Figure 5 This is an example of the Allen variance characteristics of the A / D converted data in the comparative example.

[0038] Figure 6 This is an example of the structure of the circuit device in this embodiment.

[0039] Figure 7 This is an explanatory diagram illustrating the principle of the method in this embodiment.

[0040] Figure 8 This is a characteristic example of a function that converts code data into error data.

[0041] Figure 9 This is a detailed structural example of a data generation circuit.

[0042] Figure 10 This is a detailed structural example of a modulation circuit.

[0043] Figure 11 This is an example of the frequency characteristics of the error in A / D conversion data caused by code shift in this embodiment.

[0044] Figure 12 These are comparative examples and examples of the Allan variance characteristics of A / D converted data in this embodiment.

[0045] Figure 13 It is a variation of the data generation circuit.

[0046] Figure 14 This diagram illustrates the operation of a modified example of the data generation circuit.

[0047] Figure 15 This is an example of the structure of an A / D conversion circuit.

[0048] Figure 16This is the first detailed structural example of an A / D conversion circuit.

[0049] Figure 17 This diagram illustrates the operation of the first detailed structural example of an A / D conversion circuit.

[0050] Figure 18 This is the second detailed structural example of an A / D conversion circuit.

[0051] Figure 19 This is an example of the structure of a physical quantity measuring device.

[0052] Figure 20 It is an example of a moving object.

[0053] Figure 21 These are examples of electronic devices.

[0054] Label Explanation

[0055] 10: Comparator circuit; 20: Control circuit; 30: S / H circuit; 32: Amplifier circuit; 40: Gain control circuit; 41: First capacitor array section; 42: Second capacitor array section; 43: Third capacitor array section; 50: Drive signal output circuit; 51: First switch array section; 52: Second switch array section; 53: Third switch array section; 54: Synchronization signal output circuit; 60: Detection circuit; 64: Amplifier circuit; 70: Drive circuit 81: Synchronous Detection Circuit; 100: Circuit Device; 110: Code Data Generation Circuit; 112: Data Generation Circuit; 114: Modulation Circuit; 116: Conversion Circuit; 120: A / D Conversion Circuit; 121: Code Data D / A Conversion Circuit; 122: Successive Comparison Circuit; 123: Subtraction Circuit; 131: Addition Processing Unit; 132: Subtraction Processing Unit; 133: Delay Unit; 141: Linear Feedback Shift Register; 142: Output Circuit 150: Processing circuit; 190: Circuit device; 191: Linear feedback shift register; 192: A / D conversion circuit; 193: Code data D / A conversion circuit; 206: Automobile (moving body); 207: Vehicle body; 208: Vehicle body attitude control device; 209: Wheel; 400: Physical quantity measuring device; 410: Oscillator (physical quantity transducer); 610: Digital still camera (electronic device); CS: Code data; DAC1: First D / A conversion circuit (successive comparison data D / A conversion circuit); DAC2: Second D / A conversion circuit (code data D / A conversion circuit); DAR: Generated data; DOUT: A / D conversion data; ERR: Error data; RDA: Successive comparison data; RMD1: Pseudo-random number data; RMD2: Second random number data; SAR: Successive comparison register; SIN: Sampled signal; VIN: Input signal; f: Function; f -1 Inverse function. Detailed Implementation

[0056] The preferred embodiments of the present invention will now be described in detail. Furthermore, the embodiments described below are not intended to unduly limit the scope of the invention as defined in the claims, and not all structures described in these embodiments are essential solutions to the present invention.

[0057] 1. Comparative Example

[0058] Figure 1 This is a comparative example of a circuit device. The circuit device 190 includes a linear feedback shift register 191 (code data generation circuit) and an A / D conversion circuit 192.

[0059] Linear feedback shift register 191 generates, for example, pseudo-random number data and outputs the generated data as code data CDA. A / D conversion circuit 192 is a successive approximation type A / D conversion circuit that performs A / D conversion on the input signal VIN (input voltage) and outputs the result as A / D conversion data DOUT. A / D conversion circuit 192 includes a code data D / A conversion circuit 193 that performs D / A conversion on the code data CDA. Furthermore, the output signal of the code data D / A conversion circuit is used to shift (code shift) the A / D conversion value relative to the input signal VIN by an amount of code data CDA. The code data CDA is subtracted from the obtained A / D conversion value, and the result is output as A / D conversion data DOUT.

[0060] In such an A / D conversion circuit, the output signal of the code data D / A conversion circuit 193 is non-linear relative to the code data CDA. Therefore, the output signal of the code data D / A conversion circuit 193 contains an ideal component corresponding to the code data CDA and an error component caused by the non-linearity. The ideal component is removed when the code data CDA is subtracted from the A / D conversion value, but the error component is not removed; therefore, the data corresponding to this error component remains in the A / D conversion data DOUT.

[0061] Figure 2 This is an example of the integral nonlinearity characteristic of a D / A conversion circuit for code data. The error corresponding to this integral nonlinearity manifests as the error in the A / D conversion data DOUT. Figure 2 In the example, the range of the code data CDA is -31 to +31. In the middle of this range (CDA = 0), the value of the integral nonlinearity changes significantly. This characteristic corresponds to the conversion characteristics of the D / A conversion circuit used for code data. Figure 2 This is one example.

[0062] For example in Figure 16In the A / D conversion circuit described later, DAC2 is equivalent to a D / A conversion circuit for code data. The capacitance value of the unit capacitor is set to C. The capacitors CC1, CC2, CC3, and CC4 of DAC2 have weighted capacitance values ​​of C, 2C, 4C, and 8C, respectively. Due to the deviation in the capacitance values ​​of the unit capacitors, integral nonlinearity is generated. DAC2 performs D / A conversion on 4-bit code data; therefore, the range of code data CDA is 0 to +15. CDA = 0 is "0000", and CDA = +15 is "1111". Switching elements SC1, SC2, SC3, and SC4 are controlled by the LSB, 2nd bit, 3rd bit, and MSB of the code data CDA. When a bit is "1", the reference voltage VREF is selected; when a bit is "0", the ground voltage GND is selected. Therefore, CDA = +7 is "0111", CDA = +8 is "1000", predicting that during this period, the voltage at one end of all capacitors CC1~CC4 alternates between VREF and GND, with the greatest change in the value of the integral nonlinearity. Furthermore, as... Figure 18 Therefore, when using differential D / A conversion circuits (DAC2P, DAC2N), the range of the code data CDA is -7 to +7. Figure 18 In the example, the MSB of the code data CDA is considered to be the bit obtained by inverting the sign bit in two's complement. That is, CDA = -1 is represented as "1111" in two's complement, so inverting the sign bit results in "0111". CDA = 0 is represented as "0000" in two's complement, so inverting the sign bit results in "1000". Therefore, it is predicted that between CDA = -1 ("0111") and CDA = 0 ("1000"), the voltage at one end of all capacitors CC1P~CC4P and CC1N~CC4N alternates between VREF and GND, and the value of the integral nonlinearity changes the most. Thus, the integral nonlinearity characteristic of the D / A conversion circuit for code data is predicted to be... Figure 2 That way.

[0063] Figure 3 This is a schematic diagram illustrating the time variation of the error in A / D conversion data caused by code shift. For example... Figure 1 As explained, the time-varying code data CDA is generated via a linear feedback shift register 191, such as Figure 2 As explained, the error (the value of the integral nonlinearity) varies depending on the code data CDA. Therefore, as Figure 3 As shown, the error in A / D conversion data caused by code shift varies over time.

[0064] The linear feedback shift register 191 cycles the generated code once within a specified period, thus the code data CDA exhibits periodicity. When this period is denoted as TA, the error in the A / D conversion data caused by code shifting repeats the same waveform in each TA cycle. Therefore, the error in the A / D conversion data caused by code shifting contains a periodic component.

[0065] Figure 4 This is an example of the frequency characteristics of the error in A / D conversion data caused by code shift in the comparative example. Figure 4 The simulation results are shown by performing a Fourier transform on the time variation of the error. Furthermore, Figure 5 This is an example of the Allan variance characteristic of the A / D conversion data in the comparative example. Allan variance is a metric for evaluating noise over time; it is a metric that normalizes the variance of the error generated over a time interval τ.

[0066] like Figure 4 As shown, it has the following characteristics: the frequency component of the error (signal power) is relatively flat even at low frequencies. SPA represents the approximate signal power level at low frequencies. Figure 5 In the Allan variance shown, the frequency component on the low-frequency side can affect the characteristics of long time intervals τ. For example, when a time-domain comparator is used in the comparison circuit of an A / D conversion circuit, since it is not affected by the 1 / f noise of the amplifier circuit, it is possible to obtain a characteristic where the Allan variance decreases as τ increases. However, as... Figure 5 As shown in A1, the frequency components of the error in A / D conversion data may disrupt the characteristics of Allan variance (generating peaks) in the region where τ is large.

[0067] 2. Circuit device

[0068] Figure 6 This is an example of the structure of the circuit device in this embodiment. The circuit device 100 includes a code data generation circuit 110 and an A / D conversion circuit 120. Furthermore, this embodiment is not limited to... Figure 6 The structure can be modified in various ways, such as omitting a part of its structural elements or adding other structural elements.

[0069] The code data generation circuit 110 generates time-varying code data CS. The A / D conversion circuit 120 is a successive approximation type A / D conversion circuit that performs code shifting based on the code data CS to perform A / D conversion on the input signal VIN (input voltage). Furthermore, the code data generation circuit 110 generates error data ERR with frequency-shaping characteristics and converts the error data ERR into code data CS.

[0070] Specifically, the A / D conversion circuit 120 compares the signal obtained by D / A conversion of the successive comparison data with the input signal VIN, and updates the successive comparison data according to the comparison result. By repeating this update, the input signal VIN is converted into A / D conversion data DOUT. The action of obtaining one A / D conversion data DOUT from the input signal VIN is considered as one A / D conversion action.

[0071] The code data generation circuit 110 outputs different code data CS through each A / D conversion operation. At this time, the code data generation circuit 110 converts the error data ERR into code data CS, thereby generating code data CS. The error data ERR corresponds to the error in the A / D conversion data DOUT caused by code shifting (due to the integral nonlinearity of the code data D / A conversion circuit). That is, when the A / D conversion circuit 120 performs code shifting based on the code data CS and outputs A / D conversion data DOUT, the error included in the A / D conversion data DOUT is considered to be the error data ERR. The code data generation circuit 110 generates error data ERR with shaping characteristics; therefore, the error included in the A / D conversion data DOUT also has shaping characteristics. Shaping characteristics refer to the high-pass frequency characteristics where low-frequency components (noise components) are suppressed. In this embodiment, error data ERR is generated based on generated data DAR, but the low-frequency components in the frequency characteristics of the generated data DAR are suppressed in the error data ERR.

[0072] In this way, by converting the error data ERR into code data CS, the error in the A / D conversion data DOUT caused by code shift can be made to correspond to the error data ERR. Therefore, the low-frequency components of the error in the A / D conversion data DOUT caused by code shift can be controlled by the frequency characteristics of the error data ERR. That is, by generating error data ERR with shaping characteristics in its frequency characteristics, the error in the A / D conversion data DOUT caused by code shift can be made to have shaping characteristics. Since the error has shaping characteristics, the frequency components on the low-frequency side are reduced, thus improving the Allan variance characteristics of the A / D conversion circuit 120 (e.g., characteristics over longer time intervals τ).

[0073] like Figure 6 As shown, the code data generation circuit 110 includes: a data generation circuit 112; a modulation circuit 114 that modulates the generated data DAR from the data generation circuit 112 to generate error data ERR; and a conversion circuit 116 that converts the error data ERR into code data CS.

[0074] Specifically, the data generation circuit 112 generates random time-series data (data that varies over time), i.e., generated data DAR. For example, the generated data DAR is pseudo-random number data. The modulation circuit 114 performs modulation to shape the frequency characteristics of the error data ERR. For example, the modulation can use ΔΣ modulation. The conversion circuit 116 converts the error data ERR into code data CS using a predetermined conversion function. When the A / D conversion circuit 120 is considered to be converting the code data CS into the A / D converted data DOUT, the inverse function of its conversion function (model) is the predetermined conversion function.

[0075] Thus, by providing a modulation circuit 114 in the code data generation circuit 110, error data ERR with frequency-shaping characteristics can be generated. Furthermore, by providing a conversion circuit 116 in the code data generation circuit 110, the error data ERR can be converted into code data CS.

[0076] Figure 7 This is an explanatory diagram illustrating the principle of the method in this embodiment. (For example...) Figure 7 As shown, the A / D conversion circuit 120 includes a D / A conversion circuit 121 for code data, a successive comparison circuit 122, and a subtraction circuit 123. For example, in Figure 15 In the A / D conversion circuit, DAC2 corresponds to the code data via D / A conversion circuit 121, while S / H circuit 30, DAC1, comparator circuit 10, control circuit 20 correspond to successive comparator circuit 122 and subtraction circuit 123. Additionally, in Figure 7 In this circuit, assuming the input signal is VIN=0, the successive comparison circuit 122 has ideal A / D conversion characteristics (no differential nonlinearity or integral nonlinearity).

[0077] The conversion circuit 116 uses the function f(CS) = the inverse function f of ERR to represent the relationship between the code data CS and the error data ERR. -1 The error data ERR is converted into code data CS by the D / A conversion circuit 121. The code data CS is then converted into a D / A signal V(CS) + e(CS). V(CS) is the ideal D / A conversion result, and e(CS) is the error caused by the nonlinearity of the D / A conversion circuit 121. The successive approximation circuit 122 outputs the A / D conversion value CS + De(CS) corresponding to VIN + V(CS) + e(CS) = V(CS) + e(CS). De(CS) corresponds to the A / D conversion result of e(CS). The subtraction circuit 123 subtracts the code data CS from the A / D conversion value CS + De(CS) to output the A / D conversion data DOUT = De(CS).

[0078] Thus, it can be seen that the A / D conversion data DOUT contains the error data De(CS) corresponding to the code data CS. De(CS) becomes the function that converts the code data CS into error data. When the inverse function f used in the conversion circuit 116... -1 When (ERR) = CS is substituted into De(CS), it becomes De(CS) = De(f -1 (ERR)). In this embodiment, function f adopts a function with the same (or approximately the same) properties as function De. Therefore, De(CS) = De(De) -1 (ERR))=ERR, which enables the shaping characteristics of the error data ERR generated in the modulation circuit 114 to be reflected in the error data De(CS) of the A / D conversion data DOUT.

[0079] De(f -1 (ERR)) is equivalent to the system's error transfer function. In this embodiment, the error transfer function De(f) is made to... -1 The result of the operation (ERR) is approximately ERR (or a constant × ERR), and the function f is set in such a way that the result is approximately ERR. The characteristics of De are determined by the characteristics of the D / A conversion circuit 121 using the code data. Therefore, a function with characteristics that are the same (approximately the same) as the function e representing its nonlinearity is used as the function f. For example, the function e is estimated based on the operation of the D / A conversion circuit 121 using the code data, and this estimated function is set as the function f.

[0080] In the above embodiments, the code data generation circuit 110 converts the code data CS into the inverse function f of the error data ERR. -1 This will convert the error data ERR into code data CS.

[0081] In this way, by appropriately setting the function f that converts the code data CS into error data ERR, the frequency characteristics of the error data De(CS) of the A / D conversion data DOUT can be made the same (or approximately the same) as the frequency characteristics of the error data ERR. Therefore, the error data De(CS) of the A / D conversion data DOUT can have shaping characteristics.

[0082] Furthermore, in this embodiment, the A / D conversion circuit 120 includes a code data D / A conversion circuit 121 for performing D / A conversion on the code data CS. The function f is a function based on the conversion characteristics of the code data D / A conversion circuit 121.

[0083] The conversion characteristic of the D / A conversion circuit 121 for the coded data is represented by V(CS) + e(CS). The function f is set based on e(CS), which is its error component, thereby enabling the system's error transfer function De(f) to be optimized. -1The result of the operation (ERR) is approximately ERR (or a constant × ERR). Therefore, the error data De(CS) of the A / D conversion data DOUT caused by code shift can be made to be the same (approximately the same) as the error data ERR.

[0084] 3. Detailed structural example

[0085] Figure 8 This is a characteristic example of a function that converts code data into error data. The function f is represented by the following equation (1). The following equation (1) is an example for the case where the code data CS is in the range of -31 to +31.

[0086]

[0087] The nonlinearity (integral nonlinearity) inherent in D / A conversion circuits for code data is... Figure 2 The characteristics described above. The function f in equation (1) is set based on this nonlinearity. The conversion circuit 116 uses the inverse function f of the function f in equation (1). -1 The error data ERR is converted into code data CS. For example, the conversion circuit 116 uses a DSP (Digital Signal Processor), dedicated logic circuits, etc., to perform the inverse function f. -1 The computational processing. When using a DSP, the function of the conversion circuit 116 is implemented as a part of multiple processes performed by the DSP in a time-division manner. Alternatively, the conversion circuit 116 may store and inverse function f. -1 The corresponding lookup table is used to convert the error data ERR into code data CS.

[0088] According to the above implementation method, when the specified values ​​corresponding to the range of code data CS are CM and CA, the function f is represented by the following formula (2).

[0089]

[0090] Comparing equations (1) and (2) above, the specified values ​​are CM = 32 and CA = 31. That is, when the range of the code data CS is -CA to CA, half of the size of this range (CA - (-CA) = 2CA) is the specified value CA. In addition, the specified value CM = CA + 1.

[0091] By employing such a function f, it is possible to define a function f that corresponds to the nonlinearity of a typical D / A conversion circuit. For example, in Figure 16 and Figure 18 In a capacitor array type D / A converter circuit, it is assumed that the integral nonlinearity changes most significantly at the center code (CS=0). The function f reflects this characteristic.

[0092] Furthermore, the function f is not limited to equations (1) and (2) above. For example, in equation (1) above, f(CS) monotonically decreases from CS = -31 towards CS = -1, and at CS = 0, f(CS) changes sharply in the positive direction, while f(CS) monotonically decreases from CS = +1 towards CS = +31. Such characteristics are determined by the structure and operation of the code data D / A conversion circuit. Therefore, in the case of code data D / A conversion circuits with different structures and operations, it is only necessary to set the function f accordingly.

[0093] Figure 9 This is a detailed structural example of a data generation circuit. The data generation circuit 112 includes flip-flop circuits FF1 to FF16 and XOR circuits EX1 to EX3.

[0094] The data input terminals of trigger circuits FF2 to FF16 contain the outputs Q1 to Q15 of trigger circuits FF1 to FF15. XOR circuit EX1 outputs the XOR of the outputs Q14 and Q16 of trigger circuits FF14 and FF16. XOR circuit EX2 outputs the XOR of the output Q13 of trigger circuit FF13 with the output of XOR circuit EX1. XOR circuit EX3 outputs the XOR of the output Q11 of trigger circuit FF11 with the output of XOR circuit EX2. The data input terminal of trigger circuit FF1 contains the output of XOR circuit EX3.

[0095] Thus, the data generation circuit 112 becomes a shift register (linear feedback shift register) that receives feedback through the XOR circuits EX1 to EX3. Figure 9 In the example, a 16-bit data Q[16:1] consisting of Q1 to Q16 is generated, and this data Q[16:1] becomes pseudo-random number data. When the frequency of the clock signal that causes the flip-flop circuits FF1 to FF16 to operate is fck, the data Q[16:1] in period 2... 16 The loop in / fck is repeated once. The generated data DAR uses a portion of the data Q[16:1]. For example, when the code data CS is 6 bits (-31 to +31), the lower 6 bits of the data Q[16:1] are output as the generated data DAR.

[0096] According to the above implementation method, the data generation circuit 112 generates pseudo-random number data as generated data DAR.

[0097] In this way, code data CS can be generated based on pseudo-random number data. Using pseudo-random number data can reduce the periodicity of the code data CS, but... Figure 3As explained, periodicity remains in the code data CS due to the operating cycle of the data generation circuit 112. In this embodiment, by generating the code data CS by modulating the pseudo-random number data (shaping the frequency characteristics), the influence of the periodicity of the code data CS can be reduced.

[0098] In addition, the data generation circuit 112 is not limited to Figure 9 The structure can be any circuit capable of generating pseudo-random number data.

[0099] Figure 10 This is a detailed structural example of a modulation circuit. The modulation circuit 114 includes an addition processing unit 131 (subtraction circuit), a subtraction processing unit 132 (subtraction circuit), and a delay unit 133 (register and flip-flop circuit).

[0100] The addition processing unit 131 adds the generated data DAR to the output of the delay unit 133 and outputs the result as error data ERR. The subtraction processing unit 132 subtracts the output of the addition processing unit 131 from the output of the delay unit 133 and outputs the result. The delay unit 133 stores (latches) the output of the subtraction processing unit 132 and outputs the stored data. The modulation circuit 114 is a ΔΣ modulation circuit that performs one ΔΣ modulation on the generated data DAR. For example, the modulation circuit 114 is implemented using a DSP and dedicated logic circuits. When using a DSP, the function of the modulation circuit 114 is implemented as part of a series of processes performed by the DSP in a time-division manner.

[0101] Figure 11 This is an example of the frequency characteristics of the error in A / D conversion data caused by code shift in this embodiment. Figure 11 The middle shows the will Figures 8-10 Applied to Figure 6 The simulation results were obtained by performing a Fourier transform on the time variation of the error under the given conditions. Furthermore, Figure 12 This is a comparative example and an example of the Allan variance characteristics of the A / D converted data in this embodiment. AD1 is... Figure 5 The Allen variance characteristics of the comparative examples described herein are shown, and AD2 is the Allen variance characteristic of this embodiment.

[0102] like Figure 11 As shown, the frequency characteristics of the A / D conversion data error are shaped by a single ΔΣ modulation. It can be seen that compared to the signal power level SPA in the comparative example, the frequency components (signal power) on the low-frequency side are significantly reduced. Therefore, as... Figure 12As shown in B1, compared to the comparative example, the Allan variance characteristics in the region with larger τ are improved. That is, the degradation (peak) of Allan variance characteristics caused by the frequency components of the error is reduced. In addition, due to the reduction of the frequency components (signal power) on the low-frequency side of the error, the floor of Allan variance characteristics decreases, and the overall characteristics of Allan variance are improved.

[0103] According to the above implementation method, the modulation circuit 114 performs n times (n is an integer greater than or equal to 1) ΔΣ modulation on the generated data DAR to generate error data ERR.

[0104] In this way, it is possible to Figure 11 The shaping characteristics shown are assigned to the error data ERR. In this embodiment, the error data De(CS) of the A / D conversion data DOUT has the same (approximately the same) frequency characteristics as the error data ERR, therefore, the shaping characteristics can be assigned to the error data De(CS) of the A / D conversion data DOUT.

[0105] In addition, Figure 10 The example described uses a single-order ΔΣ modulation circuit, but the modulation circuit 114 can also be a double-order or higher ΔΣ modulation circuit. The order of the ΔΣ modulation circuit corresponds to the number of feedback loops, including the ΔΣ modulation circuit.

[0106] 4. Variations

[0107] Figure 13 This is a variation of the data generation circuit. In Figure 13 In the middle, the data generation circuit 112 includes a linear feedback shift register 141 and an output circuit 142.

[0108] Linear feedback shift register 141 generates pseudo-random number data RMD1 (the first random number data). Linear feedback shift register 141 is, for example... Figure 9 The linear feedback shift register 142 outputs generated data DAR based on pseudo-random number data RMD1 and second random number data RMD2. For example, the pseudo-random number data RMD1 is processed (e.g., permuted, operated on, combined, etc.) using the second random number data RMD2 to generate the generated data DAR. The second random number data RMD2 is, for example, random number data output from internal circuitry of the circuit device 100 or random number data supplied from outside the circuit device 100. For example, the data generation circuit 112 may include a pseudo-random number data generation circuit different from the linear feedback shift register 141, which outputs the second random number data RMD2.

[0109] According to the above implementation method, the data generation circuit 112 outputs generated data DAR based on the pseudo-random number data RMD1 and the second random number data RMD2.

[0110] This allows for the generation of DAR data with higher randomness. For example, if the frequency of occurrence of each code in the generated DAR data is uneven, it can make the frequency of occurrence more uniform.

[0111] Figure 14 This diagram illustrates the operation of a modified example of the data generation circuit. Figure 14 The example shown illustrates the case where a 4-bit two's complement is generated as code data CS. In this case, the generated data DAR is also a 4-bit two's complement.

[0112] A 4-bit pseudo-random number data RMD1 can take values ​​from 0000 to 1111 in binary. In decimal, this is 0 to 15, resulting in 16 values. However, when considered in decimal, the 4-bit two's complement is -7 to +7, resulting in 15 values. Therefore, when generating the two's complement data DAR from the pseudo-random number data RMD1, there is a remainder of 1. For example, when converting 1 to 15 from the pseudo-random number data RMD1 to -7 to +7 from the generated data DAR, a remainder of 0 from the pseudo-random number data RMD1 remains. This remainder can be matched with a 0 in the generated data DAR. In this case, when the generation frequency of each code in the pseudo-random number data RMD1 is uniform, the generation frequency of DAR = 0 is twice the generation frequency of codes other than 0.

[0113] In this embodiment, when the pseudo-random number data is RMD1 = 0, a second random number data, RMD2, is allocated and converted into generated data DAR. If the occurrence frequency of each code in the second random number data RMD2 is uniform, then the occurrence frequency of RMD1 = 0 is dispersed among the codes in the generated data DAR. In this way, the occurrence frequency of each code in the generated data DAR can be made uniform.

[0114] 5. A / D conversion circuit

[0115] Figure 15 This is an example of the structure of an A / D conversion circuit. The A / D conversion circuit 120 includes a comparator circuit 10, a control circuit 20, a first D / A conversion circuit DAC1, a second D / A conversion circuit DAC2, and an S / H circuit 30 (sample and hold circuit). The second D / A conversion circuit DAC2 and... Figure 7 The coded data corresponds to the D / A conversion circuit 121. Furthermore, this embodiment is not limited to... Figure 15 The structure can be modified in various ways, such as omitting some structural elements or adding other structural elements.

[0116] The comparison circuit 10 is implemented using a comparator to compare the signal SADD with the signal DCQ. For example, the comparison circuit 10 is a time-domain comparator that converts the input signals into time (e.g., pulse width or pulse delay time) for comparison. For example, the time-domain comparator includes a first voltage-to-time conversion circuit, a second voltage-to-time conversion circuit, and a decision circuit. The first voltage-to-time conversion circuit delays the pulse signal by a delay time corresponding to the difference between the first input signal DCQ and the second input signal SADD. The second voltage-to-time conversion circuit delays the pulse signal by a delay time corresponding to the difference between the second input signal SADD and the first input signal DCQ. The decision circuit compares the pulse signal delayed by the first voltage-to-time conversion circuit with the pulse signal delayed by the second voltage-to-time conversion circuit and determines the magnitudes of the first and second input signals.

[0117] The control circuit 20 has a successive compare register SAR, which outputs successive compare data RDA stored in the successive compare register SAR. The successive compare register SAR is a register whose register value is set according to the comparison result signal CPQ from the comparison circuit 10. For example, when the comparison circuit 10 performs successive compare processing from MSB to LSB, the comparison processing result of each bit ("1", "0") is stored as the register value of the successive compare register SAR.

[0118] In addition, the control circuit 20 can also control the various circuit blocks of the A / D conversion circuit. For example, it can control the switching elements (switch arrays) contained in the D / A conversion circuits DAC1 and DAC2 to turn on and off.

[0119] The D / A conversion circuit DAC1 (Successive Comparison Data D / A Conversion Circuit) performs D / A conversion on the successive comparison data RDA from the control circuit 20. Furthermore, it outputs a D / A output signal DCQ corresponding to the successive comparison data RDA. This D / A conversion circuit DAC1 can be a charge redistribution type utilizing a capacitor array, or it can be partially or entirely of a trapezoidal resistor type.

[0120] The D / A conversion circuit DAC2 performs D / A conversion on the code data CS. It also outputs the code signal SCD corresponding to the code data CS. Here, the code data CS is digital data that changes at each specified time, taking different values ​​at each of the one or more A / D conversions.

[0121] The S / H circuit 30 is a circuit that samples and holds the input signal VIN, which is the target of A / D conversion. Furthermore, in the case of charge redistribution, the function of the S / H circuit 30 can be implemented by a D / A conversion circuit.

[0122] Furthermore, in this embodiment, the comparator circuit 10 performs the following processing: comparing the signal SADD obtained by adding the sampled signal SIN and the code signal SCD of the input signal VIN with the D / A output signal DCQ. Alternatively, the comparator circuit 10 can perform the following processing: comparing the signal obtained by adding the D / A output signal DCQ and the code signal SCD with the sampled signal SIN.

[0123] Furthermore, the control circuit 20 outputs the A / D conversion data DOUT of the input signal VIN as the output data calculated based on the successive comparison result data QDA (the final successive comparison data RDA after the successive comparisons are completed) and the code data CS from the successive comparison register SAR. For example, when comparing the signal SADD obtained by adding the sampled signal SIN and the code signal SCD with the D / A output signal DCQ, the control circuit 20 subtracts the code data CS from the successive comparison result data QDA. On the other hand, when comparing the signal obtained by adding the D / A output signal DCQ and the code signal SCD with the sampled signal SIN, the control circuit 20 adds the successive comparison result data QDA and the code data CS.

[0124] When the D / A conversion circuit DAC1, which performs D / A conversion on the successive comparison data RDA, has nonlinearity (differential nonlinearity, integral nonlinearity), this nonlinearity becomes the cause of nonlinearity in the A / D conversion characteristics of the A / D conversion circuit 120. For example, a specific code of the A / D conversion data may become a missing code. In this embodiment, by using code data CS that varies over time, the successive comparison result data QDA relative to the (same) input signal VIN can be changed. As a result, the nonlinearity is dispersed over time, which can improve the characteristics of the A / D conversion circuit observed in a time-averaged manner. For example, it is possible to disperse the codes that generate missing codes over time.

[0125] Figure 16 This is the first detailed structural example of an A / D conversion circuit. Figure 16 Show Figure 15 The detailed structure of DAC1, DAC2 and comparator circuit 10 is shown in the example. DAC1 and DAC2 are composed of charge redistribution type D / A conversion circuits.

[0126] The first D / A conversion circuit DAC1 includes a first capacitor array section 41 and a first switch array section 51. It also includes a first series capacitor CS1 disposed between the comparator node NC and the first node N1. DAC1 further includes a second capacitor array section 42 and a second switch array section 52. It also includes switching elements SS1 and SS2 for setting nodes NC and N1 to ground voltage GND (power supply voltage, reference voltage) during sampling.

[0127] The first capacitor array section 41 includes multiple capacitors CA1 to CA4. One end of each capacitor CA1 to CA4 is connected to the comparison node NC of the comparator circuit 10. Here, the comparison node NC (sampling node) is a node connected to the first input terminal (inverting input terminal) of the comparator circuit 10, and the second input terminal (non-inverting input terminal) of the comparator circuit 10 is set to GND. Furthermore, the capacitors CA1 to CA4 are weighted according to binary; for example, in the case of 4 bits, the capacitance values ​​of CA1, CA2, CA3, and CA4 are C, 2C, 4C, and 8C, respectively. In addition, the first capacitor array section 41 also includes a dummy capacitor CDM.

[0128] The first switch array section 51 includes a plurality of switch elements SA1 to SA4. These switch elements SA1 to SA4 are connected to the other ends of capacitors CA1 to CA4 in the first capacitor array section 41. Moreover, the switch elements SA1 to SA4 are switched and controlled according to the data of the upper bit of the successive comparison data RDA (for example, the upper 4 bits of data when RDA is 8 bits).

[0129] The second capacitor array section 42 includes multiple capacitors CB1 to CB4. One end of these capacitors CB1 to CB4 is connected to the first node N1. Here, the first node N1 is the node on the other end of the series capacitor CS1, which is connected to the comparison node NC at one end. Furthermore, the capacitors CB1 to CB4 are weighted according to binary, for example, in the case of 4 bits, the capacitance values ​​of CB1, CB2, CB3, and CB4 are C, 2C, 4C, and 8C, respectively.

[0130] The second switch array section 52 includes a plurality of switch elements SB1 to SB4. These switch elements SB1 to SB4 are connected to the other ends of capacitors CB1 to CB4 in the second capacitor array section 42. Moreover, the switch elements SB1 to SB4 are switched and controlled according to the data of the lower bit of the successive comparison data RDA (for example, the lower 4 bits of data when RDA is 8 bits).

[0131] The second D / A conversion circuit DAC2 includes a second series capacitor CS2 disposed between the comparator node NC and the second node N2. It also includes a third capacitor array 43 and a third switch array 53. Furthermore, it includes a switching element SS3 for setting the second node N2 to GND during sampling.

[0132] The third capacitor array section 43 includes multiple capacitors CC1 to CC4. One end of these capacitors CC1 to CC4 is connected to the second node N2. Here, the second node N2 is the node on the other end of the series capacitor CS2, which is connected to the comparison node NC at one end. Furthermore, the capacitors CC1 to CC4 are weighted according to binary, for example, in the case of 4 bits, the capacitance values ​​of CC1, CC2, CC3, and CC4 are C, 2C, 4C, and 8C, respectively.

[0133] The third switch array section 53 of DAC2 includes multiple switching elements SC1 to SC4. These switching elements SC1 to SC4 are connected to the other ends of capacitors CC1 to CC4 of the third capacitor array section 43. Moreover, the switching elements SC1 to SC4 are switched and controlled according to the code data CS.

[0134] Figure 17 This diagram illustrates the operation of the first detailed structural example of an A / D conversion circuit. (Example:) Figure 17 As shown, during the sampling period of the input signal VIN, the switching elements SS1 and SS2 of the D / A conversion circuit DAC1 are turned on, and nodes NC and N1 are set to GND. In addition, the other ends of capacitors CA1-CA4 and CB1-CB4 are set to the voltage level of VIN via the switching elements SA1-SA4 and SB1-SB4 of the D / A conversion circuit DAC1.

[0135] Therefore, the input signal VIN is sampled. Furthermore, when switching elements SA1-SA4 and SB1-SB4 are open, the voltage of the input signal VIN at that moment is maintained. Additionally, during the sampling period, the other end of the dummy capacitor CDM is set to the voltage level of VIN via the switching element SDM for the dummy capacitor.

[0136] Furthermore, during sampling, the switching element SS3 of the D / A conversion circuit DAC2 used for code shifting is turned on, and node N2 is set to GND. Additionally, the other ends of capacitors CC1 to CC4 are set to GND via switching elements SC1 to SC4. Thus, the two ends of capacitors CC1 to CC4 are set to GND, becoming a state without any accumulated charge.

[0137] Next, during the successive approximation period of the A / D conversion, the switching elements SS1 and SS2 of the D / A conversion circuit DAC1 are turned off. Furthermore, the other end of the switching element SDM used for the dummy capacitor is set to GND.

[0138] Furthermore, the switching elements SA1-SA4 and SB1-SB4 of DAC1 are switched according to each bit of the successive comparison data RDA, and the other ends of capacitors CA1-CA4 and CB1-CB4 are set to VREF or GND. For example, when the successive comparison data RDA = 10000000, the other end of capacitor CA4, which corresponds to the MSB of RDA, is set to the reference voltage VREF. In addition, the other ends of capacitors CA3-CA1 and CB4-CB1 are set to GND.

[0139] Furthermore, during the successive comparison period of the A / D conversion, the switching element SS3 of the D / A conversion circuit DAC2 is turned off. Moreover, the switching elements SC1 to SC4 of DAC2 are switched according to each bit of the code data CS, and the other ends of capacitors CC1 to CC4 are set to VREF or GND. For example, when the code data is CDA = 1000, the other end of capacitor CC4 is set to VREF, and the other ends of capacitors CC3 to CC1 are set to GND.

[0140] exist Figure 16 In a charge redistribution type A / D conversion circuit, the signal obtained by adding the D / A output signal and the code signal is compared with the sampled signal of VIN. In this case, Figure 15 The control circuit 20 performs the process of adding the successive comparison result data QDA to the code data CS.

[0141] Figure 18 This is the second detailed structural example of an A / D conversion circuit. Figure 18 The diagram shows a structural example of a fully differential A / D conversion circuit. The A / D conversion circuit 120 includes a comparator circuit 10, a first D / A conversion circuit DAC1P connected to the non-inverting input terminal of the comparator circuit 10, and a second D / A conversion circuit DAC1N connected to the inverting input terminal of the comparator circuit 10. Furthermore, the A / D conversion circuit 120 includes a third D / A conversion circuit DAC2P connected to the non-inverting input terminal of the comparator circuit 10, and a fourth D / A conversion circuit DAC2N connected to the inverting input terminal.

[0142] The structure of D / A conversion circuits DAC1P and DAC1N and Figure 16 The D / A conversion circuit DAC1 also includes a capacitor array section and a switch array section. Furthermore, the input signal PIN, which constitutes the non-inverting side (positive side) of the differential signal, is input to DAC1P, and the input signal NIN, which constitutes the inverting side (negative side) of the differential signal, is input to DAC1N.

[0143] Furthermore, during sampling, nodes NCP and N1P of DAC1P are set to the common voltage (intermediate voltage) VCM via switching elements SS1P and SS2P. Similarly, nodes NCN and N1N of DAC1N are set to the common voltage VCM via switching elements SS1N and SS2N. Additionally, during sampling, one end of switching elements SA1P to SA4P and SB1P to SB4P of DAC1P is connected to the signal pin on the non-inverting side of the differential signal, and one end of switching elements SA1N to SA4N and SB1N to SB4N of DAC1N is connected to the signal NIN on the inverting side of the differential signal.

[0144] On the other hand, during successive comparisons, when the corresponding bit of the successive comparison data is "1", one end of the switching elements SA1P~SA4P and SB1P~SB4P of DAC1P is connected to VREF; when the corresponding bit of the successive comparison data is "0", one end of the switching elements SA1P~SA4P and SB1P~SB4P of DAC1P is connected to GND. Conversely, when the corresponding bit of the successive comparison data is "1", one end of the switching elements SA1N~SA4N and SB1N~SB4N of DAC1N is connected to GND; when the corresponding bit of the successive comparison data is "0", one end of the switching elements SA1N~SA4N and SB1N~SB4N of DAC1N is connected to VREF.

[0145] D / A conversion circuits DAC2P, DAC2N and Figure 16 The D / A conversion circuit DAC2 used for code shifting also includes a capacitor array section and a switch array section.

[0146] Furthermore, during sampling, node N2P of DAC2P is set to VCM via switching element SS3P. Similarly, node N2N of DAC2N is set to VCM via switching element SS3N. Additionally, one end of switching elements SC1P to SC4P of DAC2P and switching elements SC1N to SC4N of DAC2N are connected to VCM.

[0147] On the other hand, during successive comparisons, when the corresponding bit of the code data is "1", one end of the switching elements SC1P to SC4P of DAC2P is connected to VREF; when the corresponding bit of the code data is "0", one end of the switching elements SC1P to SC4P of DAC2P is connected to GND. Conversely, when the corresponding bit of the code data is "1", one end of the switching elements SC1N to SC4N of DAC2N is connected to GND; when the corresponding bit of the code data is "0", one end of the switching elements SC1N to SC4N of DAC2N is connected to VREF.

[0148] 6. Physical quantity measuring device

[0149] Figure 19 This is a structural example of a physical quantity measuring device including the circuit arrangement of this embodiment. The physical quantity measuring device 400 includes a physical quantity transducer and a circuit arrangement 100. The circuit arrangement 100 includes a drive circuit 70 that drives the physical quantity transducer and a detection circuit 60 that receives a detection signal from the physical quantity transducer and detects a physical quantity signal corresponding to the physical quantity. Furthermore, the detection circuit 60 includes an A / D conversion circuit 120 that performs A / D conversion on the input signal based on the detection signal.

[0150] A physical quantity transducer is a component or device used to detect physical quantities. Physical quantities include, for example, angular velocity, angular acceleration, velocity, acceleration, distance, pressure, sound pressure, magnetic quantity, or time. Furthermore, the circuit device 100 can detect physical quantities based on detection signals from multiple physical quantity transducers. For example, the first to third physical quantity transducers detect physical quantities about the first, second, and third axes, respectively. As an example of physical quantities about the first, second, and third axes, these are angular velocities or angular accelerations about the first, second, and third axes, or velocities or accelerations in the directions of the first, second, and third axes. As an example of the first, second, and third axes, these are the X-axis, Y-axis, and Z-axis. Alternatively, physical quantities can be detected only on two of the first to third axes.

[0151] exist Figure 19 The diagram illustrates a structural example of a gyroscope sensor for detecting angular velocity, serving as an example of a physical quantity measuring device. Figure 19 In this device, the physical quantity measuring device 400 includes an oscillator 410 as a physical quantity transducer. Furthermore, the circuit device 100 may include a processing circuit 150 (DSP).

[0152] The oscillator 410 (angular velocity sensing element) is a component that detects the Coriolis force acting on the oscillator 410 by rotating it about a predetermined axis and outputs a signal corresponding to the Coriolis force. The oscillator 410 is, for example, a piezoelectric oscillator. For example, the oscillator 410 can be a double-T-shaped, T-shaped, tuning fork-shaped, or other quartz oscillator. Alternatively, the oscillator 410 can be a MEMS (Micro Electro Mechanical Systems) oscillator, which is formed using a silicon substrate and is a silicon oscillator.

[0153] The drive circuit 70 includes: an amplifier circuit 32, which receives a feedback signal DI from the oscillator 410 as input; a gain control circuit 40, which performs automatic gain control; and a drive signal output circuit 50, which outputs a drive signal DQ to the oscillator 410. Furthermore, the drive circuit 70 includes a synchronization signal output circuit 54 that outputs a synchronization signal SYC to the detection circuit 60.

[0154] Amplifier circuit 32 (I / V conversion circuit) amplifies the feedback signal DI from oscillator 410. For example, it converts the current signal DI from oscillator 410 into a voltage signal DV for output. This amplifier circuit 32 can be implemented using an operational amplifier, a feedback resistor, a feedback capacitor, etc.

[0155] The drive signal output circuit 50 outputs a drive signal DQ based on the signal DV amplified by the amplifier circuit 32. For example, when the drive signal output circuit 50 outputs a rectangular wave (or a sine wave) drive signal, the drive signal output circuit 50 can be implemented using a comparator or the like.

[0156] The gain control circuit 40 (AGC) outputs a control voltage DS to the drive signal output circuit 50 to control the amplitude of the drive signal DQ. Specifically, the gain control circuit 40 monitors the signal DV and controls the gain of the oscillation loop. For example, in the drive circuit 70, in order to keep the sensitivity of the gyroscope sensor constant, it is necessary to keep the amplitude of the drive voltage supplied to the drive vibration section of the oscillator 410 constant. Therefore, a gain control circuit 40 for automatically adjusting the gain is provided in the oscillation loop of the drive vibration system. The gain control circuit 40 automatically adjusts the gain in a variable manner to keep the amplitude of the feedback signal DI from the oscillator 410 (the vibration velocity of the drive vibration section of the oscillator 410) constant. This gain control circuit 40 can be implemented by a full-wave rectifier that performs full-wave rectification of the output signal DV of the amplifier circuit 32 or an integrator that performs integration processing of the output signal of the full-wave rectifier.

[0157] The synchronization signal output circuit 54 receives the amplified signal DV from the amplifier circuit 32 and outputs the synchronization signal SYC (reference signal) to the detection circuit 60. This synchronization signal output circuit 54 can be implemented using a comparator or a phase adjustment circuit (phase shifter) that adjusts the phase of the synchronization signal SYC. The comparator performs binarization processing on the sinusoidal (AC) signal DV to generate a rectangular wave synchronization signal SYC.

[0158] The detection circuit 60 also includes an amplifier circuit 64, a synchronous detection circuit 81, and a code data generation circuit 110. The amplifier circuit 64 receives the first and second detection signals IQ1 and IQ2 from the oscillator 410 and performs charge-to-voltage conversion, differential signal amplification, and gain adjustment. The synchronous detection circuit 81 performs synchronous detection based on the synchronization signal SYC from the drive circuit 70. The A / D conversion circuit 120 performs code shifting based on the code data from the code data generation circuit 110 and performs A / D conversion on the synchronously detected signal. The processing circuit 150 performs digital filtering and digital correction processing (e.g., zero-point correction and sensitivity correction) on the digital signal from the A / D conversion circuit 120.

[0159] 7. Mobile objects and electronic devices

[0160] Figure 20 , Figure 21 Examples include mobile bodies and electronic devices that include the circuit device of this embodiment. The circuit device 100 of this embodiment can be assembled into various mobile bodies such as cars, airplanes, motorcycles, bicycles, or ships. Mobile bodies are, for example, devices / apparatus that have drive mechanisms such as engines and motors, steering mechanisms such as steering wheels or rudders, and various electronic devices and move on land, in the sky, or at sea.

[0161] Figure 20 A car 206, as a specific example of a moving body, is schematically shown. A gyroscope sensor (not shown), including a circuit device 100, is assembled in the car 206. The gyroscope sensor can detect the posture of the vehicle body 207. The detection signal from the gyroscope sensor is supplied to a vehicle posture control device 208. The vehicle posture control device 208 can, for example, control the stiffness of the suspension or control the braking of each wheel 209 based on the posture of the vehicle body 207. Furthermore, such posture control can be used in various moving bodies such as bipedal walking robots, airplanes, and helicopters. A gyroscope sensor can be assembled to implement posture control.

[0162] Figure 21 A digital still camera 610 is schematically shown as a specific example of an electronic device. The digital still camera 610 is equipped with a gyroscope sensor (not shown) and an accelerometer sensor (not shown), including a circuit device 100. For example, in the digital still camera 610, hand shakiness correction using the gyroscope sensor and accelerometer sensor can be performed. Furthermore, a liveness detection device (wearable healthcare device, such as a pulse meter, pedometer, activity meter, etc.) can be assumed as a specific example of an electronic device. In a liveness detection device, the gyroscope sensor and accelerometer sensor can be used to detect the user's body movements or motion state. Thus, the circuit device 100 of this embodiment can be applied to various electronic devices such as the digital still camera 610 or a liveness detection device.

[0163] Furthermore, it is possible to assume that the robot is a specific example of a mobile body or an electronic device. The circuit device 100 of this embodiment can be applied, for example, to the movable part (arm, joint) and main body of the robot. The robot can be assumed to be any robot, either a mobile body (driving / walking robot) or an electronic device (non-driving / non-walking robot). In the case of a driving / walking robot, for example, a gyroscope sensor (including the circuit device of this embodiment) can be used during autonomous driving.

[0164] Furthermore, while this embodiment has been described in detail above, those skilled in the art will readily understand that numerous modifications can be implemented without substantially departing from the new aspects and effects of the invention. Therefore, all such modifications are included within the scope of the invention. For example, terms described at least once in the specification or drawings along with broader or synonymous terms can be replaced with those different terms at any point in the specification or drawings. Moreover, all combinations of this embodiment and its modifications are also included within the scope of the invention. Furthermore, the structure / operation of code data generation circuits, A / D conversion circuits, circuit devices, physical quantity measuring devices, electronic devices, moving bodies, etc., are not limited to those described in this embodiment, and various modifications can be implemented.

Claims

1. A circuit device, characterized in that, It includes: Code data generation circuit, which generates code data; and An A / D conversion circuit performs code shifting based on the code data to convert the input signal into an A / D value. The A / D conversion circuit includes a first D / A conversion circuit that performs D / A conversion on the code data and outputs a code signal. The code data generation circuit generates error data with frequency characteristics that have shaping properties, and converts the error data into code data according to the conversion characteristics of the first D / A conversion circuit. The code data generation circuit converts the error data back into code data by converting the code data into the inverse function of the error data. The function is based on the conversion characteristics of the first D / A conversion circuit.

2. The circuit device according to claim 1, characterized in that, The code data generation circuit includes: Data generation circuit; A modulation circuit that modulates generated data from the data generation circuit to generate the error data; and A conversion circuit that converts the error data into the code data.

3. The circuit device according to claim 2, characterized in that, The modulation circuit performs n ΔΣ modulations on the generated data to generate the error data, where n is an integer greater than or equal to 1.

4. The circuit device according to claim 3, characterized in that, The data generation circuit generates pseudo-random numbers as the generated data.

5. The circuit device according to claim 4, characterized in that, The data generation circuit outputs the generated data based on the pseudo-random number data and the second random number data.

6. The circuit device according to claim 1, characterized in that, The A / D conversion circuit includes: Comparator circuit; The control circuit has a register and outputs comparison data; and The second D / A conversion circuit performs D / A conversion on the comparison data from the control circuit and outputs a D / A output signal. The register is set to a value based on the comparison result signal from the comparison circuit. The comparison circuit performs the following processing: comparing the signal obtained by adding the sampled signal of the input signal and the code signal with the D / A output signal, or comparing the signal obtained by adding the D / A output signal and the code signal with the sampled signal. The control circuit outputs the A / D conversion data of the input signal as the output data obtained by comparing the data in the register and the code data.

7. The circuit device according to claim 1, characterized in that, When the code data is CS, the specified values ​​corresponding to the range of the code data are CM and CA, the error data is ERR, and the function is f, the following conditions are met: When CS > 0, ERR = f(CS) = (CM - CS) / CA When CS=0, ERR=f(CS)=0 When CS < 0, ERR = f(CS) = -(CM + CS) / CA.

8. The circuit device according to claim 1, characterized in that, The circuit device includes: The driving circuit drives the physical quantity transducer; and The detection circuit receives the detection signal from the physical quantity transducer and detects the physical quantity signal corresponding to the physical quantity. The detection circuit includes an A / D conversion circuit that performs A / D conversion on the input signal based on the detection signal.

9. A physical quantity measuring device, characterized in that, It includes: The circuit device according to any one of claims 1 to 8; and Physical quantity transducer.

10. An electronic device, characterized in that, The electronic device includes the circuit arrangement as described in any one of claims 1 to 8.

11. A mobile body, characterized in that, The mobile body comprises the circuitry as described in any one of claims 1 to 8.

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