Data checking method, device and equipment and storage medium

Abstract

The present disclosure relates to a data verification method and device, equipment and storage medium, and belongs to the field of communication, which can improve the calculation speed of checksum and reduce the CPU overhead. The method comprises: obtaining network transmission data, and performing division processing on the network transmission data, so that each data segment obtained by division includes multiple bytes, and the number of bytes of each data segment is less than or equal to a first threshold; performing first accumulation processing on the multiple expansion vectors corresponding to each data segment respectively, to determine the first target vector corresponding to each data segment; performing second accumulation processing on the intermediate vector of the multiple expansion vectors corresponding to each data segment, and determining the vector obtained by final accumulation as the second target vector of the corresponding data segment; and determining the checksum for verifying the network transmission data according to the first target vector of each data segment and the second target vector of each data segment.

Description

Technical Field

[0001] This disclosure relates to the field of communications, and more particularly to a data verification method, apparatus, device, and storage medium. Background Technology

[0002] During network data transmission, data may be corrupted due to factors such as transmission medium and signal strength, causing discrepancies between the received data and the transmitted data. To verify these discrepancies, a checksum corresponding to the data can be transmitted simultaneously with the network data. Checksums, as a common method for verifying data integrity, are widely used in various network protocols, such as Internet Protocol version 4 (IPv4), User Datagram Protocol (UDP), and Transmission Control Protocol (TCP).

[0003] Among them, Fletcher checksum has advantages over common parity checksum in terms of verifying data order and preventing checksum collisions, and is therefore adopted by many transmission protocols.

[0004] However, in high-speed data transmission networks, the calculation of Fletcher checksums may consume a large amount of central processing unit (CPU) resources, resulting in a slow calculation speed. Summary of the Invention

[0005] To address the aforementioned technical issues, this disclosure provides a data verification method, apparatus, device, and storage medium that can perform parallel processing of network transmission data using the streaming single instruction multiple data extensions (SSE) instruction set, thereby improving the calculation speed of checksums and reducing CPU overhead.

[0006] According to a first aspect of the present disclosure, a data verification method is provided. The method includes: acquiring network transmission data and dividing the network transmission data into multiple data segments, such that each data segment includes multiple bytes, and the number of bytes in each data segment is less than or equal to a first threshold; expanding each data segment to obtain multiple expanded vectors, such that each expanded vector has the same number of bits as the elements in a preset first preset vector and a preset second preset vector, both being preset values; each data segment corresponds to multiple expanded vectors; and performing a first accumulation process on the multiple expanded vectors corresponding to each data segment, so that the vector obtained after accumulating each expanded vector is determined as the middle of each expanded vector. The first accumulation process involves sequentially accumulating the multiple expansion vectors corresponding to each data segment to a first preset vector; performing a second accumulation process on the intermediate vector of the multiple expansion vectors corresponding to each data segment to determine the finally accumulated vector as the second target vector of the corresponding data segment; the second accumulation process involves sequentially accumulating the intermediate vector of the multiple expansion vectors corresponding to each data segment to a second preset vector; and determining a checksum for verifying network transmission data based on the first target vector and the second target vector of each data segment.

[0007] In one possible implementation, each data segment's first target vector and second target vector both include multiple vector blocks. Determining a checksum for verifying network transmission data based on the first target vector and the second target vector of each data segment includes: determining a first parameter for each data segment based on the first target vector and a first preset relationship, resulting in multiple first parameters; the first preset relationship indicates the weight coefficients of the multiple vector blocks in each first target vector; determining a second parameter for each data segment based on the second target vector and the second preset relationship, resulting in multiple second parameters; the second preset relationship indicates the weight coefficients of the multiple vector blocks in each second target vector; and determining a checksum for verifying network transmission data based on the multiple first parameters and the multiple second parameters.

[0008] In one possible implementation, determining the first parameter of each data segment based on the first target vector and the first preset relationship for each data segment includes: multiplying each vector block in the first target vector with the corresponding weight coefficient in the first preset relationship, and accumulating the results of multiplying each vector block in the first target vector with the corresponding weight coefficient to obtain the first parameter; determining the second parameter of each data segment based on the second target vector and the second preset relationship for each data segment includes: multiplying each vector block in the second target vector with the corresponding weight coefficient in the second preset relationship, and accumulating the results of multiplying each vector block in the second target vector with the corresponding weight coefficient to obtain the second parameter. Optionally, the weight coefficients indicated by the second preset relationship include positive and negative coefficients; the results of multiplying each vector block in the second target vector with its corresponding weight coefficient are accumulated to obtain the second parameter, including: accumulating the product of vector blocks with positive weight coefficients with their corresponding weight coefficients to obtain a first result; accumulating the product of vector blocks with negative weight coefficients with their corresponding weight coefficients to obtain a second result; and obtaining the second parameter based on the first result, the second result, and the third preset relationship.

[0009] In one possible implementation, determining a checksum for verifying network transmission data based on multiple first parameters and multiple second parameters includes: accumulating the multiple first parameters to obtain a first target parameter; accumulating the multiple second parameters to obtain a second target parameter; using the second target parameter as the high-order parameter of the checksum and the first target parameter as the low-order parameter of the checksum to obtain the checksum.

[0010] Optionally, both the first target vector and the second target vector include multiple vector blocks; the method further includes: after determining the middle vector of the last extended vector among the multiple extended vectors corresponding to each data segment as the first target vector of the corresponding data segment, performing same-position addition processing on each vector block in the first target vector, where same-position addition processing means adding the Nth bit in the high-order bits of each vector block to the Nth bit in the low-order bits of the vector block, where N is a positive integer; after sequentially performing accumulation processing on the middle vector of the multiple extended vectors corresponding to each data segment and the second preset vector to obtain the second target vector of the corresponding data segment, performing same-position addition processing on each vector block in the second target vector.

[0011] In one possible implementation, each data segment is expanded to obtain multiple expanded vectors, including: obtaining multiple initial vectors based on the data in each data segment; each data segment corresponds to multiple initial vectors; and expanding the bit depth of each of the multiple initial vectors corresponding to each data segment to obtain multiple expanded vectors corresponding to each data segment.

[0012] In one possible implementation, each of the multiple initial vectors corresponding to each data segment is subjected to bit expansion processing to obtain multiple expanded vectors corresponding to each data segment. This includes: expanding the highest bit element of each vector block in the multiple vector blocks to obtain multiple expanded vectors; the expansion processing includes expanding the highest bit element of each vector block in the multiple vector blocks by M preset characters, where the product of M and the number of vector blocks in each expanded vector is equal to the difference between the preset value and the number of bits of the elements in the initial vector.

[0013] Optionally, the first threshold is 160 bytes; the number of bits in both the first preset vector and the second preset vector is 128; both the first preset vector and the second preset vector include 8 vector blocks; each vector block is a vector including 16-bit elements; the lower 8 bits in each vector block are all 1.

[0014] According to a second aspect of the present disclosure, a data verification apparatus is provided, the apparatus comprising: an acquisition module and a processing module; The acquisition module is used to acquire network transmission data and divide the network transmission data so that each data segment in the multiple data segments obtained includes multiple bytes, and the number of bytes in each data segment is less than or equal to a first threshold. The processing module is used to expand each data segment to obtain multiple expanded vectors, such that the number of bits in each expanded vector is the same as the number of bits in the first and second preset vectors, and both are preset values; each data segment corresponds to multiple expanded vectors; a first accumulation process is performed on the multiple expanded vectors corresponding to each data segment to determine the vector obtained after accumulation as the intermediate vector of each expanded vector, and the intermediate vector of the last expanded vector in the multiple expanded vectors corresponding to each data segment is determined as the first target vector of the corresponding data segment; the first accumulation process includes sequentially accumulating the multiple expanded vectors corresponding to each data segment to the first preset vector; a second accumulation process is performed on the intermediate vectors of the multiple expanded vectors corresponding to each data segment to determine the vector obtained by the final accumulation as the second target vector of the corresponding data segment; the second accumulation process includes sequentially accumulating the intermediate vectors of the multiple expanded vectors corresponding to each data segment to the second preset vector; and a checksum for verifying network transmission data is determined based on the first target vector and the second target vector of each data segment.

[0015] Optionally, each data segment's first target vector and second target vector both include multiple vector blocks; the processing module is specifically used to determine a first parameter of each data segment based on the first target vector of each data segment and a first preset relationship, thereby obtaining multiple first parameters; the first preset relationship is used to indicate the weight coefficients of the multiple vector blocks in each first target vector; based on the second target vector of each data segment and the second preset relationship, determine a second parameter of each data segment, thereby obtaining multiple second parameters; the second preset relationship is used to indicate the weight coefficients of the multiple vector blocks in each second target vector; and based on the multiple first parameters and multiple second parameters, determine a checksum used to verify the network transmission data.

[0016] Optionally, the processing module is specifically configured to multiply each vector block in the first target vector with the corresponding weight coefficient in the first preset relationship, and then accumulate the results of multiplying each vector block in the first target vector with the corresponding weight coefficient to obtain a first parameter; and to multiply each vector block in the second target vector with the corresponding weight coefficient in the second preset relationship, and then accumulate the results of multiplying each vector block in the second target vector with the corresponding weight coefficient to obtain a second parameter.

[0017] Optionally, the weight coefficients indicated by the second preset relationship include positive and negative coefficients; the processing module is specifically used to accumulate the product of the vector block with positive weight coefficients and the corresponding weight coefficient to obtain a first result; accumulate the product of the vector block with negative weight coefficients and the corresponding weight coefficient to obtain a second result; and obtain a second parameter based on the first result, the second result, and the third preset relationship.

[0018] Optionally, the processing module is specifically used to accumulate multiple first parameters to obtain a first target parameter; accumulate multiple second parameters to obtain a second target parameter; use the second target parameter as the high-order parameter of the checksum and the first target parameter as the low-order parameter of the checksum to obtain the checksum.

[0019] Optionally, both the first target vector and the second target vector include multiple vector blocks; the processing module is further configured to, after determining the middle vector of the last extended vector among the multiple extended vectors corresponding to each data segment as the first target vector of the corresponding data segment, perform same-position addition processing on each vector block in the first target vector, where same-position addition processing means adding the Nth bit in the high-order bits of each vector block to the Nth bit in the low-order bits of the vector block, where N is a positive integer; after sequentially accumulating the middle vector of the multiple extended vectors corresponding to each data segment with the second preset vector to obtain the second target vector of the corresponding data segment, perform same-position addition processing on each vector block in the second target vector.

[0020] Optionally, the processing module is specifically used to obtain multiple initial vectors based on the data in each data segment; each data segment corresponds to multiple initial vectors; and to perform bit expansion processing on each of the multiple initial vectors corresponding to each data segment to obtain multiple expanded vectors corresponding to each data segment.

[0021] Optionally, the processing module is specifically used to divide each of the multiple expanded vectors corresponding to each data segment into multiple vector blocks; to expand the most significant element of each vector block into multiple expanded vectors; the expansion process includes expanding the most significant element of each vector block into M preset characters, and expanding the most significant element of each vector block into M preset characters, to obtain multiple expanded vectors for each data segment; the product of M and the number of vector blocks in each expanded vector is equal to the difference between the preset value and the number of bits in the initial vector.

[0022] Optionally, the first threshold is 160 bytes; the number of bits in both the first preset vector and the second preset vector is 128; both the first preset vector and the second preset vector include 8 vector blocks; each vector block is a vector including 16-bit elements; the lower 8 bits in each vector block are all 1.

[0023] According to a third aspect of the present disclosure, an electronic device is provided, which may include: a processor and a memory for storing processor-executable instructions; wherein the processor is configured to execute instructions to implement any of the optional data verification methods in the first aspect described above.

[0024] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided, on which instructions are stored, such that when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is able to perform any of the optional data verification methods of the first aspect described above.

[0025] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising instructions that, when executed on a processor of an electronic device, cause the electronic device to perform any of the optional data verification methods of the first aspect described above.

[0026] The technical solution provided in this disclosure brings at least the following beneficial effects: Based on any of the above, in this disclosure, network transmission data can be divided into multiple data segments, each of which may include multiple bytes of data. Each data segment is vectorized and then accumulated to obtain the checksum of the network transmission data. Compared with the existing technology that calculates network transmission data sum1 and sum2 byte by byte, multiple bytes in the data segment can be processed in parallel, which improves the calculation speed, effectively reduces the CPU overhead caused by data verification, and thus can increase the number of users that a single machine can support and reduce server costs. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0028] Figure 1 This is a schematic diagram of the composition of a data transmission system provided in an embodiment of the present disclosure; Figure 2 This is a schematic diagram of the electronic device provided in the embodiments of this disclosure; Figure 3 A flowchart illustrating the data verification method provided in this embodiment of the disclosure; Figure 4 This is a schematic diagram illustrating the data verification time consumption provided in the embodiments of this disclosure; Figure 5 An initialization diagram of the first preset vector and the second preset vector provided in the embodiments of this disclosure; Figure 6 A schematic diagram of bit expansion provided for an embodiment of this disclosure; Figure 7 This is a schematic diagram of same-position addition provided in an embodiment of the present disclosure; Figure 8 Another initialization diagram of the first and second preset vectors provided in the embodiments of this disclosure; Figure 9 This is another schematic diagram of bit expansion provided in an embodiment of the present disclosure; Figure 10 This is another schematic diagram of same-position addition provided by an embodiment of the present disclosure; Figure 11 This is a schematic diagram illustrating the composition of a data verification device provided in an embodiment of this disclosure. Detailed Implementation

[0029] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0030] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0031] It should also be understood that the term "comprising" indicates the presence of the described feature, whole, step, operation, element and / or component, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements and / or components.

[0032] The data disclosed herein may be data authorized by the user or fully authorized by all parties.

[0033] The prior art involved in this disclosure is explained below.

[0034] 1. Checksum: A checksum is a sum of a set of data items used in data processing and data communication for verification purposes. It is commonly used in communication, especially in long-distance communication, to ensure the integrity and accuracy of data transmitted over a network.

[0035] 2. Fletcher checksum: Taking the 16-bit Fletcher-16 as an example, Fletcher-16 consists of two parts: the high 8 bits and the low 8 bits. The low 8 bits are obtained by summing the data being verified, and the high 8 bits are obtained by summing the low 8 bits. The specific calculation process is as follows: Step 1: Initialize both sum1 and sum2 to 16-bit integers 255.

[0036] Step 2: Divide the data to be verified into multiple data segments, each of which is 20 bytes.

[0037] Step 3: In each data segment, sum each byte and the existing sum1 to obtain sum1. Then sum the intermediate sum1 obtained from each summation and the existing sum2 to obtain sum2.

[0038] Step 4: Add the high and low 8 bits of sum1 together to make sum1 no greater than 510. Add the high and low 8 bits of sum2 together to make sum2 no greater than 510.

[0039] Step 5: Repeat the operations in Step 3 and Step 4 for each data segment until all data segments have been processed, and finally obtain the target sum1 and target sum2.

[0040] Step 6: Add the high and low 8 bits of target sum1 to make target sum1 no greater than 255. Add the high and low 8 bits of target sum2 to make target sum2 no greater than 255.

[0041] Step 7: Use the target sum2 as the high 8 bits of the checksum and the target sum1 as the low 8 bits of the checksum, and output the 16-bit checksum.

[0042] As can be seen from the specific calculation process of Fletcher-16, this scheme needs to process each byte in the data to be verified in sequence. In the scenario of high-speed data transmission network, using this scheme may consume a lot of CPU resources and the calculation speed is slow.

[0043] Based on this, the present disclosure provides a data verification method, apparatus, device, and storage medium that can process multiple bytes in a data segment divided by network transmission data in parallel using the SSE instruction set, thereby reducing the CPU resources occupied and improving the calculation speed.

[0044] The following description is provided in conjunction with the accompanying drawings.

[0045] Figure 1 This is a schematic diagram illustrating the composition of a data transmission system provided in an embodiment of this disclosure. Figure 1 As shown, the data transmission system may include a transmitter 100 and a receiver 200. The transmitter 100 and the receiver 200 may be connected via a wired network or a wireless network.

[0046] The sending end 100 can be an electronic device with computing processing capabilities, such as a computer or server. The server can be a single server or a server cluster consisting of multiple servers. In some embodiments, the server cluster can also be a distributed cluster. Optionally, the server can also be implemented on a cloud platform, such as a private cloud, public cloud, hybrid cloud, community cloud, distributed cloud, inter-cloud, and multi-cloud, or any combination thereof. This disclosure does not limit this aspect.

[0047] The sending end 100 is used to acquire (to be) transmitted network data and calculate a checksum based on the (to be) transmitted network data. The specific process of calculating the checksum based on the (to be) transmitted network data can be referred to the method embodiment below, and will not be repeated here.

[0048] In some embodiments, the sending end 100 is also used to send (to be) transmitted network data and the calculated checksum to the receiving end 200.

[0049] As described above, the sending end 100 and the receiving end 200 can be connected via a wired network or a wireless network. This wired network or wireless network may include one or more media or devices capable of transmitting network data and checksums to the receiving end 200.

[0050] In some embodiments, the wired or wireless network may include one or more communication media that enable the transmitter 100 to transmit network transmission data and checksums directly to the receiver 200 in real time. In this embodiment, the transmitter 100 may modulate the network transmission data and checksum according to a communication standard (e.g., a wireless communication protocol) and transmit the modulated network transmission data and checksum to the receiver 200. The one or more communication media may include wireless and / or wired communication media, such as radio frequency spectrum or one or more physical transmission lines. Optionally, the one or more communication media may form part of a packet-based network, such as a local area network (LAN), a wide area network (WAN), or a global network (e.g., the Internet). Optionally, the one or more communication media may include a router, switch, base station, or other devices facilitating communication from the transmitter 100 to the receiver 200.

[0051] The form of the receiver 200 can be referred to as described in the transmitter 100 above, and will not be repeated here.

[0052] The receiving end 200 is used to receive network transmission data and checksums sent by the sending end 100, and calculate the checksum based on the network transmission data. The specific process of the receiving end 200 calculating the checksum based on the network transmission data can also be referred to the method embodiments below, and will not be repeated here.

[0053] In some embodiments, the receiving end 200 is further configured to verify the network transmission data sent by the sending end 100 based on the calculated checksum and the checksum sent by the receiving end 100. The specific verification process can be found in related technologies and will not be repeated here.

[0054] The data verification method provided in this embodiment is executed by a data verification device, which can be the aforementioned sending end 100 or receiving end 200, and the sending end 100 or receiving end 200 can be collectively referred to as an electronic device. Optionally, the data verification device can also be a processor in the aforementioned electronic device; or, the data verification device can also be an application (APP) installed in the aforementioned electronic device that provides data verification function; or, the data verification device can also be a functional module in the aforementioned electronic device used to perform the data verification function, etc. This embodiment does not limit this.

[0055] For simplicity, the following method embodiments will use electronic devices as examples to illustrate the data verification device.

[0056] Figure 2 This is a schematic diagram illustrating the composition of an electronic device provided in an embodiment of this disclosure. For example... Figure 2 As shown, the electronic device may include: a processor 10, a memory 20, a communication line 30, a communication interface 40, and an input / output interface 50.

[0057] The processor 10, memory 20, communication interface 40, and input / output interface 50 can be connected via communication line 30.

[0058] Processor 10 is configured to execute instructions stored in memory 20 to implement the data verification method provided in the following embodiments of this disclosure. Processor 10 may be a CPU, a general-purpose processor, a network processor (NP), a digital signal processor (DSP), a microprocessor, a microcontroller (MCU) / single-chip microcomputer / microcontroller, a programmable logic device (PLD), or any combination thereof. Processor 10 may also be any other device with processing capabilities, such as a circuit, device, or software module; this disclosure does not limit this. In one example, processor 10 may include one or more CPUs, for example... Figure 2 CPU0 and CPU1 are included. As an optional implementation, the image display device may include multiple processors; for example, in addition to processor 10, it may also include processor 60. Figure 2 (The example shown is a dashed line).

[0059] The memory 20 is used to store instructions. For example, the instructions may be computer programs. Optionally, the memory 20 may be a read-only memory (ROM) or other type of static storage device that can store static information and / or instructions; it may also be a random access memory (RAM) or other type of dynamic storage device that can store information and / or instructions; it may also be an electrically erasable programmable read-only memory (EEPROM), a CD-ROM or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices, etc. The embodiments disclosed herein do not limit this.

[0060] It should be noted that the memory 20 may exist independently of the processor 10 or may be integrated with the processor 10. The memory 20 may be located inside or outside the electronic device, and this disclosure does not impose any restrictions on this.

[0061] Communication line 30 is used to transmit information between the components included in the electronic device.

[0062] The communication interface 40 is used to communicate with other devices (such as the aforementioned transmitter 100 or receiver 200) or other communication networks. These other communication networks can be Ethernet, radio access network (RAN), wireless local area network (WLAN), etc. The communication interface 40 can be a module, circuit, transceiver, or any device capable of enabling communication.

[0063] Input / output interface 50 is used to enable human-computer interaction between users and electronic devices. This includes, for example, gesture-based, text-based, or voice-based interactions between users and electronic devices.

[0064] For example, the input / output interface 50 can be a keyboard or a mouse. Action or text interaction between the user and the electronic device can be achieved through the keyboard or mouse.

[0065] It should be noted that, Figure 2 The structures shown do not constitute a limitation on electronic devices, except... Figure 2 In addition to the components shown, electronic devices may include more or fewer components than illustrated, or combinations of certain components, or different component arrangements.

[0066] The data verification method provided in the embodiments of this disclosure will now be described in conjunction with the accompanying drawings.

[0067] Figure 3 This is a flowchart illustrating the data verification method provided in an embodiment of this disclosure. Optionally, this method can be implemented by someone with the above-described... Figure 2 The electronic device with the hardware structure shown performs the operation. For example... Figure 3 As shown, the method may include S101 to S105.

[0068] S101. The electronic device acquires network transmission data and divides the network transmission data into segments such that each segment of the multiple data segments includes multiple bytes, and the number of bytes in each segment is less than or equal to a first threshold.

[0069] As described above, the electronic device can be either a transmitter or a receiver. When the electronic device is a transmitter, the network transmission data here can be understood as the data to be transmitted; when the electronic device is a receiver, the network transmission data here can be understood as the data transmitted from the transmitter. The first threshold can be preset in the electronic device by the administrator. For example, the first threshold can be 160 bytes or 2872 bytes, etc. This disclosure embodiment does not limit the specific number of bytes for the first threshold.

[0070] For example, as described above, the electronic device may include an input / output interface, which may include a mouse and a keyboard, etc. The electronic device can receive a first threshold of input from the administrator via the mouse and keyboard, etc.

[0071] For example, taking 105 bytes of network transmission data as an example, assuming the first threshold is 20 bytes, the electronic device can divide the 105 bytes of network transmission data into 5 data segments in the manner of each 20-byte segment, and take the last 5 bytes of network transmission data as the remaining data segment. The processing of the remaining data segment can be referred to the method embodiment below, and will not be repeated here.

[0072] S102. The electronic device performs expansion processing on each data segment to obtain multiple expansion vectors for each data segment, such that the number of bits of each expansion vector is the same as the number of bits of the elements in the first preset vector and the second preset vector, which are all preset values.

[0073] Each data segment corresponds to multiple extended vectors. The preset values ​​can be preset in the electronic device by the administrator; for example, the preset value can be 128 or other values, and this embodiment does not limit this.

[0074] In one possible implementation, S102 above may specifically include the following two steps: Step 1: The electronic device obtains multiple initial vectors based on the data in each data segment.

[0075] Each data segment corresponds to multiple initial vectors.

[0076] For example, an electronic device can use network transmission data in a data segment as elements in an initial vector to obtain an initial vector. The initial vector can include multiple vector blocks, and each vector block corresponds one-to-one with each byte in the data segment.

[0077] For example, if the network transmission data of a certain two bytes is “00000000 11111111”, then the initial vector obtained from the data of the two bytes is the initial vector composed of the vector block [0, 0, 0, 0, 0, 0, 0] and the vector block [1, 1, 1, 1, 1, 1, 1, 1].

[0078] Step 2: The electronic device performs bit expansion processing on each of the multiple initial vectors corresponding to each data segment to obtain multiple expanded vectors corresponding to each data segment.

[0079] For example, an electronic device can divide each of the multiple extended vectors corresponding to each data segment into multiple vector blocks for each extended vector, and then extend the highest bit element of each vector block (or each vector block) to obtain multiple extended vectors.

[0080] The expansion process includes expanding the most significant element of each vector in the multiple vector blocks by M preset characters. The product of M and the number of vector blocks in each expanded vector is equal to the difference between the preset value and the number of bits in the initial vector. The preset characters can be 0 or other characters, etc., and this embodiment of the disclosure does not limit this.

[0081] For example, taking the first preset vector and the second preset vector as examples where the number of bits (preset value) of the elements is 128 bits, assuming that the initial vector includes 8 vector blocks, each of which is an 8-bit vector, that is, the number of bits of the elements in the initial vector is 8×8=64, then the electronic device can add 8 (that is, the above M) zeros before the highest bit element of each of the 8 vector blocks, at which time 8×8=128-64.

[0082] S103. The electronic device performs a first accumulation process on the multiple expansion vectors corresponding to each data segment, so as to determine the vector after accumulation of each expansion vector as the intermediate vector of each expansion vector, and determines the last expansion vector among the multiple expansion vectors corresponding to each data segment as the first target vector of the corresponding data segment.

[0083] The first accumulation process includes sequentially accumulating multiple extended vectors corresponding to each data segment to a first preset vector.

[0084] For example, taking multiple extended vectors of a data segment including A=[a1, a2, a3], B=[b1, b2, b3], and C=[c1, c2, c3] as an example, assuming the first preset vector is D=[d1, d2, d3], the electronic device can first add vector A to the first preset vector D to obtain the intermediate vector A1=[a1+d1, a2+d2, a3+d3] of vector A, and then add vector B to the extended vector A. The intermediate vectors A1 are added together to obtain the intermediate vector B1 of vector B = [a1+d1+b1, a2+d2+b2, a3+d3+b3]. Then, vector C is added to the intermediate vector B1 of vector B to obtain the intermediate vector C1 of vector C = [a1+d1+b1+c1, a2+d2+b2+c2, a3+d3+b3+c3]. Finally, the intermediate vector C1 of the last vector C is taken as the first target vector of this data segment.

[0085] Optionally, the first target vector and the second target vector may include multiple vector blocks. After S103 above, the electronic device may also perform on-the-spot addition on each vector block in the first target vector.

[0086] The same-bit addition process refers to adding the Nth bit of the high-order bits of each vector block to the Nth bit of the low-order bits of that vector block, where N is a positive integer.

[0087] For example, taking the hexadecimal string "0x6677" as an example, the high 8 bits "66" of this string can be represented as "0110 0110" in binary, and the low 8 bits "77" can be represented as "0111 0111" in binary. Adding the same bits means adding the 8th bit "0" in the high 8 bits to the 8th bit "1" in the low 8 bits, and getting the 8th bit "1" in the result. Then, add the 7th bit "1" in the high 8 bits to the 7th bit "1" in the low 8 bits, and get the 7th bit "0" in the result. Carry 1 to the next bit, and so on, to get the result of adding the same bits "1101 1101", which is represented as "0x00DD" in hexadecimal.

[0088] S104. The electronic device performs a second accumulation process on the intermediate vector of the multiple extended vectors corresponding to each data segment, so as to determine the finally accumulated vector as the second target vector of the corresponding data segment.

[0089] The second accumulation process includes sequentially accumulating the intermediate vectors of the multiple expanded vectors corresponding to each data segment to the second preset vector.

[0090] For example, taking multiple extended vectors of a certain data segment as an example, including A=[a1, a2, a3], B=[b1, b2, b3], and C=[c1, c2, c3], assuming the first preset vector is D=[d1, d2, d3] and the second preset vector is E=[e1, e2, e3], the electronic device can first add vector A to the first preset vector D to obtain the first intermediate vector A1=[a1+d1, a2+d3]. 2, a3+d3], then add the intermediate vector A1 of the extended vector A to the second preset vector E to obtain the second intermediate vector A2 of vector A = [a1+d1+e1, a2+d2+e2, a3+d3+e3]. Then add vector B to the first intermediate vector A1 of vector A to obtain the first intermediate vector B1 of vector B = [a1+d1+b1, a2+d2+b2, a3+d3+b3]. Then add B1 to A2 to obtain The second intermediate vector of vector B, B2, is given by: [a1+d1+b1+a1+d1+e1, a2+d2+b2+a2+d2+e2, a3+d3+b3+a3+d2+e3]. Then, vector C is added to the first intermediate vector B1 of vector B, resulting in the first intermediate vector C1 of vector C, which is given by: [a1+d1+b1+c1, a2+d2+b2+c2, a3+d3+b3+c3]. Finally, the first intermediate vector of vector C is... Add C1 and the second intermediate vector B2 of vector B to obtain the second intermediate vector C2 of vector C = [a1+d1+b1+c1+a1+d1+b1+a1+d1+e1,a2+d2+b2+c2+a2+d2+b2+a2+d2+e2,a3+d3+b3+c3+a3+d3+b3+a3+d2+e3]. Finally, the second intermediate vector C2 of the last vector C is used as the second target vector of this data segment.

[0091] Optionally, after S104 above, the electronic device may also perform same-position addition processing on the second target vector. Same-position addition processing can be referred to in S103 above, and will not be repeated here.

[0092] It should be understood that data overflow may occur during the process of accumulating the extended vector to the first preset vector to obtain the first target vector, and accumulating the first preset vector to the second preset vector to obtain the second target vector. In this embodiment of the present disclosure, by performing the same-position addition process on the first target vector and the second target vector, the elements in the first vector and the second vector can be folded, thereby avoiding data overflow.

[0093] S105. The electronic device determines a checksum for verifying network-transmitted data based on the first target vector of each data segment and the second target vector of each data segment.

[0094] In one possible implementation, S105 above may specifically include the following three steps: Step 1: The electronic device determines the first parameter of each data segment based on the first target vector and the first preset relationship of each data segment, thus obtaining multiple first parameters.

[0095] In one possible implementation, as described above, the electronic device can divide the extended vector into multiple vector blocks. The first and second target vectors after accumulation can also include multiple vector blocks, and the number of vector blocks in the extended vector, the first target vector, and the second target vector are the same. In this case, the first preset relationship can be used to indicate the weight coefficients of the multiple vector blocks in each first target vector. Step 1 can specifically include: the electronic device multiplies each vector block in the first target vector block with the corresponding weight coefficient in the first preset relationship, and accumulates the results of dividing each vector block in the first target vector with its corresponding weight coefficient to obtain the first parameter.

[0096] Step 2: The electronic device determines the second parameter of each data segment based on the second target vector and the second preset relationship of each data segment, thus obtaining multiple second parameters.

[0097] In one possible implementation, taking the above-mentioned electronic device dividing the extended vector into multiple vector blocks as an example, the second preset relationship can be used to indicate the weight coefficients of multiple vector blocks in each second vector. The above step 2 can specifically include: the electronic device multiplies each vector block in the second target vector with the corresponding weight coefficient in the second preset relationship, and accumulates the results after multiplying each vector block in the second target vector with the corresponding weight coefficient to obtain the second parameter.

[0098] Optionally, the weight coefficients indicated by the second preset relationship may include positive and negative coefficients. In this case, the electronic device accumulates the results of multiplying each vector block in the second target vector with its corresponding weight coefficient to obtain the second parameter. Specifically, this may include: the electronic device accumulating the product of vector blocks with positive weight coefficients with their corresponding weight coefficients to obtain the first result; the electronic device accumulating the product of vector blocks with negative weight coefficients with their corresponding weight coefficients to obtain the second result; and the electronic device obtaining the second parameter based on the first result, the second result, and the third preset relationship. The third preset relationship is used to indicate the coefficients of the first result and the second result. The coefficient of the first result is 2 to the power of P, where P is half the number of bits in the checksum, and the coefficient of the second result is -1.

[0099] For example, an electronic device can multiply a first result by a coefficient of the first result to obtain a first target result, multiply a second result by a coefficient of the second result to obtain a second target result, and add the first target result and the second target result to obtain a second parameter.

[0100] It should be understood that the accumulation of positive and negative coefficients may lead to non-negative integer overflow. The embodiments of this disclosure can avoid data overflow by calculating vector blocks with positive and negative weight coefficients separately.

[0101] Step 3: The electronic device determines the checksum of the network transmission data based on multiple first parameters and multiple second parameters.

[0102] For example, an electronic device can accumulate multiple first parameters to obtain a first target parameter, and accumulate multiple second parameters to obtain a second target parameter. The sum of the number of bits of the first target parameter and the second target parameter is equal to the number of bits of the checksum of the network transmission data. The second target parameter is used as the high-order bit of the checksum, and the first target parameter is used as the low-order bit of the checksum to obtain the checksum.

[0103] The data verification method provided in this disclosure can divide network transmission data into multiple data segments, each of which includes multiple bytes of data. After vectorizing each data segment, the data segments are accumulated to obtain the checksum of the network transmission data. Compared with the existing technology that calculates the network transmission data sum1 and sum2 byte by byte, the multiple bytes in the data segment can be processed in parallel, which improves the calculation speed, effectively reduces the CPU overhead caused by data verification, increases the number of users that a single machine can support, and reduces the server cost.

[0104] For example, Figure 4 This diagram illustrates the data verification time consumption provided in an embodiment of this disclosure. Figure 4 As shown, the data verification method provided in this disclosure offers performance improvements over existing solutions across all data scales. As the scale of network-transmitted data increases, the performance advantage of the data verification method provided in this disclosure further expands.

[0105] In some possible embodiments, the data verification method provided by this disclosure is described using a 16-bit checksum as an example. In the case of a 16-bit checksum, the data verification method provided by this disclosure may include the following steps: X1. The electronic device initializes both the first preset vector and the second preset vector into 8 vector blocks, and sets the lower 8 bits of each vector block to 1.

[0106] Each vector block contains 16-bit elements.

[0107] For example, Figure 5This diagram illustrates the initialization of the first and second preset vectors provided in embodiments of this disclosure. Figure 5 As shown, the first preset vector ( Figure 6 (Taking Sum1 as an example) It includes 8 vector blocks, and the element in each vector block is "0x00ff", which is "0000 0000 1111 1111" in binary. The first preset vector includes a total of 8 × 16 = 128 bits. The second preset vector ( Figure 6 (Taking Sum2 as an example) It includes 8 vector blocks, and the elements in each vector block are also "0x00ff", which is "0000 0000 1111 1111" in binary. The second preset vector includes a total of 8 × 16 = 128 bits.

[0108] X2. The electronic device vectorizes every 8 bytes of data transmitted over the network, determines an extended vector containing 64-bit elements, obtains multiple extended vectors, and groups the multiple extended vectors into groups of 20 each, obtaining multiple groups of extended vectors.

[0109] It is understandable that the network transmission data corresponding to each set of extended vectors here can be understood as the data segment in S101 above. In this case, the first threshold can be set to 160, and the number of bytes of a data segment here is 8×20=160.

[0110] X3. For each expanded vector in each group of expanded vectors, the electronic device pads the most significant bit of each vector block in the expanded vector with 8 zeros to expand it into a vector containing 128 bits.

[0111] For example, Figure 6 This is a schematic diagram illustrating bit expansion provided for an embodiment of this disclosure. For example... Figure 6 As shown, the element "0xef (binary representation 1110 1111)" in the first vector block of the expanded vector is expanded into a vector block "0x00ef (binary representation 0000 0000 1110 1111)" containing 16 bits after being padded with 8 zeros before the highest bit. Similarly, the element "0xcd" in the second vector block is expanded to "0x00cd", the element "0xab" in the third vector block is expanded to "0x00ab", the element "0x89" in the fourth vector block is expanded to "0x0089", the element "0x67" in the fifth vector block is expanded to "0x0067", the element "0x45" in the sixth vector block is expanded to "0x0045", the element "0x23" in the seventh vector block is expanded to "0x0023", and the element "0x01" in the eighth vector block is expanded to "0x0001".

[0112] X4. For each group of expanded vectors, the electronic device sequentially adds the 20 expanded vectors in the group to the first preset vector to obtain the intermediate vector of each expanded vector, and determines the intermediate vector of the 20th expanded vector as the first target vector.

[0113] X4 can be referred to in S103 above, and will not be repeated here.

[0114] X5. For each group of expanded vectors, the electronic device sequentially adds the middle vector of the 20 expanded vectors in the group to the second preset vector to obtain the second target vector.

[0115] X5 can be referred to in S104 above, and will not be repeated here.

[0116] X6. The electronic device performs a bitwise addition of the high 8 bits and low 8 bits of each vector block in the first target vector, so that the decimal value of each element in each vector block in the first target vector is not greater than 510.

[0117] For example, Figure 7 This is a schematic diagram of same-position addition provided for embodiments of this disclosure. For example... Figure 7 As shown, the first target vector ( Figure 7 Taking Sum1 as an example, the elements in the first vector block are "0xeeff", the second vector block is "0xccdd", the third vector block is "0xaabb", the fourth vector block is "0x8899", the fifth vector block is "0x6677", the sixth vector block is "0x4455", the seventh vector block is "0x2233", and the eighth vector block is "0x0011". After performing bitwise addition on each vector block, the elements in the first vector block become "0x01ed", the elements in the second vector block become "0x01a9", the elements in the third vector block become "0x0165", the elements in the fourth vector block become "0x0121", the elements in the fifth vector block become "0x00dd", the elements in the sixth vector block become "0x0099", the elements in the seventh vector block become "0x0055", and the elements in the eighth vector block become "0x0011".

[0118] X7. The electronic device performs a bitwise addition of the high 8 bits and low 8 bits of each vector block in the second target vector, so that the decimal value of each element in each vector block in the second target vector is not greater than 510.

[0119] X7 can be referred to the above description of X6, and will not be repeated here.

[0120] X8. The electronic device determines the first parameter of the set of extended vectors based on the first target vector and the first preset relationship.

[0121] The first preset relationship can be represented by the following formula (1): Formula (1) In formula (1), Indicates the first parameter; This represents the first vector block out of the eight vector blocks representing the first target vector. This represents the second vector block out of the eight vector blocks representing the first target vector. This represents the third vector block out of the eight vector blocks representing the first target vector. This represents the fourth vector block out of the eight vector blocks representing the first target vector. This represents the fifth vector block out of the eight vector blocks representing the first target vector. This represents the sixth vector block out of the eight vector blocks representing the first target vector. This represents the seventh vector block out of the eight vector blocks representing the first target vector. This represents the eighth vector block out of the eight vector blocks representing the first target vector.

[0122] X9. The electronic device determines the second parameter of the set of extended vectors based on the second target vector and the second preset relationship.

[0123] Optionally, the second preset relationship can be as shown in the following formula (2): Formula (2) In formula (2), Indicates the second parameter; This represents the first of eight vector blocks representing the second target vector. This represents the second vector block out of the eight vector blocks representing the second target vector. This represents the third vector block out of the eight vector blocks representing the second target vector. This represents the fourth vector block out of the eight vector blocks representing the second target vector. This represents the fifth vector block out of the eight vector blocks representing the second target vector. This represents the sixth vector block out of the eight vector blocks representing the second target vector. This represents the seventh vector block out of the eight vector blocks representing the second target vector. This represents the eighth vector block out of the eight vector blocks representing the second target vector.

[0124] Alternatively, the second preset relationship can also be as shown in formulas (3) to (5) below: Formula (3) Formula (3) can also be understood as the third preset relationship when the checksum is 16 bits. 256 is also the coefficient of the first result mentioned above. When the checksum is 16 bits, half of the checksum bits is 8 (that is, P mentioned above). 2 to the power of 8 is also the coefficient 256 of the first result in formula (3).

[0125] Formula (4) In formula (4), This represents the first result when the checksum is 16 bits.

[0126] Formula (5) In formula (5), This represents the second result when the checksum is 16 bits.

[0127] Optionally, after calculating the first result, the electronic device can also perform two bitwise additions on the high 8 bits and low 8 bits of the first result to ensure that the decimal value of the first result is no greater than 255.

[0128] Optionally, after calculating the second result, the electronic device can also perform two bitwise additions on the high 8 bits and low 8 bits of the second result to ensure that the decimal value of the second result is no greater than 255. X10. The electronic device adds the high 8 bits and low 8 bits of the first parameter in the same position so that the first parameter is not greater than 510.

[0129] X11. The electronic device adds the high 8 bits and low 8 bits of the second parameter in the same position so that the second parameter is not greater than 510.

[0130] X12. The electronic device accumulates the first parameters of multiple sets of extended vectors and the remaining less than 8 bytes of data in the network transmission data to obtain the first intermediate parameter.

[0131] X13. The electronic device adds the first intermediate parameter to the second parameter to obtain the second intermediate parameter.

[0132] X14. The electronic device adds the high 8 bits and low 8 bits of the first intermediate parameter and the high 8 bits and low 8 bits of the second intermediate parameter twice, respectively, to obtain the first target parameter and the second target parameter whose decimal values ​​are not greater than 255.

[0133] X15. The electronic device uses the second target parameter as the high 8 bits of the checksum of the network transmission data and the first target parameter as the low 8 bits of the checksum of the network transmission data, and outputs the checksum of the network transmission data.

[0134] In other possible embodiments, the data verification method provided by this disclosure is described using a 32-bit checksum as an example. In the case of a 32-bit checksum, the data verification method provided by this disclosure may include the following steps: C1. The electronic device initializes both the first preset vector and the second preset vector into 4 vector blocks, and sets the lower 16 bits of each vector block to 1.

[0135] Each vector block contains 32-bit elements.

[0136] For example, Figure 8 This is another initialization diagram of the first and second preset vectors provided in the embodiments of this disclosure. (See diagram below.) Figure 8 As shown, the first preset vector ( Figure 8 (Taking Sum1 as an example) It includes 4 vector blocks, each containing the element "0x0000ffff", which in binary is "0000 0000 0000 0000 1111 11111111 1111". The first preset vector contains a total of 4 × 32 = 128 bits. The second preset vector ( Figure 8 (Taking Sum2 as an example) It includes 4 vector blocks, and the elements in each vector block are also "0x0000ffff", which is "00000000 0000 0000 1111 1111 1111 1111" in binary. The second preset vector includes a total of 4 × 32 = 128 bits.

[0137] C2. The electronic device vectorizes every 8 bytes of data transmitted over the network, determines an extended vector containing 64-bit elements, obtains multiple extended vectors, and groups the multiple extended vectors into groups of 359 each, obtaining multiple groups of extended vectors.

[0138] It is understandable that the network transmission data corresponding to each set of extended vectors here can be understood as the data segment in S101 above. In this case, the first threshold can also be set to 2872, so the number of bytes of a data segment here is 8×359=2872.

[0139] C3. For each expanded vector in each group of expanded vectors, the electronic device pads the most significant bit of each vector block in the expanded vector with 16 zeros to expand it into a vector containing 128 bits.

[0140] For example, Figure 9 This is a schematic diagram illustrating another bit expansion method provided in an embodiment of this disclosure. For example... Figure 9As shown, the element "0xcdef" (binary representation 1100 1101 1110 1111) in the first vector block of the expanded vector is expanded by adding 16 zeros before the most significant bit, resulting in a 32-bit vector block "0x0000cdef" (binary representation 0000 0000 00000000 1100 1101 1110 1111)". Similarly, the element "0x89ab" in the second vector block is expanded to "0x000089ab", the element "0x4567" in the third vector block is expanded to "0x00004567", and the element "0x0123" in the fourth vector block is expanded to "0x00000123".

[0141] C4. For each group of expanded vectors, the electronic device sequentially adds the 20 expanded vectors in the group to the first preset vector to obtain the intermediate vector of each expanded vector, and determines the intermediate vector of the 20th expanded vector as the first target vector.

[0142] C4 can be referred to in S103 above, and will not be repeated here.

[0143] C5. For each group of expanded vectors, the electronic device sequentially adds the middle vector of the 20 expanded vectors in the group to the second preset vector to obtain the second target vector.

[0144] C5 can be referred to in S104 above, and will not be repeated here.

[0145] C6. The electronic device performs bitwise addition on the high 16 bits and low 16 bits of each vector block in the first target vector so that the decimal value of each element in the first target vector is not greater than 131070.

[0146] For example, Figure 10 This is another schematic diagram of same-position addition provided by an embodiment of this disclosure. For example... Figure 10 As shown, the first target vector ( Figure 10 Taking Sum1 as an example, the element in the first vector is "0x66667777", the element in the second vector block is "0x44445555", the element in the third vector block is "0x22223333", and the element in the fourth vector block is "0x00001111". After performing bitwise addition on each vector block, the element in the first vector block becomes "0x0000dddd", the element in the second vector block becomes "0x00009999", the element in the third vector block becomes "0x00005555", and the element in the fourth vector block becomes "0x00001111".

[0147] C7. The electronic device determines the first parameter of the set of extended vectors based on the first target vector and the first preset relationship.

[0148] The first preset relationship can be represented by the following formula (6): Formula (6) In formula (6), Indicates the first parameter; This represents the first vector block out of the four vector blocks representing the first target vector. This represents the second vector block out of the four vector blocks representing the first target vector. This represents the third vector block out of the four vector blocks representing the first target vector. This represents the fourth vector block out of the four vector blocks representing the first target vector.

[0149] C8. The electronic device determines the second parameter of the set of extended vectors based on the second target vector and the second preset relationship.

[0150] Optionally, the second preset relationship can be as shown in the following formula (7): Formula (7) In formula (7), Indicates the second parameter; This represents the first of four vector blocks representing the second target vector. This represents the second vector block out of the four vector blocks representing the second target vector. This represents the third vector block out of the four vector blocks representing the second target vector. This represents the fourth vector block out of the four vector blocks representing the second target vector.

[0151] Alternatively, the second preset relationship can also be as shown in formulas (8) to (10) below: Formula (8) Formula (8) can also be understood as the third preset relationship when the checksum is 32 bits. 65536 is the coefficient of the first result in the third preset relationship. When the checksum is 32 bits, half of the checksum bits is 16 (that is, P above). 2 to the power of 16 is the coefficient of the first result in formula (8), 65536.

[0152] Formula (9) In formula (9), This represents the first result when the checksum is 32 bits.

[0153] Formula (10) In formula (10), This represents the second result when the checksum is 32.

[0154] Optionally, after calculating the first result, the electronic device can also perform two bitwise additions on the high 16 bits and low 16 bits of the first result to ensure that the decimal value of the first result is no greater than 65535.

[0155] Optionally, after calculating the second result, the electronic device can also perform two bitwise additions on the high 16 bits and low 16 bits of the second result to ensure that the decimal value of the second result is no greater than 65535.

[0156] C9. The electronic device adds the high 16 bits and low 16 bits of the first parameter in the same position so that the first parameter is not greater than 131070.

[0157] C10. The electronic device adds the high 16 bits and low 16 bits of the second parameter in the same position so that the second parameter is not greater than 131070.

[0158] C11. The electronic device adds the first parameters of multiple sets of extended vectors and the remaining less than 8 bytes of data in the network transmission data to obtain the first intermediate parameter.

[0159] C12. The electronic device adds the first intermediate parameter to the second parameter to obtain the second intermediate parameter.

[0160] C13. The electronic device adds the high 16 bits and low 16 bits of the first intermediate parameter and the high 16 bits and low 16 bits of the second intermediate parameter twice, respectively, to obtain the first target parameter and the second target parameter whose decimal values ​​are not greater than 65535.

[0161] C14. The electronic device uses the second target parameter as the high 16 bits of the checksum of the network transmission data and the second target parameter as the low 16 bits of the checksum of the network transmission data, and outputs the checksum of the network transmission data.

[0162] It is understood that, in actual implementation, the data verification device described in the embodiments of this disclosure may include one or more hardware structures and / or software modules for implementing the aforementioned corresponding data verification methods. These hardware structures and / or software modules can constitute an electronic device. Those skilled in the art should readily recognize that, based on the algorithm steps of the various examples described in conjunction with the embodiments disclosed herein, this disclosure can be implemented in hardware or a combination of hardware and computer software. Whether a function is implemented in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0163] Based on this understanding, this disclosure also provides a data verification device. Figure 11 This is a schematic diagram illustrating the composition of the data verification device provided in an embodiment of this disclosure. Figure 11 As shown, the data verification device includes an acquisition module 1101 and a processing module 1102.

[0164] The acquisition module 1101 is used to acquire network transmission data and divide the network transmission data so that each data segment in the multiple data segments obtained by division includes multiple bytes, and the number of bytes in each data segment is less than or equal to a first threshold. Processing module 1102 is used to expand each data segment to obtain multiple expanded vectors, such that the number of bits in each expanded vector is the same as the number of bits in the first and second preset vectors, and both are preset values; each data segment corresponds to multiple expanded vectors; a first accumulation process is performed on the multiple expanded vectors corresponding to each data segment to determine the vector obtained after accumulation of each expanded vector as the intermediate vector of each expanded vector, and the intermediate vector of the last expanded vector among the multiple expanded vectors corresponding to each data segment is determined as the first target vector of the corresponding data segment; the first accumulation process includes sequentially accumulating the multiple expanded vectors corresponding to each data segment to the first preset vector; a second accumulation process is performed on the intermediate vectors of the multiple expanded vectors corresponding to each data segment to determine the vector obtained by the final accumulation as the second target vector of the corresponding data segment; the second accumulation process includes sequentially accumulating the intermediate vectors of the multiple expanded vectors corresponding to each data segment to the second preset vector; and a checksum for verifying network transmission data is determined based on the first target vector and the second target vector of each data segment.

[0165] In some possible embodiments, each data segment's first target vector and second target vector both include multiple vector blocks; the processing module 1102 is specifically used to determine a first parameter of each data segment based on the first target vector of each data segment and a first preset relationship, thereby obtaining multiple first parameters; the first preset relationship is used to indicate the weight coefficients of the multiple vector blocks in each first target vector; based on the second target vector of each data segment and the second preset relationship, determine a second parameter of each data segment, thereby obtaining multiple second parameters; the second preset relationship is used to indicate the weight coefficients of the multiple vector blocks in each second target vector; and based on the multiple first parameters and the multiple second parameters, determine a checksum used to verify the network transmission data.

[0166] In other possible embodiments, the processing module 1102 is specifically used to multiply each vector block in the first target vector with the corresponding weight coefficient in the first preset relationship, and to accumulate the results of multiplying each vector block in the first target vector with the corresponding weight coefficient to obtain a first parameter; and to multiply each vector block in the second target vector with the corresponding weight coefficient in the second preset relationship, and to accumulate the results of multiplying each vector block in the second target vector with the corresponding weight coefficient to obtain a second parameter.

[0167] In some other possible embodiments, the weight coefficients indicated by the second preset relationship include positive and negative coefficients; the processing module 1102 is specifically used to accumulate the product of the vector block with positive weight coefficients and the corresponding weight coefficient to obtain a first result; accumulate the product of the vector block with negative weight coefficients and the corresponding weight coefficient to obtain a second result; and obtain a second parameter based on the first result, the second result, and the third preset relationship.

[0168] In some other possible embodiments, the processing module 1102 is specifically used to accumulate multiple first parameters to obtain a first target parameter; accumulate multiple second parameters to obtain a second target parameter; use the second target parameter as the high-order parameter of the checksum and the first target parameter as the low-order parameter of the checksum to obtain the checksum.

[0169] In some other possible embodiments, both the first target vector and the second target vector include multiple vector blocks; the processing module 1102 is further configured to, after determining the middle vector of the last extended vector among the multiple extended vectors corresponding to each data segment as the first target vector of the corresponding data segment, perform same-position addition processing on each vector block in the first target vector, where same-position addition processing means adding the Nth bit in the high bits of each vector block to the Nth bit in the low bits of the vector block, where N is a positive integer; after sequentially accumulating the middle vector of the multiple extended vectors corresponding to each data segment with the second preset vector to obtain the second target vector of the corresponding data segment, perform same-position addition processing on each vector block in the second target vector.

[0170] In some other possible embodiments, the processing module 1102 is specifically used to obtain multiple initial vectors based on the data in each data segment; each data segment corresponds to multiple initial vectors; and to perform bit expansion processing on each of the multiple initial vectors corresponding to each data segment to obtain multiple expanded vectors corresponding to each data segment.

[0171] In some other possible embodiments, the processing module 1102 is specifically used to divide each of the multiple expanded vectors corresponding to each data segment into multiple vector blocks; to expand the most significant element of each vector block into multiple expanded vectors; the expansion process includes expanding M preset characters before the most significant element of each vector block into multiple expanded vectors, and expanding M preset characters before the most significant element of each vector block into multiple expanded vectors, to obtain multiple expanded vectors for each data segment; the product of M and the number of vector blocks in each expanded vector is equal to the difference between the preset value and the number of bits of the elements in the initial vector.

[0172] In some other possible embodiments, the first threshold is 160 bytes; the number of bits in both the first preset vector and the second preset vector is 128; both the first preset vector and the second preset vector include 8 vector blocks; each vector block is a vector including 16-bit elements; and the lower 8 bits in each vector block are all 1.

[0173] As described above, the embodiments of this disclosure can divide the storage device into functional modules according to the above method examples. The integrated modules can be implemented in hardware or as software functional modules. Furthermore, it should be noted that the module division in these embodiments is illustrative and represents only one logical functional division; in actual implementation, other division methods may be used. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into a single processing module.

[0174] Regarding the data verification device in the above embodiments, the specific methods of operation of each module and its beneficial effects have been described in detail in the foregoing method embodiments, and will not be repeated here.

[0175] This disclosure also provides a computer-readable storage medium including instructions stored thereon, which, when executed by a processor of a data verification device, enables the data verification device to perform the data verification method provided in the embodiments described above. For example, the computer-readable storage medium may be a memory 20 including instructions, which may be executed by a processor of the data verification device (the aforementioned electronic device) to complete the above method.

[0176] Optionally, the computer-readable storage medium may be a non-transitory computer-readable storage medium, such as ROM, RAM, CD-ROM, magnetic tape, floppy disk, and optical data storage device.

[0177] This disclosure also provides a computer program product containing instructions that, when run on an electronic device, causes the electronic device to perform the data verification method provided in the embodiments described above.

[0178] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0179] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A data verification method, characterized in that, The method includes: The network transmission data is acquired and divided into segments such that each segment includes multiple bytes, and the number of bytes in each segment is less than or equal to a first threshold. Each data segment is expanded to obtain multiple expanded vectors, such that each expanded vector has the same number of bits as the elements in the first and second preset vectors, and both are preset values; each data segment corresponds to multiple expanded vectors. A first accumulation process is performed on the multiple extended vectors corresponding to each data segment, so that the vector obtained after accumulating each extended vector is determined as the intermediate vector of each extended vector, and the intermediate vector of the last extended vector among the multiple extended vectors corresponding to each data segment is determined as the first target vector of the corresponding data segment; the first accumulation process includes: taking the first preset vector as the initial accumulation value, adding each extended vector to the current accumulation value in sequence according to the order of the multiple extended vectors corresponding to the data segment, determining the vector obtained by each addition as the intermediate vector corresponding to the extended vector, and taking the vector obtained by each addition as the new accumulation value, and determining the intermediate vector of the last extended vector corresponding to the data segment as the first target vector; A second accumulation process is performed on the intermediate vectors of the multiple expanded vectors corresponding to each data segment to determine the final accumulated vector as the second target vector of the corresponding data segment. The second accumulation process includes: for the first expanded vector among the multiple expanded vectors corresponding to the data segment, adding the intermediate vector corresponding to the first expanded vector to the second preset vector to obtain the accumulated intermediate vector corresponding to the first expanded vector; for each expanded vector after the first expanded vector, adding the intermediate vector corresponding to the expanded vector to the accumulated intermediate vector corresponding to the previous expanded vector to obtain the accumulated intermediate vector corresponding to that expanded vector; and determining the accumulated intermediate vector of the last expanded vector as the second target vector. A checksum for verifying the network-transmitted data is determined based on a first target vector for each data segment and a second target vector for each data segment.

2. The method according to claim 1, characterized in that, Each data segment's first target vector and second target vector each include multiple vector blocks; determining the checksum for verifying the network-transmitted data based on the first target vector and the second target vector of each data segment includes: Based on the first target vector and the first preset relationship of each data segment, the first parameter of each data segment is determined, resulting in multiple first parameters; the first preset relationship is used to indicate the weight coefficients of multiple vector blocks in each first target vector. Based on the second target vector and the second preset relationship of each data segment, the second parameter of each data segment is determined, resulting in multiple second parameters; the second preset relationship is used to indicate the weight coefficients of multiple vector blocks in each second target vector. A checksum for verifying the network transmission data is determined based on the plurality of first parameters and the plurality of second parameters.

3. The method according to claim 2, characterized in that, The step of determining the first parameter of each data segment based on the first target vector and the first preset relationship of each data segment includes: The first parameter is obtained by multiplying each vector block in the first target vector with the corresponding weight coefficient in the first preset relationship, and then summing the results of multiplying each vector block in the first target vector with the corresponding weight coefficient. The step of determining the second parameter of each data segment based on the second target vector and the second preset relationship of each data segment includes: The second parameter is obtained by multiplying each vector block in the second target vector with the corresponding weight coefficient in the second preset relationship, and then summing the results of multiplying each vector block in the second target vector with the corresponding weight coefficient.

4. The method according to claim 3, characterized in that, The weighting coefficients indicated by the second preset relationship include positive and negative coefficients; The step of summing the results of multiplying each vector block in the second target vector with its corresponding weight coefficient to obtain the second parameter includes: The first result is obtained by accumulating the product of the vector blocks with positive weight coefficients and their corresponding weight coefficients. The second result is obtained by accumulating the product of the vector blocks with negative weight coefficients and their corresponding weight coefficients. The second parameter is obtained based on the first result, the second result, and the third preset relationship.

5. The method according to any one of claims 2-4, characterized in that, The step of determining a checksum for verifying the network transmission data based on the plurality of first parameters and the plurality of second parameters includes: The first parameters are accumulated to obtain the first target parameter; The multiple second parameters are accumulated to obtain the second target parameter; The checksum is obtained by using the second target parameter as the high-order parameter of the checksum and the first target parameter as the low-order parameter of the checksum.

6. The method according to claim 1, characterized in that, Both the first target vector and the second target vector comprise multiple vector blocks; the method further includes: After determining the middle vector of the last extended vector among the multiple extended vectors corresponding to each data segment as the first target vector of the corresponding data segment, perform same-position addition processing on each vector block in the first target vector. The same-position addition processing means adding the Nth bit in the high bits of each vector block to the Nth bit in the low bits of the vector block, where N is a positive integer. After sequentially accumulating the intermediate vector of the multiple extended vectors corresponding to each data segment with the second preset vector to obtain the second target vector of the corresponding data segment, the same-position addition process is performed on each vector block in the second target vector.

7. The method according to claim 1, characterized in that, The process of expanding each data segment yields multiple expanded vectors, including: Based on the data in each data segment, multiple initial vectors are obtained; each data segment corresponds to multiple initial vectors. Each initial vector in the plurality of initial vectors corresponding to each data segment is subjected to bit expansion processing to obtain the plurality of expanded vectors corresponding to each data segment.

8. The method according to claim 7, characterized in that, The step of performing bit-expansion processing on each of the multiple initial vectors corresponding to each data segment to obtain multiple expanded vectors corresponding to each data segment includes: Each initial vector is divided to obtain multiple vector blocks corresponding to the initial vector; the highest bit element of each vector block corresponding to the initial vector is expanded to obtain multiple expanded vectors; the expansion process includes expanding the highest bit element of each vector block by M preset characters, where the product of M and the number of vector blocks in each expanded vector is equal to the difference between the preset value and the number of bits in the initial vector.

9. The method according to claim 1, characterized in that, The first threshold is 160 bytes; the number of bits in the elements of the first preset vector and the second preset vector is 128; the first preset vector and the second preset vector each include 8 vector blocks; each vector block is a vector including 16-bit elements; the lower 8 bits of each vector block are all 1.

10. A data verification device, characterized in that, The device includes: The acquisition module is used to acquire network transmission data and divide the network transmission data so that each data segment in the multiple data segments obtained by the division includes multiple bytes, and the number of bytes in each data segment is less than or equal to a first threshold. The processing module is used to expand each data segment to obtain multiple expanded vectors, such that the number of bits in each expanded vector is the same as the number of bits in the first and second preset vectors, and both are preset values; each data segment corresponds to multiple expanded vectors; a first accumulation process is performed on the multiple expanded vectors corresponding to each data segment, so that the vector obtained after accumulating each expanded vector is determined as the middle vector of each expanded vector, and the middle vector of the last expanded vector in the multiple expanded vectors corresponding to each data segment is determined as the first target vector of the corresponding data segment; the first accumulation process includes: taking the first preset vector as the initial accumulation value, sequentially adding each expanded vector to the current accumulation value according to the order of the multiple expanded vectors corresponding to the data segment, determining the vector obtained by each addition as the middle vector corresponding to that expanded vector, and taking the vector obtained by each addition as the new accumulation value, and setting the data segment to... The intermediate vector of the last extended vector is determined as the first target vector; a second accumulation process is performed on the intermediate vectors of the multiple extended vectors corresponding to each data segment to determine the finally accumulated vector as the second target vector of the corresponding data segment; the second accumulation process includes: for the first extended vector among the multiple extended vectors corresponding to the data segment, adding the intermediate vector corresponding to the first extended vector to the second preset vector to obtain the accumulated intermediate vector corresponding to the first extended vector; for each extended vector after the first extended vector, adding the intermediate vector corresponding to the extended vector to the accumulated intermediate vector corresponding to the previous extended vector to obtain the accumulated intermediate vector corresponding to that extended vector; the accumulated intermediate vector of the last extended vector is determined as the second target vector; and a checksum for verifying the network transmitted data is determined according to the first target vector of each data segment and the second target vector of each data segment.

11. An electronic device, characterized in that, The electronic device includes: a processor and a memory; The memory stores instructions that the processor can execute; When the processor is configured to execute the instructions, it causes the electronic device to implement the method as described in any one of claims 1-9.

12. A computer-readable storage medium storing instructions thereon, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device performs the method as described in any one of claims 1-9.

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