Three-dimensional memory and methods of forming the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-04-26
- Publication Date
- 2026-07-24
AI Technical Summary
In existing three-dimensional memory, the parasitic capacitance effect between adjacent leads is strong, which affects the electrical performance of the memory.
By employing a staggered lead structure, adjacent leads are distributed at both ends of the word line, increasing the distance between adjacent leads. Furthermore, by forming a staggered lead structure at both ends of the word line, the parasitic capacitance effect is reduced.
It reduces the parasitic capacitance effect between adjacent leads, simplifies the memory manufacturing process, and increases storage density.
Smart Images
Figure CN117015229B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a three-dimensional memory and a method for forming the same. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.
[0003] In 3D memories such as DRAM, leads are typically required to connect to word lines and transmit external control signals. However, in current 3D memories, all leads used to connect to each word line are located at the same end of the word line, resulting in short distances between adjacent leads. This leads to strong parasitic capacitance between adjacent leads, thus affecting the electrical performance of the memory.
[0004] Therefore, how to reduce the capacitive parasitic effect between adjacent leads, thereby improving the performance of 3D memory, is a technical problem that urgently needs to be solved. Summary of the Invention
[0005] This disclosure provides some embodiments of a three-dimensional memory and a method for forming the same, which reduces the parasitic capacitance effect between adjacent leads, thereby improving the performance of the three-dimensional memory.
[0006] According to some embodiments, this disclosure provides a three-dimensional memory, including:
[0007] Substrate;
[0008] Multiple word lines are located on the substrate, each word line extends along a first direction, and each word line includes a first end and a second end opposite to the first end along the first direction. The multiple word lines are arranged at intervals along a direction perpendicular to the top surface of the substrate, and the first direction is a direction parallel to the top surface of the substrate.
[0009] Multiple leads are located on the substrate, each lead extending in a direction perpendicular to the top surface of the substrate. The multiple leads are connected to multiple word lines in a one-to-one correspondence. At least two adjacent word lines exist in the direction perpendicular to the top surface of the substrate. The lead connected to one of the word lines is located at the first end of the word line, and the lead connected to the other word line is located at the second end of the other word line.
[0010] In some embodiments, the word lines arranged at intervals along a direction perpendicular to the top surface of the substrate are sequentially ordered, and the leads connected to the odd-numbered word lines are all located at the first end of the odd-numbered word lines, and the leads connected to the even-numbered word lines are all located at the second end of the even-numbered word lines.
[0011] In some embodiments, each of the word lines includes a first end face and a second end face opposite to the first end face along the first direction;
[0012] The first end faces of the word lines, which are arranged at intervals along a direction perpendicular to the top surface of the substrate, are flush with each other, and the second end faces of the word lines are also flush with each other.
[0013] In some embodiments, the depth of the plurality of leads connected to the plurality of odd-numbered word lines gradually changes along the first direction;
[0014] The depth of the multiple leads connected to the multiple even-numbered word lines gradually changes along the first direction.
[0015] In some embodiments, the depth of the plurality of leads connected to the plurality of odd-numbered word lines gradually decreases in a direction parallel to the first end of the word line and pointing to the second end.
[0016] In a direction parallel to the second end of the word line and pointing towards the first end, the depth of the multiple leads connected to the multiple even-numbered word lines gradually decreases.
[0017] In some embodiments, the multiple leads connected to the multiple odd-numbered word lines are arranged at equal intervals along the first direction;
[0018] The multiple leads connected to the multiple even-numbered word lines are arranged at equal intervals along the first direction.
[0019] In some embodiments, along the first direction, the spacing between two leads connected to two adjacent odd-numbered word lines is equal to the spacing between two leads connected to two adjacent even-numbered word lines.
[0020] In some embodiments, the bottom surface of the lead wire connected to the word line is completely located on the word line.
[0021] In some embodiments, the bottom portion of the lead wire connected to the word line is located on the word line.
[0022] In some embodiments, each word line includes a third end and a fourth end opposite to the third end along a second direction, the second direction being parallel to the top surface of the substrate and intersecting the first direction;
[0023] The bottom portion of the lead connected to the word line of the odd-numbered position is located on the third end;
[0024] The bottom portion of the lead connected to the even-numbered word line is located on the fourth end.
[0025] In some embodiments, each word line includes a third end and a fourth end opposite to the third end along a second direction, the second direction being parallel to the top surface of the substrate and intersecting the first direction;
[0026] The bottom surface of each lead wire connected to the word line is partially located on the third end.
[0027] In some embodiments, in any two word lines spaced apart along a direction perpendicular to the top surface of the substrate, the lead connected to the word line closer to the substrate passes through the other word line; the three-dimensional memory further includes:
[0028] An isolation layer covers the sidewalls of the lead wire.
[0029] According to other embodiments, this disclosure also provides a method for forming a three-dimensional memory, comprising the following steps:
[0030] A substrate is formed, and a plurality of word lines are located on the substrate, each word line extending along a first direction, and each word line includes a first end and a second end opposite to the first end along the first direction, the plurality of word lines being spaced apart along a direction perpendicular to the top surface of the substrate, the first direction being a direction parallel to the top surface of the substrate;
[0031] Multiple leads are formed above the substrate, each lead extending in a direction perpendicular to the top surface of the substrate. The multiple leads are connected to multiple word lines in a one-to-one correspondence. At least two adjacent word lines exist in the direction perpendicular to the top surface of the substrate. The lead connected to one of the word lines is located at the first end of the word line, and the lead connected to the other word line is located at the second end of the other word line.
[0032] In some embodiments, the specific steps of forming a substrate and a plurality of word lines located on the substrate include:
[0033] A substrate is formed, and a stacked layer is located on the substrate. The stacked layer includes a first semiconductor layer and a second semiconductor layer that are alternately stacked along a direction perpendicular to the top surface of the substrate. The thickness of the second semiconductor layer is D1. The first semiconductor layer includes a plurality of channel regions arranged along a first direction and source regions and drain regions distributed on opposite sides of the channel regions along a second direction. Both the first direction and the second direction are parallel to the top surface of the substrate, and the first direction intersects the second direction.
[0034] A plurality of first openings are formed in the second semiconductor layer to expose a plurality of the channel regions, wherein the gap width between two adjacent first openings along the first direction is D2, and D1>D2;
[0035] Conductive material is deposited along the first opening to form word lines that extend along the first direction and continuously cover the plurality of channel regions arranged along the first direction.
[0036] In some embodiments, the specific steps of forming word lines that extend along the first direction and continuously cover the plurality of channel regions arranged along the first direction include:
[0037] Conductive material is deposited along multiple first openings to form multiple word lines spaced apart along a direction perpendicular to the top surface of the substrate. Each word line includes a first end face and a second end face opposite to the first end face along the first direction. The first end faces of the word lines spaced apart along a direction perpendicular to the top surface of the substrate are flush with each other, and the second end faces of the word lines are also flush with each other.
[0038] In some embodiments, the specific steps of forming multiple leads located above the substrate include:
[0039] A surface is formed that covers the word lines, and a dielectric layer is formed that fills the gaps between adjacent word lines;
[0040] The dielectric layer and a portion of the word lines are etched to form a plurality of lead slots that expose multiple word lines. At least two adjacent word lines exist in a direction perpendicular to the top surface of the substrate. The lead slot exposing one of the word lines is located at the first end of the word line, and the lead slot exposing the other word line is located at the second end of the other word line.
[0041] The conductive material is filled into the lead groove to form the lead.
[0042] In some embodiments, the specific steps for forming the lead include:
[0043] An isolation layer is formed covering the sidewalls of the lead groove;
[0044] The conductive material is filled into the lead groove to form the lead that covers the surface of the exposed word line and the surface of the isolation layer.
[0045] In some embodiments, the word lines arranged at intervals along a direction perpendicular to the top surface of the substrate are sequentially ordered; the specific steps of forming a plurality of lead slots exposing a plurality of word lines include:
[0046] The dielectric layer and a portion of the word lines are etched to form a plurality of lead slots, wherein the lead slots exposing the odd-numbered word lines are all located on the first end of the odd-numbered word lines, and the lead slots exposing the even-numbered word lines are located on the second end of the even-numbered word lines.
[0047] In some embodiments, the specific steps of forming a plurality of lead slots that expose a plurality of the word lines include:
[0048] The dielectric layer and a portion of the word lines are etched to form a plurality of lead slots, and the depth of the lead slots exposing a plurality of odd-numbered word lines gradually changes along the first direction, and the depth of the lead slots exposing a plurality of even-numbered word lines gradually changes along the first direction.
[0049] In some embodiments, the depth of the plurality of lead slots exposing a plurality of odd-numbered word lines gradually decreases in a direction parallel to the first end of the word line and pointing to the second end.
[0050] In a direction parallel to the second end of the word line and pointing towards the first end, the depth of the multiple leads connected to the multiple even-numbered word lines gradually decreases.
[0051] In some embodiments, the specific steps of forming a plurality of lead slots that expose a plurality of the word lines include:
[0052] The dielectric layer and a portion of the word lines are etched to form a plurality of lead slots, and the plurality of lead slots exposing a plurality of odd-numbered word lines are arranged at equal intervals along the first direction, and the plurality of lead slots exposing a plurality of even-numbered word lines are arranged at equal intervals along the first direction.
[0053] In some embodiments, along the first direction, the spacing between two leads connected to two adjacent odd-numbered word lines is equal to the spacing between two leads connected to two adjacent even-numbered word lines.
[0054] In some embodiments, the specific steps of forming a plurality of lead slots that expose a plurality of the word lines include:
[0055] The dielectric layer and a portion of the word lines are etched to form a plurality of lead slots, with the bottom of the lead slots exposing only the word lines.
[0056] In some embodiments, the specific steps of forming a plurality of lead slots that expose a plurality of the word lines include:
[0057] The dielectric layer and a portion of the word lines are etched to form a plurality of lead slots, and the bottom of the lead slots exposes a portion of the word lines and a portion of the dielectric layer.
[0058] In some embodiments, each word line includes a third end and a fourth end opposite to the third end along the second direction; the specific steps of forming a plurality of lead slots exposing a plurality of word lines include:
[0059] The dielectric layer and a portion of the word lines are etched to form a plurality of lead slots. The bottom portion of the lead slot on the surface of the odd-numbered word lines exposes the third end and partially exposes the dielectric layer. The bottom portion of the lead slot on the surface of the even-numbered word lines exposes the fourth end and partially exposes the dielectric layer.
[0060] This disclosure provides a three-dimensional memory and its formation method in some embodiments. By having at least two adjacent word lines along a direction perpendicular to the top surface of the substrate, with a lead connected to one of the word lines located at a first end of the word line and a lead connected to the other word line located at a second end of the other word line, the leads of the two adjacent word lines are distributed at both ends of the word lines, achieving a staggered lead structure. This increases the distance between the two adjacent leads and reduces the capacitive parasitic effect between adjacent leads. Furthermore, this disclosure uses a staggered lead structure formed at both ends of the word lines, eliminating the need for a stepped structure at the ends of the word lines. This not only simplifies the memory manufacturing process but also helps to increase the memory's storage density. Attached Figure Description
[0061] Appendix Figure 1 This is a top view of the structure of the three-dimensional memory in a specific embodiment of this disclosure;
[0062] Appendix Figure 2 The three-dimensional memory in the specific embodiments of this disclosure is along Figure 1 A schematic diagram of the cross-section along the a-a' direction;
[0063] Appendix Figure 3 The three-dimensional memory in the specific embodiments of this disclosure is along Figure 1A schematic diagram of the cross-section along the b-b' direction;
[0064] Appendix Figures 4A-4B This is a schematic diagram showing the positional relationship between word lines and leads in a three-dimensional memory according to a specific embodiment of this disclosure;
[0065] Appendix Figure 5 This is a flowchart of a method for forming a three-dimensional memory according to a specific embodiment of this disclosure;
[0066] Appendix Figures 6A-6C This is a schematic diagram of the main process cross-section of the three-dimensional memory during its formation process in a specific embodiment of this disclosure. Detailed Implementation
[0067] The specific embodiments of the three-dimensional memory and its formation method provided in this disclosure will be described in detail below with reference to the accompanying drawings.
[0068] This specific embodiment provides a three-dimensional memory, with appendix Figure 1 This is a top view schematic diagram of the three-dimensional memory structure in a specific embodiment of this disclosure, with attached... Figure 2 The three-dimensional memory in the specific embodiments of this disclosure is along Figure 1 A schematic diagram of the cross-section along the a-a' direction is attached. Figure 3 The three-dimensional memory in the specific embodiments of this disclosure is along Figure 1 A schematic diagram of the cross-section along the b-b' direction is attached. Figures 4A-4B This is a schematic diagram illustrating the positional relationship between word lines and leads in a three-dimensional memory according to a specific embodiment of this disclosure. The three-dimensional memory described in this embodiment can be, but is not limited to, DRAM memory. For example... Figures 1-3 , Figures 4A-4B As shown, the three-dimensional memory includes:
[0069] Substrate 20;
[0070] Multiple word lines 23 are located on the substrate 20. Each word line 23 extends along a first direction a-a' and includes a first end P1 and a second end P2 opposite to the first end P1 along the first direction a-a'. The multiple word lines 23 are arranged at intervals along a direction perpendicular to the top surface of the substrate 20. The first direction a-a' is a direction parallel to the top surface of the substrate 20.
[0071] Multiple leads 11 are located on the substrate 20. Each lead 11 extends in a direction perpendicular to the top surface of the substrate 20. The multiple leads 11 are connected to multiple word lines 23 in a one-to-one correspondence. There are at least two adjacent word lines 23 in the direction perpendicular to the top surface of the substrate 20. The lead 11 connected to one of the word lines 23 is located at the first end P1 of the word line 23, and the lead 11 connected to the other word line 23 is located at the second end P2 of the other word line 23.
[0072] Specifically, the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. In other examples, the substrate 20 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 20 is used to support a device structure on its top surface. The top surface of the substrate 20 also includes a plurality of first semiconductor layers arranged at intervals along a direction perpendicular to the top surface of the substrate 20. Each first semiconductor layer includes a plurality of active pillars 10 arranged at intervals along the first direction a-a'. Each active pillar 10 includes a channel region 25 and drain regions 26 and source regions 27 distributed on opposite sides of the channel region 25 along a second direction b-b'. Each word line 23 extends along the first direction a-a', and each word line 23 continuously covers a plurality of channel regions 25 arranged at intervals along the first direction a-a' in one of the first semiconductor layers. A gate dielectric layer 24 is also included between the word line 23 and the channel region 25. The channel region 25 can be made of monocrystalline silicon, polycrystalline silicon, indium gallium zinc oxide (IGZO), monocrystalline Si, monocrystalline Ge, or monocrystalline silicon germanium (SiGe). The gate dielectric layer 24 can be made of a high-k dielectric material, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof. The high-k dielectric material may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO2), lanthanum oxide (LaO), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide (BaSrTiO3), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3, STO), lithium oxide (Li2O), aluminum oxide (Al2O3), lead scandium tantalum oxide (PbScTaO), lead zinc niobate (PbZnNbO3), or a combination thereof. The top surface of the substrate 20 also includes a capacitor structure, which includes a capacitor comprising a lower electrode layer 21, a dielectric layer 22 covering the surface of the lower electrode layer 21, and an upper electrode layer 14 covering the surface of the dielectric layer 22. The top surface of the substrate 20 also includes a bit line 12 extending in a direction perpendicular to the top surface of the substrate 20. The capacitor is electrically connected to the drain region 26, and the bit line 12 is electrically connected to the source region 27. A support pillar 15 is also disposed on the top surface of the substrate 20 to support the first semiconductor layer, thereby improving the stability of the overall structure of the three-dimensional memory. The material of the bit line 12 may include conductive materials, such as doped Si, doped Ge, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten silicide (WSi), cobalt silicide (CoSi), titanium silicide (TiSi), or combinations thereof.
[0073] In one embodiment, metal silicide can be formed as an ohmic contact layer between the capacitor and the drain region 26, and between the bit line 12 and the source region 27, to reduce the contact resistance between the capacitor and the drain region 26, and the contact resistance between the bit line 12 and the source region 27, respectively.
[0074] In one embodiment, the support post 15 is located on the side of the capacitor away from the drain region 26, and the first semiconductor layer is partially inserted into the support post 15 to further improve the support performance of the support post 15 for the three-dimensional memory.
[0075] The leads 11 are located on the top surface of the substrate 20. Each lead 11 extends in a direction perpendicular to the top surface of the substrate 20, and the bottom surface of each lead 11 is electrically connected to a word line 23, while the top surface is used to connect to external control signals. Multiple word lines 23 are arranged at intervals in a direction perpendicular to the top surface of the substrate 20. For any two adjacent word lines 23, the lead 11 connected to one of the word lines 23 is located at the first end P1 of that word line 23, and the lead 11 connected to the other word line 23 is located at the second end P2 of that word line 23. That is, the leads of two adjacent word lines are distributed at both ends of the word line, thereby reducing the density of the multiple leads 11 and increasing the distance between adjacent leads 11, thus reducing the parasitic capacitance effect between the multiple leads 11 and improving the electrical performance of the three-dimensional memory.
[0076] In some embodiments, all the word lines 23 arranged at intervals along a direction perpendicular to the top surface of the substrate 20 are sequentially ordered, and the lead 11 connected to the odd-numbered word line 23 is located at the first end P1 of the odd-numbered word line 23, and the lead 11 connected to the even-numbered word line 23 is located at the second end of the even-numbered word line 23.
[0077] Appendix Figure 4A This is a cross-sectional schematic diagram showing the positional relationship between word lines and lead lines in a three-dimensional memory according to a specific embodiment of this disclosure. Figure 4B This is a three-dimensional structural diagram illustrating the positional relationship between word lines and leads in a three-dimensional memory according to a specific embodiment of this disclosure. For example, as... Figure 4A and Figure 4BAs shown, the three-dimensional memory includes a first word line WL1, a second word line WL2, a third word line WL3, a fourth word line WL4, ..., an nth word line WLn, an (n+1)th word line WLn+1, and an (n+2)th word line WLn+2, where n is a positive integer. The first word line WL1, the second word line WL2, ..., the (n+2)th word line WLn+2 are arranged at intervals along a direction perpendicular to the top surface of the substrate 20. The leads 11 connecting to the odd-numbered word lines (e.g., the first word line WL1, the third word line WL3, and the fifth word line WL5) are all located at the first end P1 of each odd-numbered word line, and the leads 11 connecting to the even-numbered word lines (e.g., the second word line WL2 and the fourth word line WL4) are all located at the second end P2 of each even-numbered word line. By distributing the lead 11 connected to the odd-numbered word line 23 and the lead 11 connected to the even-numbered word line 23 at both ends of the word line 23, not only can the parasitic capacitance effect between the lead 11 be reduced, but the manufacturing process of multiple lead 11 can also be simplified.
[0078] In some embodiments, each word line 23 includes a first end face 40 and a second end face 41 opposite to the first end face 40 along the first direction a-a';
[0079] The first end faces 40 of all the word lines 23 arranged at intervals along a direction perpendicular to the top surface of the substrate 20 are flush with each other, and the second end faces 41 of all the word lines 23 are flush with each other.
[0080] In some embodiments, in any two word lines 23 spaced apart along a direction perpendicular to the top surface of the substrate 20, the lead 11 connected to one word line 23 closer to the substrate 20 passes through the other word line 23; the three-dimensional memory further includes:
[0081] An isolation layer 16 covers the sidewall of the lead 11.
[0082] Specifically, the first end faces 40 of all word lines 23 arranged at intervals along a direction perpendicular to the top surface of the substrate 20 are flush with each other, and the second end faces 41 of all word lines 23 are flush with each other. This eliminates the need to form stepped structures at the ends of multiple word lines 23, thereby simplifying the manufacturing process of the three-dimensional memory and also helping to increase the storage density of the three-dimensional memory. To prevent the leads 11 connected to the lower-layer word lines 23 from interfering with the upper-layer word lines 23, the sidewalls of the leads 11 are covered with the isolation layer 16. The bottom surface of the leads 11 is electrically connected to the word lines 23, and the sidewalls of the leads 11 are electrically isolated from other word lines 23 by the isolation layer 16. The material of the isolation layer 16 may be, but is not limited to, oxide materials (e.g., silicon dioxide). Figure 4A and Figure 4B To clearly show the relative positional relationship between the surface letter lines and the leads, the isolation layer 16 is not shown.
[0083] To further simplify the structure of the three-dimensional memory, in some embodiments, the depth of the multiple leads 11 connected to the multiple odd-numbered word lines 23 gradually changes along the first direction a-a';
[0084] The depth of the multiple leads 11 connected to the multiple even-numbered word lines 23 gradually changes a-a' along the first direction.
[0085] In some embodiments, the depth of the plurality of leads 11 connected to the plurality of odd-numbered word lines 23 gradually decreases in a direction parallel to the first end P1 of a word line 23 and pointing to the second end P2.
[0086] In a direction parallel to the second end P2 of one of the word lines 23 and pointing towards the first end P1, the depth of the plurality of leads 11 connected to the plurality of even-numbered word lines 23 gradually decreases.
[0087] In some embodiments, the multiple leads 11 connected to the multiple odd-numbered word lines 23 are arranged at equal intervals along the first direction a-a';
[0088] The multiple leads 11 connected to the multiple even-numbered word lines 23 are arranged at equal intervals along the first direction a-a'.
[0089] To reduce the number of photomasks and thus lower the manufacturing cost of the three-dimensional memory, in some embodiments, the interval D1 between two leads 11 connected to two adjacent odd-numbered word lines 23 along the first direction a-a' is equal to the interval D2 between two leads 11 connected to two adjacent even-numbered word lines 23.
[0090] To enhance the connection stability between the word line 23 and the lead line 11, in some embodiments, the bottom surface of the lead line 11 connected to a word line 23 is completely located on the word line 23.
[0091] In other embodiments, the bottom portion of the lead 11 connected to one of the word lines 23 is located on the word line 23.
[0092] Specifically, the bottom surface of the lead 11 is only partially located on the word line 23. For example, in a direction perpendicular to the top surface of the substrate 20, the overlapping area between the projection of the bottom surface of the lead 11 and the projection of the word line 23 is greater than or equal to 60% of the total projected area of the bottom surface of the lead 11. This structure ensures a stable electrical connection between the lead 11 and the word line 23 while also increasing the process window for forming the lead 11, improving the tolerance of the 3D memory manufacturing process, and contributing to improved yield of the 3D memory.
[0093] This specific embodiment is illustrated by taking the lead wire 11 overlapping the surface of the word line 23 (i.e., the lead wire 11 and the word line 23 are in contact with the top surface away from the substrate 20) as an example. In other specific embodiments, the lead wire 11 can also be embedded inside the word line 23, thereby increasing the contact area between the lead wire 11 and the word line 23 and reducing the contact resistance between the lead wire 11 and the word line 23.
[0094] To further reduce the parasitic capacitance effect among the multiple leads 11, in some embodiments, each word line 23 includes a third end and a fourth end opposite to the third end along a second direction, the second direction being parallel to the top surface of the substrate 20 and intersecting the first direction a-a'.
[0095] The bottom portion of the lead 11 connected to the word line 23 of the odd-numbered position is located on the third end;
[0096] The bottom portion of the lead 11 connected to the even-numbered word line 23 is located on the fourth end.
[0097] The intersection described in this specific embodiment can be a perpendicular intersection or an oblique intersection.
[0098] To simplify the manufacturing process, in some embodiments, each word line 23 includes a third end and a fourth end opposite to the third end along a second direction, the second direction being parallel to the top surface of the substrate 20 and intersecting with the first direction a-a';
[0099] The bottom surface of the lead 11 connected to all the word lines 23 is partially located on the third end.
[0100] This specific embodiment also provides a method for forming a three-dimensional memory, attached... Figure 5 This is a flowchart illustrating the method for forming a three-dimensional memory according to a specific embodiment of this disclosure, with appended... Figures 6A-6C This is a schematic diagram of the main process cross-section during the formation of the three-dimensional memory in this specific embodiment. The structure of the three-dimensional memory formed in this specific embodiment can be found in [reference needed]. Figures 1-3 ,as well as Figures 4A-4B .like Figures 1-3 , Figures 4A-4B , Figure 5 and Figures 6A-6C As shown, the method for forming the three-dimensional memory includes the following steps:
[0101] Step S51: Form a substrate 20 and a plurality of word lines 23 located on the substrate 20. Each word line 23 extends along a first direction a-a', and each word line 23 includes a first end P1 and a second end P2 opposite to the first end P1 along the first direction a-a'. The plurality of word lines 23 are spaced apart along a direction perpendicular to the top surface of the substrate 20, where the first direction a-a' is parallel to the top surface of the substrate 20. See [link to previous section] Figure 6A , Figure 4A and Figure 4B .
[0102] Step S52: Forming multiple leads 11 above the substrate 20. Each lead 11 extends in a direction perpendicular to the top surface of the substrate 20. The multiple leads 11 are connected one-to-one with multiple word lines 23. At least two adjacent word lines 23 exist in the direction perpendicular to the top surface of the substrate 20. The lead 11 connected to one of the word lines 23 is located at the first end P1 of that word line 23, and the lead 11 connected to the other word line 23 is located at the second end P2 of that word line 23. See [link to previous steps]. Figure 6C , Figures 1-3 , Figure 4A and Figure 4B .
[0103] In some embodiments, the specific steps of forming the substrate 20 and the plurality of word lines 23 located on the substrate 20 include:
[0104] A substrate 20 is formed, and a stacked layer is located on the substrate 20. The stacked layer includes a first semiconductor layer and a second semiconductor layer that are alternately stacked along a direction perpendicular to the top surface of the substrate 20. The thickness of the second semiconductor layer is D1. The first semiconductor layer includes a plurality of channel regions 25 arranged along a first direction a-a', and source regions 27 and drain regions 26 distributed on opposite sides of each channel region 25 along a second direction b-b'. The first direction a-a' and the second direction b-b' are both parallel to the top surface of the substrate 20, and the first direction a-a' and the second direction b-b' intersect.
[0105] A plurality of first openings are formed in the second semiconductor layer to expose a plurality of the channel regions 25, wherein the gap width between two adjacent first openings along the first direction a-a' is D2, and the thickness D1 of the second semiconductor layer is greater than the gap width D2 between two adjacent first openings along the first direction a-a'; by setting the thickness of the second semiconductor layer to be greater than the gap width between two adjacent first openings along the first direction a-a', the conductive material in the plurality of first openings arranged along the first direction a-a' is first connected into a line when the conductive material is deposited, thereby simplifying the process steps for forming horizontal letter lines;
[0106] Conductive material is deposited along the first opening to form word lines 23 that extend along the first direction a-a' and continuously cover the plurality of channel regions 25 arranged along the first direction a-a'.
[0107] In some embodiments, the specific steps of forming word lines 23 that extend along the first direction a-a' and continuously cover the plurality of channel regions 25 arranged along the first direction a-a' include:
[0108] Conductive material is deposited along multiple first openings to form multiple word lines 23 spaced apart along a direction perpendicular to the top surface of the substrate 20. Each word line 23 includes a first end face 40 and a second end face 41 opposite to the first end face 40 along the first direction a-a'. The first end faces 40 of all word lines 23 spaced apart along a direction perpendicular to the top surface of the substrate 20 are flush with each other, and the second end faces 41 of all word lines are flush with each other.
[0109] Specifically, the first semiconductor layer can be made of silicon, and the second semiconductor layer can be made of SiGe. The first and second semiconductor layers can be alternately stacked along a direction perpendicular to the top surface of the substrate 20 using atomic layer deposition (ALD) to form the stacked layer with a superlattice stack structure. The specific number of alternating first and second semiconductor layers can be selected by those skilled in the art according to actual needs. Then, the second semiconductor layer is etched to form the first opening exposing the channel region 25 in the first semiconductor layer.
[0110] In one embodiment, to simplify the manufacturing process, selective atomic layer deposition (SLD) can be used to deposit conductive materials such as tungsten along multiple first openings, directly forming multiple word lines 23 spaced apart along a direction perpendicular to the top surface of the substrate 20. Each word line 23 extends along the first direction a-a' and continuously covers the multiple channel regions 25 arranged along the first direction a-a'. In this case, the edge of each word line 23 along the second direction b-b' is flush with the edge of the channel region 25 it covers.
[0111] In another embodiment, to fully avoid the connection of two adjacent word lines 23 along a direction perpendicular to the top surface of the substrate 20, an atomic layer deposition process can be used to deposit a conductive material such as tungsten along multiple first openings to form an initial conductive layer. This initial conductive layer includes a first portion extending along the first direction a-a' and continuously covering a plurality of channel regions 25 arranged along the first direction a-a', and a second portion extending along a direction perpendicular to the top surface of the substrate 20 and connected to the first portion. Subsequently, an etching process can be used to fully remove the second portion, leaving the remaining first portion as the word line 23. In this case, to fully remove the second portion, a portion of the first portion can be removed simultaneously with the second portion, such that the channel regions 25 protrude from the word lines 23 along the first direction a-a'.
[0112] In some embodiments, the specific steps for forming a plurality of leads 11 located above the substrate 20 include:
[0113] A dielectric layer 13 is formed that covers the surface of the word lines 23 and fills the gaps between adjacent word lines 23;
[0114] The dielectric layer 13 and a portion of the word lines 23 are etched to form a plurality of lead slots 60 that expose multiple word lines 23. At least two adjacent word lines 23 exist in a direction perpendicular to the top surface of the substrate 20. The lead slot 60 exposing one word line 23 is located at the first end P1 of that word line, and the lead slot P2 exposing the other word line 23 is located at the second end of that word line 23. Figure 6A As shown;
[0115] The conductive material is filled into the lead groove 60 to form the lead 11, as follows. Figure 6C As shown.
[0116] In some embodiments, the specific steps for forming the lead 11 include:
[0117] An isolation layer 16 is formed covering the sidewalls of the lead groove 60, such as Figure 6B As shown;
[0118] The conductive material is filled into the lead groove 60 to form the lead 11 covering the exposed surface of the word line 23 and the surface of the isolation layer 16.
[0119] Specifically, after forming a structure in which the first end faces 40 of all word lines 23 arranged at intervals along a direction perpendicular to the top surface of the substrate 20 are flush with each other, and the second end faces 41 of all word lines are flush with each other, there is no need to etch the word lines 23 again; instead, the dielectric layer 13 can be directly deposited. Then, a dry etching process is used to etch a portion of the dielectric layer 13 and a portion of the word lines 23 along a direction perpendicular to the top surface of the substrate 20, forming multiple lead grooves 60 that expose multiple word lines 23 respectively. For any two adjacent word lines 23, the lead groove 60 exposing the word line 23 closer to the substrate 20 penetrates the other word line 23. Next, an electrically insulating material such as silicon dioxide is deposited on the sidewalls and bottom wall of the lead groove 60. Then, the electrically insulating material at the bottom of the lead groove 60 is etched away, leaving the electrically insulating material remaining on the sidewalls of the lead groove 60 as the isolation layer 16. In this specific embodiment, the isolation layer 16 is formed on the sidewall of the lead groove 60 using an electrically insulating material (e.g., silicon dioxide), which electrically isolates the sidewall of the lead 11 from the other word lines 23.
[0120] In some embodiments, all the word lines arranged at intervals along a direction perpendicular to the top surface of the substrate are sequentially ordered; the specific steps of forming a plurality of lead slots exposing a plurality of word lines include:
[0121] The dielectric layer 13 and a portion of the word lines 23 are etched to form a plurality of lead slots 60. The lead slots 60 exposing the odd-numbered word lines 23 are all located on the first end P1 of the odd-numbered word lines 23, and the lead slots 60 exposing the even-numbered word lines 23 are located on the second end P2 of the even-numbered word lines 23.
[0122] Specifically, by distributing the lead slots 60 of the word lines 23 that expose odd-numbered bits and the lead slots 60 of the word lines 23 that expose even-numbered bits at opposite ends of the word lines 23, the two leads subsequently formed to connect with the two adjacent word lines 23 can be distributed at opposite ends of the word lines 23. This not only reduces the parasitic capacitance effect between the leads 11, but also simplifies the manufacturing process of multiple leads 11.
[0123] In some embodiments, the specific steps of forming a plurality of lead slots 60 that expose a plurality of the word lines 23 include:
[0124] The dielectric layer 13 and a portion of the word lines 23 are etched to form a plurality of lead slots 60, and the depth of the lead slots 60 exposing a plurality of odd-numbered word lines 23 gradually changes along the first direction a-a', and the depth of the lead slots 60 exposing a plurality of even-numbered word lines 23 gradually changes along the first direction a-a'.
[0125] In some embodiments, the depth of a plurality of lead slots 60 that expose a plurality of odd-numbered word lines 23 gradually decreases in a direction parallel to a first end P1 of a word line 23 pointing to a second end P2.
[0126] In a direction parallel to the second end P2 of one of the word lines 23 and pointing towards the first end P1, the depth of the plurality of leads 11 connected to the plurality of even-numbered word lines 23 gradually decreases.
[0127] In some embodiments, the specific steps of forming a plurality of lead slots 60 that expose a plurality of the word lines 23 include:
[0128] The dielectric layer 13 and a portion of the word lines 23 are etched to form a plurality of lead slots 60. The plurality of lead slots 60 that expose a plurality of odd-numbered word lines 23 are arranged at equal intervals along the first direction a-a', and the plurality of lead slots 60 that expose a plurality of even-numbered word lines 23 are arranged at equal intervals along the first direction a-a'.
[0129] In some embodiments, along the first direction a-a', the interval between the two leads 11 connected to the two adjacent odd-numbered word lines 23 is equal to the interval between the two leads 11 connected to the two adjacent even-numbered word lines 23.
[0130] In some embodiments, the specific steps of forming a plurality of lead slots 60 that expose a plurality of the word lines 23 include:
[0131] The dielectric layer 13 and a portion of the word lines 23 are etched to form a plurality of lead grooves 60, with the bottom of the lead grooves 60 exposing only the word lines 23.
[0132] Specifically, by using an alignment etching process, the bottom of the lead groove 60 is made to expose only the word line 23, so that the bottom surface of the lead line 11 formed in the lead groove 60 is entirely located on the surface of the word line 23, thereby further enhancing the connection stability between the lead line 11 and the word line 23.
[0133] In some embodiments, the specific steps of forming a plurality of lead slots 60 that expose a plurality of the word lines 23 include:
[0134] The dielectric layer 13 and a portion of the word lines 23 are etched to form a plurality of lead grooves 60, and the bottom of the lead grooves 60 exposes a portion of the word lines 23 and a portion of the dielectric layer 13.
[0135] Specifically, the bottom of the lead groove 60 exposes a portion of the word line 23 and a portion of the dielectric layer 13, such that the bottom surface of the lead 11 formed within the lead groove 60 is partially located on the surface of the word line 23 and partially on the surface of the dielectric layer 13. For example, in a direction perpendicular to the top surface of the substrate 20, the overlapping area between the projection of the bottom surface of the lead 11 and the projection of the word line 23 is greater than or equal to 60% of the total projected area of the bottom surface of the lead 11. This structure ensures a stable electrical connection between the lead 11 and the word line 23 while also increasing the process window for forming the lead groove 60, improving the tolerance of the 3D memory manufacturing process, and contributing to improved 3D memory yield.
[0136] This specific embodiment uses the word line 23 as an etching stop layer during the etching of the lead groove 60, so that the lead groove 60 stops at the surface of the word line 23, and the lead 11 formed in the lead groove 60 overlaps the surface of the word line 23 (i.e., the lead 11 and the word line 23 contact the top surface away from the substrate 20). In other specific embodiments, the lead groove 60 can also extend into the interior of the word line 23, so that the lead 11 formed in the lead groove 60 can also be embedded inside the word line 23, thereby increasing the contact area between the lead 11 and the word line 23 and reducing the contact resistance between the lead 11 and the word line 23.
[0137] In some embodiments, each word line 23 includes a third end and a fourth end opposite to the third end along the second direction b-b'; the specific steps of forming a plurality of lead slots 60 that expose a plurality of word lines 23 include:
[0138] The dielectric layer 13 and a portion of the word lines 23 are etched to form a plurality of lead grooves 60. The bottom portion of the lead groove 60 located on the surface of the odd-numbered word lines 23 exposes the third end and partially exposes the dielectric layer 13. The bottom portion of the lead groove 60 located on the surface of the even-numbered word lines 23 exposes the fourth end and partially exposes the dielectric layer 13.
[0139] The three-dimensional memory and its formation method provided in some embodiments of this specific implementation have at least two adjacent word lines along a direction perpendicular to the top surface of the substrate. A lead connected to one of the word lines is located at the first end of the word line, and a lead connected to the other word line is located at the second end of the other word line. This results in the leads of the two adjacent word lines being distributed at both ends of the word lines, achieving a staggered lead structure. This increases the distance between the two adjacent leads and reduces the capacitive parasitic effect between adjacent leads. Furthermore, this disclosure uses a staggered lead structure formed at both ends of the word lines, eliminating the need to form a stepped structure at the ends of the word lines. This not only simplifies the memory manufacturing process but also helps to increase the memory's storage density.
[0140] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.
Claims
1. A three-dimensional memory, characterized in that, include: Substrate; Multiple word lines are located on the substrate, each word line extends along a first direction, and each word line includes a first end and a second end opposite to the first end along the first direction. The multiple word lines are arranged at intervals along a direction perpendicular to the top surface of the substrate, and the first direction is a direction parallel to the top surface of the substrate. Multiple leads are located on the substrate, each lead extending in a direction perpendicular to the top surface of the substrate. Each lead is connected to a corresponding word line. At least two adjacent word lines exist in the direction perpendicular to the top surface of the substrate. The lead connected to one of the word lines is located at the first end of that word line, and the lead connected to the other word line is located at the second end of that word line. In any two word lines spaced apart along a direction perpendicular to the top surface of the substrate, the lead connected to the word line closer to the substrate passes through the other word line. The three-dimensional memory also includes: An isolation layer covers the sidewalls of the lead wire.
2. The three-dimensional memory according to claim 1, characterized in that, The word lines arranged at intervals along a direction perpendicular to the top surface of the substrate are sequentially ordered. The leads connected to the odd-numbered word lines are all located at the first end of the odd-numbered word lines, and the leads connected to the even-numbered word lines are all located at the second end of the even-numbered word lines.
3. The three-dimensional memory according to claim 1, characterized in that, Each of the character lines includes a first end face and a second end face opposite to the first end face along the first direction; The first end faces of the word lines, which are arranged at intervals along a direction perpendicular to the top surface of the substrate, are flush with each other, and the second end faces of the word lines are also flush with each other.
4. The three-dimensional memory according to claim 2, characterized in that, The depth of the multiple leads connected to the multiple odd-numbered word lines gradually changes along the first direction; The depth of the multiple leads connected to the multiple even-numbered word lines gradually changes along the first direction.
5. The three-dimensional memory according to claim 4, characterized in that, In a direction parallel to the first end of the word line and pointing to the second end, the depth of the multiple leads connected to the multiple odd-numbered word lines gradually decreases; In a direction parallel to the second end of the word line and pointing towards the first end, the depth of the multiple leads connected to the multiple even-numbered word lines gradually decreases.
6. The three-dimensional memory according to claim 2, characterized in that, The multiple leads connected to the multiple odd-numbered word lines are arranged at equal intervals along the first direction; The multiple leads connected to the multiple even-numbered word lines are arranged at equal intervals along the first direction.
7. The three-dimensional memory according to claim 6, characterized in that, Along the first direction, the spacing between two leads connected to two adjacent odd-numbered word lines is equal to the spacing between two leads connected to two adjacent even-numbered word lines.
8. The three-dimensional memory according to claim 1, characterized in that, The bottom surface of the lead wire connected to the word line is completely located on the word line.
9. The three-dimensional memory according to claim 2, characterized in that, The bottom portion of the lead wire connected to the word line is located on the word line.
10. The three-dimensional memory according to claim 9, characterized in that, Each of the word lines includes a third end and a fourth end opposite to the third end along a second direction, the second direction being parallel to the top surface of the substrate and intersecting the first direction; The bottom portion of the lead connected to the odd-numbered word line is located on the third end; the bottom portion of the lead connected to the even-numbered word line is located on the fourth end.
11. The three-dimensional memory according to claim 9, characterized in that, Each of the word lines includes a third end and a fourth end opposite to the third end along a second direction, the second direction being parallel to the top surface of the substrate and intersecting the first direction; The bottom surface of each lead wire connected to the word line is partially located on the third end.
12. A method for forming a three-dimensional memory, characterized in that, Includes the following steps: A substrate is formed, and a plurality of word lines are located on the substrate, each word line extending along a first direction, and each word line includes a first end and a second end opposite to the first end along the first direction, the plurality of word lines being spaced apart along a direction perpendicular to the top surface of the substrate, the first direction being a direction parallel to the top surface of the substrate; Multiple leads are formed above the substrate, each lead extending in a direction perpendicular to the top surface of the substrate. Each lead is connected to a corresponding word line. At least two adjacent word lines exist in the direction perpendicular to the top surface of the substrate. The lead connected to one of the word lines is located at the first end of that word line, and the lead connected to the other word line is located at the second end of that word line. The specific steps for forming the substrate and the multiple word lines located on the substrate include: A substrate is formed, and a stacked layer is located on the substrate. The stacked layer includes a first semiconductor layer and a second semiconductor layer that are alternately stacked along a direction perpendicular to the top surface of the substrate. The thickness of the second semiconductor layer is D1. The first semiconductor layer includes a plurality of channel regions arranged along a first direction and source regions and drain regions distributed on opposite sides of the channel regions along a second direction. Both the first direction and the second direction are parallel to the top surface of the substrate, and the first direction intersects the second direction. A plurality of first openings are formed in the second semiconductor layer to expose a plurality of the channel regions, wherein the gap width between two adjacent first openings along the first direction is D2, and D1>D2; Conductive material is deposited along the first opening to form word lines that extend along the first direction and continuously cover the plurality of channel regions arranged along the first direction.
13. The method for forming a three-dimensional memory according to claim 12, characterized in that, The specific steps for forming word lines that extend along the first direction and continuously cover the plurality of channel regions arranged along the first direction include: Conductive material is deposited along multiple first openings to form multiple word lines spaced apart along a direction perpendicular to the top surface of the substrate. Each word line includes a first end face and a second end face opposite to the first end face along the first direction. The first end faces of the word lines spaced apart along a direction perpendicular to the top surface of the substrate are flush with each other, and the second end faces of the word lines are also flush with each other.
14. The method for forming a three-dimensional memory according to claim 12, characterized in that, The specific steps for forming multiple leads located above the substrate include: A surface covering the word lines and a dielectric layer filling the gaps between adjacent word lines are formed; the dielectric layer and a portion of the word lines are etched to form a plurality of lead grooves exposing multiple word lines, wherein at least two adjacent word lines exist in a direction perpendicular to the top surface of the substrate, the lead groove exposing one of the word lines is located at the first end of one word line, and the lead groove exposing the other word line is located at the second end of the other word line; The conductive material is filled into the lead groove to form the lead.
15. The method for forming a three-dimensional memory according to claim 14, characterized in that, The specific steps for forming the lead include: An isolation layer is formed covering the sidewalls of the lead groove; The conductive material is filled into the lead groove to form the lead that covers the surface of the exposed word line and the surface of the isolation layer.
16. The method for forming a three-dimensional memory according to claim 14, characterized in that, The word lines, arranged at intervals along a direction perpendicular to the top surface of the substrate, are sequentially ordered; the specific steps for forming multiple lead slots that expose multiple word lines include: The dielectric layer and a portion of the word lines are etched to form a plurality of lead slots, wherein the lead slots exposing the odd-numbered word lines are all located on the first end of the odd-numbered word lines, and the lead slots exposing the even-numbered word lines are located on the second end of the even-numbered word lines.
17. The method for forming a three-dimensional memory according to claim 16, characterized in that, The specific steps for forming multiple lead slots that expose multiple word lines include: The dielectric layer and a portion of the word lines are etched to form a plurality of lead slots, and the depth of the lead slots exposing a plurality of odd-numbered word lines gradually changes along the first direction, and the depth of the lead slots exposing a plurality of even-numbered word lines gradually changes along the first direction.
18. The method for forming a three-dimensional memory according to claim 17, characterized in that, In a direction parallel to the first end of the word line and pointing to the second end, the depth of the plurality of lead slots exposing the plurality of odd-numbered word lines gradually decreases; In a direction parallel to the second end of the word line and pointing towards the first end, the depth of the multiple leads connected to the multiple even-numbered word lines gradually decreases.
19. The method for forming a three-dimensional memory according to claim 16, characterized in that, The specific steps for forming multiple lead slots that expose multiple word lines include: The dielectric layer and a portion of the word lines are etched to form a plurality of lead slots, and the plurality of lead slots exposing a plurality of odd-numbered word lines are arranged at equal intervals along the first direction, and the plurality of lead slots exposing a plurality of even-numbered word lines are arranged at equal intervals along the first direction.
20. The method for forming a three-dimensional memory according to claim 19, characterized in that, Along the first direction, the spacing between two leads connected to two adjacent odd-numbered word lines is equal to the spacing between two leads connected to two adjacent even-numbered word lines.
21. The method for forming a three-dimensional memory according to claim 14, characterized in that, The specific steps for forming multiple lead slots that expose multiple word lines include: The dielectric layer and a portion of the word lines are etched to form a plurality of lead slots, with the bottom of the lead slots exposing only the word lines.
22. The method for forming a three-dimensional memory according to claim 14, characterized in that, The specific steps for forming multiple lead slots that expose multiple word lines include: The dielectric layer and a portion of the word lines are etched to form a plurality of lead slots, and the bottom of the lead slots exposes a portion of the word lines and a portion of the dielectric layer.
23. The method for forming a three-dimensional memory according to claim 22, characterized in that, Each of the word lines includes a third end and a fourth end opposite to the third end along the second direction; the specific steps of forming a plurality of lead slots exposing the plurality of word lines include: The dielectric layer and a portion of the word lines are etched to form a plurality of lead slots. The bottom portion of the lead slot on the surface of the odd-numbered word lines exposes the third end and partially exposes the dielectric layer. The bottom portion of the lead slot on the surface of the even-numbered word lines exposes the fourth end and partially exposes the dielectric layer.