Antifuse structure and method of forming same, memory

Abstract

The present disclosure relates to the field of semiconductor technology, and relates to a kind of anti-fuse structure and its forming method, memory, the anti-fuse structure includes substrate, first oxide layer, isolation layer, second oxide layer, first gate layer and second gate layer, wherein: substrate is formed with active layer, and active layer includes the first channel region and the second channel region of interval arrangement;First oxide layer, the side wall of active layer is covered;The thickness of the first oxide layer on the side wall of the active layer of first channel region is less than the thickness of the first oxide layer on the side wall of the active layer of second channel region;Isolation layer, at the side of first oxide layer away from active layer;Second oxide layer, at the side of isolation layer away from first oxide layer;First gate layer, at the top of the active layer of first channel region;Second gate layer, at the top of the active layer of second channel region.The anti-fuse structure of the present disclosure can reduce programming voltage, improve product yield.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to an antifuse structure and a method for forming the same, and a memory. Background Technology

[0002] One-time programmable devices based on anti-fuse technology are widely used in various chips. For example, in DRAM chips, anti-fuse programmable modules can achieve redundancy repair (including row repair and column repair) by breaking down anti-fuse cells. They can also be programmed to precisely adjust various parameters inside the chip (such as voltage, current, frequency, etc.).

[0003] With the continuous advancement of semiconductor technology, the miniaturization of antifuse-related spatial dimensions greatly helps to save costs and generate profits. However, the size of the antifuse is positively correlated with its accuracy and stability. How to achieve miniaturization of the antifuse size while ensuring that its performance is not affected, or even improved, has become a research hotspot. However, the programming voltage of existing antifuse structures is relatively high, and the product yield is relatively low.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] In view of this, the present disclosure provides an antifuse structure and a method for forming the same, as well as a memory, which can reduce programming voltage and improve product yield.

[0006] According to one aspect of this disclosure, an antifuse structure is provided, comprising: The substrate includes a base and an active layer formed on the base, the active layer including a first channel region and a second channel region arranged at intervals; A first oxide layer covers the sidewall of the active layer; the thickness of the first oxide layer on the sidewall of the active layer in the first channel region is less than the thickness of the first oxide layer on the sidewall of the active layer in the second channel region. An isolation layer is located on the side of the first oxide layer away from the active layer; The second oxide layer is located on the side of the isolation layer away from the first oxide layer; A first gate layer is located on top of the active layer in the first channel region; The second gate layer is located on top of the active layer in the second channel region.

[0007] In one exemplary embodiment of this disclosure, the first oxide layer on the sidewall of the active layer in the first channel region includes a first portion away from the substrate and a second portion close to the substrate, wherein the thickness of the first portion is less than the thickness of the second portion.

[0008] In one exemplary embodiment of this disclosure, the thickness of the first oxide layer on the sidewall of the active layer in the first channel region gradually decreases from the side closer to the substrate to the side farther away from the substrate.

[0009] In one exemplary embodiment of this disclosure, the active layer further includes a first doped region and a second doped region arranged at intervals, the first doped region being located between the first channel region and the second channel region, and the second doped region being located on the side of the second channel region away from the first doped region, both the first doped region and the second doped region being P-type doped regions.

[0010] In one exemplary embodiment of this disclosure, the active layer further includes a third doped region located on the side of the first channel region away from the first doped region, and the third doped region is a P-type doped region.

[0011] In one exemplary embodiment of this disclosure, the first gate layer includes: A first gate oxide layer is located on top of the active layer in the first channel region and is in contact with the first oxide layer. The first gate electrode layer is located on the side of the first gate oxide layer away from the substrate; The second gate layer includes: The second gate oxide layer is located on top of the active layer in the second channel region and is in contact with the second oxide layer. The second gate electrode layer is located on the side of the second gate oxide layer away from the substrate.

[0012] In one exemplary embodiment of this disclosure, the thickness of the first gate oxide layer is less than the thickness of the second gate oxide layer.

[0013] According to one aspect of this disclosure, a method for forming an antifuse structure is provided, comprising: A substrate is provided, the substrate including a base and an active layer formed on the base, the active layer including a first channel region and a second channel region arranged at intervals; A first oxide layer is formed, which covers the sidewall of the active layer; the thickness of the first oxide layer on the sidewall of the active layer in the first channel region is less than the thickness of the first oxide layer on the sidewall of the active layer in the second channel region. An isolation layer and a second oxide layer are formed, the isolation layer being located on the side of the first oxide layer away from the active layer, and the second oxide layer being located on the side of the isolation layer away from the first oxide layer; and A first gate layer and a second gate layer are formed, wherein the first gate layer is located on top of the active layer in the first channel region, and the second gate layer is located on top of the active layer in the second channel region.

[0014] In one exemplary embodiment of this disclosure, forming the first oxide layer includes: Ion implantation is performed on the sidewalls of the active layer in the first channel region using type I ions. The first oxide layer is formed by alternating thermal oxidation and atomic layer deposition processes; The first type of ions is used to reduce the oxidation rate of the active layer material in the thermal oxidation process.

[0015] In one exemplary embodiment of this disclosure, the active layer of the first channel region includes a third portion away from the substrate and a fourth portion close to the substrate; during the ion implantation process, the ion concentration of the third portion is greater than the ion concentration of the fourth portion; The first oxide layer on the sidewall of the active layer in the first channel region includes a first portion away from the substrate and a second portion close to the substrate, wherein the thickness of the first portion is less than the thickness of the second portion.

[0016] In one exemplary embodiment of this disclosure, the ion concentration of the active layer in the first channel region gradually decreases from the side away from the substrate to the side closer to the substrate; The thickness of the first oxide layer on the sidewall of the active layer in the first channel region gradually decreases from the side closer to the substrate to the side farther away from the substrate.

[0017] In one exemplary embodiment of this disclosure, forming the first oxide layer includes: Ion implantation of the active layer in the second channel region is performed using type II ions. The first oxide layer is formed by a thermal oxidation process; The second type of ions is used to increase the oxidation rate of the active layer material in the thermal oxidation process.

[0018] In one exemplary embodiment of this disclosure, forming the insulating layer and the second oxide layer includes: A third oxide layer and a dielectric layer are sequentially formed on top of the active layer; An isolation material layer and an oxide material layer are sequentially formed on the surface of the structure jointly formed by the active layer, the first oxide layer, the third oxide layer and the dielectric layer; Remove the dielectric layer, the third oxide layer, the oxide material layer and the isolation material layer located on top of the active layer to expose the top of the active layer.

[0019] In one exemplary embodiment of this disclosure, forming the first gate layer and the second gate layer includes: A gate oxide layer and a gate electrode layer are sequentially formed on top of the active layer; The gate oxide layer and the gate electrode layer are patterned to form a first gate oxide layer, a second gate oxide layer, a first gate electrode layer, and a second gate electrode layer; The first gate layer includes the first gate oxide layer and the first gate electrode layer, and the second gate layer includes the second gate oxide layer and the second gate electrode layer.

[0020] In one exemplary embodiment of this disclosure, forming the gate oxide layer includes: A gate oxide material layer is formed on top of the active layer; The gate oxide material layer located on top of the active layer in the first channel region is thinned to obtain the first gate oxide layer.

[0021] In one exemplary embodiment of this disclosure, forming the gate oxide layer includes: A first gate oxide material layer is formed on top of the active layer; A second gate oxide layer is formed on the first gate oxide layer located on top of the active layer in the second channel region; The second gate oxide layer includes the first gate oxide material layer and the second gate oxide material layer.

[0022] In one exemplary embodiment of this disclosure, after the gate oxide layer and the gate electrode layer are patterned, the active layer between the first channel region and the second channel region, and the active layer on the side of the second channel region away from the first channel region, are exposed; The forming method further includes: The active layer between the first channel region and the second channel region, and the active layer on the side of the second channel region away from the first channel region, are doped to obtain a first doped region and a second doped region.

[0023] In one exemplary embodiment of this disclosure, after the gate oxide layer and the gate electrode layer are patterned, the active layer between the first channel region and the second channel region, the active layer on the side of the second channel region away from the first channel region, and the active layer on the side of the first channel region away from the second channel region are exposed; The forming method further includes: The active layer between the first channel region and the second channel region, the active layer on the side of the second channel region away from the first channel region, and the active layer on the side of the first channel region away from the second channel region are doped to obtain a first doped region, a second doped region, and a third doped region.

[0024] According to one aspect of this disclosure, a memory is provided, comprising the antifuse structure described in any one of the foregoing claims.

[0025] The disclosed antifuse structure, its formation method, and memory allow for the formation of an antifuse using a first gate layer for programming. Simultaneously, a second gate layer forms a read transistor, which functions as a switching element during antifuse programming. Because the thickness of the first oxide layer on the sidewall of the active layer in the first channel region is less than that on the sidewall of the active layer in the second channel region, hot carriers are more easily injected into the isolation structure (e.g., including an isolation layer) on the sidewall of the active layer in the first channel region. This enhances the hot electron-induced punch-through (HEIP) effect in the antifuse compared to the read transistor, making it easier to break down and thus reducing the programming voltage. Furthermore, the isolation layer provides insulation protection for the first and second channel regions, preventing coupling between the read transistor and the antifuse and other surrounding components, thereby improving product yield.

[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0028] Figure 1 This is a schematic diagram of the antifuse structure in the embodiments of this disclosure; Figure 2 For along Figure 1 A schematic diagram of a section cut along the CC' direction; Figure 3 This is a flowchart of the method for forming the antifuse structure in the embodiments of this disclosure; Figure 4 This is a schematic diagram of the third oxide layer and the dielectric layer in the embodiments of this disclosure; Figure 5 This is a schematic diagram of the isolation material layer in an embodiment of this disclosure.

[0029] Explanation of reference numerals in the attached figures: 200, Antifuse; 300, Read transistor; 1, Active layer; 14, Second channel region; 3, Second gate layer; 301, Second gate oxide layer; 302, Second gate electrode layer; 4, First oxide layer; 5, Isolation layer; 510, Isolation material layer; 6, Second oxide layer; 7, Third oxide layer; 8, Dielectric layer. Detailed Implementation

[0030] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0031] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0032] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0033] The antifuse structure is a crucial programming element in memory, primarily consisting of an antifuse and a read transistor. As memory sizes continue to shrink, the dimensions of the internal antifuse structure are also decreasing, leading to a smaller gap between the antifuse and the read transistor. This intensifies the coupling between them. To program the antifuse, a higher programming voltage is required to break it down and complete the programming operation. However, this voltage can easily damage the read transistor, affecting the performance and stability of the antifuse structure. Furthermore, higher programming voltages require more complex drive circuitry and increase manufacturing costs. If the read transistor is to be protected from damage, the programming voltage needs to be reduced. However, this might prevent the antifuse from breaking down, thus hindering programming. Therefore, reducing the programming voltage without damaging the read transistor is a pressing problem to be solved in this field.

[0034] Based on this, the present disclosure provides an antifuse structure, such as... Figure 1 As shown, the antifuse structure may include a substrate, a first oxide layer 4, an isolation layer 5, a second oxide layer 6, a first gate layer, and a second gate layer 3, wherein: An active layer 1 is formed on the substrate, and the active layer 1 may include a first channel region and a second channel region 14 arranged at intervals. The first oxide layer 4 can cover the sidewall of the active layer 1; The isolation layer 5 may be located on the side of the first oxide layer 4 away from the active layer 1; The second oxide layer 6 may be located on the side of the isolation layer 5 away from the first oxide layer 4; The first gate layer may be located on top of the active layer 1 in the first channel region; The second gate layer 3 may be located on top of the active layer 1 of the second channel region 14; The thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the first channel region can be less than the thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the second channel region 14.

[0035] In the antifuse structure disclosed herein, a first gate layer can be used to form an antifuse 200, which can be used for programming; simultaneously, a second gate layer 3 can be used to form a read transistor 300, which can function as a switching element during the programming process of the antifuse 200. Since the thickness of the first oxide layer 4 on the sidewall of the active layer 1 of the first channel region is less than the thickness of the first oxide layer 4 on the sidewall of the active layer 1 of the second channel region 14, hot carriers are more easily injected into the isolation structure (e.g., including the isolation layer 5) on the sidewall of the active layer 1 of the first channel region. Therefore, compared to the read transistor 300, the hot electron-induced punch-through (HEIP) effect can be enhanced in the antifuse 200, making it easier to break down and thus reducing the programming voltage. Furthermore, the isolation layer 5 can provide insulation protection for the first channel region and the second channel region 14, preventing the read transistor 300 and the antifuse 200 from coupling with other surrounding components, thereby improving product yield.

[0036] The specific details of each part of the antifuse structure in the embodiments of this disclosure are described in detail below: The substrate may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be a semiconductor material, such as silicon, but not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of the substrate.

[0037] In one embodiment, the substrate may be a silicon substrate, with multiple shallow trench isolation structures (e.g., including a first oxide layer 4, an isolation layer 5, and a second oxide layer 6) formed therein. The shallow trench isolation structures are formed by forming trenches in the substrate and then filling the trenches with a material layer. The material of the shallow trench isolation structures may include silicon nitride or silicon oxide, etc., and is not particularly limited herein. The cross-sectional shape of the shallow trench isolation structures can be set according to actual needs. Multiple shallow trench isolation structures may be arranged side by side, and can isolate several spaced active layers 1 on the substrate. In some embodiments, the substrate may further include a substrate (not shown in the figure), and each active layer 1 may be located on the substrate.

[0038] In one exemplary embodiment of this disclosure, the active layer 1 may include a first channel region and a second channel region 14 spaced apart, which may be spaced apart along the extension direction of the active layer 1. A first gate layer may be located on top of the active layer 1 in the first channel region, and the first channel region may form an antifuse 200 (e.g., an antifuse in the form of a capacitor) with the first gate layer above it to realize a programming function. The second channel region 14 is available for current flow, and a second gate layer 3 may be located on top of the active layer 1 in the second channel region 14. The current in the second channel region 14 may be controlled by the voltage of the second gate layer 3 above it to realize a gate control function.

[0039] In some embodiments of this disclosure, the active layer 1 may further include a first doped region and a second doped region arranged at intervals. The first doped region may be located between the first channel region and the second channel region 14, and the second doped region may be located on the side of the second channel region 14 away from the first doped region. The substrate may be an n-type substrate, and both the first and second doped regions may be p-type doped regions. The first and second doped regions may be p-type doped to form p-type doped regions. For example, p-type doping material may be doped into the first and second doped regions to form p-type semiconductors. The p-type doping material may be an element located in Group III of the periodic table, for example, boron, but it may also be other elements, which will not be listed here.

[0040] It should be noted that the first doped region and the second doped region, before doping, can also be referred to as the first region to be doped and the second region to be doped, respectively; the case of the third doped region in the following text is similar. The first doped region can be used as the source and the second doped region can be used as the drain; or, the first doped region can be used as the drain and the second doped region can be used as the source.

[0041] In one embodiment, boron ions can be implanted into the first doped region and the second doped region by ion implantation. Of course, other processes can also be used to dope the first doped region and the second doped region, and no special limitation is made here.

[0042] The second gate layer 3 can be located on top of the active layer 1 of the second channel region 14, and the orthogonal projection of the second gate layer 3 on the substrate can overlap with the second channel region 14. The first doped region and the second doped region can serve as the source and drain, respectively. The second gate layer 3, the source, and the drain can together form a p-type transistor, which can serve as a read transistor 300 with an antifuse structure, and the read transistor 300 can serve as a switching device.

[0043] In one exemplary embodiment of this disclosure, the second gate layer 3 may include a second gate oxide layer 301 and a second gate electrode layer 302 stacked together. Both the second gate oxide layer 301 and the second gate electrode layer 302 are located on top of the active layer 1 between the first doped region and the second doped region. For example, the second gate oxide layer 301 may be located on top of the active layer 1 of the second channel region 14, and the second gate electrode layer 302 may be located on the side of the second gate oxide layer 301 away from the substrate. For example, the second gate electrode layer 302 may be located on the surface of the second gate oxide layer 301 away from the second channel region 14.

[0044] The second gate oxide layer 301 can be a thin film or a coating formed on the surface of the second channel region 14, and there is no particular limitation. In one embodiment, the second gate oxide layer 301 can be formed on the surface of the second channel region 14 by processes such as chemical vapor deposition, thermal oxidation, physical vapor deposition, atomic layer deposition, or in-situ water oxidation. Of course, the second gate oxide layer 301 can also be formed by other methods, and there is no particular limitation.

[0045] The material of the second gate oxide layer 301 can be an insulating material, such as silicon dioxide, a high-k dielectric material, or other dielectric materials, or any combination thereof. The thickness of the second gate oxide layer 301 can be set according to actual needs.

[0046] The second gate electrode layer 302 can be formed on the side of the second gate oxide layer 301 away from the substrate. In some embodiments, the second gate electrode layer 302 can be formed by processes such as chemical vapor deposition, vacuum evaporation, or atomic layer deposition. When the second gate electrode layer 302 includes a multilayer structure, it can be deposited layer by layer, and the forming process corresponding to each material type can be selected according to the material type of each layer.

[0047] For example, the second gate electrode layer 302 can be made of a conductive material, such as polycrystalline silicon or a metal, or a combination of both. The thickness of the second gate electrode layer 302 can be set according to actual needs. The second gate electrode layer 302 can be formed on the side of the second gate oxide layer 301 away from the substrate using processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, magnetron sputtering, or vacuum evaporation.

[0048] The first gate layer may be located on top of the active layer 1 in the first channel region, and the orthogonal projection of the first gate layer on the substrate may overlap with the second channel region 14. The second gate layer 3 and the first gate layer may share the first doped region, which helps to reduce the device size.

[0049] In one exemplary embodiment of this disclosure, the first gate layer may include a first gate oxide layer and a first gate electrode layer stacked together, both of which may be located on top of the active layer 1 in the first channel region. For example, the first gate oxide layer may be located on the surface of the active layer 1 in the first channel region, and the first gate electrode layer may be located on the side of the first gate oxide layer away from the substrate, for example, it may be located on the surface of the first gate oxide layer away from the substrate.

[0050] The first gate oxide layer can be a thin film formed on top of the first channel region or a coating formed on top of the first channel region, without particular limitation. In one embodiment, the first gate oxide layer can be formed on top of the first channel region by processes such as chemical vapor deposition, thermal oxidation, physical vapor deposition, atomic layer deposition or in-situ water oxidation. Of course, the first gate oxide layer can also be formed by other means, without particular limitation.

[0051] The material of the first gate oxide layer can be the same as that of the second gate oxide layer 301. Therefore, its material can be referenced from the material of the second gate oxide layer 301, and will not be described again here. The thickness of the first gate oxide layer can be less than or equal to the thickness of the second gate oxide layer 301. No special limitation is made on the thickness of the first gate oxide layer here.

[0052] The first gate electrode layer may be located on the side of the first gate oxide layer away from the substrate. In some embodiments, the first gate electrode layer may be formed by processes such as chemical vapor deposition, vacuum evaporation, or atomic layer deposition. When the first gate electrode layer comprises a multilayer structure, it may be deposited layer by layer, and the forming process corresponding to each material type may be selected according to the material type of each layer.

[0053] For example, the first gate electrode layer can be made of a conductive material, such as polycrystalline silicon or a metal, or a combination of both. The thickness of the first gate electrode layer can be set according to actual needs. The first gate electrode layer can be formed on the side of the first gate oxide layer away from the substrate using processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, magnetron sputtering, or vacuum evaporation.

[0054] In some embodiments, the first gate layer may further include a first cover layer, which may cover the surface of the first gate electrode layer and the sidewalls of the first gate electrode layer and the first gate oxide layer, so as to provide insulation protection for the first gate electrode layer and the first gate oxide layer and prevent the first gate electrode layer and the first gate oxide layer from coupling or short-circuiting with other structures.

[0055] In one exemplary embodiment of this disclosure, to maintain the symmetry of the device, the active layer 1 may further include a third doped region. The third doped region may be located on the side of the first channel region away from the first doped region, and the third doped region may be a p-type doped region. The third doped region may be p-type doped to form a p-type doped region in the third doped region. The formation method of the third doped region can refer to the formation method of the first doped region and the second doped region, and will not be repeated here.

[0056] The third doped region and the first doped region can serve as the source and drain, respectively. The first gate layer, the source, and the drain can together form a transistor, which can serve as an antifuse 200 of an antifuse structure (e.g., an antifuse in the form of a transistor). Since the antifuse 200 in the form of a p-type transistor is prone to the hot electron-induced punch-through (HEIP) effect, the antifuse 200 is easily broken down, which can reduce the programming voltage.

[0057] In one exemplary embodiment of this disclosure, the thickness of the first gate oxide layer may be less than the thickness of the second gate oxide layer 301. That is, the thickness of the gate oxide layer in the antifuse 200 is less than the thickness of the gate oxide layer in the read transistor 300. As a result, the antifuse 200 is easier to break down, while the read transistor 300 is less likely to break down, which helps to reduce the programming voltage and further simplifies the drive circuitry that provides the programming voltage, thereby reducing manufacturing costs.

[0058] In some embodiments, the second gate layer 3 may further include a second cover layer, which may cover the surface of the second gate electrode layer 302 and the sidewalls of the second gate electrode layer 302 and the second gate oxide layer 301, so as to provide insulation protection for the second gate electrode layer 302 and the second gate oxide layer 301 and prevent the second gate electrode layer 302 and the second gate oxide layer 301 from coupling or short-circuiting with other structures.

[0059] like Figure 2 As shown, the first oxide layer 4 can cover the sidewalls of the active layer 1 and can be in contact with the first gate oxide layer, and can also be in contact with the second gate oxide layer 301. For example, the first oxide layer 4 can cover the sidewalls of the first channel region and the second channel region 14. It can be a coating formed on the sidewalls of the first channel region and the second channel region 14, or it can be a thin film formed on the sidewalls of the first channel region and the second channel region 14. The specific form of the first oxide layer 4 is not particularly limited here. In one embodiment, the first oxide layer 4 can be formed on the sidewalls of the first channel region and the second channel region 14 by means of ion implantation, chemical vapor deposition, thermal oxidation, physical vapor deposition or atomic layer deposition, etc. Of course, the first oxide layer 4 can also be formed by other means, and is not particularly limited here.

[0060] The material of the first oxide layer 4 can be an insulating material, for example, it can be silicon dioxide or other dielectric materials, or any combination thereof.

[0061] In one exemplary embodiment of this disclosure, the thickness of the first oxide layer 4 on the sidewall of the active layer 1 of the first channel region is less than the thickness of the first oxide layer 4 on the sidewall of the active layer 1 of the second channel region 14. This makes it easier for hot carriers to be injected into the isolation structure (e.g., including the isolation layer 5) on the sidewall of the active layer of the first channel region. As a result, the hot electron induced punch-through (HEIP) effect can be enhanced in the antifuse 200 compared to the read transistor 300. The antifuse 200 is easier to break down, which can reduce the programming voltage, further simplify the driving circuit system that provides the programming voltage, and reduce manufacturing costs. It should be noted that, in the disclosure, the thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the first channel region is less than the thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the second channel region 14. This means that, overall, the average thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the first channel region is less than the average thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the second channel region 14; locally, the thickness of the first oxide layer 4 near the top of the sidewall of the active layer 1 in the first channel region is less than the thickness of the first oxide layer 4 at various locations on the sidewall of the active layer 1 in the second channel region 14, while the thickness of the first oxide layer 4 at other locations on the sidewall of the active layer 1 in the first channel region can be less than or equal to the thickness of the first oxide layer 4 at the corresponding location on the sidewall of the active layer 1 in the second channel region 14.

[0062] For example, the thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the first channel region can be 0.5 nm to 30 nm, and the thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the second channel region 14 can be 1 nm to 50 nm.

[0063] In one exemplary embodiment of this disclosure, the first oxide layer 4 on the sidewall of the active layer 1 in the first channel region includes a first portion away from the substrate and a second portion close to the substrate. For example, the first portion and the second portion can be demarcated by the centerline in the thickness direction of the active layer 1, that is, the first oxide layer 4 on the side away from the substrate in the thickness direction of the active layer 1 is the first portion, and the first oxide layer 4 on the side close to the substrate in the thickness direction of the active layer 1 is the second portion; the first portion and the second portion can also be demarcated by the interface line at one-third of the thickness direction of the active layer 1, that is, the first oxide layer 4 on the side away from the substrate at one-third of the thickness direction of the active layer 1 can be the first portion, and the first oxide layer 4 on the side close to the substrate at one-third of the thickness direction of the active layer 1 can be the second portion; or, the first portion and the second portion can also be demarcated by the interface line at two-thirds of the thickness direction of the active layer 1, that is, the first oxide layer 4 on the side away from the substrate at two-thirds of the thickness direction of the active layer 1 can be the first portion, and the first oxide layer 4 on the side close to the substrate at two-thirds of the thickness direction of the active layer 1 can be the second portion. Of course, the first part and the second part can also be divided by other dimension lines in the thickness direction of the active layer 1, which are not specifically limited here.

[0064] In some implementations, the thickness of the first portion may be less than the thickness of the second portion in the direction parallel to the substrate.

[0065] In one exemplary embodiment of this disclosure, the thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the first channel region gradually decreases from the side closer to the substrate to the side farther from the substrate. That is, in the direction perpendicular to the substrate, the thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the first channel region gradually shrinks from the side closer to the substrate to the side farther from the substrate, thereby making the first oxide layer 4 have a smooth surface in the direction perpendicular to the substrate.

[0066] The isolation layer 5 can be located on the side of the first oxide layer 4 away from the active layer 1. For example, the isolation layer 5 can be disposed on the sidewall of the first channel region and the second channel region 14 and located on the surface of the first oxide layer 4. The isolation layer 5 can be made of an insulating material, for example, a nitride, such as silicon nitride. The isolation layer 5 can provide insulation protection for the surface of the first oxide layer 4 to prevent leakage. For example, the isolation layer 5 can also be used to adjust the effect of the isolation structure on the stress of the active layer 1.

[0067] For example, the isolation layer 5 can be a thin film or a coating formed on the surface of the first oxide layer 4, without any particular limitation. The isolation layer 5 can be formed on the surface of the first oxide layer 4 using processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, without any particular limitation on the process for forming the isolation layer 5.

[0068] In some embodiments of this disclosure, the thickness of the isolation layer 5 can be 5nm to 70nm, for example, it can be 5nm, 10nm, 20nm, 40nm or 70nm, etc. Of course, the isolation layer 5 can also be other thicknesses, which will not be listed here.

[0069] The second oxide layer 6 can be located on the side of the isolation layer 5 away from the first oxide layer 4. The second oxide layer 6 can be made of insulating material. The second oxide layer 6 can provide further insulation protection for the first channel region and the second channel region 14, and prevent coupling between the first channel region and the second channel region 14 and other conductive structures, thereby improving product stability and yield. At the same time, the second oxide layer 6 has tension, which can balance the stress in the isolation layer 5. The combination of the second oxide layer 6 and the isolation layer 5 can regulate the stress on the active layer 1, and further regulate the carrier mobility.

[0070] For example, the second oxide layer 6 can be a thin film or a coating formed on the surface of the isolation layer 5, without any special limitation. The second oxide layer 6 can be formed on the surface of the isolation layer 5 using processes such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition, without any special limitation on the process for forming the second oxide layer 6.

[0071] In some embodiments of this disclosure, the thickness of the second oxide layer 6 can be 5nm to 500nm, for example, it can be 5nm, 50nm, 100nm, 200nm or 500nm, etc. Of course, the second oxide layer 6 can also have other thicknesses, which will not be listed here.

[0072] The working principle of the antifuse structure in the embodiments of this disclosure is explained below: In the antifuse structure disclosed herein, the first gate layer can form an antifuse 200 together with a first doped region and a third doped region (if any). Designing the first and third doped regions as P-type doped regions helps to induce the HEIP effect of the antifuse 200, making the antifuse 200 easier to break down, thereby reducing the programming voltage. At the same time, since the thickness of the first oxide layer 4 on the sidewall of the active layer 1 of the first channel region is less than the thickness of the first oxide layer 4 on the sidewall of the active layer 1 of the second channel region 14, hot carriers are more easily injected into the isolation structure (e.g., including the isolation layer 5) on the sidewall of the active layer 1 of the first channel region. Thus, compared with the read transistor 300, the hot electron induced punch-through (HEIP) effect can be enhanced in the antifuse 200, making the antifuse 200 easier to break down, further reducing the programming voltage, and further simplifying the driving circuit system that provides the programming voltage, thereby reducing manufacturing costs. Simultaneously, it can reduce the possibility of read transistor 300 being broken down, thereby reducing the probability of read transistor 300 damage and improving device stability; in addition, the first gate layer and the second gate layer 3 sharing the first doped region can also reduce device size. Furthermore, the isolation layer 5 and the second oxide layer 6 can be used to insulate and protect the sidewalls of the first channel region and the second channel region 14, preventing read transistor 300 and antifuse 200 from coupling with other surrounding components, which can improve product yield.

[0073] This disclosure also provides a method for forming an antifuse structure, such as... Figure 3 As shown, the forming method includes steps S110-S140, wherein: Step S110, providing a substrate, the substrate including a base and an active layer formed on the base, the active layer including a first channel region and a second channel region arranged at intervals; Step S120: A first oxide layer is formed, which covers the sidewall of the active layer. The thickness of the first oxide layer on the sidewall of the active layer in the first channel region is less than the thickness of the first oxide layer on the sidewall of the active layer in the second channel region. Step S130: Forming an isolation layer and a second oxide layer, wherein the isolation layer is located on the side of the first oxide layer away from the active layer, and the second oxide layer is located on the side of the isolation layer away from the first oxide layer; and Step S140: A first gate layer and a second gate layer are formed, wherein the first gate layer is located on top of the active layer in the first channel region, and the second gate layer is located on top of the active layer in the second channel region.

[0074] The method for forming the antifuse structure disclosed herein allows for the formation of an antifuse 200 using a first gate layer, which can be used for programming. Simultaneously, a second gate layer 3 can be used to form a read transistor 300, which functions as a switching element during the programming process of the antifuse 200. Because the thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the first channel region is less than the thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the second channel region 14, hot carriers are more easily injected into the isolation structure (e.g., including an isolation layer 5) on the sidewall of the active layer 1 in the first channel region. Therefore, compared to the read transistor 300, the hot electron-induced punch-through (HEIP) effect is enhanced in the antifuse 200, making it easier to break down and thus reducing the programming voltage. Furthermore, the isolation layer 5 provides insulation protection for the first and second channel regions 14, preventing coupling between the read transistor 300 and the antifuse 200 and other surrounding components, thereby improving product yield.

[0075] The steps of the method for forming the antifuse structure in the embodiments of this disclosure will be described in detail below: like Figure 3 As shown, in step S110, a substrate is provided, the substrate including a base and an active layer formed on the base, the active layer including a first channel region and a second channel region arranged at intervals.

[0076] The substrate may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be a semiconductor material, such as silicon, but not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of the substrate.

[0077] In one embodiment, the substrate may be a silicon substrate with multiple shallow trenches (not shown in the figure) formed therein. The subsequently formed first oxide layer 4, isolation layer 5, and second oxide layer 6 can fill the shallow trenches. The cross-sectional shape of the shallow trench isolation structure can be set according to actual needs. The multiple shallow trenches can be distributed side by side and can isolate several spaced active layers 1 on the substrate. In some embodiments, the substrate may further include a substrate, and each active layer 1 can be located on the substrate.

[0078] like Figure 3 As shown, in step S120, a first oxide layer is formed, which covers the sidewall of the active layer. The thickness of the first oxide layer on the sidewall of the active layer in the first channel region is less than the thickness of the first oxide layer on the sidewall of the active layer in the second channel region.

[0079] The first oxide layer 4 can cover the sidewalls of the active layer 1 and can be in contact with the first gate oxide layer, and can also be in contact with the second gate oxide layer 301. For example, the first oxide layer 4 can cover the sidewalls of the first channel region and the second channel region 14. It can be a coating formed on the sidewalls of the first channel region and the second channel region 14, or it can be a thin film formed on the sidewalls of the first channel region and the second channel region 14. The specific form of the first oxide layer 4 is not particularly limited here. In one embodiment, the first oxide layer 4 can be formed on the sidewalls of the first channel region and the second channel region 14 by means of ion implantation, chemical vapor deposition, thermal oxidation, physical vapor deposition or atomic layer deposition, etc. Of course, the first oxide layer 4 can also be formed by other means, and is not particularly limited here.

[0080] The material of the first oxide layer 4 can be an insulating material, for example, it can be silicon dioxide or other dielectric materials, or any combination thereof.

[0081] In one exemplary embodiment of this disclosure, the thickness of the first oxide layer 4 on the sidewall of the active layer 1 of the first channel region is less than the thickness of the first oxide layer 4 on the sidewall of the active layer 1 of the second channel region 14. This makes it easier for hot carriers to be injected into the isolation structure on the sidewall of the active layer 1 of the first channel region (e.g., including the subsequently formed isolation layer 5). As a result, the hot electron-induced punch-through (HEIP) effect can be enhanced in the antifuse 200 compared to the read transistor 300. The antifuse 200 is easier to break down, which can reduce the programming voltage, further simplify the driving circuit system that provides the programming voltage, and reduce manufacturing costs. It should be noted that, in the disclosure, the thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the first channel region is less than the thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the second channel region 14. This means that, overall, the average thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the first channel region is less than the average thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the second channel region 14; locally, the thickness of the first oxide layer 4 near the top of the sidewall of the active layer 1 in the first channel region is less than the thickness of the first oxide layer 4 at various locations on the sidewall of the active layer 1 in the second channel region 14, while the thickness of the first oxide layer 4 at other locations on the sidewall of the active layer 1 in the first channel region can be less than or equal to the thickness of the first oxide layer 4 at the corresponding location on the sidewall of the active layer 1 in the second channel region 14.

[0082] For example, the thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the first channel region can be 0.5 nm to 30 nm, and the thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the second channel region 14 can be 1 nm to 50 nm.

[0083] In one exemplary embodiment of this disclosure, the first oxide layer 4 on the sidewall of the active layer 1 in the first channel region includes a first portion away from the substrate and a second portion close to the substrate. For example, the first portion and the second portion can be separated by the centerline in the thickness direction of the active layer 1, that is, the portion of the centerline in the thickness direction of the active layer 1 away from the substrate is the first portion, and the portion of the centerline in the thickness direction of the active layer 1 close to the substrate is the second portion; the first portion and the second portion can also be separated by the interface line at one-third of the thickness direction of the active layer 1, that is, the first oxide layer 4 at one-third of the thickness direction of the active layer 1 away from the substrate can be the first portion, and the first oxide layer 4 at one-third of the thickness direction of the active layer 1 close to the substrate can be the second portion; or, the first portion and the second portion can also be separated by the interface line at two-thirds of the thickness direction of the active layer 1, that is, the first oxide layer 4 at two-thirds of the thickness direction of the active layer 1 away from the substrate can be the first portion, and the first oxide layer 4 at two-thirds of the thickness direction of the active layer 1 close to the substrate can be the second portion. Of course, the first part and the second part can also be divided by other dimension lines in the thickness direction of the active layer 1, which are not specifically limited here.

[0084] In some implementations, the thickness of the first portion may be less than the thickness of the second portion in the direction parallel to the substrate.

[0085] In one exemplary embodiment of this disclosure, the thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the first channel region gradually decreases from the side closer to the substrate to the side farther from the substrate. That is, in the direction perpendicular to the substrate, the thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the first channel region gradually shrinks from the side closer to the substrate to the side farther from the substrate, thereby making the first oxide layer 4 have a smooth surface in the direction perpendicular to the substrate.

[0086] In one exemplary embodiment of this disclosure, forming the first oxide layer 4 (i.e., step S120) may include steps S210-S220, wherein: Step S210: Ion implantation is performed on the sidewall of the active layer 1 in the first channel region using a first type of ion.

[0087] Ion implantation (e.g., tilted ion implantation) can be used to implant first-type ions into the sidewalls of the active layer 1. For example, ion implantation can be used to implant ions into the sidewalls of the active layer 1 in the first channel region to form a first oxide layer 4 on the sidewalls of the active layer 1 in the first channel region. For example, the first-type ions may include, but are not limited to, nitrogen.

[0088] In one exemplary embodiment of this disclosure, the active layer 1 of the first channel region may include a third portion away from the substrate and a fourth portion close to the substrate. For example, the third portion and the fourth portion may be separated by the centerline in the thickness direction of the active layer 1, that is, the side of the centerline in the thickness direction of the active layer 1 away from the substrate is the third portion, and the side of the centerline in the thickness direction of the active layer 1 close to the substrate is the fourth portion. Alternatively, the third portion and the fourth portion may be separated by an interface line at one-third of the thickness direction of the active layer 1, that is, the thickness of the third portion may be one-third of the thickness of the active layer 1, and the thickness of the fourth portion may be two-thirds of the thickness of the active layer 1; or, the thickness of the third portion may be two-thirds of the thickness of the active layer 1, and the thickness of the fourth portion may be one-third of the thickness of the active layer 1. Of course, the third portion and the fourth portion may also be separated by other dimensional lines in the thickness direction of the active layer 1, which are not specifically limited here.

[0089] In one exemplary embodiment of this disclosure, during the ion implantation process, the ion concentration of the third part can be greater than that of the fourth part, thereby controlling the formation of a first oxide layer 4 of different thickness on the surface of the active layer 1 in the first channel region by different ion concentrations.

[0090] Step S220: The first oxide layer 4 is formed by alternating thermal oxidation and atomic layer deposition processes.

[0091] A first oxide layer 4 can be formed on the sidewall of the active layer 1 by alternating thermal oxidation and atomic layer deposition processes. During this process, the oxidation rate of the material in the active layer 1 in the thermal oxidation process can be reduced by injecting first-type ions on the sidewall of the active layer 1.

[0092] It should be noted that the higher the concentration of the first type of ions, the slower the oxidation rate of the active layer 1 material. Within the same deposition time, a higher concentration of the first type of ions results in a thinner first oxide layer 4 formed on its surface. Since the ion concentration in the third part is greater than that in the fourth part, the thickness of the first oxide layer 4 formed on the surface of the third part is less than that formed on the surface of the fourth part. Furthermore, because no first type of ions are injected into the sidewalls of the second channel region 14, the thickness of the first oxide layer 4 formed on the surface of the first channel region is less than that formed on the surface of the second channel region 14.

[0093] In some embodiments, the first part may cover the surface of the third part, the second part may cover the surface of the fourth part, and the thickness of the first oxide layer 4 formed on the surface of the third part is less than the thickness of the first oxide layer 4 formed on the surface of the fourth part, that is, in the direction parallel to the substrate, the thickness of the first part is less than the thickness of the second part.

[0094] In one exemplary embodiment of this disclosure, the ion concentration of the active layer 1 in the first channel region gradually decreases from the side away from the substrate to the side closer to the substrate, thereby causing the thickness of the first oxide layer 4 formed on the surface of the first oxide layer 4 in the first channel region to gradually decrease from the side closer to the substrate to the side away from the substrate. That is, in the direction perpendicular to the substrate, the thickness of the first oxide layer 4 on the sidewall of the active layer 1 in the first channel region gradually shrinks from the side closer to the substrate to the side away from the substrate, thereby causing the first oxide layer 4 to have a smooth surface in the direction perpendicular to the substrate.

[0095] In some other embodiments of this disclosure, forming the first oxide layer 4 (i.e., step S120) may include steps S310 and S320, wherein: Step S310: Ion implantation is performed on the sidewall of the active layer 1 of the second channel region 14 using a second type of ion.

[0096] A second type of ion can be implanted into the sidewall of the active layer 1 using an ion implantation process. For example, an ion implantation process can be used to implant ions into the sidewall of the active layer 1 in the second channel region 14, so as to form a first oxide layer 4 on the sidewall of the active layer 1 in the second channel region 14. For example, the second type of ion may include, but is not limited to, germanium.

[0097] Step S320: The first oxide layer 4 is formed by thermal oxidation process.

[0098] A first oxide layer 4 can be formed on the sidewall of the active layer 1 in the second channel region 14 using a thermal oxidation process. During this process, the oxidation rate of the active layer 1 material in the thermal oxidation process can be increased by injecting second-type ions onto the sidewall of the active layer 1, which helps to quickly form a thicker first oxide layer 4 on the sidewall of the active layer 1 in the second channel region 14. In this process, since no second-type ions are injected into the sidewall of the first channel region, the rate at which the first oxide layer 4 is formed on the sidewall of the first channel region is slower than the rate at which the first oxide layer 4 is formed on the sidewall of the second channel region 14. In the same amount of time, the thickness of the first oxide layer 4 formed on the sidewall of the first channel region is less than the thickness of the first oxide layer 4 formed on the sidewall of the second channel region 14.

[0099] like Figure 3 As shown, in step S130, an isolation layer and a second oxide layer are formed. The isolation layer is located on the side of the first oxide layer away from the active layer, and the second oxide layer is located on the side of the isolation layer away from the first oxide layer.

[0100] An isolation layer 5 can be formed on the side of the first oxide layer 4 away from the active layer 1. For example, the isolation layer 5 can be formed on the sidewall of the first channel region and the second channel region 14 and located on the surface of the first oxide layer 4. The isolation layer 5 can be made of an insulating material, for example, a nitride, such as silicon nitride. The isolation layer 5 can provide insulation protection for the surface of the first oxide layer 4 to prevent leakage. For example, the isolation layer 5 can also be used to adjust the effect of the isolation structure on the stress of the active layer 1.

[0101] For example, the isolation layer 5 can be a thin film formed on the surface of the first oxide layer 4, or it can be a coating formed on the surface of the first oxide layer 4, without any special limitation. The thickness of the isolation layer 5 can be 5nm to 70nm, for example, it can be 5nm, 10nm, 20nm, 40nm or 70nm, etc. Of course, the isolation layer 5 can also be other thicknesses, which will not be listed here.

[0102] The second oxide layer 6 can be located on the side of the isolation layer 5 away from the first oxide layer 4. The second oxide layer 6 can be made of insulating material. The second oxide layer 6 can provide further insulation protection for the first channel region and the second channel region 14, avoid coupling between the first channel region and the second channel region 14 and other conductive structures, and improve product stability and yield.

[0103] For example, the second oxide layer 6 can be a thin film or a coating formed on the surface of the isolation layer 5, without any special limitation. The second oxide layer 6 can be formed on the surface of the isolation layer 5 using processes such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition, without any special limitation on the process for forming the second oxide layer 6.

[0104] In some embodiments of this disclosure, the thickness of the second oxide layer 6 can be 5nm to 500nm, for example, it can be 5nm, 50nm, 100nm, 200nm or 500nm, etc. Of course, the second oxide layer 6 can also have other thicknesses, which will not be listed here.

[0105] In one exemplary embodiment of this disclosure, forming the isolation layer 5 and the second oxide layer 6 (i.e., step S130) may include steps S410-S430, wherein: In step S410, a third oxide layer and a dielectric layer are sequentially formed on top of the active layer.

[0106] A third oxide layer 7 and a dielectric layer 8 can be sequentially formed on the surface of the active layer 1 using processes such as vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Figure 4As shown, the third oxide layer 7 and the dielectric layer 8 have different stress effects on the active layer 1 (one is tensile stress, and the other is compressive stress). The combination of the two can adjust the stress effect on the surface of the active layer 1, thus avoiding surface damage to the active layer 1. It can be understood that the third oxide layer 7 and the dielectric layer 8 can act as mask layers during the formation of the active layer 1 and the shallow trench.

[0107] In one embodiment, the substrate may include an active region, an active material layer may be formed on the surface of the active region, a third oxide material layer and a dielectric material layer may be formed on the surface of the active material layer, and the active material layer, the third oxide material layer and the dielectric material layer may be etched to form an active layer 1 and a third oxide layer 7 and a dielectric layer 8 located on top of the active layer 1.

[0108] In some embodiments, the third oxide layer 7 may be made of an oxidizing material, for example, silicon oxide. The dielectric layer 8 may be made of an insulating material, for example, silicon nitride.

[0109] In one embodiment, a third oxide layer 7 and a dielectric layer 8 may be formed on top of the active layer 1, and then a first oxide layer 4 may be formed, wherein the first oxide layer 4 may at least cover the sidewall of the active layer 1.

[0110] In step S420, an isolation material layer 510 and an oxide material layer are sequentially formed on the surface of the structure jointly formed by the active layer 1, the first oxide layer 4, the third oxide layer 7 and the dielectric layer 8.

[0111] An isolation material layer 510 can be formed on the surface of the structure composed of the active layer 1, the first oxide layer 4, the third oxide layer 7, and the dielectric layer 8 using processes such as vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Specifically, the isolation material layer 510 can cover the surface of the first oxide layer 4 on the sidewall of the active layer 1, the sidewall of the third oxide layer 7, the sidewall of the dielectric layer 8, and the top. The structure after step S420 is as follows: Figure 5 As shown.

[0112] The insulating material layer 510 may be made of an insulating material, for example, it may be a nitride, such as silicon nitride, and the insulating material layer 510 may be used to insulate and protect the surface of the first oxide layer 4 to prevent leakage.

[0113] An oxide material layer can be formed on the surface of the insulating material layer 510 using processes such as vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The oxide material layer can be composed of an oxide material, for example, silicon oxide. The oxide material layer can further insulate and protect the first and second channel regions 14, preventing coupling between the first and second channel regions 14 and other conductive structures, thereby improving product stability and yield.

[0114] Step S430: Remove the dielectric layer 8, the third oxide layer 7, and the oxide material layer and the isolation material layer 510 located on top of the active layer 1 to expose the top of the active layer 1.

[0115] Chemical mechanical polishing (CMP) can be used to polish the dielectric layer 8 and the third oxide layer 7 to remove part of the dielectric layer 8 and the third oxide layer 7. At the same time, selective etching can be used to remove the dielectric layer 8, the third oxide layer 7, and the oxide material layer and the isolation material layer 510 located on top of the active layer 1, thereby exposing the top of the active layer 1.

[0116] like Figure 3 As shown, in step S140, a first gate layer and a second gate layer 3 are formed. The first gate layer is located on top of the active layer 1 in the first channel region, and the second gate layer 3 is located on top of the active layer 1 in the second channel region 14.

[0117] A first gate layer may be formed on top of the active layer 1 in the first channel region, and a second gate layer 3 may be formed on top of the active layer 1 in the second channel region 14. The first gate layer may include a first gate oxide layer and a first gate electrode layer stacked together, both of which may be located on top of the active layer 1 in the first channel region. The second gate layer 3 may include a second gate oxide layer 301 and a second gate electrode layer 302 stacked together, both of which may be located on top of the active layer 1 in the second channel region 14.

[0118] In one exemplary embodiment of this disclosure, forming the first gate layer and the second gate layer 3 may include steps S510 and S520, wherein: In step S510, a gate oxide layer and a gate electrode layer are sequentially formed on top of the active layer 1.

[0119] The gate oxide layer and the gate electrode layer can be sequentially formed on top of the active layer 1 by means of chemical vapor deposition, thermal oxidation, physical vapor deposition or atomic layer deposition. Of course, the gate oxide layer and the gate electrode layer can also be formed by other means, and no special limitation is made here.

[0120] Step S520: Pattern the gate oxide layer and the gate electrode layer to form a first gate oxide layer, a second gate oxide layer 301, a first gate electrode layer and a second gate electrode layer 302.

[0121] A photoresist layer can be formed on the surface of the gate electrode layer away from the substrate by spin coating or other methods. The material of the photoresist layer can be positive or negative photoresist, without special limitation. A photomask can be used to expose the photoresist layer, and the pattern of the photomask can match the required patterns of the first gate layer and the second gate layer 3. Subsequently, the exposed photoresist layer can be developed to form multiple development areas, each of which exposes the gate electrode layer. The pattern of the development area can be the same as the required patterns of the first gate layer and the second gate layer 3, and the width of the development area can be the same as the required dimensions of the first gate layer and the second gate layer 3.

[0122] Anisotropic etching can be used to etch the gate electrode layer and the gate oxide layer in the developing region, thereby forming a first gate oxide layer and a first gate electrode layer on the surface of the first channel region. The first gate oxide layer and the first gate electrode layer can together constitute a first gate layer. At the same time, a second gate oxide layer 301 and a second gate electrode layer 302 are formed on the surface of the second channel region 14. The second gate oxide layer 301 and the second gate electrode layer 302 can together constitute a second gate layer 3.

[0123] It should be noted that after the above etching process is completed, the photoresist layer can be removed by cleaning with a cleaning solution or by ashing or other processes.

[0124] In some embodiments, the first gate layer may further include a first cover layer, which may cover the surface of the first gate electrode layer and the sidewalls of the first gate electrode layer and the first gate oxide layer, so as to provide insulation protection for the first gate electrode layer and the first gate oxide layer and prevent the first gate electrode layer and the first gate oxide layer from coupling or short-circuiting with other structures.

[0125] In some embodiments, the second gate layer 3 may further include a second cover layer, which may cover the surface of the second gate electrode layer 302 and the sidewalls of the second gate electrode layer 302 and the second gate oxide layer 301, so as to provide insulation protection for the second gate electrode layer 302 and the second gate oxide layer 301 and prevent the second gate electrode layer 302 and the second gate oxide layer 301 from coupling or short-circuiting with other structures.

[0126] In a first exemplary embodiment of this disclosure, forming a gate oxide layer may include steps S5101 and S5102, wherein: Step S5101: A gate oxide material layer is formed on top of the active layer 1.

[0127] The gate oxide material layer can be formed on the top of the first channel region and the second channel region 14 by means of chemical vapor deposition, thermal oxidation, physical vapor deposition or atomic layer deposition. Of course, the gate oxide material layer can also be formed by other means, and no special limitation is made here.

[0128] The gate oxide layer can be made of an insulating material, such as silicon dioxide, a high-k dielectric material, or other dielectric materials, or any combination thereof. The thickness of the first gate oxide layer can be set according to actual needs.

[0129] Step S5102: The gate oxide material layer on top of the active layer 1 located in the first channel region is thinned to obtain the first gate oxide layer.

[0130] An etching process can be used to etch the gate oxide material layer located at the top of the first channel region so that the thickness of the gate oxide material layer located at the top of the first channel region is less than the thickness of the gate oxide material layer located at the top of the second channel region 14. The gate oxide material layer at the top of the first channel region after thinning is the first gate oxide layer, and the gate oxide material layer at the top of the second channel region 14 without thinning is the second gate oxide layer 301.

[0131] In a second exemplary embodiment of this disclosure, forming the gate oxide layer may include steps S5103 and S5104, wherein: Step S5103: A first gate oxide material layer is formed on top of the active layer 1.

[0132] The first gate oxide material layer can be formed on the top of the first channel region and the second channel region 14 by means of chemical vapor deposition, thermal oxidation, physical vapor deposition or atomic layer deposition. Of course, the first gate oxide material layer can also be formed by other means, and no special limitation is made here.

[0133] The material of the first gate oxide layer can be an insulating material, such as silicon dioxide, a high-k dielectric material, or other dielectric materials, or any combination thereof. The thickness of the first gate oxide layer can be set according to actual needs.

[0134] Step S5104: A second gate oxide layer is formed on the first gate oxide layer located on top of the active layer 1 in the second channel region 14.

[0135] The second gate oxide layer can be formed on the surface of the first gate oxide layer by means of chemical vapor deposition, thermal oxidation, physical vapor deposition or atomic layer deposition. Of course, the second gate oxide layer can also be formed by other means, and no special limitation is made here.

[0136] The material of the second gate oxide layer can be the same as that of the first gate oxide layer, so it will not be elaborated here. The thickness of the second gate oxide layer can be less than or equal to the thickness of the first gate oxide layer, and no special limitation is made here.

[0137] It should be noted that the first gate oxide material layer located at the top of the first channel region can be used as the first gate oxide layer, and the first gate oxide material layer and the second gate oxide layer 301 located at the top of the second channel region 14 can together constitute the second gate oxide layer 301.

[0138] In some embodiments of this disclosure, the active layer 1 may further include a first doped region and a second doped region arranged at intervals. The first doped region may be located between the first channel region and the second channel region 14, and the second doped region may be located on the side of the second channel region 14 away from the first doped region. After patterning the gate oxide layer and the gate electrode layer, the active layer 1 between the first channel region and the second channel region 14, and the active layer 1 on the side of the second channel region 14 away from the first channel region, are exposed, that is, the first doped region and the second doped region are exposed.

[0139] In some embodiments of this disclosure, the method of forming this disclosure may further include: Step S150: The active layer 1 between the first channel region and the second channel region 14 and the active layer 1 on the side of the second channel region 14 away from the first channel region are doped to obtain a first doped region and a second doped region.

[0140] The substrate can be an n-type substrate, and both the first and second doped regions can be p-type doped regions. The first and second doped regions can be p-type doped to form p-type doped regions in both regions.

[0141] For example, p-type dopant material can be doped into the first doped region and the second doped region to form a p-type semiconductor. The p-type dopant material can be an element located in Group III of the periodic table, for example, it can be boron, and of course, it can be materials of other elements, which will not be listed here.

[0142] It should be noted that before doping, the first doped region and the second doped region can also be referred to as the first region to be doped and the second region to be doped, respectively.

[0143] In one embodiment, boron ions can be implanted into the first doped region and the second doped region by ion implantation. Of course, other processes can also be used to dope the first doped region and the second doped region, and no special limitation is made here.

[0144] The first doped region and the second doped region can serve as the source and drain, respectively. The second gate layer 3, the source, and the drain can together form a p-type transistor. This transistor can serve as a read transistor 300 with an antifuse structure, and the read transistor 300 can serve as a switching element.

[0145] In other embodiments of this disclosure, in order to maintain the symmetry of the device and facilitate process operation, the active layer 1 may further include a third doped region. The third doped region may be located on the side of the first channel region away from the first doped region. After patterning the gate oxide layer and the gate electrode layer, the active layer 1 between the first channel region and the second channel region 14, the active layer 1 on the side of the second channel region 14 away from the first channel region, and the active layer 1 on the side of the first channel region away from the second channel region 14 are exposed, that is, the first doped region, the second doped region, and the third doped region are all exposed. The formation method of this disclosure may further include: Step S160: Doping is performed on the active layer 1 between the first channel region and the second channel region 14, the active layer 1 on the side of the second channel region 14 away from the first channel region, and the active layer 1 on the side of the first channel region away from the second channel region 14 to obtain a first doped region, a second doped region, and a third doped region.

[0146] The third doped region can be p-type doped to form a p-type doped region. The formation method of the third doped region can refer to the formation method of the first and second doped regions, and will not be repeated here.

[0147] The third doped region and the first doped region can serve as the source and drain, respectively. The first gate layer, the source, and the drain can together form a transistor, which can serve as an antifuse 200 of an antifuse structure (e.g., an antifuse in the form of a transistor). Since the antifuse 200 in the form of a p-type transistor is prone to the hot electron-induced punch-through (HEIP) effect, the antifuse 200 is easily broken down, which can reduce the programming voltage.

[0148] It should be noted that although the steps of the method for forming the antifuse structure in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0149] This disclosure also provides a memory, which may include the antifuse structure of any of the above embodiments. Its specific details, formation process and beneficial effects have been described in detail in the corresponding antifuse structure and the method for forming the antifuse structure, and will not be repeated here.

[0150] For example, the memory can be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. Of course, it can also be other storage devices, which will not be listed here.

[0151] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An antifuse structure, characterized in that, include: The substrate includes a base and an active layer formed on the base, the active layer including a first channel region and a second channel region arranged at intervals; A first oxide layer covers the sidewall of the active layer; the thickness of the first oxide layer on the sidewall of the active layer in the first channel region is less than the thickness of the first oxide layer on the sidewall of the active layer in the second channel region. An isolation layer is located on the side of the first oxide layer away from the active layer; The second oxide layer is located on the side of the isolation layer away from the first oxide layer; A first gate layer is located on top of the active layer in the first channel region; The second gate layer is located on top of the active layer in the second channel region; The antifuse structure includes a read transistor and an antifuse, wherein the first gate layer is the gate of the antifuse and the second gate layer is the gate of the read transistor.

2. The antifuse structure according to claim 1, characterized in that, The first oxide layer on the sidewall of the active layer in the first channel region includes a first portion away from the substrate and a second portion close to the substrate, wherein the thickness of the first portion is less than the thickness of the second portion.

3. The antifuse structure according to claim 1, characterized in that, The thickness of the first oxide layer on the sidewall of the active layer in the first channel region gradually decreases from the side closer to the substrate to the side farther away from the substrate.

4. The antifuse structure according to claim 1, characterized in that, The active layer further includes a first doped region and a second doped region arranged at intervals. The first doped region is located between the first channel region and the second channel region, and the second doped region is located on the side of the second channel region away from the first doped region. Both the first doped region and the second doped region are P-type doped regions.

5. The antifuse structure according to claim 4, characterized in that, The active layer further includes a third doped region, which is located on the side of the first channel region away from the first doped region, and the third doped region is a P-type doped region.

6. The antifuse structure according to any one of claims 1-5, characterized in that, The first gate layer includes: A first gate oxide layer is located on top of the active layer in the first channel region and is in contact with the first oxide layer. The first gate electrode layer is located on the side of the first gate oxide layer away from the substrate; The second gate layer includes: The second gate oxide layer is located on top of the active layer in the second channel region and is in contact with the second oxide layer. The second gate electrode layer is located on the side of the second gate oxide layer away from the substrate.

7. The antifuse structure according to claim 6, characterized in that, The thickness of the first gate oxide layer is less than the thickness of the second gate oxide layer.

8. A method for forming an antifuse structure, characterized in that, include: A substrate is provided, the substrate including a base and an active layer formed on the base, the active layer including a first channel region and a second channel region arranged at intervals; A first oxide layer is formed, which covers the sidewall of the active layer; the thickness of the first oxide layer on the sidewall of the active layer in the first channel region is less than the thickness of the first oxide layer on the sidewall of the active layer in the second channel region. An isolation layer and a second oxide layer are formed, wherein the isolation layer is located on the side of the first oxide layer away from the active layer, and the second oxide layer is located on the side of the isolation layer away from the first oxide layer; as well as A first gate layer and a second gate layer are formed, wherein the first gate layer is located on top of the active layer in the first channel region, and the second gate layer is located on top of the active layer in the second channel region; The antifuse structure includes a read transistor and an antifuse, wherein the first gate layer is the gate of the antifuse and the second gate layer is the gate of the read transistor.

9. The forming method according to claim 8, characterized in that, Forming the first oxide layer includes: Ion implantation is performed on the sidewalls of the active layer in the first channel region using type I ions. The first oxide layer is formed by alternating thermal oxidation and atomic layer deposition processes; The first type of ions is used to reduce the oxidation rate of the active layer material in the thermal oxidation process.

10. The forming method according to claim 9, characterized in that, The active layer of the first channel region includes a third portion away from the substrate and a fourth portion close to the substrate; during the ion implantation process, the ion concentration of the third portion is greater than the ion concentration of the fourth portion; The first oxide layer on the sidewall of the active layer in the first channel region includes a first portion away from the substrate and a second portion close to the substrate, wherein the thickness of the first portion is less than the thickness of the second portion.

11. The forming method according to claim 9, characterized in that, The ion concentration of the active layer in the first channel region gradually decreases from the side away from the substrate to the side closer to the substrate; The thickness of the first oxide layer on the sidewall of the active layer in the first channel region gradually decreases from the side closer to the substrate to the side farther away from the substrate.

12. The forming method according to claim 8, characterized in that, Forming the first oxide layer includes: Ion implantation of the active layer in the second channel region is performed using type II ions. The first oxide layer is formed by a thermal oxidation process; The second type of ions is used to increase the oxidation rate of the active layer material in the thermal oxidation process.

13. The forming method according to claim 8, characterized in that, Forming the insulating layer and the second oxide layer includes: A third oxide layer and a dielectric layer are sequentially formed on top of the active layer; An isolation material layer and an oxide material layer are sequentially formed on the surface of the structure jointly formed by the active layer, the first oxide layer, the third oxide layer and the dielectric layer; Remove the dielectric layer, the third oxide layer, the oxide material layer and the isolation material layer located on top of the active layer to expose the top of the active layer.

14. The forming method according to claim 13, characterized in that, Forming the first gate layer and the second gate layer includes: A gate oxide layer and a gate electrode layer are sequentially formed on top of the active layer; The gate oxide layer and the gate electrode layer are patterned to form a first gate oxide layer, a second gate oxide layer, a first gate electrode layer, and a second gate electrode layer; The first gate layer includes the first gate oxide layer and the first gate electrode layer, and the second gate layer includes the second gate oxide layer and the second gate electrode layer.

15. The forming method according to claim 14, characterized in that, Forming the gate oxide layer includes: A gate oxide material layer is formed on top of the active layer; The gate oxide material layer located on top of the active layer in the first channel region is thinned to obtain the first gate oxide layer.

16. The forming method according to claim 14, characterized in that, Forming the gate oxide layer includes: A first gate oxide material layer is formed on top of the active layer; A second gate oxide layer is formed on the first gate oxide layer located on top of the active layer in the second channel region; The second gate oxide layer includes the first gate oxide material layer and the second gate oxide material layer.

17. The forming method according to claim 14, characterized in that, After the gate oxide layer and the gate electrode layer are patterned, the active layer between the first channel region and the second channel region, and the active layer on the side of the second channel region away from the first channel region are exposed; The forming method further includes: The active layer between the first channel region and the second channel region, and the active layer on the side of the second channel region away from the first channel region, are doped to obtain a first doped region and a second doped region.

18. The forming method according to claim 14, characterized in that, After the gate oxide layer and the gate electrode layer are patterned, the active layer between the first channel region and the second channel region, the active layer on the side of the second channel region away from the first channel region, and the active layer on the side of the first channel region away from the second channel region are exposed. The forming method further includes: The active layer between the first channel region and the second channel region, the active layer on the side of the second channel region away from the first channel region, and the active layer on the side of the first channel region away from the second channel region are doped to obtain a first doped region, a second doped region, and a third doped region.

19. A memory, characterized in that, Includes the antifuse structure according to any one of claims 1-7.

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