Special-shaped display panel and display device

Abstract

The application provides a special-shaped display panel, comprising a display area, the display area comprising a plurality of sub-display areas; the special-shaped display panel comprising a plurality of cascade signal lines for coupling two adjacent gate driving sub-circuits, at least one cascade signal line comprising a first cascade trace extending along a first direction and a second cascade trace extending along a second direction; the first cascade trace comprising a plurality of first conductive patterns arranged on a first conductive layer and a second conductive pattern arranged on a second conductive layer, the plurality of first conductive patterns being electrically connected with the second conductive pattern; the second cascade trace comprising a third conductive pattern arranged on the first conductive layer. The special-shaped display panel provided by the embodiment of the application can avoid cascade abnormality caused by the fact that the length of the cascade signal line between the two adjacent gate driving sub-circuits is relatively long and thus the resistance is relatively large.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to an irregularly shaped display panel and display device. Background Technology

[0002] The global display industry is developing rapidly, and market demand is becoming increasingly diversified. Traditional displays have a single shape, limited functions, and cannot be changed at will according to different scenarios. They have begun to fail to meet the needs of high-end displays, so irregularly shaped screens have emerged.

[0003] Due to the varying shapes of irregularly shaped screens, Gate Drive In Active Area (GIA) technology is required. The cascaded signal lines between different GIA groups are fabricated using a gate metal layer (GT layer). However, the GT layer is made of Mo metal, which has excessively high resistance. This high resistance in the cascaded signal lines between different GIA groups can lead to cascading abnormalities. The signal bus, also fabricated using a single-layer GT, suffers from the same problem. Summary of the Invention

[0004] The present invention provides an irregularly shaped display panel and display device, which can avoid cascading abnormalities between two adjacent gate drive sub-circuits.

[0005] A first aspect of the present invention provides an irregularly shaped display panel, including a display area, the display area including a plurality of sub-display areas;

[0006] The irregularly shaped display panel includes a substrate and a gate driving circuit located on the substrate;

[0007] The gate driving circuit includes multiple cascaded gate driving sub-circuits; each of the multiple cascaded gate driving sub-circuits corresponds one-to-one with the multiple sub-display areas, and each gate driving sub-circuit is located within its corresponding sub-display area.

[0008] Multiple cascaded signal lines are used to couple two adjacent gate driver sub-circuits, and at least one cascaded signal line includes a first cascaded trace extending along a first direction and a second cascaded trace extending along a second direction.

[0009] The first cascaded trace includes a plurality of first conductive patterns disposed on a first conductive layer and a second conductive pattern disposed on a second conductive layer. The plurality of first conductive patterns are electrically connected to the second conductive pattern, and the orthographic projection of the plurality of first conductive patterns on the substrate at least partially overlaps with the orthographic projection of the second conductive pattern on the substrate. The second cascaded trace includes a third conductive pattern disposed on the first conductive layer.

[0010] Optionally, the plurality of first conductive patterns and the second conductive patterns are electrically connected through a plurality of vias.

[0011] Optionally, the plurality of first conductive patterns are spaced apart.

[0012] Optionally, the irregularly shaped display panel includes a first gate metal layer, a second gate metal layer, and a first source / drain metal layer stacked sequentially along a direction away from the substrate, wherein the first conductive layer is made of the first source / drain metal layer, and the second conductive layer is made of the first gate metal layer.

[0013] Optionally, the first cascaded wiring further includes:

[0014] A fourth conductive pattern is electrically connected to the plurality of first conductive patterns, and the orthographic projections of the plurality of first conductive patterns on the substrate at least partially overlap with the orthographic projections of the fourth conductive pattern on the substrate.

[0015] The fourth conductive pattern is electrically connected to the second conductive pattern, and the orthographic projection of the second conductive pattern on the substrate at least partially overlaps with the orthographic projection of the fourth conductive pattern on the substrate.

[0016] Optionally, the second cascaded wiring also includes:

[0017] A fifth conductive pattern is electrically connected to the third conductive pattern, and the orthographic projection of the fifth conductive pattern on the substrate at least partially overlaps with the orthographic projection of the third conductive pattern on the substrate.

[0018] Optionally, the irregularly shaped display panel further includes: a multi-row sub-pixel driving circuit located on the substrate, the sub-pixel driving circuit further including:

[0019] Multiple first initialization signal lines, at least a portion of which extend along the second direction;

[0020] Multiple second initialization signal lines, at least a portion of which extend along the second direction;

[0021] Multiple data lines, at least a portion of which extend along the second direction; and

[0022] Multiple power lines, at least a portion of which extend along the second direction;

[0023] The orthographic projection of the first conductive pattern on the substrate does not overlap with the orthographic projections of the data line, the power line, the first initialization signal line, and the second initialization signal line on the substrate.

[0024] Optionally, the first initialization signal line, the second initialization signal line, the data line, and the power line are made of the same layer and material as the first conductive pattern.

[0025] Optionally, the sub-pixel driving circuit further includes:

[0026] The transistor includes a data writing transistor, a first reset transistor, a driving transistor, a second reset transistor, and a light-emitting control transistor.

[0027] The sub-pixel driving circuit also includes:

[0028] First scan line, second scan line, third scan line, and light emission control signal line;

[0029] The first terminal of the data writing transistor is coupled to the corresponding data line, the second terminal of the data writing transistor is coupled to the second terminal of the first reset transistor, and the gate of the data writing transistor is coupled to the corresponding first scan line.

[0030] The first terminal of the first reset transistor is coupled to the corresponding second initialization signal line, the second terminal of the first reset transistor is coupled to the second terminal of the data write transistor, and the gate of the first reset transistor is coupled to the corresponding second scan line.

[0031] The first terminal of the driving transistor is coupled to the second terminal of the second reset transistor, the second terminal of the driving transistor is coupled to the second terminal of the light-emitting control transistor, and the gate of the driving transistor is coupled to the second terminal of the data writing transistor.

[0032] The first terminal of the second reset transistor is coupled to the corresponding first initialization signal line, the second terminal of the second reset transistor is coupled to the anode of the light-emitting element, and the gate of the second reset transistor is coupled to the corresponding third scan line.

[0033] The first terminal of the light-emitting control transistor is coupled to the corresponding power supply line, the second terminal of the light-emitting control transistor is coupled to the second terminal of the driving transistor, and the gate of the light-emitting control transistor is coupled to the light-emitting control signal line.

[0034] The first plate of the storage capacitor is reused as the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the second electrode of the second reset transistor.

[0035] Optionally, at least one gate drive sub-circuit includes: a plurality of cascaded first GOA units, a plurality of cascaded second GOA units, a plurality of cascaded third GOA units, and a plurality of cascaded fourth GOA units.

[0036] The first GOA unit includes at least: a first cascaded output terminal, a reset signal terminal, and a first signal input terminal;

[0037] The second GOA unit includes a second signal input terminal and a second cascaded output terminal;

[0038] The third GOA unit includes a third signal input terminal and a third cascaded output terminal; and

[0039] The fourth GOA unit includes a fourth signal input terminal and a fourth cascaded output terminal;

[0040] The multiple cascaded signal lines include: a first cascaded output signal line, a reset signal line, a second signal input line, a third signal input line, and a fourth signal input line;

[0041] The first cascaded output signal line has one end coupled to the first cascaded output terminal of the last first GOA unit of one of the two adjacent gate driving sub-circuits, and the other end coupled to the first signal input terminal of the first first GOA unit of the other gate driving sub-circuit in the other two adjacent gate driving sub-circuits.

[0042] The reset signal line is coupled at one end to the reset signal terminal of the last first GOA unit of one of the two adjacent gate driving sub-circuits, and at the other end to the first signal input terminal of the first first GOA unit of the other gate driving sub-circuit.

[0043] The second signal input line has one end coupled to the second cascaded output terminal of the last second GOA unit of one of the two adjacent gate driving sub-circuits, and the other end coupled to the second signal input terminal of the first second GOA unit of the other gate driving sub-circuit.

[0044] The third signal input line is coupled at one end to the third cascade output terminal of the last third GOA unit of one of the two adjacent gate driving sub-circuits, and at the other end to the third signal input terminal of the first third GOA unit of the other gate driving sub-circuit.

[0045] The fourth signal input line is coupled at one end to the fourth cascade output terminal of the last fourth GOA unit of one of the two adjacent gate driver sub-circuits, and at the other end to the fourth signal input terminal of the first fourth GOA unit of the other gate driver sub-circuit.

[0046] Optionally, there is a first gap between two adjacent columns of sub-pixel driving circuits;

[0047] There is a second gap between two adjacent rows of sub-pixel driving circuits;

[0048] The second signal input line includes two parallel second sub-signal input lines, wherein at least a portion of one second sub-signal input line extends along the second direction, and at least a portion of the other second sub-signal input line extends along the second direction, and the two parallel second sub-signal input lines are located within the same second gap;

[0049] The third signal input line includes two parallel third sub-signal input lines, wherein at least a portion of one third sub-signal input line extends along the second direction, and at least a portion of the other third sub-signal input line extends along the second direction, and the two parallel third sub-signal input lines are located in different first gaps;

[0050] The fourth signal input line includes two parallel fourth sub-signal input lines, wherein at least a portion of one fourth sub-signal input line extends along the second direction, and at least a portion of the other third sub-signal input line extends along the second direction, and the two parallel third sub-signal input lines are located in different first gaps.

[0051] Optionally, the first GOA unit is coupled to the first scan line;

[0052] The second GOA unit is coupled to the second scan line;

[0053] The third GOA unit is coupled to the third scan line;

[0054] The fourth GOA unit is coupled to the light emission control signal line.

[0055] Optionally, the orthographic projections of the first GOA unit, the second GOA unit, the third GOA unit, and the fourth GOA unit on the substrate are located between the orthographic projections of two adjacent rows of sub-pixel driving circuits on the substrate.

[0056] Optionally, the first GOA unit, the second GOA unit, the third GOA unit, and the fourth GOA unit include:

[0057] The panel includes a total reset terminal, a first clock signal terminal, a second clock signal terminal, and a high-level terminal; the irregularly shaped display panel also includes:

[0058] Multiple buses and multiple common signal line groups located on the substrate;

[0059] The multiple buses include at least: multiple reset buses, multiple first clock buses, multiple second clock buses, and multiple high-level buses;

[0060] At least one of the common signal line groups includes:

[0061] Multiple total reset signal lines are located on the substrate, at least one of the total reset signal lines is coupled to the corresponding reset bus at one end, and the other end is coupled to the total reset terminal of the first GOA unit, the second GOA unit, the third GOA unit or the fourth GOA unit;

[0062] Multiple first clock signal lines located on the substrate, at least one of the first clock signal lines is coupled at one end to the corresponding first clock bus, and the other end is coupled to the first clock signal terminal of the first GOA unit, the second GOA unit, the third GOA unit or the fourth GOA unit;

[0063] Multiple second clock signal lines located on the substrate, at least one of the second clock signal lines is coupled at one end to the corresponding second clock bus, and the other end is coupled to the second clock signal terminal of the first GOA unit, the second GOA unit, the third GOA unit or the fourth GOA unit;

[0064] Multiple high-level signal lines are located on the substrate, at least one of which is coupled at one end to a corresponding high-level bus, and the other end is coupled to the high-level terminal of the first GOA unit, the second GOA unit, the third GOA unit, or the fourth GOA unit.

[0065] Optionally, the length of the cascaded signal line between the two gate driver sub-circuits is greater than the length of the cascaded signal line between the two first GOA units included in the gate driver sub-circuit.

[0066] The length of the cascaded signal line between the two gate driver sub-circuits is greater than the length of the cascaded signal line between the two second GOA units included in the gate driver sub-circuit.

[0067] The length of the cascaded signal line between the two gate driver sub-circuits is greater than the length of the cascaded signal line between the two third GOA units included in the gate driver sub-circuit.

[0068] The length of the cascaded signal line between the two gate driver sub-circuits is greater than the length of the cascaded signal line between the two fourth GOA units included in the gate driver sub-circuit.

[0069] Optionally, the orthographic projection of the first conductive pattern on the substrate does not overlap with the orthographic projections of the first clock signal line and the second clock signal line on the substrate.

[0070] Optionally, the first clock signal line and the second clock signal line are fabricated using a first source-drain metal layer.

[0071] Optionally, the at least one bus includes a third conductive layer and a fourth conductive layer, wherein the third conductive layer is fabricated using a first source / drain metal layer and the fourth conductive layer is fabricated using a first gate metal layer.

[0072] Optionally, the plurality of cascaded gate drive sub-circuits include: a first gate drive sub-circuit, a second gate drive sub-circuit, a third gate drive sub-circuit, and a fourth gate drive sub-circuit.

[0073] The first common signal line group is coupled to the first gate driver sub-circuit and the second gate driver sub-circuit;

[0074] The second common signal line group is coupled to the third gate driver sub-circuit;

[0075] The third common signal line group is coupled to the fourth gate driver sub-circuit.

[0076] A second aspect of the present invention provides a display device including the irregularly shaped display panel described above.

[0077] The embodiments of the present invention have the following beneficial effects:

[0078] The irregularly shaped display panel provided in this embodiment of the invention can avoid cascading abnormalities caused by the large resistance due to the long length of the cascaded signal line between two adjacent gate driving sub-circuits. Attached Figure Description

[0079] Figure 1 This is a schematic diagram of GIA grouping for an irregularly shaped display panel provided in an embodiment of the present invention;

[0080] Figure 2 This is a schematic diagram of the routing method for cascaded signal lines between different GIA groups provided in an embodiment of the present invention;

[0081] Figure 3 A schematic diagram of the common signal line group for an irregularly shaped display panel provided in an embodiment of the present invention;

[0082] Figure 4 for Figure 3 Enlarged view of region A3 in the middle;

[0083] Figure 5 for Figure 4 A schematic diagram of the cascaded signal line connection at point ①.

[0084] Figure 6 for Figure 4 Schematic diagram of the cascaded signal line connection at point ②;

[0085] Figure 7 for Figure 4 Schematic diagram of the cascaded signal line connection at point ③;

[0086] Figure 8 for Figure 4 Schematic diagram of the cascaded signal line connection at point ④;

[0087] Figure 9 for Figure 4 Schematic diagram of cascaded signal line connection at point ⑤;

[0088] Figure 10 for Figure 4 Schematic diagram of cascaded signal line connection at point ⑥;

[0089] Figure 11 To and Figure 10 A schematic diagram of the layout of the first gate metal layer at the corresponding position;

[0090] Figure 12 To and Figure 10 A schematic diagram of the layout of the first source / drain metal layer at the corresponding location;

[0091] Figure 13 This is a schematic diagram showing the connection between the first common signal line group and the bus.

[0092] Figure 14 This is a schematic diagram of the architecture of the first GOA unit U1;

[0093] Figure 15 This is a schematic diagram of the architecture of the second GOA unit U2, the third GOA unit U3, and the fourth GOA unit U4;

[0094] Figure 16 This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present invention;

[0095] Figure 17 A cross-sectional view of the double-layer routing interval segmentation position of the first cascaded routing provided in an embodiment of the present invention.

[0096] Figure Labels

[0097] A1 - Display area; A2 - Non-display area; A3 - Cascade signal line connection area

[0098] A4 - Connection area between the first common signal line group and the bus

[0099] L1 - First common signal line group; L2 - Second common signal line group; L3 - Third common signal line group

[0100] U1 - First GOA Unit; U2 - Second GOA Unit; U3 - Third GOA Unit

[0101] U4 - Fourth GOA Unit

[0102] 11-bus

[0103] 21-First cascade output signal line; 22-Reset signal line; 23-Second signal input line

[0104] 24 - Third signal input line; 25 - Fourth signal input line

[0105] 231 - Second sub-signal input line; 241 - Third sub-signal input line; 251 - Fourth sub-signal input line

[0106] 31-First scan line; 32-Second scan line; 33-Third scan line; 34-Light emission control signal line

[0107] 35 - First initialization signal line; 36 - Second initialization signal line; 37 - Data line; 38 - Power line

[0108] 41 - First clock signal line; 42 - Second clock signal line

[0109] 51-First conductive pattern 52-Orthogonal projection of the first conductive pattern onto the first gate metal layer

[0110] 61-First gate insulating layer; 62-First gate metal layer; 63-Second gate insulating layer; 64-Interlayer dielectric layer; 65-First source / drain metal layer

[0111] 71-via Detailed Implementation

[0112] To make the technical problems, technical solutions and advantages of the embodiments of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0113] The present invention addresses the problem in the prior art where excessive resistance of cascaded signal lines between different GIA groups can lead to cascade abnormalities by providing an irregularly shaped display panel and a display device.

[0114] Embodiments of the present invention provide an irregularly shaped display panel, including a display area, wherein the display area includes a plurality of sub-display areas;

[0115] The irregularly shaped display panel includes a substrate and a gate driving circuit located on the substrate;

[0116] The gate driving circuit includes multiple cascaded gate driving sub-circuits; each of the multiple cascaded gate driving sub-circuits corresponds one-to-one with the multiple sub-display areas, and each gate driving sub-circuit is located within its corresponding sub-display area.

[0117] Multiple cascaded signal lines are used to couple two adjacent gate driver sub-circuits, and at least one cascaded signal line includes a first cascaded trace extending along a first direction and a second cascaded trace extending along a second direction.

[0118] The first cascaded trace includes a plurality of first conductive patterns disposed on a first conductive layer and a second conductive pattern disposed on a second conductive layer. The plurality of first conductive patterns are electrically connected to the second conductive pattern, and the orthographic projection of the plurality of first conductive patterns on the substrate at least partially overlaps with the orthographic projection of the second conductive pattern on the substrate. The second cascaded trace includes a third conductive pattern disposed on the first conductive layer.

[0119] The embodiments of the present invention reduce the resistance of the first cascaded trace and prevent abnormal cascading of cascaded signal lines by making the first cascaded trace include a plurality of first conductive patterns disposed on a first conductive layer and a second conductive pattern disposed on a second conductive layer, and electrically connecting the plurality of first conductive patterns with the second conductive pattern.

[0120] Optionally, the plurality of sub-display areas include: a first sub-display area, a second sub-display area, a third sub-display area, and a fourth sub-display area, wherein the first sub-display area and the third sub-display area are arranged opposite to each other, the second sub-display area and the fourth sub-display area are arranged opposite to each other, and the third sub-display area is located on the side of the irregular display panel where the multiple buses are located;

[0121] The plurality of cascaded gate drive sub-circuits include: a first gate drive sub-circuit, a second gate drive sub-circuit, a third gate drive sub-circuit, and a fourth gate drive sub-circuit.

[0122] The first gate driving sub-circuit is located in the first sub-display area, the second gate driving sub-circuit is located in the second sub-display area, the third gate driving sub-circuit is located in the third sub-display area, and the fourth gate driving sub-circuit is located in the fourth sub-display area.

[0123] The embodiments of the present invention can realize the grouping design of the gate driving circuit by setting gate driving sub-circuits in different sub-display areas.

[0124] refer to Figure 1 The irregularly shaped display panel has a D-shaped non-display area A2 in the center, surrounded by a display area A1. Four gate drive sub-circuits are located in the four sub-display areas of display area A1. Since the gate drive circuits are located in the display area, they are called GIA groups (Gate Drive In Active Area).

[0125] Simultaneously combined Figure 2The four GIA groups are cascaded with each other, and every two GIA groups are coupled together via cascaded signal lines.

[0126] The first direction described in this invention is the transverse direction, and the second direction is the longitudinal direction.

[0127] It should be noted that the irregularly shaped display panel provided in this embodiment of the invention is not only applicable to D-shaped display panels, but also to Y-shaped or I-shaped display panels.

[0128] At least one cascaded signal line has multiple horizontal segments and multiple vertical segments.

[0129] Optionally, the plurality of first conductive patterns are spaced apart.

[0130] The multiple first conductive patterns provided in the embodiments of the present invention are spaced apart to avoid the first conductive patterns from overlapping with other signal lines on the same layer.

[0131] The more first conductive patterns there are, the lower the resistance on the first cascaded trace.

[0132] Optionally, the plurality of first conductive patterns and the second conductive patterns are electrically connected through a plurality of vias. Figure 17 A cross-sectional view of the double-layer trace spacing segmentation position of the first cascaded trace provided in an embodiment of the present invention, as shown below. Figure 17 As shown, in the direction away from the substrate, the irregularly shaped display panel sequentially includes: a first gate insulating layer 61, a first gate metal layer 62, a second gate insulating layer 63, an interlayer dielectric layer 64, and a first source / drain metal layer 65. The first conductive pattern 51 is coupled to the first gate metal layer 65 through a via 71 and combined with... Figure 12 The first conductive pattern 51 avoids the power line 38. For example, the first conductive pattern 51 also needs to avoid the first initialization signal line 35, the second initialization signal line 36, and the data line 37. It should be noted that the number of vias corresponding to one conductive pattern is not limited.

[0133] Figure 12 The diagram shows multiple first conductive patterns 51 on the first source / drain metal layer of the first cascaded trace, formed by... Figure 12 It can be seen that the multiple first conductive patterns 51 are spaced apart to avoid the vertical signal lines on the first source / drain metal layer.

[0134] Optionally, the irregularly shaped display panel includes a first gate metal layer, a second gate metal layer, and a first source / drain metal layer stacked sequentially along a direction away from the substrate, wherein the first conductive layer is made of the first source / drain metal layer, and the second conductive layer is made of the first gate metal layer.

[0135] In embodiments of the present invention, the first conductive layer is fabricated using a first source / drain metal layer, and the second conductive layer is fabricated using a first gate metal layer. Since the sheet resistance of the source / drain metal layer is less than that of the gate metal layer, the resistance on the second cascaded trace can be reduced.

[0136] As an example, the first source / drain metal layer has a sheet resistance of Made of Ti / AL / Ti material, the first gate metal layer has a sheet resistance of It is made of Mo material.

[0137] refer to Figure 2 In this process, the vertical segment is made using the first source-drain metal layer, whereas in the prior art, the vertical segment is made using the first gate metal layer. Since the sheet resistance of the first source-drain metal layer is less than that of the first gate metal layer, the resistance on the vertical segment is reduced, which can prevent severe attenuation of the GIA signal.

[0138] The horizontal segmentation includes both a first source / drain metal layer and a first gate metal layer. This double-layer routing method can reduce the overall resistance of the routing.

[0139] Also refer to Figure 11 , Figure 11 To and Figure 10 A schematic diagram of the layout of the first gate metal layer at the corresponding position, wherein the first gate metal layer includes a first conductive pattern 51 projected onto the first gate metal layer as an orthographic projection 52.

[0140] Optionally, at least one gate drive sub-circuit includes: a plurality of cascaded first GOA units, a plurality of cascaded second GOA units, a plurality of cascaded third GOA units, and a plurality of cascaded fourth GOA units.

[0141] The first GOA unit includes at least: a first cascaded output terminal, a reset signal terminal, and a first signal input terminal;

[0142] The second GOA unit includes a second signal input terminal and a second cascaded output terminal;

[0143] The third GOA unit includes a third signal input terminal and a third cascaded output terminal; and

[0144] The fourth GOA unit includes a fourth signal input terminal and a fourth cascaded output terminal;

[0145] The multiple cascaded signal lines include: a first cascaded output signal line, a reset signal line, a second signal input line, a third signal input line, and a fourth signal input line;

[0146] The first cascaded output signal line has one end coupled to the first cascaded output terminal of the last first GOA unit of one of the two adjacent gate driving sub-circuits, and the other end coupled to the first signal input terminal of the first first GOA unit of the other gate driving sub-circuit in the other two adjacent gate driving sub-circuits.

[0147] The reset signal line is coupled at one end to the reset signal terminal of the last first GOA unit of one of the two adjacent gate driving sub-circuits, and at the other end to the first signal input terminal of the first first GOA unit of the other gate driving sub-circuit.

[0148] The second signal input line has one end coupled to the second cascaded output terminal of the last second GOA unit of one of the two adjacent gate driving sub-circuits, and the other end coupled to the second signal input terminal of the first second GOA unit of the other gate driving sub-circuit.

[0149] The third signal input line is coupled at one end to the third cascade output terminal of the last third GOA unit of one of the two adjacent gate driving sub-circuits, and at the other end to the third signal input terminal of the first third GOA unit of the other gate driving sub-circuit.

[0150] The fourth signal input line is coupled at one end to the fourth cascade output terminal of the last fourth GOA unit of one of the two adjacent gate driver sub-circuits, and at the other end to the fourth signal input terminal of the first fourth GOA unit of the other gate driver sub-circuit.

[0151] The irregularly shaped display panel provided in this embodiment of the invention includes multiple cascaded signal lines, which include: a first cascaded output signal line, a reset signal line, a second signal input line, a third signal input line, and a fourth signal input line; there are a total of 5 cascaded signal lines, which can realize the coupling between two adjacent gate driving sub-circuits.

[0152] refer to Figures 3 to 8 as well as Figure 14 , Figure 15 , Figure 4 As shown Figure 3 An enlarged schematic diagram of the cascaded signal line connection area A3, wherein the gate drive sub-circuit on the left side of the display panel includes a first GOA unit U1, a third GOA unit U3, a second GOA unit U2, and a fourth GOA unit U4 along a first direction from away from the non-display area to close to the non-display area.

[0153] The first GOA unit U1, the third GOA unit U3, the second GOA unit U2, and the fourth GOA unit U4 are driven independently.

[0154] At least one gate drive sub-circuit further includes a plurality of first GOA units U1 arranged along the second direction, a plurality of third GOA units U3 arranged along the second direction, a plurality of second GOA units U2 arranged along the second direction, and a plurality of fourth GOA units U4 arranged along the second direction.

[0155] At least one gate driving sub-circuit includes multiple first GOA units U1 cascaded to each other, at least one gate driving sub-circuit includes multiple third GOA units U3 cascaded to each other, and at least one gate driving sub-circuit includes multiple fourth GOA units U4 cascaded to each other.

[0156] refer to Figure 14 , Figure 14 This is a schematic diagram of the architecture of the first GOA unit U1. Figure 15 This is a schematic diagram of the architecture of the second GOA unit U2, the third GOA unit U3, and the fourth GOA unit U4.

[0157] The architecture of the first GOA unit U1 adopts a cascaded shift register, with the first row input signal being STU, the first row output CR being the input of the next row, and the second row output serving as the reset STD of the previous row.

[0158] The second GOA unit U2, the third GOA unit U3, and the fourth GOA unit U4 have the same architecture. Using a PWM architecture, it is only necessary to cascade the output signal of the previous row to the input of the next row.

[0159] There are a total of 5 cascaded signal lines between two adjacent gate driver sub-circuits, namely the first cascaded output signal line, the reset signal line, the second signal input line, the third signal input line, and the fourth signal input line.

[0160] refer to Figure 5 , Figure 5 for Figure 4 The schematic diagram of the cascaded signal line connection at point ① shows that the first cascaded output signal line 21 and the reset signal line 22 are used to connect the last first GOA unit of one gate driver sub-circuit in two adjacent gate driver sub-circuits and the first first GOA unit of the other gate driver sub-circuit in two adjacent gate driver sub-circuits.

[0161] refer to Figure 7 , Figure 7 for Figure 4The cascaded signal line connection diagram at point ③ shows that the second signal input line 23 is used to connect the last second GOA unit of one gate driving sub-circuit in two adjacent gate driving sub-circuits to the first second GOA unit of the other gate driving sub-circuit in two adjacent gate driving sub-circuits.

[0162] refer to Figure 6 , Figure 6 for Figure 4 The third signal input line 24 in the cascaded signal line connection diagram at point ② is used to connect the last third GOA unit of one gate driving sub-circuit in two adjacent gate driving sub-circuits and the first third GOA unit of the other gate driving sub-circuit in two adjacent gate driving sub-circuits.

[0163] refer to Figure 8 , Figure 8 for Figure 4 The cascaded signal line connection diagram at point ④ shows that the fourth signal input line 25 is used to connect the last fourth GOA unit of one gate driving sub-circuit and the first fourth GOA unit of the other gate driving sub-circuit in the two adjacent gate driving sub-circuits.

[0164] Optionally, there is a first gap between two adjacent columns of sub-pixel driving circuits;

[0165] There is a second gap between two adjacent rows of sub-pixel driving circuits;

[0166] The second signal input line includes two parallel second sub-signal input lines, wherein at least a portion of one second sub-signal input line extends along the second direction, and at least a portion of the other second sub-signal input line extends along the second direction, and the two parallel second sub-signal input lines are located within the same second gap;

[0167] The third signal input line includes two parallel third sub-signal input lines, wherein at least a portion of one third sub-signal input line extends along the second direction, and at least a portion of the other third sub-signal input line extends along the second direction, and the two parallel third sub-signal input lines are located in different first gaps;

[0168] The fourth signal input line includes two parallel fourth sub-signal input lines, wherein at least a portion of one fourth sub-signal input line extends along the second direction, and at least a portion of the other third sub-signal input line extends along the second direction, and the two parallel third sub-signal input lines are located in different first gaps.

[0169] The embodiments of the present invention, by setting two parallel sub-signal input lines, can prevent the attenuation of a single sub-signal input line during the transmission of cascaded signals.

[0170] refer to Figure 6 The third signal input line 24 coupled to the third GOA unit U3 includes two parallel third sub-signal input lines 241.

[0171] refer to Figure 7 The second signal input line 23 coupled to the second GOA unit U2 includes two parallel second sub-signal input lines 231.

[0172] refer to Figure 8 The fourth signal input line 25 coupled to the fourth GOA unit U4 includes two parallel fourth sub-signal input lines 251.

[0173] Figure 9 for Figure 4 A schematic diagram of the cascaded signal line connection at point ⑤.

[0174] refer to Figure 16 The irregularly shaped display panel further includes: a multi-row sub-pixel driving circuit located on the substrate, the sub-pixel driving circuit comprising at least:

[0175] The transistors are: data writing transistor T1, first reset transistor T2, driving transistor T3, second reset transistor T4, and light-emitting control transistor T5.

[0176] The sub-pixel driving circuit also includes:

[0177] First scan line 31, second scan line 32, third scan line 33, light emission control signal line 34, first initialization signal line 35, second initialization signal line 36, data line 37, and power line 38;

[0178] The first terminal of the data writing transistor T1 is coupled to the corresponding data line 37, the second terminal of the data writing transistor T1 is coupled to the second terminal of the first reset transistor T2, and the gate of the data writing transistor T1 is coupled to the corresponding first scan line 31.

[0179] The first terminal of the first reset transistor T2 is coupled to the corresponding second initialization signal line 36, the second terminal of the first reset transistor T2 is coupled to the second terminal of the data writing transistor T1, and the gate of the first reset transistor T2 is coupled to the corresponding second scan line 32.

[0180] The first terminal of the driving transistor T3 is coupled to the second terminal of the second reset transistor T4, the second terminal of the driving transistor T3 is coupled to the second terminal of the light-emitting control transistor T5, and the gate of the driving transistor T3 is coupled to the second terminal of the data writing transistor T1.

[0181] The first terminal of the second reset transistor T4 is coupled to the corresponding first initialization signal line 35, the second terminal of the second reset transistor T4 is coupled to the anode of the light-emitting element, and the gate of the second reset transistor T4 is coupled to the corresponding third scan line 33.

[0182] The first terminal of the light-emitting control transistor T5 is coupled to the corresponding power supply line 38, the second terminal of the light-emitting control transistor T5 is coupled to the second terminal of the driving transistor T3, and the gate of the light-emitting control transistor T5 is coupled to the light-emitting control signal line 34.

[0183] The first plate of the storage capacitor Cst is reused as the gate of the driving transistor T3, and the second plate of the storage capacitor Cst is coupled to the second electrode of the second reset transistor T4.

[0184] The sub-pixel driving circuit of the irregularly shaped display panel provided in the embodiments of the present invention is a 5T1C pixel driving circuit, which can ensure the uniformity of brightness of organic light-emitting diodes.

[0185] Optionally, the first GOA unit is coupled to the first scan line;

[0186] The second GOA unit is coupled to the second scan line;

[0187] The third GOA unit is coupled to the third scan line;

[0188] The fourth GOA unit is coupled to the light emission control signal line.

[0189] In this embodiment of the invention, the first GOA unit is coupled to the first scan line 31, and the first scan line 31 is coupled to the gate of the data writing transistor T1, that is, the first GOA unit can provide a gate drive signal for the data writing transistor T1; the second GOA unit is coupled to the second scan line 32, and the second scan line 32 is coupled to the gate of the first reset transistor T2, that is, the second GOA unit can provide a gate drive signal for the first reset transistor T2; the third GOA unit is coupled to the third scan line 33, and the third scan line 33 is coupled to the gate of the second reset transistor T4, that is, the third GOA unit can provide a gate drive signal for the second reset transistor T4; the fourth GOA unit is coupled to the light emission control signal line 34, and the light emission control signal line 34 is coupled to the gate of the light emission control transistor T5, that is, the fourth GOA unit can provide a gate drive signal for the light emission control transistor T5.

[0190] Optionally, the orthographic projections of the first GOA unit, the second GOA unit, the third GOA unit, and the fourth GOA unit on the substrate are located between the orthographic projections of two adjacent rows of sub-pixel driving circuits on the substrate.

[0191] The irregularly shaped display panel provided in this embodiment of the invention places the gate driving circuit in the display area, thereby reducing the transmission distance between the gate driving circuit and the sub-pixel driving circuit and increasing the refresh rate of the display panel.

[0192] refer to Figure 5 The orthographic projection of the first GOA unit on the substrate is located between the orthographic projections of two adjacent rows of sub-pixel driving circuits on the substrate, and is located in the gap between the two rows of sub-pixel driving circuits.

[0193] Similarly, the second, third, and fourth GOA units are also located in the gap between the two rows of sub-pixel driving circuits.

[0194] Optionally, the orthographic projection of the first conductive pattern on the substrate does not overlap with the orthographic projections of the data line, the power line, the first initialization signal line, and the second initialization signal line on the substrate.

[0195] Since the first conductive pattern is made using the first source-drain metal layer, and the data line, power line, first initialization signal line, and second initialization signal line are also made using the first source-drain metal layer, the orthographic projection of the first conductive pattern on the substrate avoids the orthographic projections of the data line, power line, first initialization signal line, and second initialization signal line on the substrate. This avoids crosstalk between the cascaded signal lines and the data line, power line, first initialization signal line, and second initialization signal line.

[0196] Optionally, the first GOA unit, the second GOA unit, the third GOA unit, and the fourth GOA unit include:

[0197] The panel includes a total reset terminal, a first clock signal terminal, a second clock signal terminal, and a high-level terminal; the irregularly shaped display panel also includes:

[0198] Multiple buses and multiple common signal line groups located on the substrate;

[0199] The multiple buses include at least: multiple reset buses, multiple first clock buses, multiple second clock buses, and multiple high-level buses;

[0200] At least one of the common signal line groups includes:

[0201] Multiple total reset signal lines are located on the substrate, at least one of the total reset signal lines is coupled to the corresponding reset bus at one end, and the other end is coupled to the total reset terminal of the first GOA unit, the second GOA unit, the third GOA unit or the fourth GOA unit;

[0202] Multiple first clock signal lines located on the substrate, at least one of the first clock signal lines is coupled at one end to the corresponding first clock bus, and the other end is coupled to the first clock signal terminal of the first GOA unit, the second GOA unit, the third GOA unit or the fourth GOA unit;

[0203] Multiple second clock signal lines located on the substrate, at least one of the second clock signal lines is coupled at one end to the corresponding second clock bus, and the other end is coupled to the second clock signal terminal of the first GOA unit, the second GOA unit, the third GOA unit or the fourth GOA unit;

[0204] Multiple high-level signal lines are located on the substrate, at least one of which is coupled at one end to a corresponding high-level bus, and the other end is coupled to the high-level terminal of the first GOA unit, the second GOA unit, the third GOA unit, or the fourth GOA unit.

[0205] In this embodiment of the invention, multiple common signal line groups are connected to a bus, enabling the bus to provide common signals to multiple gate driver sub-circuits through the multiple common signal line groups.

[0206] Optionally, the length of the cascaded signal line between the two gate driver sub-circuits is greater than the length of the cascaded signal line between the two first GOA units included in the gate driver sub-circuit.

[0207] The length of the cascaded signal line between the two gate driver sub-circuits is greater than the length of the cascaded signal line between the two second GOA units included in the gate driver sub-circuit.

[0208] The length of the cascaded signal line between the two gate driver sub-circuits is greater than the length of the cascaded signal line between the two third GOA units included in the gate driver sub-circuit.

[0209] The length of the cascaded signal line between the two gate driver sub-circuits is greater than the length of the cascaded signal line between the two fourth GOA units included in the gate driver sub-circuit.

[0210] Since each gate driver sub-circuit is located in a different sub-display area, the length of the cascaded signal line between two gate driver sub-circuits must be longer than the length of the cascaded signal line between two first GOA units, two second GOA units, two third GOA units, or two fourth GOA units included in the same gate driver sub-circuit.

[0211] However, at the same time, the increased length of the cascaded signal line between the two gate driver sub-circuits leads to an increase in resistance on the cascaded signal line between the two gate driver sub-circuits. Therefore, the resistance on the cascaded signal line between the two gate driver sub-circuits was not reduced. A double-layer spacing design was adopted for the first cascaded trace; and a first source-drain metal layer with a smaller sheet resistance was adopted for the second cascaded trace.

[0212] Optionally, the first cascaded wiring further includes:

[0213] A fourth conductive pattern is electrically connected to the plurality of first conductive patterns, and the orthographic projections of the plurality of first conductive patterns on the substrate at least partially overlap with the orthographic projections of the fourth conductive pattern on the substrate.

[0214] The fourth conductive pattern is electrically connected to the second conductive pattern, and the orthographic projection of the second conductive pattern on the substrate at least partially overlaps with the orthographic projection of the fourth conductive pattern on the substrate. Embodiments of the present invention enable a three-layer routing design for the first cascaded trace by further including a fourth conductive pattern disposed on the second gate metal layer.

[0215] Furthermore, the fourth conductive pattern is disposed in the second gate metal layer.

[0216] Furthermore, the irregularly shaped display panel also includes a second source / drain metal layer located on the side of the first source / drain metal layer away from the substrate.

[0217] The dual-layer traces in embodiments of the present invention can be fabricated using two of the following metal layers: a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer.

[0218] The three-layer traces in embodiments of the present invention can be fabricated using two of the following metal layers: the first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the second source / drain metal layer.

[0219] Optionally, the second cascaded trace further includes a third gate metal layer located between the second gate metal layer and the first source / drain metal layer.

[0220] The dual-layer traces in embodiments of the present invention can be fabricated using two of the following metal layers: a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer.

[0221] The three-layer traces in embodiments of the present invention can be fabricated using two of the following metal layers: the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source / drain metal layer, and the second source / drain metal layer.

[0222] It should be noted that, depending on the number of metal film layers included in the irregularly shaped display panel, the first cascaded traces can be designed as three or more layers of traces.

[0223] Optionally, the second cascaded wiring also includes:

[0224] A fifth conductive pattern is electrically connected to the third conductive pattern, and the orthographic projection of the fifth conductive pattern on the substrate at least partially overlaps with the orthographic projection of the third conductive pattern on the substrate.

[0225] Furthermore, the fifth conductive pattern is disposed in the first gate metal layer.

[0226] The first-level cascaded trace can be designed as a double-layer, triple-layer, or multi-layer trace depending on the number of metal film layers. Similarly, the second-level cascaded trace can be designed as a single-layer trace, as well as a double-layer, triple-layer, or multi-layer trace.

[0227] It should be noted that double-layer and triple-layer traces can be made not only by using two or three metal layers of different layers, but also by using two stacked conductive layers on the same metal layer.

[0228] For example, in the embodiment of the present invention, when the double-layered trace of the first cascaded trace uses two different metal layers, such as the first gate metal layer and the first source drain metal layer, the electrical connection between the first gate metal layer and the first source drain metal layer can be achieved without vias. Instead, the first gate metal layer and the first source drain metal layer are directly electrically connected, eliminating the need for the insulating layer between the first gate metal layer and the first source drain metal layer.

[0229] For example, when the double-layer trace of the first cascaded trace in the embodiment of the present invention is made using two stacked conductive layers on the same metal layer, for example, two signal lines extending along a first direction can be made through the first gate metal layer, and the two signal lines are stacked sequentially in the direction away from the substrate.

[0230] Optionally, the plurality of cascaded gate drive sub-circuits include: a first gate drive sub-circuit, a second gate drive sub-circuit, a third gate drive sub-circuit, and a fourth gate drive sub-circuit.

[0231] The first common signal line group is coupled to the first gate driver sub-circuit and the second gate driver sub-circuit;

[0232] The second common signal line group is coupled to the third gate driver sub-circuit;

[0233] The third common signal line group is coupled to the fourth gate driver sub-circuit.

[0234] The embodiments of the present invention reduce the display panel area occupied by the common signal line group by coupling the first common signal line group with the first gate driving sub-circuit and the second gate driving sub-circuit, that is, one common signal line group provides common signals to two gate driving sub-circuits at the same time.

[0235] refer to Figure 3 , Figure 4 and Figure 13 The irregularly shaped display panel includes three common signal line groups located on the substrate, namely the first common signal line group L1, the second common signal line group L2, and the third common signal line group L3.

[0236] The first common signal line group L1 provides common signals for the gate drive sub-circuits of both the upper and left borders. The reference... Figure 4 The common signal line coupled to the gate driver sub-circuit on the left side is transferred to the common signal line coupled to the gate driver sub-circuit on the upper side, and the first common signal line group L1 is then coupled to the bus. Figure 13 This is a schematic diagram showing the connection between the first common signal line group and the bus. Figure 3 The A4 area is the connection area between the first common signal line group and the bus.

[0237] The second common signal line group L2 provides common signals for the gate driver sub-circuit of the lower frame. Since the gate driver sub-circuit of the lower frame is close to the bus, the common signal line coupled to the gate driver sub-circuit of the lower frame is directly coupled to the bus.

[0238] The third common signal line group L3 provides common signals for the gate driver sub-circuit of the right frame.

[0239] Among them, at least one of the first GOA unit, the second GOA unit, the third GOA unit and the fourth GOA unit includes: a total reset terminal TRS, a first clock signal terminal CK, a second clock signal terminal CKB and a high-level terminal VGH, and the signal lines connected to the total reset terminal TRS, the first clock signal terminal CK, the second clock signal terminal CKB and the high-level terminal VGH are common signal lines.

[0240] At least one of the first GOA unit, the second GOA unit, the third GOA unit, and the fourth GOA unit is connected to multiple common signal lines.

[0241] The common signal line coupled to the total reset terminal TRS is the total reset signal line. One end of the total reset signal line is coupled to the reset bus among multiple buses, and the other end of the total reset signal line is coupled to the total reset terminal of the first GOA unit, the second GOA unit, the third GOA unit, or the fourth GOA unit.

[0242] The common signal line coupled to the first clock signal terminal CK is the first clock signal line. One end of the first clock signal line is coupled to the first clock bus among multiple buses, and the other end of the first clock signal line is coupled to the first clock signal terminal of the first GOA unit, the second GOA unit, the third GOA unit, or the fourth GOA unit.

[0243] The common signal line coupled to the second clock signal terminal CKB is the second clock signal line. One end of the second clock signal line is coupled to the second clock bus among multiple buses, and the other end of the second clock signal line is coupled to the second clock signal terminal of the first GOA unit, the second GOA unit, the third GOA unit, or the fourth GOA unit.

[0244] The common signal line coupled to the high-level terminal VGH is a high-level signal line. One end of the high-level signal line is coupled to the high-level bus among multiple buses, and the other end of the high-level signal line is coupled to the high-level terminal of the first GOA unit, the second GOA unit, the third GOA unit, or the fourth GOA unit.

[0245] Optionally, the orthographic projection of the first conductive pattern on the substrate does not overlap with the orthographic projections of the first clock signal line and the second clock signal line on the substrate.

[0246] By ensuring that the orthographic projection of the first conductive pattern on the substrate does not overlap with the orthographic projections of the first clock signal line and the second clock signal line on the substrate, crosstalk between the cascaded signal lines and the first and second clock signal lines can be avoided.

[0247] refer to Figure 12 The first conductive pattern 51 is made of the same layer and material as the first clock signal line 41 and the second clock signal line 42.

[0248] Since the gate driver sub-circuit is located in the display area, the first clock signal line 41 and the second clock signal line 42 are also located in the display area. In the prior art, since the gate driver circuit is located in the bezel area, the clock signal lines are usually located in the bezel area.

[0249] Optionally, the at least one bus includes a third conductive layer and a fourth conductive layer, wherein the third conductive layer is fabricated using a first source / drain metal layer and the fourth conductive layer is fabricated using a first gate metal layer.

[0250] Embodiments of the present invention can reduce the resistance of the bus by including at least one bus in a third conductive layer and a fourth conductive layer.

[0251] refer to Figure 11 At least one of the buses was changed from the original single-layer GT to a spaced SD / GT double-layer trace.

[0252] Optionally, the irregularly shaped display panel includes a D-shaped display panel.

[0253] The irregularly shaped display panel provided in this embodiment of the invention includes a D-shaped display panel, which can achieve diversified display according to different application scenarios.

[0254] In this embodiment of the invention, the irregularly shaped display panel can be a letter screen, including a D-shaped display panel, or other shapes including a D-shape, such as a B-shape, a P-shape, or a q-shape. The left and right sides of the D-shape are asymmetrical.

[0255] A second aspect of the present invention also provides a display device including the aforementioned irregularly shaped display panel.

[0256] The display device includes, but is not limited to, components such as: a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Those skilled in the art will understand that the above-described structure of the display device does not constitute a limitation on the display device; the display device may include more or fewer of the aforementioned components, or combine certain components, or arrange different components. In embodiments of the present invention, the display device includes, but is not limited to, a monitor, a mobile phone, a tablet computer, a television set, a wearable electronic device, a navigation display device, etc.

[0257] The display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes a flexible circuit board, a printed circuit board, and a backplate.

[0258] In the various method embodiments of the present invention, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps without creative effort are also within the scope of protection of the present invention.

[0259] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, since the embodiments are basically similar to the product embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the product embodiments.

[0260] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0261] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0262] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0263] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An irregularly shaped display panel, comprising a display area, wherein the display area includes a plurality of sub-display areas; The irregularly shaped display panel includes a substrate and a gate driving circuit located on the substrate; The gate driving circuit includes multiple cascaded gate driving sub-circuits; each of the multiple cascaded gate driving sub-circuits corresponds one-to-one with the multiple sub-display areas, and each gate driving sub-circuit is located within its corresponding sub-display area. Multiple cascaded signal lines are used to couple two adjacent gate driver sub-circuits, and at least one cascaded signal line includes a first cascaded trace extending along a first direction and a second cascaded trace extending along a second direction. The first cascaded trace includes a plurality of first conductive patterns disposed on a first conductive layer and a second conductive pattern disposed on a second conductive layer. The plurality of first conductive patterns are electrically connected to the second conductive pattern, and the orthographic projection of the plurality of first conductive patterns on the substrate at least partially overlaps with the orthographic projection of the second conductive pattern on the substrate. The second cascaded trace includes a third conductive pattern disposed on the first conductive layer.

2. The irregularly shaped display panel according to claim 1, wherein, The plurality of first conductive patterns and the second conductive patterns are electrically connected through a plurality of vias.

3. The irregularly shaped display panel according to claim 1, wherein, The plurality of first conductive patterns are spaced apart.

4. The irregularly shaped display panel according to claim 3, wherein, The irregularly shaped display panel includes a first gate metal layer, a second gate metal layer and a first source / drain metal layer stacked sequentially along a direction away from the substrate. The first conductive layer is made of the first source / drain metal layer and the second conductive layer is made of the first gate metal layer.

5. The irregularly shaped display panel according to claim 1, wherein, The first cascaded routing also includes: A fourth conductive pattern is electrically connected to the plurality of first conductive patterns, and the orthographic projections of the plurality of first conductive patterns on the substrate at least partially overlap with the orthographic projections of the fourth conductive pattern on the substrate. The fourth conductive pattern is electrically connected to the second conductive pattern, and the orthographic projection of the second conductive pattern on the substrate at least partially overlaps with the orthographic projection of the fourth conductive pattern on the substrate.

6. The irregularly shaped display panel according to claim 1, wherein, The second cascaded routing also includes: A fifth conductive pattern is electrically connected to the third conductive pattern, and the orthographic projection of the fifth conductive pattern on the substrate at least partially overlaps with the orthographic projection of the third conductive pattern on the substrate.

7. The irregularly shaped display panel according to claim 1, wherein, The irregularly shaped display panel further includes: a multi-row sub-pixel driving circuit located on the substrate, the sub-pixel driving circuit further including: Multiple first initialization signal lines, at least a portion of which extend along the second direction; Multiple second initialization signal lines, at least a portion of which extend along the second direction; Multiple data lines, at least a portion of which extend along the second direction; and Multiple power lines, at least a portion of which extend along the second direction; The orthographic projection of the first conductive pattern on the substrate does not overlap with the orthographic projections of the data line, the power line, the first initialization signal line, and the second initialization signal line on the substrate.

8. The irregularly shaped display panel according to claim 7, wherein, The first initialization signal line, the second initialization signal line, the data line, and the power line are made of the same layer and material as the first conductive pattern.

9. The irregularly shaped display panel according to claim 8, wherein, The sub-pixel driving circuit also includes: The transistor includes a data writing transistor, a first reset transistor, a driving transistor, a second reset transistor, and a light-emitting control transistor. The sub-pixel driving circuit also includes: First scan line, second scan line, third scan line, and light emission control signal line; The first terminal of the data writing transistor is coupled to the corresponding data line, the second terminal of the data writing transistor is coupled to the second terminal of the first reset transistor, and the gate of the data writing transistor is coupled to the corresponding first scan line. The first terminal of the first reset transistor is coupled to the corresponding second initialization signal line, the second terminal of the first reset transistor is coupled to the second terminal of the data write transistor, and the gate of the first reset transistor is coupled to the corresponding second scan line. The first terminal of the driving transistor is coupled to the second terminal of the second reset transistor, the second terminal of the driving transistor is coupled to the second terminal of the light-emitting control transistor, and the gate of the driving transistor is coupled to the second terminal of the data writing transistor. The first terminal of the second reset transistor is coupled to the corresponding first initialization signal line, the second terminal of the second reset transistor is coupled to the anode of the light-emitting element, and the gate of the second reset transistor is coupled to the corresponding third scan line. The first terminal of the light-emitting control transistor is coupled to the corresponding power supply line, the second terminal of the light-emitting control transistor is coupled to the second terminal of the driving transistor, and the gate of the light-emitting control transistor is coupled to the light-emitting control signal line. The first plate of the storage capacitor of the irregularly shaped display panel is reused as the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the second electrode of the second reset transistor.

10. The irregularly shaped display panel according to claim 9, wherein, At least one of the gate drive sub-circuits includes: a plurality of cascaded first GOA units, a plurality of cascaded second GOA units, a plurality of cascaded third GOA units, and a plurality of cascaded fourth GOA units. The first GOA unit includes at least: a first cascaded output terminal, a reset signal terminal, and a first signal input terminal; The second GOA unit includes a second signal input terminal and a second cascaded output terminal; The third GOA unit includes a third signal input terminal and a third cascaded output terminal; and The fourth GOA unit includes a fourth signal input terminal and a fourth cascaded output terminal; The multiple cascaded signal lines include: a first cascaded output signal line, a reset signal line, a second signal input line, a third signal input line, and a fourth signal input line; The first cascaded output signal line has one end coupled to the first cascaded output terminal of the last first GOA unit of one of the two adjacent gate driving sub-circuits, and the other end coupled to the first signal input terminal of the first first GOA unit of the other gate driving sub-circuit in the other two adjacent gate driving sub-circuits. The reset signal line is coupled at one end to the reset signal terminal of the last first GOA unit of one of the two adjacent gate driving sub-circuits, and at the other end to the first signal input terminal of the first first GOA unit of the other gate driving sub-circuit. The second signal input line has one end coupled to the second cascaded output terminal of the last second GOA unit of one of the two adjacent gate driving sub-circuits, and the other end coupled to the second signal input terminal of the first second GOA unit of the other gate driving sub-circuit. The third signal input line is coupled at one end to the third cascade output terminal of the last third GOA unit of one of the two adjacent gate driving sub-circuits, and at the other end to the third signal input terminal of the first third GOA unit of the other gate driving sub-circuit. The fourth signal input line is coupled at one end to the fourth cascade output terminal of the last fourth GOA unit of one of the two adjacent gate driver sub-circuits, and at the other end to the fourth signal input terminal of the first fourth GOA unit of the other gate driver sub-circuit.

11. The irregularly shaped display panel according to claim 10, wherein, There is a first gap between two adjacent columns of sub-pixel driving circuits; There is a second gap between two adjacent rows of sub-pixel driving circuits; The second signal input line includes two parallel second sub-signal input lines, wherein at least a portion of one second sub-signal input line extends along the second direction, and at least a portion of the other second sub-signal input line extends along the second direction, and the two parallel second sub-signal input lines are located within the same second gap; The third signal input line includes two parallel third sub-signal input lines, wherein at least a portion of one third sub-signal input line extends along the second direction, and at least a portion of the other third sub-signal input line extends along the second direction, and the two parallel third sub-signal input lines are located in different first gaps; The fourth signal input line includes two parallel fourth sub-signal input lines, wherein at least a portion of one fourth sub-signal input line extends along the second direction, and at least a portion of the other third sub-signal input line extends along the second direction, and the two parallel third sub-signal input lines are located in different first gaps.

12. The irregularly shaped display panel according to claim 10, wherein, The first GOA unit is coupled to the first scan line; The second GOA unit is coupled to the second scan line; The third GOA unit is coupled to the third scan line; The fourth GOA unit is coupled to the light emission control signal line.

13. The irregularly shaped display panel according to claim 10, wherein, The orthographic projections of the first GOA unit, the second GOA unit, the third GOA unit, and the fourth GOA unit on the substrate are located between the orthographic projections of two adjacent rows of sub-pixel driving circuits on the substrate.

14. The irregularly shaped display panel according to claim 10, wherein, The first GOA unit, the second GOA unit, the third GOA unit, and the fourth GOA unit include: The panel includes a total reset terminal, a first clock signal terminal, a second clock signal terminal, and a high-level terminal; the irregularly shaped display panel also includes: Multiple buses and multiple common signal line groups located on the substrate; The multiple buses include at least: multiple reset buses, multiple first clock buses, multiple second clock buses, and multiple high-level buses; At least one of the common signal line groups includes: Multiple total reset signal lines are located on the substrate, at least one of the total reset signal lines is coupled to the corresponding reset bus at one end, and the other end is coupled to the total reset terminal of the first GOA unit, the second GOA unit, the third GOA unit or the fourth GOA unit; Multiple first clock signal lines located on the substrate, at least one of the first clock signal lines is coupled at one end to the corresponding first clock bus, and the other end is coupled to the first clock signal terminal of the first GOA unit, the second GOA unit, the third GOA unit or the fourth GOA unit; Multiple second clock signal lines located on the substrate, at least one of the second clock signal lines is coupled at one end to the corresponding second clock bus, and the other end is coupled to the second clock signal terminal of the first GOA unit, the second GOA unit, the third GOA unit or the fourth GOA unit; Multiple high-level signal lines are located on the substrate, at least one of which is coupled at one end to a corresponding high-level bus, and the other end is coupled to the high-level terminal of the first GOA unit, the second GOA unit, the third GOA unit, or the fourth GOA unit.

15. The irregularly shaped display panel according to claim 14, wherein, The length of the cascaded signal line between the two gate driver sub-circuits is greater than the length of the cascaded signal line between the two first GOA units included in the gate driver sub-circuit. The length of the cascaded signal line between the two gate driver sub-circuits is greater than the length of the cascaded signal line between the two second GOA units included in the gate driver sub-circuit. The length of the cascaded signal line between the two gate driver sub-circuits is greater than the length of the cascaded signal line between the two third GOA units included in the gate driver sub-circuit. The length of the cascaded signal line between the two gate driver sub-circuits is greater than the length of the cascaded signal line between the two fourth GOA units included in the gate driver sub-circuit.

16. The irregularly shaped display panel according to claim 14, wherein, The orthographic projection of the first conductive pattern on the substrate does not overlap with the orthographic projections of the first clock signal line and the second clock signal line on the substrate.

17. The irregularly shaped display panel according to claim 14, wherein, The first clock signal line and the second clock signal line are fabricated using a first source-drain metal layer.

18. The irregularly shaped display panel according to claim 14, wherein, At least one bus includes a third conductive layer and a fourth conductive layer, wherein the third conductive layer is fabricated using a first source / drain metal layer and the fourth conductive layer is fabricated using a first gate metal layer.

19. The irregularly shaped display panel according to claim 14, wherein, The plurality of cascaded gate drive sub-circuits include: a first gate drive sub-circuit, a second gate drive sub-circuit, a third gate drive sub-circuit, and a fourth gate drive sub-circuit. The first common signal line group of the irregularly shaped display panel is coupled to the first gate driving sub-circuit and the second gate driving sub-circuit; The second common signal line group of the irregularly shaped display panel is coupled to the third gate driving sub-circuit; The third common signal line group of the irregularly shaped display panel is coupled to the fourth gate driver sub-circuit.

20. A display device comprising an irregularly shaped display panel as described in any one of claims 1-19.

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