Light emitting element

Abstract

A light emitting element has a semiconductor laminate having a first light emitting portion, a second light emitting portion, and a tunnel junction layer, the first light emitting portion is composed of a nitride semiconductor including a first n-side semiconductor layer, a first p-side semiconductor layer, and a first active layer, the second light emitting portion is located on the first light emitting portion and is composed of a nitride semiconductor including a second n-side semiconductor layer, a second p-side semiconductor layer, and a second active layer, the tunnel junction layer is provided between the first p-side semiconductor layer and the second n-side semiconductor layer, the first n-side semiconductor layer includes a first layer stack portion of a first n-type impurity concentration, the first layer stack portion has a multilayer structure in which a first layer and a second layer are alternately stacked, the second n-side semiconductor layer includes a second layer stack portion of a second n-type impurity concentration, the second layer stack portion has a multilayer structure in which a third layer and a fourth layer having a lattice constant different from that of the third layer are alternately stacked, and the second n-type impurity concentration is higher than the first n-type impurity concentration.

Description

Technical Field

[0001] Embodiments of the present invention relate to light-emitting elements. Background Technology

[0002] For example, Patent Document 1 discloses a light-emitting element comprising a nitride semiconductor layer having a tunnel junction layer.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2017-157667 Summary of the Invention

[0006] The technical problem that the invention aims to solve

[0007] In such light-emitting elements, it is desirable to reduce the forward voltage. The object of embodiments of the present invention is to provide a light-emitting element capable of reducing the forward voltage.

[0008] Technical solutions for solving technical problems

[0009] A light-emitting element according to one embodiment of the present invention includes: a semiconductor stack having a first light-emitting portion, a second light-emitting portion, and a tunnel junction layer. The first light-emitting portion is composed of a nitride semiconductor including a first n-side semiconductor layer, a first p-side semiconductor layer, and a first active layer disposed between the first n-side semiconductor layer and the first p-side semiconductor layer. The second light-emitting portion is located on the first light-emitting portion and is composed of a nitride semiconductor including a second n-side semiconductor layer, a second p-side semiconductor layer, and a second active layer disposed between the second n-side semiconductor layer and the second p-side semiconductor layer. The tunnel junction layer is disposed on the first p-side semiconductor layer. Between the body layer and the second n-side semiconductor layer; an n-side electrode electrically connected to the first n-side semiconductor layer; a p-side electrode electrically connected to the second p-side semiconductor layer; the first n-side semiconductor layer includes a first layer stack with a first n-type impurity concentration, the first layer stack having a multilayer structure formed by alternating layers of a first layer and a second layer with a lattice constant different from the first layer; the second n-side semiconductor layer includes a second layer stack with a second n-type impurity concentration, the second layer stack having a multilayer structure formed by alternating layers of a third layer and a fourth layer with a lattice constant different from the third layer; the second n-type impurity concentration is higher than the first n-type impurity concentration.

[0010] Beneficial effects

[0011] According to one embodiment of the present invention, a light-emitting element is provided that can reduce the forward voltage. Attached Figure Description

[0012] Figure 1 This is a schematic cross-sectional view showing the structure of a light-emitting element according to one embodiment of the present invention.

[0013] Figure 2 This is a flowchart illustrating a method for manufacturing a light-emitting element according to one embodiment of the present invention.

[0014] Figure 3A This is a schematic diagram illustrating a method for manufacturing a light-emitting element according to one embodiment of the present invention.

[0015] Figure 3B This is a schematic diagram illustrating a method for manufacturing a light-emitting element according to one embodiment of the present invention.

[0016] Figure 3C This is a schematic diagram illustrating a method for manufacturing a light-emitting element according to one embodiment of the present invention. Detailed Implementation

[0017] The following describes embodiments of the light-emitting element of the present invention. It should be noted that the accompanying drawings referenced in the following description are schematic representations of the present invention; therefore, there may be exaggerations of the dimensions or spacing, positional relationships, etc., of the components, or omissions of portions of the components. Furthermore, inconsistencies in the dimensions or spacing of the components may exist between the top view and the sectional view. In the following description, the same names and reference numerals generally denote the same or homogeneous components, and detailed descriptions are appropriately omitted.

[0018] Figure 1 This is a schematic cross-sectional view of a light-emitting element 1 according to one embodiment of the present invention. The light-emitting element 1 of this embodiment has a semiconductor stack 100, which includes: a first light-emitting portion 11, which is composed of a nitride semiconductor including a first n-side semiconductor layer 20, a first p-side semiconductor layer 40, and a first active layer 30 disposed between the first n-side semiconductor layer 20 and the first p-side semiconductor layer 40; a second light-emitting portion 12, which is located on the first light-emitting portion 11 and is composed of a nitride semiconductor including a second n-side semiconductor layer 60, a second p-side semiconductor layer 80, and a second active layer 70 disposed between the second n-side semiconductor layer 60 and the second p-side semiconductor layer 80; and a tunnel junction layer 50, which is disposed between the first p-side semiconductor layer 40 and the second n-side semiconductor layer 60. The light-emitting element 1 has an n-side electrode 91 electrically connected to the first n-side semiconductor layer 20 and a p-side electrode 92 electrically connected to the second p-side semiconductor layer 80.

[0019] The substrate 10 can be made of materials such as sapphire, silicon, SiC, or GaN. A buffer layer may also be provided between the substrate 10 and the first light-emitting part 11. As a buffer layer, for example, a layer made of AlGaN or AlN can be used.

[0020] Semiconductor stack 100 is a stack of multiple semiconductor layers composed of nitride semiconductors. The nitride semiconductors can be contained within In... x Al y Ga 1－x－y A semiconductor comprising all components in a chemical formula N (0≤x≤1, 0≤y≤1, x+y≤1) in which the composition ratios of x and y vary within their respective ranges. In the semiconductor stack 100, a first light-emitting portion 11, a tunnel junction layer 50, and a second light-emitting portion 12 are sequentially arranged from the substrate 10 side.

[0021] The first light-emitting portion 11 includes a first n-side semiconductor layer 20, a first p-side semiconductor layer 40, and a first active layer 30 disposed between the first n-side semiconductor layer 20 and the first p-side semiconductor layer 40. The first light-emitting portion 11 is made of a nitride semiconductor.

[0022] The first n-side semiconductor layer 20 includes an n-contact layer 21, a first layer stack 22, and a substrate layer 23. The first n-side semiconductor layer 20 includes one or more n-type semiconductor layers. Examples of n-type semiconductor layers include those containing n-type impurities such as silicon (Si) and germanium (Ge). For example, the n-type semiconductor layer is GaN, and may also contain indium (In) or aluminum (Al). For example, the n-type impurity concentration of an n-type semiconductor layer containing Si as an n-type impurity is 1 × 10⁻⁶. 18 / cm 3 Above 2×10 19 / cm 3 The first n-side semiconductor layer 20 may also include an undoped layer. The undoped layer is a layer that is not intentionally doped with n-type or p-type impurities. The concentration of the n-type and p-type impurities in the undoped layer is, for example, a concentration that does not exceed the detection limit in analytical results obtained by methods such as secondary ion mass spectrometry (SIMS). When the undoped layer is adjacent to a layer intentionally doped with n-type and / or p-type impurities, due to diffusion from that adjacent layer, the undoped layer may contain n-type and / or p-type impurities.

[0023] The n-contact layer 21 is disposed between the substrate layer 23 and the first layer stack 22. The n-contact layer 21 is a semiconductor layer containing n-type impurities. The n-type impurity concentration of the n-contact layer 21 can be set to 1×10⁻⁶. 18 / cm 3 Above 1×10 19 / cm 3 The thickness of the n-contact layer 21 can be set to 0.5 μm or more and 3 μm or less. The n-contact layer 21 has an upper surface without any other semiconductor layers. The n-side electrode 91, which will be described later, is provided on the surface of the n-contact layer 21 without any other semiconductor layers.

[0024] The first layer stack 22 is disposed between the n-contact layer 21 and the first active layer 30. The first layer stack 22 has a multilayer structure consisting of alternating layers of a first layer and a second layer with a lattice constant different from that of the first layer. The first layer stack 22 is a superlattice layer comprising multiple first layers and multiple second layers. The first and second layers are, for example, undoped layers. The first layer is, for example, an undoped GaN layer. The second layer is, for example, an undoped InGaN layer. The first layer stack 22 comprises, for example, 15 to 25 groups of first and second layers. The thickness of the first layer can be set to 0.5 nm to 3 nm. The thickness of the second layer can be set to 0.5 nm to 3 nm. The thickness of the first layer stack 22 can be, for example, 30 nm to 150 nm.

[0025] The concentration of the first n-type impurity in the first layer 22 can be set to, for example, 1 × 10⁻⁶. 17 / cm 3 Above 1×10 19 / cm 3 The p-type impurity concentration of the first layer 22 can be set to, for example, 1 × 10⁻⁶. 17 / cm 3 Above 1×10 18 / cm 3 It should be noted that the first n-type impurity concentration of the first layer stack 22 refers to the highest n-type impurity concentration among the n-type impurity concentrations in the first layer stack 22. The p-type impurity concentration of the first layer stack 22 refers to the highest p-type impurity concentration among the p-type impurity concentrations in the first layer stack 22. It should be noted that the n-type and p-type impurities contained in the first layer stack 22 include cases where they are included due to diffusion from adjacent layers, and cases where they are included due to doping with n-type or p-type impurities in the first layer and / or the second layer.

[0026] A substrate layer 23 is disposed between the substrate 10 and the n-contact layer 21. The substrate layer 23 is, for example, an undoped GaN layer. The thickness of the substrate layer 23 can be, for example, 5 μm or more and 10 μm or less.

[0027] A first active layer 30 is disposed between the first n-side semiconductor layer 20 and the first p-side semiconductor layer 40. The first active layer 30, for example, has a multiple quantum well structure comprising multiple well layers and multiple barrier layers. The multiple well layers are, for example, InGaN. The multiple barrier layers are, for example, GaN. The well layers and barrier layers included in the first active layer 30 are, for example, undoped layers. Alternatively, at least a portion of the well layers and barrier layers included in the first active layer 30 may contain n-type impurities and / or p-type impurities. The light emitted by the first active layer 30 is, for example, ultraviolet light or visible light. The first active layer 30 is, for example, capable of emitting blue light and green light. The emission peak wavelength of the blue light is 430 nm to 490 nm. The emission peak wavelength of the green light is 500 nm to 540 nm.

[0028] A first p-side semiconductor layer 40 is disposed between the first active layer 30 and the tunnel junction layer 50. The first p-side semiconductor layer 40 includes one or more p-type semiconductor layers. Examples of p-type semiconductor layers include those containing p-type impurities such as magnesium (Mg). The p-type semiconductor layer may be, for example, GaN, and may also contain In and / or Al. For example, the p-type impurity concentration of a p-type semiconductor layer containing Mg as a p-type impurity is 1 × 10⁻⁶. 19 / cm 3 Above 5×10 20 / cm 3 The first p-side semiconductor layer 40 may also include an undoped layer. The thickness of the first p-side semiconductor layer 40 can be set to 30 nm or more and 200 nm or less.

[0029] A tunnel junction layer 50 is disposed between the first p-side semiconductor layer 40 and the second n-side semiconductor layer 60. The tunnel junction layer 50 contains n-type impurities and / or p-type impurities. The tunnel junction layer 50 contains at least one of a p-type semiconductor layer having a higher p-type impurity concentration than the first p-side semiconductor layer 40 and an n-type semiconductor layer having a higher n-type impurity concentration than the second n-side semiconductor layer 60. For example, the tunnel junction layer 50 contains a semiconductor layer with a third n-type impurity concentration higher than the second n-side semiconductor layer 60's second n-type impurity concentration. This allows for further narrowing of the width of the depletion layer formed through the pn junction described later. The tunnel junction layer 50 can, for example, use a p-type GaN layer containing Mg as a p-type impurity or an n-type GaN layer containing Si as an n-type impurity. For example, the p-type impurity concentration of the p-type semiconductor layer containing Mg as a p-type impurity is 1 × 10⁻⁶. 20 / cm 3 Above 5×10 21 / cm 3 For example, the n-type impurity concentration of an n-type semiconductor layer containing Si as an n-type impurity is 2 × 10⁻⁶. 20 / cm 3 Above 1×10 21 / cm3 The following are examples of nitride semiconductors constituting the tunnel junction layer 50, such as GaN, InGaN, and AlGaN. The impurity concentration and thickness of the tunnel junction layer 50 can be appropriately varied. For example, the thickness of the tunnel junction layer 50 can be set to 1 nm or more and 6 μm or less.

[0030] The second n-side semiconductor layer 60 includes an intermediate layer 61 and a second layer stack 62. The second n-side semiconductor layer 60 includes one or more n-type semiconductor layers. Examples of n-type semiconductor layers include those containing n-type impurities such as silicon (Si) and germanium (Ge). For example, the n-type semiconductor layer is GaN, and may also contain indium (In) or aluminum (Al). For example, the n-type impurity concentration of an n-type semiconductor layer containing Si as an n-type impurity is 1 × 10⁻⁶. 18 / cm 3 Above 2×10 19 / cm 3 The second n-side semiconductor layer 60 may also include an undoped layer.

[0031] An intermediate layer 61 is disposed between the tunnel junction layer 50 and the second stack 62. The intermediate layer 61 includes an n-type semiconductor layer containing n-type impurities. For example, the intermediate layer 61 can be configured as a multilayer structure in which a first n-type semiconductor layer and a second n-type semiconductor layer with a lower n-type impurity concentration than the first n-type semiconductor layer are sequentially stacked from the tunnel junction layer 50 side. The n-type impurity concentration of the n-type semiconductor layer included in the intermediate layer 61 can be set to be lower than that of the n-type semiconductor layer included in the tunnel junction layer 50. By providing the intermediate layer 61, the surface condition of the semiconductor layer forming the second stack 62 can be improved compared to the surface condition of the tunnel junction layer 50, thus enabling the second stack 62 to be formed with better crystallinity. The thickness of the intermediate layer 61 can be, for example, set to 100 nm or more and 200 μm or less. When the intermediate layer 61 is a multilayer structure, for example, the thickness of the first n-type semiconductor layer can be set to 15 nm or more and 60 nm or less, and the thickness of the second n-type semiconductor layer can be set to 40 nm or more and 180 nm or less.

[0032] The second layer stack 62 is disposed between the intermediate layer 61 and the second active layer 70. The second layer stack 62 has a multilayer structure consisting of alternating layers of a third layer and a fourth layer with a lattice constant different from that of the third layer. The second layer stack 62 is a superlattice layer including multiple third layers and multiple fourth layers. The third and fourth layers are, for example, layers doped with n-type impurities. The third layer is, for example, an n-type GaN layer containing n-type impurities. The fourth layer is, for example, an n-type InGaN layer containing n-type impurities. The second layer stack 62 includes, for example, 15 to 25 groups of third and fourth layers. It should be noted that the n-type impurity only needs to be present in either the third or fourth layer. For example, the third layer can be a layer doped with n-type impurities, and the fourth layer can be an undoped layer.

[0033] The thickness of the second layer 62 can be set to be thinner than the thickness of the first layer 22. This further suppresses the expansion of the V-shaped pits formed on the upper surface of the second layer 62 compared to the first layer 22, and improves the crystallinity of the second active layer 70 formed on the second layer 62. The thickness of the third layer can be set to 0.5 nm to 3 nm. The thickness of the fourth layer can be set to 0.5 nm to 3 nm. The thickness of the second layer 62 can, for example, be set to 30 nm to 150 nm. When the thickness of the second layer 62 is thinner than the first layer 22, for example, the thickness of the first layer 22 can be set to 50 nm to 70 nm, and the thickness of the second layer 62 can be set to 30 nm to 50 nm.

[0034] The second layer stack 62 includes a semiconductor layer doped with n-type impurities. The concentration of the second n-type impurities in the second layer stack 62 is higher than the concentration of the first n-type impurities in the first layer stack 22. This suppresses the diffusion of p-type impurities from the first p-side semiconductor layer 40 and the tunnel junction layer 50 into the semiconductor layer formed on the second layer stack 62. For example, since the second n-side semiconductor layer 60 contains p-type impurities, there is a problem of easy promotion of p-type formation. According to this embodiment, the p-type formation of the semiconductor layer due to the diffusion of such p-type impurities can be reduced, and carriers can be efficiently supplied to the tunnel junction layer 50, thus reducing the forward voltage Vf. The concentration of the second n-type impurities in the second layer stack 62 is preferably, for example, 3 × 10⁻⁶. 17 / cm 3 Above 1×10 20 / cm 3 Hereinafter, 1×10 is more preferred. 18 / cm 3 Above 1×10 20 / cm 3 The p-type impurity concentration in the second layer 62 is higher than that in the first layer 22. For example, the p-type impurity concentration in the second layer 62 can be set to 3 × 10⁻⁶.17 / cm 3 Above 5×10 18 / cm 3 It should be noted that the second n-type impurity concentration of the second layer stack 62 refers to the highest n-type impurity concentration among the n-type impurity concentrations in the second layer stack 62. The p-type impurity concentration of the second layer stack 62 refers to the highest p-type impurity concentration among the p-type impurity concentrations in the second layer stack 62.

[0035] The concentration of the second n-type impurity in the second layer stack 62 is higher than the concentration of the p-type impurity in the second layer stack 62. Therefore, p-type formation in the second layer stack 62 can be suppressed. For example, even when the concentration of the p-type impurity in the second layer stack 62 is higher than the concentration of the p-type impurity in the first layer stack 22, p-type formation in the second layer stack 62 can still be suppressed.

[0036] A second active layer 70 is disposed between the second layer stack 62 and the second p-side semiconductor layer 80. The second active layer 70 may have, for example, a multiple quantum well structure comprising multiple well layers and multiple barrier layers. The multiple well layers may be, for example, InGaN. The multiple barrier layers may be, for example, GaN. The well layers and barrier layers included in the second active layer 70 may be, for example, undoped layers. At least a portion of the well layers and barrier layers included in the second active layer 70 may also contain n-type impurities and / or p-type impurities.

[0037] The light emitted by the second active layer 70 is, for example, ultraviolet light or visible light. The light emitted by the first active layer 30 and the second active layer 70 can be, for example, blue light. The emission peak wavelength of the first active layer 30 and the emission peak wavelength of the second active layer 70 can also be different. For example, the light emitted by the first active layer 30 can be set to blue light, and the light emitted by the second active layer 70 can be set to green light.

[0038] A second p-side semiconductor layer 80 is disposed on the second active layer 70. The second p-side semiconductor layer 80 includes one or more p-type semiconductor layers. Examples of p-type semiconductor layers include those containing p-type impurities such as magnesium (Mg). The p-type semiconductor layer may be, for example, GaN, and may also contain In and / or Al. For example, the p-type impurity concentration of a p-type semiconductor layer containing Mg as a p-type impurity is 1 × 10⁻⁶. 19 / cm 3 Above 5×10 20 / cm 3 The second p-side semiconductor layer 80 may also include an undoped layer. The thickness of the second p-side semiconductor layer 80 can be set to 30 nm or more and 200 nm or less.

[0039] The n-side electrode 91 is disposed on the first n-side semiconductor layer 20 and is electrically connected to the first n-side semiconductor layer. The n-side electrode 91 is disposed on the upper surface of the n-contact layer 21. The p-side electrode 92 is disposed on the second p-side semiconductor layer 80 and is electrically connected to the second p-side semiconductor layer 80.

[0040] A positive voltage is applied between the n-side electrode 91 and the p-side electrode 92. At this time, a positive voltage is applied between the second p-side semiconductor layer 80 and the n-contact layer 21, supplying holes and electrons to the first active layer 30 and the second active layer 70, thereby causing the first active layer 30 and the second active layer 70 to emit light.

[0041] When a positive potential is applied to the p-side electrode 92 and a lower potential is applied to the n-side electrode 91 than to the p-side electrode 92, a reverse voltage is applied between the second n-side semiconductor layer 60 and the first p-side semiconductor layer 40. Therefore, to allow current to flow between the second n-side semiconductor layer 60 and the first p-side semiconductor layer 40, the tunneling effect of the tunnel junction layer 50 is utilized. That is, current flows by allowing electrons existing in the valence band of the first p-side semiconductor layer 40 to tunnel into the conduction band of the second n-side semiconductor layer 60.

[0042] To achieve this tunneling effect, a tunnel junction layer 50 is formed using at least one of two semiconductor layers: a p-type semiconductor layer with a higher p-type impurity concentration than the first p-side semiconductor layer 40 and an n-type semiconductor layer with a higher n-type impurity concentration than the second n-side semiconductor layer 60. A pn ​​junction is formed using this tunnel junction layer 50. For example, a pn junction can be formed using the first p-side semiconductor layer 40 and the tunnel junction layer 50, where the tunnel junction layer 50 uses an n-type semiconductor layer highly doped with n-type impurities. Alternatively, a pn junction can be formed using the tunnel junction layer 50 and the second n-side semiconductor layer 60, where the tunnel junction layer 50 uses a p-type semiconductor layer highly doped with p-type impurities. For example, a pn junction can be formed by making the tunnel junction layer 50 a stacked structure including an n-type semiconductor layer highly doped with n-type impurities and a p-type semiconductor layer highly doped with p-type impurities. The higher the concentration of each conductivity type impurity contained in the first p-side semiconductor layer 40, the tunnel junction layer 50, and the second n-side semiconductor layer 60, the narrower the width of the depletion layer formed through the pn junction can be. Moreover, the narrower the depletion layer, the easier it is for electrons in the valence band of the first p-side semiconductor layer 40 to tunnel through the depletion layer and move to the conduction band of the second n-side semiconductor layer 60 when a voltage is applied.

[0043] As described above, the light-emitting element according to this embodiment can suppress the diffusion of p-type impurities into the second stack 62 and the semiconductor layer formed on the second stack 62, and can reduce the forward voltage Vf. Furthermore, by stacking the second active layer 70 on the first active layer 30, the average output per unit area can be increased compared to a light-emitting element having only one active layer.

[0044] Next, an example of a method for manufacturing the light-emitting element 1 of this embodiment will be described.

[0045] Figure 2 This is a flowchart illustrating a method for manufacturing the light-emitting element according to this embodiment. For example... Figure 2 As shown, the manufacturing method of the light-emitting element in this embodiment includes a first light-emitting part forming process S11, a tunnel layer forming process S12, and a second light-emitting part forming process S13. Figures 3A-3C This is a schematic cross-sectional view illustrating the manufacturing method of the light-emitting element 1 in this embodiment.

[0046] The semiconductor stack 100 contains nitride semiconductor layers formed in a furnace with adjustable pressure and temperature using MOCVD (metal-organic chemical vapor deposition). Each nitride semiconductor layer is epitaxially grown, for example, on a substrate 10. Each nitride semiconductor layer can be formed by introducing a carrier gas and a raw material gas into the furnace. Hydrogen (H2) or nitrogen (N2) can be used as the carrier gas. Ammonia (NH3) can be used as the raw material gas for N. Trimethylgallium (TMG) or triethylgallium (TEG) can be used as the raw material gas for Ga. Trimethylindium (TMI) can be used as the raw material gas for In. Trimethylaluminum (TMA) can be used as the raw material gas for Al. Silane (SiH4) can be used as the raw material gas for Si. Dicyclopentadienylmagnesium (Cp2Mg) can be used as the raw material gas for Mg.

[0047] First, a first light-emitting portion formation process S11 is performed. This process S11 includes forming a first n-side semiconductor layer 20 on the substrate 10, forming a first active layer 30 on the first n-side semiconductor layer 20, and forming a first p-side semiconductor layer 40 on the first active layer 30. In the process of forming the first n-side semiconductor layer 20, a base layer 23, an n-contact layer 21, and a first stacked portion 22 are sequentially formed on the substrate 10. For example... Figure 3A As shown, a first light-emitting portion 11, comprising a first n-side semiconductor layer 20, a first active layer 30, and a first p-side semiconductor layer 40, is formed on the substrate 10 through the first light-emitting portion formation process S11. It should be noted that a buffer layer may be formed on the surface of the substrate 10 before the base layer 23 is formed on the substrate 10. For example, GaN or AlGaN can be used as the buffer layer.

[0048] The first layer stack 22 is formed, for example, by alternately performing a first layer formation step and a second layer formation step. In the first layer formation step, for example, a first layer consisting of an undoped GaN layer is formed by introducing a carrier gas and a raw material gas containing a Ga source and an N source into the furnace. In the second layer formation step, for example, a second layer consisting of undoped InGaN is formed by introducing a carrier gas and a raw material gas containing a Ga source, an N source, and an In source into the furnace. In the step of forming the first n-side semiconductor layer 20, the first layer stack 22 is formed such that the first n-type impurity concentration is, for example, 1 × 10⁻⁶. 17 / cm 3 Above 1×10 19 / cm 3 the following.

[0049] Next, the tunnel layer formation process S12 is carried out. In the tunnel layer formation process S12, as follows: Figure 3B As shown, a tunnel junction layer 50 is formed on the first light-emitting part 11. In the tunnel junction layer forming process S12, for example, a tunnel junction layer 50 composed of a GaN layer with a third n-type impurity concentration is formed by introducing a carrier gas and a raw material gas containing a Ga source, an N source, and a Si source into the furnace. For example, the flow rate ratio of the Si raw material gas contained in the raw material gas is adjusted so that the third n-type impurity concentration is 2 × 10⁻⁶. 20 / cm 3 Above 1×10 21 / cm 3 The tunnel layer 50 is formed in the following manner. When forming the tunnel layer 50, the flow rate of the Si raw material gas is higher than that of the Si raw material gas in the third and fourth layer forming processes described later.

[0050] Next, the second light-emitting part forming process S13 is performed. In the second light-emitting part forming process S13, as follows: Figure 3C As shown, a second light-emitting portion 12 is formed on the tunnel junction layer 50. The second light-emitting portion formation step S13 includes a step of forming a second n-side semiconductor layer 60 on the tunnel junction layer 50, a step of forming a second active layer 70 on the second n-side semiconductor layer 60, and a step of forming a second p-side semiconductor layer 80 on the second active layer 70. In the step of forming the second n-side semiconductor layer 60, an intermediate layer 61 and a second layer stack 62 are sequentially formed on the tunnel junction layer 50. The intermediate layer 61 is formed, for example, in contact with the tunnel junction layer 50.

[0051] The second layer stack 62 is formed, for example, by alternately performing the third layer formation process and the fourth layer formation process. In the third layer formation process, for example, a third layer consisting of a GaN layer doped with n-type impurities is formed by introducing a carrier gas and a raw material gas containing a Ga source, an N source, and a Si source into the furnace. In the fourth layer formation process, for example, a fourth layer consisting of InGaN doped with n-type impurities is formed by introducing a carrier gas and a raw material gas containing a Ga source, an N source, an In source, and a Si source into the furnace. In both the third and fourth layer formation processes, by adjusting the flow rate ratio of the Si raw material gas contained in the raw material gas, the second layer stack 62 is formed such that the concentration of the second n-type impurity in the second layer stack 62 is higher than the concentration of the first n-type impurity in the first layer stack 22. The second layer stack 62 is formed such that the concentration of the second n-type impurity is, for example, 3 × 10⁻⁶. 17 / cm 3 Above 1×10 20 / cm 3 the following.

[0052] Next, a portion of the semiconductor stack 100 is removed, exposing a portion of the n-contact layer 21. Then, as... Figure 1 As shown, an n-side electrode 91 is formed on the n-contact layer 21, and a p-side electrode 92 is formed on the second p-side semiconductor layer 80. The n-side electrode 91 and the p-side electrode 92 can be formed, for example, by sputtering or vapor deposition. Through these processes, a solution can be obtained... Figure 1 The light-emitting element 1 shown.

[0053] The light-emitting elements of the embodiments and the comparative examples were manufactured as described below, and the values ​​of the forward voltage Vf and the output Po in the light-emitting elements of the embodiments and the comparative examples were evaluated.

[0054] [Example]

[0055] Substrate 10 is a sapphire substrate. A buffer layer consisting of an undoped AlGaN layer is formed on the sapphire substrate. A base layer 23 with a thickness of approximately 7 μm consisting of an undoped GaN layer is formed on the buffer layer. An n-contact layer 21 with a thickness of approximately 1.8 μm and doped with Si is formed on the base layer 23. The n-type impurity concentration of the n-contact layer 21 is 1 × 10⁻⁶. 19 / cm 3 Approximately. A first layer stack 22 is formed on the n-contact layer 21 by alternating layers of a first layer composed of an undoped GaN layer and a second layer composed of an undoped InGaN layer. The thickness of the first layer is set to approximately 2 nm, and the thickness of the second layer is set to approximately 1 nm. The first layer stack 22 comprises 20 groups of the first layer and the second layer. The n-type impurity concentration in the first layer stack 22 is 3 × 10⁻⁶. 17 / cm 3Left and right. On the first stack 22, as the first active layer 30, undoped InGaN layers and undoped GaN layers are alternately stacked, thereby forming 7 groups of undoped InGaN layers and undoped GaN layers. On the first active layer 30, as the first p-side semiconductor layer 40, an AlGaN layer doped with Mg, an undoped GaN layer, and a GaN layer doped with Mg are sequentially formed. The p-type impurity concentration of the GaN layer doped with Mg in the first p-side semiconductor layer 40 is 3 × 10⁻⁶. 20 / cm 3 about.

[0056] A Si-doped GaN layer is formed on the first p-side semiconductor layer 40 as a tunnel junction layer 50. The n-type impurity concentration of the tunnel junction layer 50 is 8 × 10⁻⁶. 20 / cm 3 about.

[0057] The thickness of the tunnel layer 50 is approximately 2 nm.

[0058] A Si-doped GaN layer is formed on the tunnel junction layer 50 as an intermediate layer 61. The n-type impurity concentration of the intermediate layer 61 is 8 × 10⁻⁶. 20 / cm 3 The thickness of the intermediate layer 61 is approximately 145 nm. A second layer stack 62 is formed on the intermediate layer 61, consisting of alternating layers of a third layer composed of a Si-doped GaN layer and a fourth layer composed of a Si-doped InGaN layer. The thickness of the third layer is approximately 2 nm, and the thickness of the fourth layer is approximately 1 nm. The second layer stack 62 comprises 20 groups of the third and fourth layers. The n-type impurity concentration in the second layer stack 62 is 2 × 10⁻⁶. 19 / cm 3 Left and right. On the second stack 62, as the second active layer 70, undoped InGaN layers and undoped GaN layers are alternately stacked, thereby forming 7 groups of undoped InGaN layers and undoped GaN layers. On the second active layer 70, as the second p-side semiconductor layer 80, Mg-doped AlGaN layers, undoped GaN layers, and Mg-doped GaN layers are sequentially formed. The p-type impurity concentration of the Mg-doped GaN layer in the second p-side semiconductor layer 80 is 3 × 10⁻⁶. 20 / cm 3 about.

[0059] As an example, a light-emitting element having such a semiconductor stack 100 was fabricated.

[0060] [Comparative Example]

[0061] The comparative example light-emitting element has the same structure as the light-emitting element of the embodiment, except for the structure of the second layer stack 62. Specifically, the second layer stack 62 is constructed by alternately stacking 20 groups of a third layer composed of an undoped InGaN layer and a fourth layer composed of an undoped GaN layer. That is, the third and fourth layers of the second layer stack 62 in the comparative example light-emitting element are formed without doping with n-type impurities.

[0062] The forward voltage Vf of the light-emitting element in the embodiment is 0.13V lower than that of the light-emitting element in the comparative example. Furthermore, the output Po of the light-emitting element in the embodiment is approximately the same as that of the light-emitting element in the comparative example. It should be noted that the value of the forward voltage Vf is the value when a current of 500mA flows through the light-emitting element. Based on these evaluation results, it is confirmed that the light-emitting element of the embodiment can maintain the output Po and can reduce the forward voltage Vf compared to the light-emitting element in the comparative example.

[0063] The embodiments and examples of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. Based on the above embodiments of the present invention, all methods that can be implemented by appropriate design changes by those skilled in the art, as long as they contain the spirit of the present invention, fall within the scope of the present invention. In addition, within the scope of the concept of the present invention, any variations and modifications that can be conceived by those skilled in the art also fall within the scope of the present invention.

[0064] Explanation of reference numerals in the attached figures

[0065] 1: Light-emitting element; 10: Substrate; 11: First light-emitting part; 12: Second light-emitting part; 20: First n-side semiconductor layer; 21: n-contact layer; 22: First stacked part; 23: Base layer; 30: First active layer; 40: First p-side semiconductor layer; 50: Tunnel junction layer; 60: Second n-side semiconductor layer; 61: Intermediate layer; 62: Second stacked part; 70: Second active layer; 80: Second p-side semiconductor layer; 91: n-side electrode; 92: p-side electrode; 100: Semiconductor stack.

Claims

1. A light-emitting element, comprising: A semiconductor stack has a first light-emitting portion, a second light-emitting portion, and a tunnel junction layer. The first light-emitting portion is composed of a nitride semiconductor including a first n-side semiconductor layer, a first p-side semiconductor layer, and a first active layer disposed between the first n-side semiconductor layer and the first p-side semiconductor layer. The second light-emitting portion is located on the first light-emitting portion and is composed of a nitride semiconductor including a second n-side semiconductor layer, a second p-side semiconductor layer, and a second active layer disposed between the second n-side semiconductor layer and the second p-side semiconductor layer. The tunnel junction layer is disposed between the first p-side semiconductor layer and the second n-side semiconductor layer. The n-side electrode is electrically connected to the first n-side semiconductor layer; p-side electrode, which is electrically connected to the second p-side semiconductor layer; The first n-side semiconductor layer includes a first layer stack with a first n-type impurity concentration. The first layer stack has a multilayer structure consisting of alternating layers of a first layer and a second layer with a lattice constant different from that of the first layer. The second n-side semiconductor layer includes a second layer stack with a second n-type impurity concentration. The second layer stack has a multilayer structure consisting of alternating layers of a third layer and a fourth layer with a lattice constant different from that of the third layer. The concentration of the second type n impurity is higher than that of the first type n impurity.

2. The light-emitting element according to claim 1, The third and fourth layers are layers doped with n-type impurities.

3. The light-emitting element according to claim 1, The tunnel junction layer includes a semiconductor layer with a third type n impurity concentration that is higher than the second type n impurity concentration.

4. The light-emitting element according to claim 1, The concentration of the second n-type impurity is higher than the concentration of the p-type impurity in the second layer stack.

5. A light-emitting element, comprising: A semiconductor stack has a first light-emitting portion, a second light-emitting portion, and a tunnel junction layer. The first light-emitting portion is composed of a nitride semiconductor including a first n-side semiconductor layer, a first p-side semiconductor layer, and a first active layer disposed between the first n-side semiconductor layer and the first p-side semiconductor layer. The second light-emitting portion is located on the first light-emitting portion and is composed of a nitride semiconductor including a second n-side semiconductor layer, a second p-side semiconductor layer, and a second active layer disposed between the second n-side semiconductor layer and the second p-side semiconductor layer. The tunnel junction layer is disposed between the first p-side semiconductor layer and the second n-side semiconductor layer. The n-side electrode is electrically connected to the first n-side semiconductor layer; p-side electrode, which is electrically connected to the second p-side semiconductor layer; The first n-side semiconductor layer includes a first layer stack, which has a multilayer structure consisting of alternating layers of a first layer and a second layer with a lattice constant different from that of the first layer. The second n-side semiconductor layer includes a second layer stack with a second n-type impurity concentration. The second layer stack has a multilayer structure consisting of alternating layers of a third layer and a fourth layer with a lattice constant different from that of the third layer. The first and second layers are undoped layers. The third and fourth layers are layers doped with n-type impurities.

6. The light-emitting element according to any one of claims 1 to 5, The thickness of the second layer is thinner than the thickness of the first layer.

7. The light-emitting element according to any one of claims 1 to 5, The concentration of p-type impurities in the second layer is higher than that in the first layer.

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