A triode reliability analysis method based on a FEDformer model

Abstract

The application relates to a triode reliability analysis method based on a FEDformer model, and belongs to the microelectronic technology field; the base region width, aging temperature and working current of the triode in a normal working state are collected; the current gain change Delta beta is calculated; the base region width, the aging temperature and the current gain change Delta beta are selected as characteristic data; abnormal value processing is carried out; noise reduction processing is carried out; feature scaling processing is carried out; set division is carried out; a FEDformer model is established; a high-precision FEDformer model is obtained; optimal parameters of the high-precision FEDformer model are obtained; whether the high-precision FEDformer model is established is judged; the base region width and the aging temperature collected subsequently are taken as inputs of the high-precision FEDformer model, and the reliability of the triode is judged according to the current gain change Delta beta subsequently; the overall NRMSE of the FEDformer model is reduced by 12.6%, the improvement can be more than 20%, the modeling performance is better, and the reliability modeling precision is high.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology and relates to a transistor reliability analysis method based on the FEDformer model. Background Technology

[0002] The bipolar junction transistor (BJT) is an important semiconductor device that plays a crucial role in electronic devices and circuit design. It is widely used in amplification and switching circuits, including wireless communication, power management, and audio amplifiers. The BJT was invented in 1947 by William Shockley, John Bardeen, and Walter Bratton at Bell Labs. It was the first transistor, marking a major breakthrough in semiconductor technology and triggering rapid development in the electronics industry. However, with continuous technological advancements, the manufacturing technology of BJTs has gradually increased in complexity. This necessitates more precise control over each stage of the production process to ensure the reliability of the BJTs.

[0003] In practical applications, transistors can be affected by various factors, such as temperature, voltage, and current, which may lead to performance degradation or even failure. Therefore, modeling and predicting transistor reliability is extremely important. Traditional reliability modeling methods typically rely on physical and empirical models, requiring in-depth analysis of the transistor's physical characteristics and operating environment. This not only increases modeling complexity but also significantly raises computational costs. Furthermore, due to continuous changes in transistor manufacturing technology, these models may generate substantial prediction errors in certain situations. Therefore, developing and introducing a more accurate and efficient method for modeling transistor stability is particularly necessary. Summary of the Invention

[0004] The technical problem solved by this invention is to overcome the shortcomings of the prior art and propose a transistor reliability analysis method based on the FEDformer model. The FEDformer model reduces NRMSE by 12.6% overall, and the improvement can exceed 20%, with better modeling performance and high reliability modeling accuracy.

[0005] The solution of the present invention is:

[0006] A transistor reliability analysis method based on the FEDformer model includes:

[0007] Step 1: Collect the base width, aging temperature, and operating current of the transistor under normal operating conditions; obtain the current before and after aging of the transistor through an aging experiment; obtain the current gain before aging by subtracting the current before aging from the operating current; obtain the current gain after aging by subtracting the current after aging from the operating current; obtain the change in current gain Δβ by subtracting the current gain after aging from the current gain before aging.

[0008] Step 2: Select the base region width and aging temperature as input feature data; select the change in current gain Δβ as output feature data; the change in current gain Δβ is used to evaluate the reliability of the transistor.

[0009] Step 3: Handle outliers in all feature data;

[0010] Step 4: Perform noise reduction processing on the feature data;

[0011] Step 5: Perform feature scaling on the feature data;

[0012] Step 6: Divide the feature data into sets, including training set, validation set, and test set;

[0013] Step 7: Establish the FEDformer model;

[0014] Step 8: Substitute the training set from Step 6 into the FEDformer model from Step 7 for training to obtain a high-precision FEDformer model.

[0015] Step 9: Substitute the validation set from Step 6 into the high-precision FEDformer model from Step 8 to obtain the optimal parameters of the high-precision FEDformer model.

[0016] Step 10: Obtain the normalized root mean square error and normalized bias of the high-precision FEDformer model; use the normalized root mean square error and normalized bias as evaluation indicators of the prediction accuracy of the high-precision FEDformer model; when the normalized root mean square error and normalized bias both meet the preset requirements, it is determined that the high-precision FEDformer model has been established and proceed to Step 11; otherwise, return to Step 1 and re-establish the high-precision FEDformer model.

[0017] Step 11: Substitute the subsequently acquired base region width and aging temperature into the high-precision FEDformer model as input to the high-precision FEDformer model. The high-precision FEDformer model outputs the change in current gain Δβ. Subsequently, the reliability of the transistor is evaluated based on the change in current gain Δβ.

[0018] In the aforementioned transistor reliability analysis method based on the FEDformer model, in step one, the aging test is conducted in a high-temperature environment, and the temperature does not exceed the transistor's maximum withstand temperature.

[0019] In the aforementioned transistor reliability analysis method based on the FEDformer model, step three involves using the z-score method to process outliers in the feature data; outlier processing includes handling missing values ​​and deleting duplicate values ​​from the data.

[0020] In the aforementioned transistor reliability analysis method based on the FEDformer model, step four involves using a high-pass filter to denoise the feature data. During denoising, the sampling rate is set to 1000Hz, the cutoff frequency is set to 50Hz, and the order is set to 4.

[0021] In the transistor reliability analysis method based on the FEDformer model described above, step five involves using the maximum absolute value scaling method to perform feature scaling on the feature data; the data is scaled to the range of [-1, 1] while retaining the sign information.

[0022] In the aforementioned transistor reliability analysis method based on the FEDformer model, in step six, 60% of the feature data is used as the training set, 20% of the feature data is used as the validation set, and 20% of the feature data is used as the test set.

[0023] In the aforementioned transistor reliability analysis method based on the FEDformer model, step seven involves establishing the FEDformer model as follows:

[0024] An encoder-decoder architecture is used; the model has an input length of 6 and an output length of 3; the sequence has 2 hidden states; the encoder's input is a 6×3 matrix; the decoder accepts 12 inputs; the encoder and decoder adopt a multi-layer structure.

[0025] In the aforementioned transistor reliability analysis method based on the FEDformer model, during step eight, when training the FEDformer model:

[0026] The loss function is set to MSE loss; Adam is used as the optimizer for model training; the learning rate is 10. -4 Each iteration reduces the number of iterations to one-tenth, setting the number of iterations to 5.

[0027] In the aforementioned transistor reliability analysis method based on the FEDformer model, step nine includes optimal parameters such as learning rate, iteration reduction amount, and number of iterations; by substituting the validation set, a learning rate of 10 is obtained.-4 Each iteration reduces the number of iterations to one-tenth, and the number of iterations is 5.

[0028] In the aforementioned transistor reliability analysis method based on the FEDformer model, in step ten, the test set from step six is ​​substituted into the high-precision FEDformer model after determining the optimal parameters in step nine to obtain the normalized root mean square error and normalized deviation of the high-precision FEDformer model.

[0029] The beneficial effects of this invention compared to the prior art are:

[0030] (1) This invention provides a more flexible and concise way to capture dependencies at different time scales, and achieves the highest transistor reliability prediction accuracy with the least time and memory consumption in multi-step prediction tasks of data processing, thereby improving the computational efficiency and accuracy of the model.

[0031] (2) This invention preprocesses the feature data by using the z-score method to process outliers, using a high-pass filter to reduce noise, and using feature scaling to preprocess the feature data, thus completing the preliminary feature data processing work for establishing a high-precision FEDformer model.

[0032] (3) In this invention, the training set is substituted into the FEDformer model for training to obtain a high-precision FEDformer model; the validation set is substituted into the high-precision FEDformer model in step eight to obtain the optimal parameters of the high-precision FEDformer model; the test set is substituted into the high-precision FEDformer model after determining the optimal parameters to obtain the normalized root mean square error and normalized deviation of the high-precision FEDformer model, verifying the accuracy of the high-precision FEDformer model and laying a precise foundation for subsequent transistor reliability judgment. Attached Figure Description

[0033] Figure 1 This is a flowchart of the transistor reliability analysis based on the FEDformer model of this invention. Detailed Implementation

[0034] The present invention will be further described below with reference to the embodiments.

[0035] This invention provides a transistor reliability analysis method based on the FEDformer model. It proposes a modeling approach using machine learning, which can take into account the complexity of the transistor's structural parameters during modeling and accurately predict its reliability performance. By constructing this model, it is convenient to identify and solve problems in a timely manner during production and use, thus ensuring the high quality and reliability of the transistor.

[0036] Transistor reliability analysis method based on FEDformer model, such as Figure 1 The specific steps shown are as follows:

[0037] Step 1: Collect the base width, aging temperature, and operating current of the transistor under normal operating conditions; obtain the current before and after aging of the transistor through an aging experiment; during the aging experiment, the environment is set to a high-temperature environment, and the temperature does not exceed the maximum withstand temperature of the transistor. The difference between the current before aging and the operating current is used to obtain the current gain before aging; the difference between the current after aging and the operating current is used to obtain the current gain after aging; the difference between the current gain after aging and the current gain before aging is used to obtain the change in current gain Δβ.

[0038] Step 2: Select the base region width and aging temperature as input feature data; select the change in current gain Δβ as output feature data; the change in current gain Δβ is used to evaluate the reliability of the transistor.

[0039] Step 3: Handle outliers in all feature data.

[0040] This invention employs the z-score method to handle outliers in feature data; outlier handling includes processing missing values ​​and deleting duplicate values.

[0041] Step 4: Perform noise reduction processing on the feature data.

[0042] This invention uses a high-pass filter to denoise the feature data; during denoising, the sampling rate is set to 1000Hz, the cutoff frequency is set to 50Hz, and the order is set to 4.

[0043] Step 5: Perform feature scaling on the feature data.

[0044] This invention employs the maximum absolute value scaling method to perform feature scaling on feature data; the data is scaled to the range of [-1, 1] while preserving symbol information.

[0045] Step 6: Divide the feature data into three sets: training set, validation set, and test set. 60% of the feature data will be used as the training set, 20% as the validation set, and 20% as the test set.

[0046] Step 7: Establish the FEDformer model.

[0047] The method for building the FEDformer model is as follows:

[0048] An encoder-decoder architecture is used; the model has an input length of 6 and an output length of 3; the sequence has 2 hidden states; the encoder's input is a 6×3 matrix; the decoder accepts 12 inputs; the encoder and decoder adopt a multi-layer structure.

[0049] Step 8: Substitute the training set from Step 6 into the FEDformer model from Step 7 for training to obtain a high-precision FEDformer model. When training the FEDformer model, the loss function is set to MSE loss; Adam is used as the optimizer for model training; the learning rate is 10. -4 Each iteration reduces the number of iterations to one-tenth, setting the number of iterations to 5.

[0050] Step 9: Substitute the validation set from Step 6 into the high-precision FEDformer model from Step 8 to obtain the optimal parameters of the high-precision FEDformer model.

[0051] The optimal parameters selected in this invention include the learning rate, the reduction in iterations, and the number of iterations; by substituting these parameters into the validation set, a learning rate of 10 is obtained. -4 Each iteration reduces the number of iterations to one-tenth, and the number of iterations is 5.

[0052] Step 10: Substitute the test set from Step 6 into the high-precision FEDformer model after determining the optimal parameters in Step 9, and obtain the normalized root mean square error and normalized bias of the high-precision FEDformer model; use the normalized root mean square error and normalized bias as evaluation indicators of the prediction accuracy of the high-precision FEDformer model; when both the normalized root mean square error and normalized bias meet the preset requirements, it is determined that the high-precision FEDformer model has been established and proceed to Step 11; otherwise, return to Step 1 and re-establish the high-precision FEDformer model.

[0053] Step 11: Substitute the subsequently acquired base region width and aging temperature into the high-precision FEDformer model as input to the high-precision FEDformer model. The high-precision FEDformer model outputs the change in current gain Δβ. Subsequently, the reliability of the transistor is evaluated based on the change in current gain Δβ.

[0054] Example

[0055] Step 1: Data Acquisition. Silvaco TCAD software is used to simulate the BJT device to obtain relevant model data. ATLAS tools are used to construct various BJT devices based on base width and aging temperature. Before aging, the initial current gain is obtained through TCAD simulation. The aging environment is set to high-temperature conditions, ensuring it does not exceed the device's maximum junction temperature. High-temperature pressure values ​​of 370K, 400K, and 420K are selected. The BJT device is simulated again using TCAD to obtain the final current gain, and the change in current gain (Δβ) is calculated.

[0056] Step 2: Select Input / Output Features. The width of the base region, which has a significant impact on equipment performance and is affected by the aging environment temperature, is selected as the input feature. The change in current gain (Δβ) is a core parameter reflecting equipment reliability; therefore, the change in current gain (Δβ) is chosen as the output feature to characterize the reliability level of the BJT equipment.

[0057] Step 3: Data Preprocessing. First, the data is cleaned, missing values ​​are removed, and duplicate values ​​are deleted. The z-score method is used to handle outliers; the formula is:

[0058]

[0059] Where Z is the z-score, x is the value of a data point, u is the mean of the dataset, and σ is the standard deviation of the dataset.

[0060] A high-pass filter is used for overall data noise reduction. The sampling rate is 1000Hz, the cutoff frequency is 50Hz, the order is 4, and the transfer function formula is as follows:

[0061]

[0062] Where H(s) is the transfer function of the filter, s is a complex variable, and ω c is the cutoff frequency, and n is the filter order.

[0063] For feature scaling, the Max Absolute Scaling method is used to scale data features to the range [-1, 1] while preserving the sign information of the features. The formula is as follows:

[0064]

[0065] Where x is the original data feature, and max_abs is the maximum absolute value of the feature.

[0066] For data partitioning, the dataset is divided into a 60% training set, a 20% validation set, and a 20% test set.

[0067] Step 4: Build the FEDformer model using Python version 3.8 or higher and PyTorch library version 1.9.0. Use an encoder-decoder architecture with an input length of 6 and an output length of 3. The hidden states of the sequence are 2. The encoder input is a 6×3 matrix, and the decoder accepts 12 inputs. The encoder uses a multi-layer structure, represented as follows: Where l∈{1,…,N} represents the output of the l-th layer encoder, and It is an embedded historical sequence, specifically in the form of:

[0068]

[0069]

[0070]

[0071] in These represent the seasonal components after the i-th decomposition block of the l-th layer. For the frequency enhancement module (FEB), there are two different versions (Fourier frequency enhancement attention and wavelet frequency enhancement attention), implemented through discrete Fourier transform (DFT) and discrete wavelet transform (DWT) mechanisms, respectively, which can seamlessly replace the self-attention module.

[0072] The decoder also adopts a multi-layer structure as follows: Where l∈{1,…,M} represents the l-th output decoder layer, specifically in the form:

[0073]

[0074]

[0075]

[0076]

[0077]

[0078] in These represent the seasonal and trend components after the i-th decomposition block of the l-th layer, respectively. i∈{1,2,3} represents the i-th extracted trend. The projector. Similar to the frequency enhancement module, the frequency enhancement attention module (FEA) has two different versions (Fourier frequency enhancement attention and wavelet frequency enhancement attention), which implement attention design through discrete Fourier transform (DFT) and discrete wavelet transform (DWT) projection respectively, and can replace the cross-attention module.

[0079] The model design incorporates a Mixture Of Experts Decomposition block (MOEDecomp), which includes a set of averaging filters of varying sizes to extract multiple trend components from the input signal, and a set of data-dependent weights to combine these trend components into a final trend. The specific formula is as follows:

[0080] X trend =Softmax(L(x))*(F(x)),

[0081] Where F(x) is a set of average pool filters, and Softmax(L(x)) is the weights that blend these extraction trends.

[0082] The final output is the sum of the two refined decomposition components. in It is the seasonal component after depth transformation Project onto the target dimension.

[0083] Step 5: Train the FEDformer model. Set the loss function to MSE loss, use Adam as the optimizer for model training, set the learning rate to 10⁻⁴, reduce it to one-tenth in each iteration, and set the number of iterations to 5.

[0084] Step Six: Model Evaluation and Testing. Substitute the training set data to test the model on unknown data. Use the Normalized Root Mean Square Error (NRMSE) and Normalized Bias (ND) as evaluation metrics to measure the model's predictive performance. The formula for the Normalized Root Mean Square Error is:

[0085]

[0086] The normalized deviation formula is:

[0087]

[0088] Where, x j,t This is the actual value. The predicted value is N, where N is the total number of samples in the dataset, and T is the length of the data sequence.

[0089] The base region width and aging temperature collected subsequently are substituted into the high-precision FEDformer model as inputs. The high-precision FEDformer model outputs the change in current gain Δβ. The reliability of the transistor is then evaluated based on the change in current gain Δβ.

[0090] The present invention provides a transistor reliability analysis method based on the FEDformer model. It proposes to use machine learning modeling, which can take into account the complexity of transistor structural parameters during modeling and accurately predict its reliability performance. By building this model, it is convenient to discover and solve problems in a timely manner during production and use, so as to ensure the high quality and reliability of transistors.

[0091] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A transistor reliability analysis method based on the FEDformer model, characterized in that: include: Step 1: Collect the base width, aging temperature, and operating current of the transistor under normal operating conditions; obtain the current before and after aging of the transistor through an aging experiment; obtain the current gain before aging by subtracting the current before aging from the operating current; obtain the current gain after aging by subtracting the current after aging from the operating current. The change in current gain Δβ is obtained by subtracting the current gain after aging from the current gain before aging. Step 2: Select the base region width and aging temperature as input feature data; The change in current gain Δβ is selected as the output characteristic data; The change in current gain Δβ is used to evaluate the reliability of the transistor; Step 3: Handle outliers in all feature data; Step 4: Perform noise reduction processing on the feature data; Step 5: Perform feature scaling on the feature data; Step 6: Divide the feature data into sets, including training set, validation set, and test set; Step 7: Establish the FEDformer model; Step 8: Substitute the training set from Step 6 into the FEDformer model from Step 7 for training to obtain a high-precision FEDformer model. Step 9: Substitute the validation set from Step 6 into the high-precision FEDformer model from Step 8 to obtain the optimal parameters of the high-precision FEDformer model. Step 10: Obtain the normalized root mean square error and normalized bias of the high-precision FEDformer model; use the normalized root mean square error and normalized bias as evaluation indicators of the prediction accuracy of the high-precision FEDformer model; when the normalized root mean square error and normalized bias both meet the preset requirements, it is determined that the high-precision FEDformer model has been established and proceed to Step 11; otherwise, return to Step 1 and re-establish the high-precision FEDformer model. Step 11: Substitute the subsequently acquired base region width and aging temperature into the high-precision FEDformer model as input to the high-precision FEDformer model. The high-precision FEDformer model outputs the change in current gain Δβ. Subsequently, the reliability of the transistor is evaluated based on the change in current gain Δβ.

2. The transistor reliability analysis method based on the FEDformer model according to claim 1, characterized in that: In step one, during the aging test, the environment is set to a high-temperature environment, and the temperature does not exceed the maximum withstand temperature of the transistor.

3. The transistor reliability analysis method based on the FEDformer model according to claim 1, characterized in that: In step three, the z-score method is used to process outliers in the feature data; outlier processing includes handling missing values ​​and deleting duplicate values.

4. The transistor reliability analysis method based on the FEDformer model according to claim 1, characterized in that: In step four, a high-pass filter is used to denoise the feature data; during the denoising process, the sampling rate is set to 1000Hz, the cutoff frequency is set to 50Hz, and the order is set to 4.

5. The transistor reliability analysis method based on the FEDformer model according to claim 1, characterized in that: In step five, the maximum absolute value scaling method is used to perform feature scaling on the feature data; The data is scaled to the range [-1, 1] while preserving the symbol information.

6. The transistor reliability analysis method based on the FEDformer model according to claim 1, characterized in that: In step six, 60% of the feature data is used as the training set, 20% as the validation set, and 20% as the test set.

7. The transistor reliability analysis method based on the FEDformer model according to claim 1, characterized in that: In step seven, the method for establishing the FEDformer model is as follows: An encoder-decoder architecture is used; the model has an input length of 6 and an output length of 3; the sequence has 2 hidden states; the encoder's input is a 6×3 matrix; the decoder accepts 12 inputs; the encoder and decoder adopt a multi-layer structure.

8. The transistor reliability analysis method based on the FEDformer model according to claim 1, characterized in that: In step eight, when training the FEDformer model: The loss function is set to MSE loss; Adam is used as the optimizer for model training; the learning rate is 10. -4 Each iteration reduces the number of iterations to one-tenth, setting the number of iterations to 5.

9. The transistor reliability analysis method based on the FEDformer model according to claim 1, characterized in that: In step nine, the optimal parameters include the learning rate, the iteration reduction amount, and the number of iterations; by substituting into the validation set, the learning rate is found to be 10. -4 Each iteration reduces the number of iterations to one-tenth, and the number of iterations is 5.

10. The transistor reliability analysis method based on the FEDformer model according to claim 1, characterized in that: In step ten, the test set from step six is ​​substituted into the high-precision FEDformer model after determining the optimal parameters in step nine to obtain the normalized root mean square error and normalized bias of the high-precision FEDformer model.

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