Processing system, corresponding apparatus and corresponding method

Abstract

Embodiments of the present disclosure relate to processing systems, corresponding apparatuses, and corresponding methods. An integrated circuit includes a clock control circuit coupled to a reference clock signal node and a plurality of circuits including a voltage regulator, a digital circuit, and an analog circuit. The voltage regulator provides a regulated voltage in operation. The clock control circuit generates a system clock in operation. An input / output interface circuit apparatus is coupled to the plurality of circuits and a common input / output node. The input / output interface circuit apparatus selectively couples one of the plurality of circuits to the common input / output node in operation.

Description

[0001] This application is a divisional application of the invention patent application filed on February 27, 2020, with Chinese national application number 202010124922.9 and entitled "Processing System, Corresponding Device and Corresponding Method". Technical Field

[0002] This specification relates to integrated circuits with embedded processing systems. Background Technology

[0003] In processing circuits designed for general-purpose applications (e.g., microcontrollers or system-on-a-chip (SoCs) such as the STM32 microcontroller), a crystal oscillator (either internally placed on the microcontroller chip or externally) is used to generate frequencies stably and accurately. This requires the microcontroller to be capable of providing regulated power to the external crystal oscillator as needed, particularly.

[0004] However, microcontrollers often also have requirements such as low-power operation and reduced package pin count (for example, this requires the use of general-purpose input / output nodes instead of dedicated nodes) to save package pin count and drive such general-purpose input / output nodes according to application requirements.

[0005] Known disclosures of providing an internal voltage regulator in such microcontrollers provide dedicated pins for the power connection between the internal regulated power supply and an external crystal oscillator. However, since this cannot be achieved at the expense of GPIO development flexibility, dedicated nodes are required to allow coverage of different applications in the general market.

[0006] Therefore, for microcontroller applications that do not require an external crystal oscillator, applications that do not require feeding regulated power to an external crystal oscillator, and applications that use an external crystal oscillator that receives regulated power from the microcontroller during a specific time window, the dedicated pin may become unavailable. Summary of the Invention

[0007] Despite extensive activity in this field, there is a desire for improved disclosure to provide a reasonable level of security without incurring overly complex (and correspondingly expensive) arrangements.

[0008] One or more embodiments provide circuits having the features set forth in the appended claims.

[0009] One or more embodiments may relate to corresponding devices (e.g., consumer products such as microcontroller-based consumer products (e.g., home appliances)) and corresponding methods.

[0010] The claims form part of the technical teachings provided herein with respect to the embodiments.

[0011] One or more embodiments provide a regulated voltage output without changing the pin count, which determines a reduction in the board's BoM (Bill of Materials) without affecting the package.

[0012] One or more embodiments also provide GPIO flexibility because they can handle applications with or without an external oscillator, or with or without an external oscillator having a regulated voltage from the processing circuitry, without requiring different packages or specific package options.

[0013] In some embodiments, the processing system includes: an oscillator management circuit that provides an oscillator signal to a clock controller in the microcontroller to generate a system clock, the oscillator management circuit including at least a node for coupling an external crystal oscillator; an internal voltage regulator coupled to a digital voltage supply node to provide regulated power as an output; and a general purpose input / output (GPIO) circuit including analog circuitry shared by multiple analog circuitry of the microcontroller via corresponding analog links under the control of a GPIO controller, and digital input / output circuitry shared by multiple digital circuitry of the microcontroller also operating under the control of the GPIO controller, the analog and digital circuitry being coupled to a shared input / output node.

[0014] In some embodiments, the integrated circuit includes: a clock control circuit that generates a system clock in operation, the clock control circuit being coupled to a reference clock signal node; a plurality of circuits including a voltage regulator, digital circuitry, and analog circuitry that provide an regulated voltage in operation; and an input / output interface circuitry means coupled to the plurality of circuits and a common input / output node, wherein the input / output interface circuitry means selectively couples one of the plurality of circuits to the common input / output node in operation.

[0015] In some embodiments, the system includes: a processor system and a crystal oscillator coupled to a clock control circuitry of the processor system. The processor system includes: a clock control circuitry that generates a system clock during operation, the clock control circuitry being coupled to a reference clock signal node; a plurality of circuits including a voltage regulator that provides a regulated voltage during operation, a plurality of digital circuits, and a plurality of analog circuits; and an input / output interface circuitry means coupled to the plurality of circuits and a common input / output node, wherein the input / output interface circuitry means selectively couples one of the plurality of circuits to the common input / output node during operation.

[0016] In some embodiments, the method includes: generating a system clock by a clock control circuit of an integrated circuit; and selectively coupling one of a plurality of circuits to a common input / output node, the plurality of circuits including a voltage regulator, digital circuitry, and analog circuitry that provide an regulated voltage during operation; wherein the voltage regulator is coupled to the common input / output node when the common input / output node is coupled to an input node of a crystal oscillator.

[0017] One or more embodiments can be applied to microcontroller or system-on-chip (SoC) arrangements for general-purpose applications. Attached Figure Description

[0018] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, wherein:

[0019] Figure 1 This is a block diagram of an example system according to an embodiment;

[0020] Figure 2 This is a block diagram of an example system according to a variant embodiment;

[0021] Figure 3 In a sample configuration Figure 1 System block diagram; and

[0022] Figure 4 In a sample configuration Figure 1 A block diagram of the system. Detailed Implementation

[0023] In the following description, one or more specific details are set forth to provide a thorough understanding of examples of embodiments of this specification. Embodiments may be obtained without one or more of these specific details or by utilizing other methods, components, materials, etc. In other instances, known structures, materials, or operations are not detailed or described so that certain aspects of the embodiments are not obscured.

[0024] References to "embodiment" or "one embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to an embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" appearing at one or more points in this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular configurations, structures, or features may be combined in any suitable manner.

[0025] Reference numerals used herein are provided for convenience only and therefore do not limit the extent of protection or the scope of embodiments.

[0026] Figure 1The block diagram is a partial illustration of a processing system 10 (specifically, a general-purpose microcontroller). Specifically, the core, including the central processing circuitry, is not shown and is indicated by a signal interchanged with reference numeral 30, which represents this central processing circuitry. Reference numeral 11 indicates the oscillator control circuitry 11. This oscillator management circuitry 11 is a circuit that can be coupled to an external crystal oscillator 50 to obtain a frequency reference Xosc_ref and to provide the external oscillator clock signal Xosc_clk to the clock controller 13.

[0027] As mentioned, the central processing circuit 30 of the processing system 10 (in Figure 1 (Schematably shown in the accompanying drawing 30) The control logic 132 of the clock controller 13 is commanded via the program register 131. The control logic 132 of the clock controller 13 is configured to issue a selection signal CS to a multiplexer 133 that receives multiple clock signals to select the system clock sys_clk for processing the system 10. The multiple clock signals include the external oscillator clock signal Xosc_clk and other clock signals from other sources clk_srcs. This control logic 132 is also configured to issue clock control signals including handshake signals under the control of the central processing circuit 30. The handshake signals include: enabling the external clock signal Xosc_clk, and a ready external clock signal Xosc_clk_ready for communicating with the oscillator control circuit 11, and an external oscillator enable signal Xosc_en for controlling the external oscillator 50 to be enabled and disabled by the oscillator control circuit 11.

[0028] According to one aspect of this disclosure, control logic 132 is further configured to issue an external oscillator power enable signal ext_Xosc_pwr_en under the control of CPU 30, which enables the power of the chip of processing system 10 to be supplied to external oscillator 50 (if present). As described in more detail below, the external oscillator power enable signal ext_Xosc_pwr_en performs gating on the control bits of a switch, thereby enabling power supply to external oscillator 50.

[0029] Therefore, in Figure 1 The external crystal oscillator 50 is shown in dashed lines to indicate whether this external crystal oscillator 50 can be coupled or not coupled to the processing system 10 (as follows). Figure 4(As shown in the configuration). Specifically, the processing system 10 includes two nodes P1 and P2 (e.g., pins, pads, terminals, etc.) for outputting a frequency reference Xosc_ref and inputting commands to the control circuitry 11, to which the oscillator control circuitry 11 is thus coupled. If the crystal oscillator is implemented internally by the microcontroller, nodes P1 and P2 are typically used to couple an external quartz crystal. In the case of this disclosure, an external crystal oscillator is used, the quartz crystal is not connected, and one of the nodes between P1 and P2 is used to input the clock Xosc_ref generated by the external oscillator 50 into the microcontroller.

[0030] The processing system 10 then includes an internal voltage regulator 12 coupled to a third node P3, on which a digital voltage source VDD can be coupled and configured to output regulated electrical power V to the circuitry of the processing circuitry 10. reg .

[0031] Then, a general purpose input / output (GPIO) circuit 14, including analog circuitry 14a, is provided within the processing system 10. Typically, analog circuitry 14a can be shared by multiple analog circuits 40a of the processing system 11 via corresponding analog links under the control of the general purpose input / output controller 15. This allows desired links to be selectively coupled to a common rail 14c, and then coupled to a common input / output node P4 by controlling corresponding switches on the control links.

[0032] The general-purpose input / output circuitry 14 can therefore include the hardware capability to connect multiple analog circuits 40a to the same GPIO, thereby allowing access to the same external target from different internal sources. For this purpose, access to a shared path within the GPIO can be obtained using dedicated analog switches 141 embedded in the GPIO (e.g., a dedicated analog switch for each analog circuit connected to the GPIO). These switches 141 can be controlled by a digital enable signal analog_en from digital logic (e.g., control 15 associated with the analog circuit 40a), thereby allowing or denying the transmission of analog signals associated with a particular circuit to an output node (e.g., node P4) processed by the general-purpose input / output circuitry 14.

[0033] Contention avoidance between these multiple possible connections can be achieved through software running on an embedded core (e.g., CPU 30). This can be configured for certain selected applications to allow proper coupling between one or more analog circuits 40a and a GPIO circuit (e.g., common rail 14c and common node P4).

[0034] The general-purpose input / output circuit 14 also includes digital input / output circuitry 14b, which is shared by multiple digital circuits 40b of the processing circuitry 10. These digital circuits 40b are also used to access the general-purpose input / output circuitry 14 under the control of the general-purpose input / output controller 15. Digital circuitry 143 includes digital input circuitry 143 and digital output circuitry 142, particularly input and output buffers for digital signals. Both analog circuitry 14a and digital circuitry 14b are coupled to a common input / output node P4 via a common rail 14c.

[0035] exist Figure 1 The diagram shows a general-purpose input / output controller 15 providing an analog enable signal, analog_en, to analog circuit 14a as a control signal for analog switch 141, which is coupled to voltage regulator 12 to provide a regulated voltage V. reg The output of the analog switch 141 is coupled downstream of the analog link to track 14c / node P4. The general-purpose input / output controller 15 is also configured to exchange digital input signals dig_in and digital output signals dig_out between digital input circuitry 143 and digital output circuitry 142 and digital circuitry 40b, respectively, thereby also providing digital control signals (e.g., digital input enable signals dig_in_en and digital output enable signals dig_out_en) to digital input circuitry 143 and digital output circuitry 142 to enable / disable such circuitry (e.g., to put them in an on / off operating state).

[0036] The general-purpose input / output controller 15 is configured to operate the above functions and issue the above signals under the control of the CPU 30.

[0037] exist Figure 1 Also shown are blocks representing one or more external target circuits 60 that may be coupled to the processing system 10. They are shown in dashed lines to indicate whether they may be present or absent and whether they may be coupled or not coupled to the processing system 10, depending on the application.

[0038] exist Figure 3 The diagram illustrates the configuration of the processing system 10 when an external crystal oscillator 50 is present but it is powered externally (e.g., not via the power regulator 12 of the processing circuitry 10). Figure 3 As shown, the power input V of the external crystal oscillator 50 Xosc Coupled to external power supply V ext .

[0039] In this configuration, the general-purpose input / output controller 15 provides the analog enable signal `analog_en` with a value, for example, a logic high value, which turns off (e.g., disconnects) the analog switch 141. The digital input enable signal `dig_in_en` and the digital output enable signal `dig_out_en` are provided by the GPIO controller 15 to turn on the digital input circuitry 143 and turn off the digital output circuitry 142 when digital input is needed by the digital circuitry 40b, and to turn off the digital input circuitry 143 and turn on the digital output circuitry 142 when digital output is needed, thereby avoiding contention for the shared node P4. Digital data can thus be exchanged with the external target circuitry 60.

[0040] Then Figure 4 The diagram illustrates the situation where an external crystal oscillator 50 is present and power input V is supplied on-chip via a power regulator 12 of the processing system 10. Xosc Configuration of the processing system 10 when powered (e.g., power is supplied to the oscillator 50).

[0041] In this case, the general-purpose input / output controller 15 provides an analog enable signal analog_en, which can turn analog switch 141 on or off (e.g., close or open). In this way, when the enable signal analog_en is ON, the regulated power V of the power regulator 12... reg Access to the shared node P4 is permitted, to which the external oscillator 50 is coupled. The general-purpose input / output controller 15 provides values ​​to the digital input enable (dig_in_en) and digital output enable (dig_out_en) signals to determine the shutdown values ​​of the digital input circuitry 143 and digital output circuitry 142, thereby avoiding contention for the shared node P4. In this configuration, digital data cannot be exchanged with the external target circuitry 60.

[0042] In this configuration, the software enable signal analog_en (e.g., a switch control signal) is gated by the external oscillator power enable signal ext_Xosc_pwr_en issued by control logic 132 according to the node configuration or mode.

[0043] 1. In analog mode, where, for example, for external oscillator 50, power connection is available on shared node P4, and external oscillator power enable signal ext_Xosc_pwr_en is ON, for example, enabling the enable signal analog_en to be propagated to switch 141;

[0044] 2. In digital mode, where digital circuitry 40b can be connected on shared node P4, the external oscillator power enable signal ext_Xosc_pwr_en is off, so the enable signal analog_en is not propagated, and the digital circuitry 14b of GPIO circuitry 14 can access shared node P4. The digital input enable signal dig_in_en and the digital output enable signal dig_out_en are then driven by general-purpose input / output controller 15 according to the requirements of the relevant application.

[0045] It is observed here that the disclosure described herein allows for the controlled driving of power or digital inputs / outputs using the same shared node P4. On the same shared node P4 configured in analog mode, digital control is again implemented in the GPIO controller block (e.g., as referenced below). Figure 2 Similarly, under the supervision of analog_en1 and analog_en2, different analog signals can be connected to external analog circuits, thus sharing the same link with the power regulated by the external oscillator.

[0046] Therefore, a gated power enable signal (e.g., analog_en gated by ext_Xosc_pwr_en) is provided to control the analog switch 141 dedicated to power coupling.

[0047] exist Figure 2 The image shows an embodiment of a processing system (indicated by 10') in which an oscillator management circuit 11' is provided, the oscillator management circuit 11' including an internal voltage regulator 12', the internal voltage regulator 12' being coupled to a digital power supply pin P3 and providing regulated power V. reg As output, the regulated power V reg It is fed to the general-purpose input / output circuit 14. However, in this case, an analog switch indicated by 111 is placed in series on the output of the internal voltage regulator 12', which is also integrated within the oscillator control circuit 11'. The oscillator control circuit 11' can be adapted for... Figure 2 Any oscillator control circuit (e.g., a core with integrated voltage regulators and switches) configured and embedded with a crystal oscillator circuitry for RF communication. This circuitry can be shared with a microcontroller that embeds such oscillator control circuitry.

[0048] Downstream of analog switch 111, the link is directly connected to shared node P4. Then, with... Figure 1 and Figure 3In the same manner as the analog enable signal analog_en, the analog switch 111 is controlled by the first analog enable signal analog_en1 of the general-purpose input / output controller 15. In other words, in this embodiment, the analog switch 111 is located in the oscillator control circuit 11', not in the general-purpose input / output circuit 14. In some embodiments, one or more of the voltage regulator 12' and the analog switch 111 may be decoupled from the oscillator control circuit 11'.

[0049] like Figure 2 As shown, analog circuit 14a includes switch 141', which can be controlled by an analog enable signal analog_en2 to couple analog circuit 40a (not shown for simplicity) to a common node P4. Similar to the control signals of digital circuit 14b, when the first analog enable signal analog_en1 controls switch 111 to turn on, allowing power to be coupled to oscillator 50, the analog enable signal analog_en2 controls switch 141' to turn off. When the first analog enable signal analog_en1 controls switch 111 to turn off (possibly gated by an external oscillator power enable signal ext_Xosc_pwr_en, thus keeping switch 111 off), the states of switch 141' and other analog switches in the circuitry of digital circuit 14b, if present, are driven by controller 15 according to application requirements and commands from CPU 30.

[0050] The advantage provided by this disclosure is that the regulated power from the processing circuitry (e.g., a microcontroller or SoC), internal voltage regulator, to the off-chip crystal oscillator does not require the addition of dedicated nodes for this purpose. This preserves the flexibility of GPIO development to cover different applications in the general market.

[0051] This is achieved through a combination of software and hardware control that allows the power connection of the internal voltage regulator to share the same node between digital / analog connections of other microcontroller embedded IPs. This control logic, depending on the software / hardware configuration, implements the required functionality by appropriately controlling general-purpose inputs / outputs (GPIOs) and ensuring no contention / short circuits occur on the shared node. More specifically, power coupling or connections are routed using analog inputs provided by the microcontroller's GPIOs.

[0052] This disclosure therefore provides software control bits (analog_en or analog_en1) to enable / disable power connections for external crystal oscillators.

[0053] This disclosure also provides for gating the power enable (e.g., software control bits) of such crystal oscillator Xosc using digital control logic (e.g., logic 132) according to the required node configuration (e.g., analog and digital modes for power connection).

[0054] Therefore, one or more embodiments can thus provide a processing system, particularly a microcontroller for general-purpose applications or SoCs, comprising:

[0055] 1. An oscillator controller circuit that, for example, provides an oscillator signal (e.g., Xosc_cl) to a clock controller 13 included in the processing system to generate a system clock, such an oscillator controller circuit including at least a node for coupling an external crystal oscillator;

[0056] 2. An internal voltage regulator (voltage regulator 12 or voltage regulator 12' within the oscillator controller 11) coupled to the digital voltage supply node provides regulated power as output;

[0057] 3. General purpose input / output (GPIO) circuitry coupled to a common input / output node, comprising:

[0058] a) Analog circuitry including at least one switch configured to couple at least one analog link of the processing system to the common input / output node under the control of a general-purpose input / output controller; and

[0059] b) A digital input / output circuit, comprising input digital circuitry and output digital circuitry, the input digital circuitry and output digital circuitry being coupled to a common input / output node and shared by multiple digital circuits of the processing system under the control of the general-purpose input / output controller.

[0060] The system includes a power-coupled analog switch configured to selectively couple regulated power to the common input / output node in response to a control signal issued by a general-purpose input / output controller.

[0061] In one or more embodiments, the general-purpose input / output controller is configured to control the switch based on an external oscillator power enable signal issued by the control logic of the clock controller.

[0062] In one or more embodiments, an external crystal oscillator is coupled to the at least one node for coupling the external crystal oscillator via its signal output and to the common input / output node via its power input, and control logic is configured to issue an external oscillator power enable signal, enabling the general-purpose input / output controller to issue a control signal to close the analog switch and issue a disable signal to the input digital circuitry and output digital circuitry of the digital input / output circuit.

[0063] In one or more embodiments, an external crystal oscillator is coupled to at least one node for coupling the external crystal oscillator via its signal output and to an external voltage source via its power input, and control logic is configured to issue an external oscillator power enable signal, enabling the general-purpose input / output controller to issue a control signal to close the analog switch and issue corresponding enable signals to input or output to the input digital circuitry and output digital circuitry of the digital input / output circuitry.

[0064] In one or more embodiments, the analog switch (e.g., 141) is included in a general-purpose input / output circuit (circuit 14, wherein the analog switch may also be one of many switches operating on different analog links).

[0065] In one or more embodiments, the analog switch (e.g., switch 111) is included in the oscillator controller circuit, and the general-purpose input / output is configured to issue at least one control signal to at least one switch (e.g., 141') operating on at least one analog link of the analog circuit (40a).

[0066] In one or more embodiments, the device (e.g., a microcontroller-based device) may include a processor system that engages with an input / output node through a system according to one or more embodiments.

[0067] Operating a system according to one or more embodiments may include a method of selectively coupling regulated power to the common input / output node under control signals issued by a general-purpose input / output controller.

[0068] In one or more embodiments, this method includes issuing an external oscillator power enable signal to gate the control signal issued by a general-purpose input / output controller.

[0069] In one or more embodiments, gating the control signal issued by the general-purpose input / output controller by publishing an external oscillator power enable signal includes:

[0070] 1. In analog mode, to share power coupling on common nodes, an external oscillator power enable signal is published, allowing the enable signal to propagate to the corresponding switch; and

[0071] 2. In digital mode, in order to allow digital circuitry to couple to a common node, an external oscillator power enable signal is issued to prevent the enable signal from propagating to the corresponding switch.

[0072] It will be understood that the embodiments are not limited to applications, for example, in the context of consumer applications based on multi-functional microprocessors (especially in RF applications such as home appliances).

[0073] In some embodiments, CPU 30 may include one or more processor circuits or processor cores and one or more memories. In some embodiments, the processor core and memory may be used alone or in various combinations with the illustrated circuitry to provide the functionality of the processing system 10.

[0074] Some embodiments may take the form of or include a computer program product. For example, according to one embodiment, a computer-readable medium is provided that includes a computer program adapted to perform one or more of the methods or functions described above. The medium may be a physical storage medium, such as a read-only memory (ROM) chip, or a disk such as a digital multifunction disc (DVD-ROM), an optical disk (CD-ROM), a hard disk, a memory, or a network or portable media article that will be read by a suitable drive or via a suitable connection (including one or more barcodes or other related codes encoded to be stored on one or more such computer-readable media and readable by a suitable reader device).

[0075] Furthermore, in some embodiments, some or all of the methods and / or functions may be implemented or provided in other ways (e.g., at least in part in firmware and / or hardware, including but not limited to one or more application-specific integrated circuits (ASICs), digital signal processors, discrete circuits, logic gates, standard integrated circuits, controllers (e.g., by executing appropriate instructions, convolution accelerators and including microcontrollers and / or embedded controllers), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and devices employing RFID technology and various combinations thereof).

[0076] For example, one or more embodiments can be applied to situations that occur in other consumer or industrial applications.

[0077] Without affecting the basic principles, details and embodiments may be changed, even significantly, relative to what has been described (by way of example only), without departing from the scope of protection.

[0078] Other embodiments can be provided by combining the various embodiments described above.

[0079] These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but rather as encompassing all possible embodiments and the full scope of equivalents claimed by such claims. Therefore, the claims are not limited by the disclosure.

Claims

1. An integrated circuit, comprising: A clock control circuit that generates a system clock during operation; Multiple circuits, including: A voltage regulator that provides a regulated voltage during operation; Digital circuits; and Analog circuits; and An input / output interface circuit device is coupled to the plurality of circuits and a common input / output node, wherein the input / output interface circuit device selectively couples one of the plurality of circuits to the common input / output node during operation. The input / output interface circuitry is configured to operate in the following modes: Analog mode, wherein the voltage regulator is coupled to the common input / output node to provide the regulated voltage to an external crystal oscillator coupled to the common input / output node; and Digital mode, wherein the digital circuitry is coupled to the common input / output node.

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