Reduced load non-volatile memory interface

Abstract

The storage circuit includes a buffer coupled between a storage controller and a non-volatile memory device. The circuit includes one or more groups of non-volatile memory (NVM) devices, a storage controller to control access to the NVM devices, and a buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals between the NVM devices and the storage controller on a bus, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.

Description

[0001] This application is a divisional application of the same patent application, filed on June 2, 2017, with application number 201780033934.7.

[0002] priority

[0003] This application claims priority to U.S. Application No. 15 / 201,370, filed July 1, 2016, entitled "Loaded Required Novolatile Memory Interface," pursuant to §365(c) of the U.S. Patent Act. This application claims the benefit of that priority application. Technical Field

[0004] In general, the description relates to storage devices, and more specifically, to non-volatile memory interfaces with reduced load.

[0005] Copyright Notice / License

[0006] This patent document disclosure may contain copyrighted material. The copyright holder does not object to any reproduction of the patent document or patent disclosure appearing in the Patent and Trademark Office patent documents or records by any person, but otherwise retains all copyright. This copyright notice applies to all data as described below and to the accompanying drawings, and to any software used in the following description: Copyright Reserved © 2016 Intel Corporation. All rights reserved. 2016,Intel Corporation,All Rights Reserved). Background Technology

[0007] The demand for more storage space and higher throughput for storage devices will continue to grow significantly. Solid-state technology offers numerous performance and technical advantages over traditional spinning disk storage devices, and the use of solid-state drives (SSDs) is increasing. SSD capacities are approaching those of devices manufactured using traditional spinning disk technology, and prices are falling to levels considered more affordable.

[0008] However, capacity is not the only metric of interest for SSDs. Unfortunately, higher-capacity SSDs do not currently offer equivalent performance to lower-capacity drives. Research indicates that mid-capacity SSDs provide the best throughput. SSD storage controllers require a minimum number of memory devices or dies to drive the memory channels to non-volatile memory (NVM) devices to keep the command and data buses maximally active and to allow memory dies to be accessed in parallel. Increasing the number of memory dies on a memory channel ultimately reduces overall throughput performance when the increased capacitive load necessitates a reduction in the clock frequency on the bus between the controller and the NVM devices. For a single memory channel, system designers have traditionally had to choose between high bandwidth and low capacity or low bandwidth and high capacity.

[0009] Because trade-offs are typically considered regarding individual channels, the usual solution is to add more memory channels and configure them all for higher bandwidth and lower capacity. However, adding more channels increases the size of the controller, as well as the die and package size of the SSD itself. The increased controller size and package size increase cost. Attached Figure Description

[0010] The following description includes a discussion of the accompanying drawings, which are given by way of example of implementations of the invention. The drawings should be understood by way of example (not by way of limitation). As used herein, references to one or more "embodiments" should be understood as describing a particular feature, structure, and / or characteristic included in at least one embodiment of the invention. Thus, phrases such as "in one embodiment" or "in an alternative embodiment" appearing herein describe various embodiments and implementations of the invention and do not necessarily refer to the same embodiment. However, they are not necessarily mutually exclusive.

[0011] Figure 1 This is a block diagram of an embodiment of a computer system in which a non-volatile storage device includes a buffer.

[0012] Figure 2 This is a block diagram of an embodiment of a system with a solid-state drive, the solid-state drive including a buffer between a controller and a non-volatile memory device.

[0013] Figure 3 This is a block diagram of an embodiment of a storage system with a data buffer.

[0014] Figure 4 This is a block diagram of an embodiment of a data buffer with trainable host-side and memory-side interfaces.

[0015] Figure 5 This is a block diagram of an embodiment of a storage system having a data buffer and a command buffer.

[0016] Figure 6 This is a block diagram of an embodiment of a storage system with cascaded data buffers.

[0017] Figure 7A This is a flowchart of an embodiment of a process for accessing data in a multi-level memory.

[0018] Figure 7B This is a flowchart of an embodiment of a process for handling read access requests in a system with highly compressible tags.

[0019] Figure 7C This is a flowchart of an embodiment of a process for handling write access requests in a system with highly compressible tags.

[0020] Figure 8 This is a block diagram of an embodiment of a computing system having a multi-level memory in which highly compressible marking can be implemented.

[0021] Figure 9 This is a block diagram of an embodiment of a mobile device having a multi-level memory in which highly compressible marking can be implemented.

[0022] The following is a description of certain details and implementation methods, including a description of the accompanying drawings, which may depict some or all of the embodiments described below, as well as other potential embodiments or implementations of the inventive concept presented herein. Detailed Implementation

[0023] As described herein, the memory circuitry includes a buffer coupled between a memory controller and non-volatile memory (NVM) devices. The circuitry includes one or more groups of NVM devices and a memory controller for controlling access to the NVM devices. The buffer reduces the electrical load on the bus from the NVM devices to the memory controller. The buffer is used to redrive signals on the bus, including synchronizing signals to a clock signal used for the signals. The circuitry may include a data buffer, a command buffer, or both. The reduced load allows for increased density of NVM devices or memory dies. As described herein, the memory circuitry can be high-bandwidth and high-capacity without adding channels.

[0024] Even in higher-capacity systems, reduced load achieves higher throughput performance. Therefore, a storage system can include a controller with memory channels having more NVM devices coupled in parallel, where the clock frequency can be kept the same or similar to that of a lower-capacity system due to the lower capacitive load on the memory channels. By increasing the capacity of the channels, the system can include higher capacity with fewer channels, which maintains package size and system form factor. Alternatively, a smaller form factor can be achieved to obtain similar capacity.

[0025] Figure 1 This is a block diagram of an embodiment of a computer system in which non-volatile memory includes buffers. System 100 provides an example of a system including non-volatile memory, such as a laptop computer, server, embedded device, handheld device, or other computer system. Processor 110 represents a processing unit of a host computing platform that executes an operating system (OS) and applications, which may be collectively referred to as a "host". The OS and applications perform operations that cause access to memory or storage devices or both. Processor 110 may include one or more individual processors. Each individual processor may include a single processing unit, a multi-core processing unit, or a combination thereof. A processing unit may be a main processor such as a CPU (Central Processing Unit), a peripheral processor, a GPU (Graphics Processing Unit), or other processors, or a combination thereof.

[0026] System 100 shows memory 122, which represents volatile memory in system 100. Volatile memory is memory whose state (and therefore the data stored thereon) is indeterminate if the power to the device is interrupted. NVM 112 is non-volatile memory, which refers to memory whose state is deterministic even if the power to the device is interrupted. Dynamically volatile memory requires refreshing the data stored in the device to maintain its state. Dynamically volatile memory is commonly used as system main memory for storing code and data to be executed by processor 110. NVM 132 does not need to be refreshed.

[0027] Processor 110 accesses memory (or memory device) 122 via memory controller 120, which represents one or more memory controller circuits or devices, including control logic that generates memory access commands in response to operations performed by processor 110. In one embodiment, memory controller 120 is integrated with processor 110 (e.g., an integrated memory controller (iMC)). In one embodiment, memory 122 includes a device directly mounted on the motherboard or host system platform of a computing device (e.g., a PCB (printed circuit board) on which processor 110 is mounted). In one embodiment, memory 122 may be organized as a memory module, such as a dual in-line memory module (DIMM).

[0028] Memory 122 may be or include dynamically volatile memory, such as DRAM (Dynamic Random Access Memory), or a variant such as Synchronous DRAM (SDRAM). Memory device 122 may include various memory technologies, such as DDR3 (Double Data Rate version 3, the original version of which was released by JEDEC (Joint Electron Device Engineering Committee) on June 27, 2007, currently version 21), DDR4 (DDR version 4, the initial specification was released by JEDEC in September 2012), DDR4E (DDR version 4 extension, currently under discussion by JEDEC), LPDDR3 (Low Power DDR version 3, JESD209-3B, released by JEDEC in August 2013), LPDDR4 (Low Power Double Data Rate (LPDDR) version 4, JESD209-4, initially released by JEDEC in August 2014), WIO2 (Wide I / O... 2 (WideIO2), JESD229-2 (originally released by JEDEC in August 2014), HBM (High Bandwidth Memory, JESD235, originally released by JEDEC in October 2013), DDR5 (DDR version 5, currently under discussion by JEDEC), LPDDR5 (currently under discussion by JEDEC), HBM2 (HBM version 2, currently under discussion by JEDEC) or other memory technologies, or combinations of memory technologies, and technologies derived from or extended based on such specifications.

[0029] Processor 110 accesses NVM (or NVM device) 132 via storage controller 130, which represents one or more storage controller circuits or devices. Storage controller 130 includes control logic that generates storage transactions to NVM 132 in response to commands executed by processor 110. A transaction refers to a memory access operation, such as a read or write, which may include a sequence of commands and data exchange, and may occur over multiple transfer cycles (clock or unit interval (UI)). Such a transaction may be accessing data to place it in memory 122 or in the cache of processor 110, or both. Storage controller 130 includes scheduling logic and command logic for generating commands. Storage controller 130 may include or access buffers or temporary storage devices for holding data for reading or writing.

[0030] NVM 132 may be or include non-volatile memory devices, such as block-addressable memory devices, such as NAND or NOR technologies. NVM 132 may include device technologies such as three-dimensional cross-point (3DXP) memory devices, other byte-addressable non-volatile memory devices, or memory devices using chalcogenide phase change materials (e.g., chalcogenide glasses). In one embodiment, the memory device may be or include multi-threshold NAND flash memory, NOR flash memory, single-level or multi-level phase change memory (PCM) or phase change memory with switches (PCMS), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) including memristor technology, or spin-transfer torque (STT)-MRAM, or a combination of any of the above or other non-volatile memory technologies.

[0031] System 100 may access volatile or non-volatile memory (which may be referred to as "memory" and "storage device" for distinction in the description) or both via one or more memory channels. For example, processor 110 may access memory 122 via one or more memory controllers 120 via one or more memory channels. In one embodiment, processor 110 accesses NVM 132 via one or more memory channels 134. In one embodiment, system 100 may include multiple memory controllers 130. In one embodiment, memory controller 130 includes multiple memory channels to NVM 132. Whether a channel originates from memory controller 120 or memory controller 130, each individual channel is coupled to buses and signal lines that are coupled in parallel to multiple devices. Each channel is independently operable. Therefore, each channel is accessed and controlled independently, and timing, data transfer, command and address exchange, and other operations are separate for each channel. As used herein, coupling may refer to electrical coupling, communication coupling, physical coupling, or a combination thereof. Physical coupling may include direct contact. Electrical coupling includes interfaces or interconnections that allow current flow between components or signaling between components, or both. Communication coupling includes connections that enable components to exchange data, including wired or wireless connections.

[0032] In one embodiment, storage controller 130 represents an ASIC (Application-Specific Integrated Circuit) or other controller on a solid-state drive (SSD). Thus, storage controller 130 may be coupled to processor 110 via one or more other control circuitry in processor 110 or in a chipset that interconnects storage resources to processor 110. Storage controller 130 may be referred to as an SSD controller. In one embodiment, NVM 132 includes devices responsive to volatile memory device command protocols (e.g., the DDR4 protocol). In one embodiment, controller 130 supports memory command protocols and command protocols for buffer 140, which enables channel 134 to couple multiple NVM devices 132 to buffer 140 in a tree network (rather than a point-to-point network).

[0033] Buffer 140 represents a buffering device on channel 134 that reduces the load on the memory channel. For example, in a point-to-point network, channel 134 experiences significant load when more NVM devices 132 are coupled to the channel. As a buffered channel, the I / O (input / output) hardware of the storage controller 130 only sees the load on buffer 140, and buffer 140 re-drives the signals on channel 134 to the NVM devices 132. Therefore, buffer 140 can act as a load shear and repeater between the storage controller 130 and the NVM 132.

[0034] As briefly mentioned, channel 134 can be considered to support two command protocols. The first command protocol is a memory command protocol for sending commands to NVM 132. The second command protocol is a command protocol for buffer 140, which enables control over the operation of the buffer. In one embodiment, the memory controller 130 first sends a memory command (e.g., on a command / address bus, which may be referred to as a C / A bus or an ADD / CMD bus, or other names). In such an embodiment, the memory controller 130 sends a command to buffer 140 on the buffer command bus, and sends such a command after sending it to NVM 132. In one embodiment, channel 134 may organize the command protocol via scheduling timing to ensure that memory channel protocol timing is satisfied.

[0035] For example, consider a scenario where channel 134 operates according to the DDR4 protocol to engage with a 3DXP memory device as NVM 132. By controlling the scheduling of command signals to the 3DXP memory device and buffer 140, memory controller 130 can ensure that channel 134 conforms to the DDR4 protocol timing used for exchanging data with memory controller 130, and to the extent that differences exist in the 3DXP protocol timing. Such protocol timing compliance does not necessarily require modification of the 3DXP device and can enable a DDR4-compliant data buffer to be used as buffer 140 (e.g., reusing the data buffer of an LRDIMM (Load-Decreased Dual In-line Memory Module)). As an alternative to timing control of command signals, buffer 140 can be designed with logic that is potentially tolerant of both protocol timings. Such logic can affect write and read latency in a DIMM implementation of system 100, where NVM device 132 is mounted in one or more DFMMs.

[0036] In one embodiment, channel 134 supports both the host interface (with respect to channel 134 coupled to storage controller 130) and the memory interface (with respect to NVM 132) of training buffer 140. In one embodiment, support for the two command protocols discussed above may be necessary for enabling training of both interfaces. In one embodiment, channel 134 may write a fixed pattern into a register (e.g., a multipurpose register (MPR)) of buffer 140, enabling buffer 140 to compare read data with a fixed pattern of the NVM used for read-latency training. Thus, storage controller 130 and buffer 140 can train the host interface, and the storage controller can write data into buffer 140, which the buffer can use to train the timing of the memory interface. It should be understood that in embodiments where the protocols are different, the memory interface or the hardware connecting buffer 140 and NVM 132 may implement the host interface, where timing is adjusted by buffer commands to also conform to the NVM 132 protocol.

[0037] In one embodiment, system 100 supports the use of cascaded tree structures or other types of trees to couple multiple buffers 140 and multiple groups of NVM devices 132. As an example, consider the following reference... Figure 6 The following description is provided. In one embodiment, regarding the timing of different protocols, the storage controller 130 can control the timing of command signals to achieve longer data transfer bursts, even in cases where different data bursts are applied to memory devices or protocols. The following is about... Figure 3 More details were provided.

[0038] Figure 2This is a block diagram of an embodiment of a system with a solid-state drive (SSD) that includes a buffer between a controller and a non-volatile memory device. System 200 includes a host 210 coupled to an SSD 230. System 200 is based on... Figure 1 System 100 provides an example of a system. Host 210 represents a host hardware platform connected to SSD 230. Host 210 includes CPU (Central Processing Unit) 212 or other processor. CPU 212 represents any host processor that generates requests for accessing data stored on SSD 230, for reading data or writing data to memory or both. Host 210 includes chipset 214, which represents other hardware components that may be included in the connection between CPU 212 and SSD 230. For example, chipset 214 may include drives and other logic or circuitry to provide access to SSD 230. In one embodiment, chipset 214 includes a storage controller, which is a host-side controller separate from controller 240 within SSD 230.

[0039] On one side of the dashed line, host 210 illustrates components of the hardware platform selection for host 210. On the other side of the dashed line, host 210 illustrates one embodiment of the logical layer of host 210. In one embodiment, host 210 includes host OS 222, which represents a host operating system or software platform for the host. CPU 212 may execute host OS 222 and provide a software platform on which applications, services, agents, or other software execute. File system 224 represents control logic for controlling access to SSD 230. File system 224 may manage what address or memory location is used to store what data. Many known file systems exist, and file system 224 may implement known file systems or other proprietary systems. In one embodiment, file system 224 is part of host OS 222. Drive 226 represents a system-level module for controlling hardware. In one embodiment, drive 226 includes software applications for controlling the hardware of SSD 230.

[0040] SSD 230 represents a solid-state drive that includes an NVM device 272 for storing data and a buffer 260 for coupling the NVM device 272 to a controller 240. The controller 240 controls access to the NVM device 272. In one embodiment, the controller 240 represents a storage controller according to any embodiment described herein. In one embodiment, the storage controller 240 is an application-specific integrated circuit (ASIC). The controller 240 includes a host interface 242 for coupling directly or via other hardware components to a CPU 212. The controller 240 includes an NVM interface 246 for engaging with the NVM device 272. The host interface 242 and the NVM interface 246 may represent hardware components for engaging with signal lines to interconnect devices, and software or firmware components for controlling the interfaces. In one embodiment, the interface may be controlled via a state machine or other logic. Such logic may be implemented in hardware, software, or a combination thereof.

[0041] Firmware 244 controls the hardware interface to enable communication. In one embodiment, firmware 244 includes at least a portion of logic that can be considered as host interface 242 or NVM interface 246 or both. In one embodiment, firmware 244 provides a sequence of commands to NVM device 272 and can control the timing of the command sequence. SSD 230 includes buffer 260, which represents a buffer according to any embodiment described herein, reducing the loading of NVM device 272 on memory channels in SSD 230. In one embodiment, firmware 244 controls the timing of commands to buffer 260 to control data transfer to NVM device 272 for write transactions or data transfer from NVM device 272 for read transactions.

[0042] Controller 240 includes a scheduler 252 for scheduling operations such as command generation and transmission or data transfer for data access transactions. In one embodiment, scheduler 252 includes one or more queues for buffering operation sequences. In one embodiment, controller 240 includes error control logic 254 for handling data errors in the accessed data and cornering situations in relation to signaling and communication integration.

[0043] SSD 230 includes one or more buffers 260. In one embodiment, buffer 260 represents a data buffer that buffers and re-drives data signals for read or write transactions. In one embodiment, buffer 260 includes a command buffer that buffers and re-drives command signals. It should be understood that a common implementation of system 200 will benefit more from data buffering than from command buffering because there are typically multiple data transfer cycles for each command. Even so, it should be understood that command buffering can also be performed in addition to data buffering.

[0044] In one embodiment, one or more buffers 260 are data buffer components with a modified purpose, such as data buffers used in volatile memory DIMM solutions. In one embodiment, one or more buffers 260 reuse DDR4 LRDIMM data buffer DDR4DB02(DB) components. In one embodiment, buffer 260 acts as a repeater for signals. Buffer 260 can be considered as a load reduction agent or proxy for host 210. Buffer 260 can provide load reduction for NVM device 272. In one embodiment, controller 240 engages with NVM device 272 at speed or with a modified interface of a conventional volatile memory interface. Even when reusing known data buffers, system 200 is configured differently from conventional volatile memory systems that include load buffering. For example, the interface to NVM device 272 will be different, at least in that one or more timings will be controlled differently from typical volatile memory interfaces. In one embodiment, in addition to re-driving signals from or to the NVM device 272 (e.g., data signals or command signals or both), the buffer 260 may also re-timing signals. Re-timing may include synchronizing signals to a strobe signal or a clock signal.

[0045] In one embodiment, NVM devices 272 are organized into one or more device groups 270. A group 270 of NVM devices 272 includes multiple devices. NVM devices 272 may be or include packaged devices. NVM devices 272 may be or include circuit dies, which may be directly mounted on a circuit board or packaged with multiple dies per I / C (integrated circuit) package. In one embodiment, an SSD 230 includes a buffer 260 for every N NVM devices 272 in a group 270, such as eight or sixteen devices. In one embodiment, an SSD 230 includes multiple NVM resource boards, each board having a data buffer 260 and an NVM device group 270. In one embodiment, such boards may be coupled in a tree network to hierarchically layer buffers.

[0046] In one embodiment, NVM device 272 and buffer 260 support data transmission in bursts. A data burst comprises a specified burst length (BL) number of unit intervals for data transmission, wherein each transmission cycle or unit interval includes one bit from each signal line of the memory interface. A data access transaction includes a data access request, in response to a data access command issued by controller 240, which is associated with consecutive bit bursts on each signal line of the data interface across multiple transmission cycles. Therefore, an implementation of buffer 260 as a data buffer will receive a bit stream for memory access transactions.

[0047] In embodiments where burst lengths are used, a mismatch may exist between the BL configuration of data buffer 260 and the BL configuration of NVM device 272. For example, consider data buffer 260 configured to buffer 8 cycles of data bits, or configured for BL8, and NVM device 272 configured for BL16 data access transactions. In one embodiment, controller 240 issues a back-to-back request or command, and data buffer 260 receives the same command twice. In another embodiment, in response to receiving the same consecutive commands, data buffer 260 treats the command as a single command with twice the burst length. For example, for consecutive commands for data transfer, where data buffer 260 treats the command as a BL8 command, the data buffer can treat two requests as a single BL16 command. Other burst lengths are possible.

[0048] In one embodiment, group 270 includes a plurality of DIMMs, each DIMM having a plurality of NVM devices. In one embodiment, a memory channel may be considered as a plurality of buffers 260 coupled to a multipoint bus. In one embodiment, in a multipoint scenario with a plurality of DIMMs (or other groups for group 270) and a plurality of buffers 260, there will be a group 270 that is the target of a command, wherein the target is to store data for reading or to store data for writing. Other groups 270 will be non-target groups 270. In one embodiment, non-target groups 270 terminate transmitted signals to reduce signal reflection, which improves the signal quality of the target group 270. In one embodiment, termination includes synchronous termination. In one embodiment, buffer 260 includes a counter for counting transmitted pulses to ensure good termination and performance.

[0049] As described, in one embodiment, system 200 includes one or more groups 270 of NVM devices 272. Each group 270 may include multiple NVM devices 272. Storage controller 240 controls or manages reads and writes to the NVM devices 272. One or more buffers 260 (e.g., one buffer per group 270) are coupled between storage controller 240 and NVM device groups 270. In one embodiment, buffers 260 are on the data bus and redrive data signals on the data bus and synchronize the data signals to a clock signal. SSD 230 may include multiple buffers 260 and groups 270.

[0050] Figure 3 This is a block diagram of an embodiment of a storage system with a data buffer. System 300 illustrates an example of a storage controller and NVM device according to an embodiment of either System 100 or System 200. In one embodiment, System 300 represents an SSD. Controller 310 represents a storage controller. System 300 includes groups 320[0] to 320[N-1], which may be simply referred to as group 320 or multiple groups 320 for convenience. Each group 320 includes multiple NVM devices 322. In one embodiment, each group 320 includes the same number of NVM devices 322, but such a configuration may not be necessary for some implementations.

[0051] System 300 includes data buffers corresponding to each group 320. Therefore, system 300 is shown having data buffers 330[0] to 330[N-1], which correspond to groups 320[0] to 320[N-1] respectively. Similar to group 320, for convenience, data buffers 330[0] to 330[N-1] may be simply referred to as data buffer 330 or multiple data buffers 330.

[0052] The lines interconnecting controller 310 to data buffer 330 and group 320 represent signal lines for memory channels of system 300. In one embodiment, a memory channel includes a command and address (C / A) bus, wherein address information is typically included in one or more information fields provided with command information. The address identifies the memory location to which a memory transaction indicated by the command should be applied. The C / A bus is represented by lines with long dashes. The memory channel of system 300 includes a data (DQ) bus, which enables data to be transferred from controller 310 to NVM device 322 for writing and data to be transferred from NVM device 322 to controller 310 for reading. The data bus is represented by solid lines. In one embodiment, a memory channel includes a buffer command bus (represented as BUF in system 300, but it may be specified by a different label). The buffer command bus is represented by a dashed line.

[0053] System 300 provides reduced load to the memory channels at controller 310, enabling high-bandwidth and high-capacity SSD implementations without adding memory channels. In one embodiment, a data bus is coupled from controller 310 to data buffer 330, which can adjust the DQS (Data Stochastic Strobe) and DQ (Data) signals to account for propagation delays to / from controller 310 and NVM device 320 or between controller 310 and NVM device 320. In one embodiment, buffer 330 can adjust the DQS and DQ data signals to account for voltage variations, temperature variations, process variations, or combinations thereof.

[0054] In one embodiment, a clock signal used for transmitting C / A signals may be coupled to data buffer 330. Data buffer 330 may re-time data signals and synchronize data signal transmission based on the timing of clock signals used for commands in system 300. Command and address information, along with the clock, may be coupled to group 320 of NVM device 322. In one embodiment, controller 310 controls the timing of signals to data buffer 330 via a buffer command bus. For example, based on the timing of signals to data buffer 330 and the timing of the transaction itself, controller 310 may enable system 300 to conform to one or more protocols.

[0055] In one embodiment, controller 310 sends a back-to-back data access command to NVM device 322, which interprets the back-to-back data access command as a single command of double the length. Data buffer 330 can buffer data between controller 310 and NVM device 322, enabling the transmission of data from two consecutive blackouts (BLs) as a single BL. For example, in one embodiment, data buffer 330 supports the DDR4 protocol configured for BL8, and NVM device 322 includes a 3DXP device operating according to the 3DXP protocol configured for BL16. In one embodiment, data buffer 330 transmits 16 bytes instead of 8 bytes. In one embodiment, data buffer 330 can internally skip the second command and continue bursting data of a second burst length (e.g., first transmitting 8 bytes and then continuing with a second 8 bytes) without pausing the loop. In addition to NVM device 322 treating twice the amount of data signal as a single transaction, the data buffer may also be triggered to operate for twice the number of BL loops.

[0056] It should be understood that the data buffer 330 provides a different function than the passive switches used in NAND SSDs, which fan out SSD write data to selected memory dies. As described herein, the data buffer 330 can broadcast data to all connected dies. In one embodiment, the NVM device 322 follows fixed write and read protocols with timing and latency, such as deterministic data transfer. Conventional NAND devices follow the ONFI (Open NAND Flash Interface) protocol, which traditionally waits for data to be ready before transmission. The ONFI protocol does not provide deterministic data transfer. As described herein, NAND NVM devices can be used with the data buffer 330 to provide load-reduced data transfer.

[0057] In one embodiment, controller 310 sends command and address data to NVM device 322 before sending a buffer command signal to data buffer 330. In one embodiment, the buffer command signal may be referred to as one or more control signals that trigger data buffer 330 to transmit data signals to associated group 320 of NVM device 322. In another embodiment, the buffer command signal may be referred to as one or more control signals that trigger data buffer 330 to transmit data signals to associated group 320 of NVM device 322. In one embodiment, the buffer command signal may synchronize the data signals to a transmission cycle of clock signals from command and address and clock information. In one embodiment, data buffer 330 may synchronize the data signals to the protocol timing of the interface of NVM device 322. In another embodiment, data buffer 330 may synchronize the data signals to the protocol timing of the storage controller interface.

[0058] Figure 4 This is a block diagram of an embodiment of a data buffer with trainable host-side and memory-side interfaces. System 400 illustrates components of a storage system according to embodiments of system 100, system 200, or system 300. System 400 includes a controller 410, which represents a storage controller. System 400 includes an NVM device 460, which represents non-volatile media.

[0059] System 400 specifically illustrates input / output (I / O) interface logic 412 in controller 410, which interfaces the storage controller with data buffer 430, and more specifically, with I / O interface logic 432. I / O interface logic 432 represents a host-side or host-facing interface for data buffer 430, while I / O interface logic 412 represents a memory-side or memory-facing interface for controller 410. Data buffer 430 includes I / O interface logic 434 for interface with NVM device 460, and more specifically, with I / O interface logic 462. I / O interface logic 462 represents a host-side or host-facing interface for NVM device 460, while I / O interface logic 434 represents a memory-side or memory-facing interface for data buffer 430. For convenience, the I / O interface logic can be simply referred to as I / O in this article, such as I / O 412, I / O 432, I / O 434 and I / O 462.

[0060] Signal line 420 represents a signal line or one or more buses that couple controller 410 to data buffer 430. Signal line 450 represents a signal line or one or more buses that couple data buffer 430 to NVM device 460. Buses may include at least one or a combination of command signal lines, data signal lines, strobe signal lines, alarm lines, auxiliary lines, or other signal lines. It should be understood that system 400 shows a data bus buffered by data buffer 430. The command bus may also be buffered by a command buffer (not explicitly shown), or may be coupled to NVM device 460 (not explicitly shown) in a point-to-point network.

[0061] I / O interface logic may include pins, pads, connectors, signal lines, traces, or wires, or other hardware for connecting devices, or combinations thereof. I / O interface logic may include a hardware interface. As shown, I / O interface logic may at least include drivers / transceivers for signal lines (420, 450) to drive the signal lines to a desired voltage level. Typically, wires within an integrated circuit interface are coupled to pads, pins, or connectors to engage signal lines, traces, or other wires between devices. I / O interface logic may include drivers, receivers, transceivers, or terminals, or other circuitry or combinations thereof, to exchange signals on signal lines between devices. Signal exchange includes at least one of sending or receiving.

[0062] Controller 410 is shown to include scheduler 414, which represents logic within the controller for controlling the timing of sending command signals to NVM 460. Although command signal lines are not explicitly shown in system 400, the controller sends commands to NVM 460 for data access. In one embodiment, controller 410 sends buffer commands to a separate data buffer 430 from the data access commands and can control how the data buffer 430 processes the data associated with the data access commands.

[0063] Data buffer 430 is shown as including one or more buffers 442, which represent data buffers for enabling data transfer with reduced load between controller 410 and NVM 460. In one embodiment, write data enters data buffer 430 via I / O 432 and is placed in buffer 442. Data buffer 430 transmits write data out of I / O 434 in response to one or more command signals or one or more clock signals or both. In one embodiment, data buffer 430 includes timing control 444 for adjusting the timing of the data signal. Therefore, data buffer 430 can re-timing the data signal based on the control logic of timing control 444 in response to a command or clock signal or both, which enables data buffer 430 to ensure that the memory channel conforms to one or more protocols. For reading data, in one embodiment, NVM 460 sends read data to data buffer 430, which receives it via I / O 434 and places it in buffer 442. Timing control 444 can represent timing control for sending read data from buffer 442 to controller 410 via I / O 432. Timing control 444 enables data buffer 430 to provide a deterministic high-speed memory interface. In one embodiment, system 400 may include a 3DXP NVM 460 operating at DDR4 frequencies. Timing control 444 ensures that the interface with controller 410 operates according to DDR4 signals while also conforming to the 3DXP timing protocol used for interfacing with NVM 460.

[0064] It should be understood that I / O interfaces 412, 432, 434, and 462 exchange signals by driving signal lines 420 and 450 to desired logic levels, such as driving the signal lines to a low voltage threshold for "0" or a logic low level, and driving the signal lines to a high voltage threshold for "1" or a logic high level. The voltage threshold may vary depending on the implementation, but typically there is a signal eye, defined as a signal that can be correctly decoded on the other side, wherein the eye includes the threshold high or low level, and the threshold rise and fall times. As understood in the art, various configuration settings can affect the signal eye, such as voltage levels, current levels, temperature, delays used for driving and receiving signals, and other settings. I / O interfaces typically participate in "handshakes" or other configuration processes used to train the signal eye. Training the signal eye refers to adjusting configuration settings to achieve signal transmission under the condition of a maximum threshold error per time period.

[0065] It should be understood that, given the different timings expected by different protocols, and given the different electrical characteristics that occur depending on the burst length or the type of signal being transmitted, the signal eye training can be different for different protocols. In one embodiment, components of system 400 include a training state machine for executing one or more training routines, and may include registers or other storage locations for storing variables or configuration settings determined by the training routines. In one embodiment, different training routines can be used to train data buffer 430 to ensure that data buffer 430 conforms to both host-side and memory-side memory channel protocols. For example, data buffer 430 can be trained for DDR4 timing for host-side switching and 3DXP timing for memory-side switching.

[0066] In one embodiment, data buffer 442 includes one or more registers 446, which may be or include multipurpose registers (MPRs). In one embodiment, controller 410 writes data to one or more registers 446 for training. In one embodiment, data buffer 430 applies data from registers 446 to train the interface with NVM 460. Data buffer 430 may iteratively apply different configuration settings to the data to find configuration settings that provide threshold performance (e.g., data transmission with a maximum number of errors per time period or per transmission cycle). Configuration settings may include at least one timing setting for timing controller 444. In one embodiment, training using the timing applied to data buffer 430 can re-drive write data according to protocol timing for NVM 460 or NVM 460's I / O interface logic 462. In one embodiment, training using the timing applied to data buffer 430 can re-drive read data according to protocol timing for controller 410 or controller 410's I / O interface logic 412.

[0067] Figure 5 This is a block diagram of an embodiment of a storage system having a data buffer and a command buffer. System 500 illustrates an example of a storage controller and NVM device according to an embodiment of either or both of system 100 or system 200. System 500 may provide an example of a system according to system 300. In one embodiment, system 500 represents an SSD. Controller 510 represents a storage controller. System 500 includes groups 520[0] to 520[N-1], which may be simply referred to as group 520 or multiple groups 520 for convenience. Each group 520 includes multiple NVM devices 522. In one embodiment, each group 520 includes the same number of NVM devices 522, but such a configuration may not be necessary for some implementations.

[0068] System 500 includes data buffers corresponding to each group 520. Therefore, system 500 is shown having data buffers 530[0] to 530[N-1], respectively corresponding to groups 520[0] to 520[N-1]. Similar to group 520, for convenience, data buffers 530[0] to 530[N-1] may be simply referred to as data buffer 530 or multiple data buffers 530. In one embodiment, system 500 includes command buffers 540[0] to 540[N-1], respectively corresponding to groups 520[0] to 520[N-1]. For convenience, command buffers 540[0] to 540[N-1] may be simply referred to as command buffer 540 or data command buffer 540.

[0069] The lines interconnecting controller 510 to data buffer 530, command buffer 540, and group 520 represent signal lines for memory channels of system 500. For simplicity, only command and data signal lines are specified in system 500. In one embodiment, a memory channel includes command and address (C / A) buses, as shown in CMD or command bus diagrams, represented by lines with dashes. The memory channel of system 500 includes a data (DQ) bus that implements the transfer of data from controller 510 to NVM device 522 for writing and from NVM device 522 to controller 510 for reading. The data bus is represented by solid lines. In one embodiment, system 500 will include one or more buffer command buses connected to data buffer 530, command buffer 540, or both.

[0070] System 500 provides reduced loading of memory channels for the data bus and command bus. In one embodiment, the data bus is coupled from controller 510 to data buffer 530, which can adjust the DQS (data strobe) and DQ (data) signals to account for propagation delay, voltage variation, temperature variation, process variation, or a combination thereof. In one embodiment, the command bus is coupled from controller 510 to command buffer 540, which can adjust command timing to account for propagation delay or one or more variations.

[0071] In one embodiment, controller 310 sends command and address data to NVM device 322 before sending a buffer command signal to data buffer 330. In one embodiment, the buffer command signal may be referred to as one or more control signals that trigger data buffer 330 to transmit data signals to associated group 320 of NVM device 322. In one embodiment, the buffer command signal may be referred to as one or more control signals that trigger data buffer 330 to transmit data signals from associated group 320 of NVM device 322. In one embodiment, the buffer command signal may synchronize the data signals to a transmission cycle of clock signals from command and address and clock information. In one embodiment, data buffer 330 may synchronize the data signals to protocol timing of the interface of NVM device 322. In one embodiment, data buffer 330 may synchronize the data signals to protocol timing of the storage controller interface.

[0072] Figure 6This is a block diagram of an embodiment of a storage system with cascaded data buffers. System 600 illustrates an example of a storage controller and NVM device according to any one or both of embodiments of system 100 or system 200. System 600 may provide an example of a system according to system 300. System 600 illustrates how to manufacture ultra-high capacity non-volatile storage devices or ultra-high capacity SSDs.

[0073] Controller 610 represents a storage controller for a storage system. System 600 includes multiple layers of data buffers. While different structures can be used, more than two layers of data buffers can be used, and System 600 illustrates a tree structure in which data buffers can be organized hierarchically. Thus, one or more data buffers can be coupled to downstream data buffers on the “memory-side interface.” For example, data buffer 620[0] is downstream coupled to data buffers 630[0] through 630[N-1]. For convenience, data buffers 620[0] through 620[N-1] and data buffers 630[0] through 630[N-1] can be simply referred to as data buffer 620 or multiple data buffers 620 or data buffer 630 or multiple data buffers 630, respectively. According to an embodiment of System 600, one or more data buffers can be coupled to upstream data buffers on the “host-side interface” instead of being directly coupled to controller 610. For example, data buffer 630 is upstream coupled to data buffer 620[0]. Data buffers 620[N-1] and 620[1] to 620[N-2] can also be understood as being coupled to one or more NVM device groups. In one embodiment, one or more of the data buffers 620 can be directly coupled to the NVM device group without an intermediate data buffer layer such as data buffer 630. Therefore, the cascading arrangement or tree structure of system 600 is flexible.

[0074] System 600 includes groups 640[0] to 640[N-1], which may be simply referred to as group 640 or multiple groups 640 for convenience. Each group 640 includes multiple NVM devices 642. In one embodiment, each group 640 includes the same number of NVM devices 642, but such a configuration may not be necessary for some implementations. For simplicity of description, only the data bus (DQ) between controller 610 and NVM devices 642 is shown in system 600. It should be understood that system 600 includes appropriate command and address buses, control buses, or combinations thereof necessary for exchanging control and commands related to exchanging data on the data bus. Data exchange occurs in response to data access commands. Data exchange is controlled by the control operations of data buffers 630 and 620.

[0075] In one embodiment, multiple data buffers 620 may be cascaded in a daisy chain on a PCB, or in a multi-ganged PCB circuit (e.g., one or more jumper boards having coupling to one or more connectors). Cascading of system 600 enables very high-capacity solid-state storage systems with performance similar to or the same as conventional SSDs without adding memory channels to controller 610. It should be understood that adding data buffers introduces some latency, and adding multiple layers of data buffers adds additional latency. However, the latency added by buffer layers is small (e.g., 1.6 ns), and the reduced load allows for increased frequency operation, which tends to compensate for more than just the added latency in the data buffers. The scheduling and issuance of commands to NVM device 642 (and other NVM devices not specifically shown), as well as the scheduling and issuance of commands including buffer control signals, can adjust for the latency introduced by data buffers 620 and 630.

[0076] Figure 7A This is a flowchart of an embodiment of a process for accessing data in a multi-level memory. Process 700 provides an example of an operation for issuing a write request to an NVM storage device according to an embodiment of a data storage system such as System 100, System 200, etc., the NVM storage device having a buffered data bus in a memory channel. The host executes processes and operations to generate a write request for storing data to the NVM storage device, 702. In one embodiment, the storage controller generates and schedules the operation to complete the write, 704. A write refers to a write transaction in which the storage controller sends one or more commands to the NVM device and sends data to write to a specific memory address. The data for writing is sent during multiple transfer cycles.

[0077] In one embodiment, as the first part of a write transaction, the storage controller sends command and address information to the NVM device, 706. Sending the command and address information can be done before data begins arriving at the NVM device. In one embodiment, the storage controller sends write data to a data buffer, 708, and sends control signals to the data buffer, 710, after sending the command and address information to the NVM device. The control signals configure the data buffer to transfer data to the NVM device. The control signals may be or include buffer commands or sequences of buffer commands.

[0078] In one embodiment, at least in part in response to a control signal from the storage controller, the data buffer retims a data signal, 712. The retiming of the data signal may include adjusting delays, signaling parameters, or other retimings to conform the data signal to a protocol. In one embodiment, retiming includes synchronizing the data signal to a clock signal associated with timings used with an NVM device (e.g., a memory-side interface). In one embodiment, the NVM device operates on a native protocol different from the native protocol of the storage controller's interface with the host. The data buffer transmits write data to the NVM device according to timings, 714.

[0079] In one embodiment, the storage controller provides a buffer command for each data access command sent to the NVM device. In another embodiment, the storage controller sends multiple consecutive buffer commands for each data access command sent to the NVM device. In one embodiment, the NVM device expects 2N transfer cycles of data for writing, and the data buffer typically sends N data transfer cycles in response to the command. In such an embodiment, consecutive commands can cause the data buffer to send 2N transfer cycles of data to the NVM device as a single command transaction. In one embodiment, the data buffer can internally eliminate any latency between the first N transfer cycles and the second N transfer cycles of data.

[0080] Figure 7B This is a flowchart of an embodiment of a process for handling read access requests in a system with highly compressible tags. Process 720 provides an example of an operation for issuing a read request to an NVM storage device according to an embodiment of a data storage system such as System 100, System 200, etc., the NVM storage device having a buffered data bus in a memory channel. 722. The host executes processes and operations to generate a read request for accessing data from the NVM storage device. In one embodiment, the storage controller generates and schedules an operation to complete the read, 704. A read refers to a read transaction in which the storage controller sends one or more commands to the NVM device, and in response to the commands, the NVM device sends data from a specific memory address to the storage controller for provision to the host. The data for the read is sent over multiple transfer cycles.

[0081] In one embodiment, as the first part of a read transaction, the storage controller sends command and address information to the NVM device, 726. Sending the command and address information can be done before the data buffer is ready to transfer data from the NVM device to the storage controller. In one embodiment, the NVM device sends the read data to the data buffer, 728, and after sending the command and address information to the NVM device, sends a control signal to the data buffer, 730. The control signal configures the data buffer to transfer data from the NVM device to the storage controller. The control signal can be or includes a buffer command or a sequence of buffer commands.

[0082] In one embodiment, at least in part in response to a control signal from the storage controller, the data buffer retimes a data signal, 732. The retimed data signal may include adjusting delays, signaling parameters, or other retimes to conform the data signal to a protocol. In one embodiment, retime includes synchronizing the data signal to a clock signal used for timing associated with the storage controller (e.g., a host-side interface). In one embodiment, the NVM device operates on a native protocol different from the native protocol of the storage controller's interface with the host. The data buffer transmits read data to the storage controller according to the timing, 734.

[0083] In one embodiment, the storage controller provides a buffer command for each data access command sent to the NVM device. In another embodiment, the storage controller sends multiple consecutive buffer commands for each data access command sent to the NVM device. In one embodiment, the NVM device sends 2N transfer cycles of data for a single read transaction, and the data buffer typically expects to receive N transfer cycles of data in response to the command. In such an embodiment, consecutive commands can cause the data buffer to receive 2N transfer cycles of data from the NVM device as a single read transaction. In one embodiment, the data buffer can internally eliminate any latency between the first N transfer cycles and the second N transfer cycles of data. In another embodiment, the data buffer transfers data to the storage controller as two separate N transfer cycles.

[0084] Figure 7CThis is a flowchart of an embodiment of a process for handling write access requests in a system with high compression tags. Process 740 provides an example of operation for training an interface for a buffer (e.g., a data buffer or command buffer) for an NVM storage system, such as system 100, system 200, etc., according to embodiments of a data storage system having a buffered data bus in a memory channel. In one embodiment, a condition or event causes the initiation of a training sequence, 742. For example, the system can train the I / O interface when a reset condition is met, whether it is the initial boot of the machine or waking from sleep or low-power mode. In one embodiment, the storage system trains both the host-side interface and the memory-side interface of the buffer. Timing parameters can be different on the host side and the memory side, especially when a different protocol than the storage controller of the management channel is used in the NVM device.

[0085] In one embodiment, the storage controller generates training data for the host interface of the buffer, 744. In one embodiment, the data buffer configures I / O settings for the host interface, 746, which may include setting one or more values ​​controlling the timing of signals between the storage controller and the data buffer. The storage controller may iteratively send the training data and evaluate the performance of transactions, 748, and determine if there are other configuration settings to be tested against the I / O interface, 750. If more settings are to be evaluated, 750 in the YES branch, the data buffer configures the I / O settings for another data transfer, 746. If the last configuration setting has been evaluated, 750 in the NO branch, then in one embodiment, the data buffer maintains the configuration settings for the I / O interface that provide the best performance for the evaluated configuration settings, 752.

[0086] In one embodiment, the storage controller first trains the host-side interface of the data buffer and then trains the memory-side interface. However, the order can be reversed, or the two training sessions can occur at substantially the same time. In one embodiment, the storage controller generates training data for the memory interface of the data buffer, 754. The training data can be the same data used to train the host-side interface or different data. In one embodiment, the storage controller can write a fixed data pattern to registers on the data buffer via the host interface, and the data buffer can then use the fixed data pattern to train the memory interface of the data buffer. In one embodiment, the data buffer configures I / O settings for the memory interface similar to the configuration used to train the host interface, 756. The data buffer can iteratively send training data to the VM device on the memory interface and evaluate the performance of transactions, 758, and determine if there are other configuration settings to test for the I / O interface, 760. If there are more settings to evaluate, 760 (YES branch), the data buffer configures I / O settings for another data transfer, 756. If the final configuration settings have been evaluated, 760 No branch, then in one embodiment, the data buffer holds the configuration settings for the I / O interface settings that provide the best performance for the evaluated configuration settings, 762.

[0087] Figure 8 This is a block diagram of an embodiment of a computing system having a multi-level memory in which highly compressible tags can be implemented. System 800 represents a computing device according to any embodiment described herein and may be a laptop computer, desktop computer, server, gaming or entertainment control system, scanner, copier, printer, routing or switching equipment, embedded computing device, or other electronic device.

[0088] System 800 includes a processor 810, which provides processing, operation management, and instruction execution for system 800. Processor 810 may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware for providing processing for system 800, or a combination of processors. Processor 810 controls the overall operation of system 800 and may be or include one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations of such devices.

[0089] In one embodiment, system 800 includes an interface 812 coupled to a processor 810, which may represent a higher-speed or high-throughput interface for system components requiring higher bandwidth connectivity, such as a memory subsystem 820 or a graphics interface component 840. Interface 812 may represent a "northbridge" circuit, which may be a standalone component or integrated onto the processor die. A graphical interface 840 is coupled to the graphics component for providing a visual display to a user of system 800. In one embodiment, the graphical interface 840 generates the display based on data stored in memory 830 or based on operations performed by the processor 810, or both.

[0090] Memory subsystem 820 represents the main memory of system 800 and provides storage for code to be executed by processor 810 or data values ​​to be used in execution routines. Memory subsystem 820 may include one or more memory devices 830, such as read-only memory (ROM), flash memory, one or more random access memories (RAM), or other memory devices, or combinations of such devices. Memory 830 stores and hosts operating system (OS) 832, etc., to provide a software platform for executing instructions in system 800. Additionally, applications 834 can execute from memory 830 on the software platform of OS 832. Applications 834 represent programs with their own operational logic to perform one or more functions. Process 836 represents an agent or routine that provides auxiliary functions to OS 832 or one or more applications 834 or combinations thereof. OS 832, applications 834, and process 836 provide logic for providing functionality to system 800. In one embodiment, memory subsystem 820 includes memory controller 822, which is a memory controller for generating and issuing commands to memory 830. It should be understood that the memory controller 822 may be a physical part of the processor 810 or a physical part of the interface 812. For example, the memory controller 822 may be an integrated memory controller that is integrated into the circuitry having the processor 810.

[0091] Although not specifically shown, it should be understood that system 800 may include one or more buses or bus systems between devices, such as memory buses, graphics buses, interface buses, etc. Buses or other signal lines can communicatively or electrically couple components together, or both communicatively and electrically. Buses may include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuitry or combinations thereof. Buses may include one or more of the following: system bus, peripheral component interconnect (PCI) bus, HyperTransport or Industry Standard Architecture (ISA) bus, small computer system interface (SCSI) bus, universal serial bus (USB), or Institute of Electrical and Electronics Engineers (IEEE) standard 1394 bus (commonly referred to as "Firewire").

[0092] In one embodiment, system 800 includes interface 814, which may be coupled to interface 812. Interface 814 may be a lower-speed interface compared to interface 812. In one embodiment, interface 814 may be a "southbridge" circuit, which may include individual components and integrated circuits. In one embodiment, multiple user interface components or peripheral components, or both, are coupled to interface 814. Network interface 850 provides system 800 with the ability to communicate with remote devices (e.g., servers or other computing devices) on one or more networks. Network interface 850 may include an Ethernet adapter, wireless interconnect component, USB (Universal Serial Bus), or other wired or wireless standards-based or proprietary interfaces. Network interface 850 may exchange data with remote devices, which may include sending data stored in memory or receiving data to be stored in memory.

[0093] In one embodiment, system 800 includes one or more input / output (I / O) interfaces 860. I / O interfaces 860 may include one or more interface components through which a user interacts with system 800 (e.g., audio, alphanumeric, haptic / touch, or other interaction). Peripheral interfaces 870 may include any hardware interfaces not specifically mentioned above. Peripheral devices generally refer to devices that depend on a connection to system 800. A dependent connection is a connection between a software platform or hardware platform, or both, on which system 800 provides operation for performance and user interaction.

[0094] In one embodiment, system 800 includes a storage subsystem 880 for storing data in a non-volatile manner. Storage subsystem 880 includes an NVM storage device 884, which can be or include any solid-state memory device enabling access over high-speed memory channels. Storage device 884 retains code or instructions and data 886 in a persistent state (i.e., values ​​are preserved despite power interruption of system 800). Storage device 884 can be genetically considered "memory," but memory 830 is typically execution or operational memory used to provide instructions to processor 810. While storage device 884 is non-volatile, memory 830 may include volatile memory (i.e., the value or state of data is indeterminate if power to system 800 is interrupted).

[0095] In one embodiment, the storage subsystem 880 includes a controller 882 for engaging with the storage device 884. In one embodiment, the controller 882 may be storage control circuitry attached to either the interface 814 or the processor 810, or may include circuitry or logic from both the processor 810 and the interface 814. In one embodiment, the storage subsystem 880 includes a buffer 890, which represents a buffer for a memory channel of the storage system according to any embodiment described herein. The buffer 890 may represent a data buffer or a buffer for command and address signals, or both. According to any embodiment described herein, the buffer 890 retiming signals between the controller 882 and the NVM storage device 884.

[0096] Power source 802 provides power to the components of system 800. More specifically, power source 802 is typically coupled to one or more power supply units 804 within system 802 to provide power to the components of system 800. In one embodiment, power supply unit 804 includes an AC-to-DC adapter for insertion into a wall socket. Such AC power may be a renewable energy source (e.g., solar power) 802. In one embodiment, power source 802 includes a DC power source, such as an external AC-to-DC converter. In one embodiment, power source 802 or power supply unit 804 includes wireless charging hardware for charging via proximity charging. In one embodiment, power source 802 may include an internal battery or fuel cell source.

[0097] System 800 illustrates a cache controller 890 in a memory subsystem 820, representing a cache controller including and using a high-compression flag according to any embodiment described herein. The cache controller 890 can be understood as a portion of a multi-level memory having a cache (not specifically shown) and a memory 830. In one embodiment, the cache controller 890 includes an HC flag on a resource that can be accessed with lower latency compared to a cache database. In one embodiment, the cache controller 890 is integrated on a processor 810 or an interface 812. In one embodiment, the cache controller 890 is a portion of a memory controller 822. According to any embodiment described herein, the cache controller 890 returns an implementation of a memory access request for cached data based at least in part on the value of the high-compression flag.

[0098] Figure 9 This is a block diagram of an embodiment of a mobile device having a multi-level memory in which highly compressible tags can be implemented. Device 900 represents a mobile computing device, such as a computing tablet, mobile phone or smartphone, wireless-enabled e-reader, wearable computing device or other mobile device or embedded computing device. It should be understood that some components of the components are shown in general, and not all components of such a device are shown in device 900.

[0099] Device 900 includes a processor 910, which performs the main processing operations of device 900. Processor 910 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing unit. The processing operations performed by processor 910 include the execution of an operating platform or operating system on which applications and device functions are executed. Processing operations include operations related to I / O (input / output) of human users or other devices, operations related to power management, operations related to connecting device 900 to another device, or combinations thereof. Processing operations may also include operations related to audio I / O, display I / O, or other engagement or combinations. Processor 910 can execute data stored in memory. Processor 910 can write to or edit data stored in memory.

[0100] In one embodiment, system 900 includes one or more sensors 912. Sensor 912 represents an embedded sensor or an interface or combination to an external sensor. Sensor 912 enables system 900 to monitor or detect one or more conditions of the environment or device in which system 900 is implemented. Sensor 912 may include environmental sensors (e.g., temperature sensors, motion detectors, light detectors, cameras, chemical sensors (e.g., carbon monoxide, carbon dioxide, or other chemical sensors)), pressure sensors, accelerometers, gyroscopes, medical or physiological sensors (e.g., biosensors, heart rate monitors, or other sensors for detecting physiological attributes), or other sensors, or combinations thereof. Sensor 912 may also include sensors for biometric systems, such as fingerprint recognition systems, facial detection or recognition systems, or other systems for detecting or identifying user characteristics. Sensor 912 should be broadly understood and is not limited to the many different types of sensors that can be implemented with system 900. In one embodiment, one or more sensors 912 are coupled to processor 910 via front-end circuitry integrated with processor 910. In one embodiment, one or more sensors 912 are coupled to processor 910 via another component of system 900.

[0101] In one embodiment, device 900 includes an audio subsystem 920, which represents hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components associated with providing audio functionality to a computing device. Audio functionality may include speaker or headphone output and microphone input. Devices for such functionality may be integrated into or connected to device 900. In one embodiment, a user interacts with device 900 by providing audio commands received and processed by processor 910.

[0102] Display subsystem 930 represents hardware (e.g., display device) and software components (e.g., drivers) that provide a visual display for presentation to a user. In one embodiment, the display includes a tactile component or touchscreen element for user interaction with a computing device. Display subsystem 930 includes display interface 932, which includes a specific screen or hardware device for providing a display to a user. In one embodiment, display interface 932 includes logic separate from processor 910 (e.g., graphics processor) for performing at least some of the processing related to the display. In one embodiment, display subsystem 930 includes a touchscreen device that provides both input and output to a user. In one embodiment, display subsystem 930 includes a high-definition (HD) display that provides output to a user. High-definition can refer to a display with a pixel density of approximately 100 PPI (pixels per inch) or greater, and can include formats such as Full HD (e.g., 1080p), Retina display, 4K (Ultra-High Definition or UHD), or other formats. In one embodiment, display subsystem 930 generates display information based on data stored in memory and operations performed by processor 910.

[0103] I / O controller 940 represents the hardware devices and software components associated with user interaction. I / O controller 940 can operate to manage hardware that is part of audio subsystem 920 or display subsystem 930, or both. Additionally, I / O controller 940 shows connection points for other devices connected to device 900 through which the user can interact with the system. For example, devices that can be attached to device 900 may include microphone devices, speakers or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I / O devices (e.g., card readers or other devices) for use with a particular application.

[0104] As mentioned above, the I / O controller 940 can interact with the audio subsystem 920 or the display subsystem 930, or both. For example, input via a microphone or other audio device can provide input or commands to one or more applications or functions of the device 900. Additionally, audio output can be provided in place of or attached to display output. In another example, if the display subsystem includes a touchscreen, the display device also acts as an input device, which can be managed at least partially by the I / O controller 940. Additional buttons or switches may also be present on the device 900 to provide I / O functionality managed by the I / O controller 940.

[0105] In one embodiment, I / O controller 940 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, gyroscopes, global positioning systems (GPS), or other hardware or sensors 912 that may be included in device 900. Inputs may be part of direct user interaction or may provide environmental inputs to the system to affect its operation (e.g., filtering noise, adjusting the display for brightness detection, applying a flash for a camera, or other features).

[0106] In one embodiment, device 900 includes power management 950 that manages battery power usage, battery charging, and features related to power-saving operation. Power management 950 manages power from power source 952, which supplies power to the components of system 900. In one embodiment, power source 952 includes an AC-to-DC adapter for plugging into a wall socket. Such AC power can be renewable energy (e.g., solar, motion-based power). In one embodiment, power source 952 includes only DC power, which can be provided by a DC power source, such as an external AC-to-DC converter. In one embodiment, power source 952 includes wireless charging hardware for charging via proximity charging. In one embodiment, power source 952 can include an internal battery or fuel cell source.

[0107] The memory subsystem 960 includes a memory device 962 for storing information in the device 900. The memory subsystem 960 may include non-volatile memory 996 (whose state does not change if power to the memory device is interrupted) or volatile memory device 962 (whose state is indeterminate if power to the memory device is interrupted) or a combination thereof. The memory 960 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions of the system 900. In one embodiment, the memory subsystem 960 includes a memory controller 964 (which may also be considered part of the control of the system 900 and potentially part of the processor 910). The memory controller 964 includes a scheduler for generating and issuing commands to control access to the memory device 962.

[0108] In one embodiment, the memory subsystem 960 includes an NVM controller 992, which includes a scheduler for generating and issuing commands to control access to the NVM 996. In one embodiment, the memory subsystem 960 includes a buffer 994, which represents a buffer for a memory channel of the memory system according to any embodiment described herein. The buffer 994 may represent a data buffer or a buffer for command and address signals, or both. According to any embodiment described herein, the buffer 944 retiming signals between the NVM controller 992 and the NVM 996.

[0109] Connection 970 includes hardware devices (e.g., wireless or wired connectors and communication hardware, or a combination of wired and wireless hardware) and software components (e.g., drivers, protocol stacks) that enable device 900 to communicate with external devices. External devices can be standalone devices, such as other computing devices, wireless access points or base stations, and peripherals such as headsets, printers, or other devices. In one embodiment, system 900 exchanges data with external devices for storage in memory or display on a display device. The exchanged data may include data to be stored in memory, or data already stored in memory, for reading, writing, or editing.

[0110] Connection 970 can include various different types of connections. In general, device 900 is shown as having cellular connection 972 and wireless connection 974. Cellular connection 972 typically refers to a cellular network connection provided by a wireless operator, such as a connection provided via GSM (Global System for Mobile Communications) or its variants or derivatives, CDMA (Code Division Multiple Access) or its variants or derivatives, TDM (Time Division Multiplexing) or its variants or derivatives, LTE (Long Term Evolution – also known as “4G”), or other cellular service standards. Wireless connection 974 refers to a non-cellular wireless connection and can include a personal area network (e.g., Bluetooth), a local area network (e.g., WiFi), or a wide area network (e.g., WiMax) or other wireless communications or combinations thereof. Wireless communication refers to the transmission of data over a non-solid medium using modulated electromagnetic radiation. Wired communication occurs over a solid communication medium.

[0111] Peripheral connection 980 includes hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) for making peripheral connections. It should be understood that device 900 can be either a peripheral device to other computing devices (“to” 982) or a peripheral device connected to it (“from” 984). Device 900 typically has a “dock” connector to connect to other computing devices for purposes such as managing (e.g., downloading, uploading, changing, synchronizing) content on device 900. Additionally, the dock connector can allow device 900 to connect to certain peripheral devices that allow device 900 to control (e.g., to audiovisual or other systems) content output.

[0112] In addition to proprietary docking connectors or other proprietary connection hardware, device 900 can also be peripherally connected 980 via public or standards-based connectors. Common types may include Universal Serial Bus (USB) connectors (which may include any of several different hardware interfaces), DisplayPort including Mini DisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0113] System 900 illustrates a cache controller 990 in a memory subsystem 960, representing a cache controller including and using a high-compression flag according to any embodiment described herein. The cache controller 990 can be understood as a portion of a multi-level memory having a cache (not specifically shown) and memory 962. In one embodiment, the cache controller 990 includes an HC flag on resources that can be accessed with lower latency compared to a cache data repository. In one embodiment, the cache controller 990 is integrated on a processor 910. In one embodiment, the cache controller 990 is a portion of a memory controller 964. The cache controller 990 returns an implementation of a memory access request for cached data based at least in part on the value of a high-compression flag according to any embodiment described herein.

[0114] In one aspect, a system for data storage includes: a group of non-volatile memory (NVM) devices; a storage controller coupled to the NVM device group, the storage controller being used to manage reads and writes to the NVM devices; and a data buffer coupled on a data bus between the NVM device group and the storage controller, the data buffer being used to redrive data signals on the data bus and synchronize data signals to clock signals.

[0115] In one embodiment, the storage controller is configured to first send a command signal to the NVM device group and then send a control signal to the data buffer, wherein the control signal is used to trigger the data buffer to transmit data signals to the NVM device group. In one embodiment, the NVM devices are configured to operate in burst mode to transmit data over 2N cycles, and the data buffer is configured to operate to transmit data over N cycles, wherein the storage controller is configured to issue continuous commands to the data buffer to cause the data buffer to operate within 2N cycles in response to the continuous commands. In one embodiment, the data buffer is configured to internally eliminate pause cycles to generate continuous data transmission over 2N cycles in response to the continuous commands. In one embodiment, the data buffer includes a host interface to the storage controller and a memory interface to the NVM device group, wherein the data buffer is configured to apply different configuration settings for the host interface and the memory interface, wherein the different configuration settings include at least different timing configuration settings. In one embodiment, the data buffer is configured to re-drive data signals from the storage controller to the NVM devices, including synchronizing the data signals to the protocol timing of the NVM device interface. In one embodiment, the data buffer is configured to re-drive data signals from the NVM devices to the storage controller, including synchronizing the data signals to the protocol timing of the storage controller interface. In one embodiment, the NVM device group includes a first group and a data buffer includes a first data buffer, and also includes a second NVM device group and a second data buffer coupled between the second NVM device group and the storage controller. In one embodiment, a third data buffer is further included, wherein the first and second groups are cascaded and coupled to the storage controller, and the third data buffer is coupled between the storage controller and the first and second data buffers. In one embodiment, a command buffer is further included, coupled on a command bus between the NVM device group and the storage controller, the command buffer being used to redrive command signals on the command bus and synchronize command signals to a clock signal. In one embodiment, one or more of the following are also included: at least one processor communicatively coupled to the storage controller; a memory controller communicatively coupled to the storage controller; a display communicatively coupled to at least one processor; a battery for powering the system; or a network interface communicatively coupled to at least one processor.

[0116] In one aspect, a solid-state drive (SSD) includes: a storage controller including an interface for coupling to a host processor, the storage controller for managing read and write requests from the host processor; and a plurality of storage circuits coupled to the storage controller, the plurality of storage circuits including: a plurality of non-volatile memory (NVM) devices; and a data buffer coupled on a data bus between the plurality of NVM devices and the storage controller, the data buffer for re-driving data signals on the data bus and synchronizing the data signals to a clock signal.

[0117] In one embodiment, the storage controller is configured to first send a command signal to the NVM device group and then send a control signal to the data buffer, wherein the control signal is used to trigger the data buffer to transmit data signals to the NVM device group. In one embodiment, the NVM devices are configured to operate in burst mode to transmit data over 2N cycles, and the data buffer is configured to operate to transmit data over N cycles, wherein the storage controller is configured to issue continuous commands to the data buffer to cause the data buffer to operate within 2N cycles in response to the continuous commands. In one embodiment, the data buffer is configured to internally eliminate pause cycles to generate continuous data transmission over 2N cycles in response to the continuous commands. In one embodiment, the data buffer includes a host interface to the storage controller and a memory interface to the NVM device group, wherein the data buffer is configured to apply different configuration settings for the host interface and the memory interface, wherein the different configuration settings include at least different timing configuration settings. In one embodiment, the data buffer is configured to re-drive data signals from the storage controller to the NVM devices, including synchronizing the data signals to the protocol timing of the NVM device interface. In one embodiment, the data buffer is configured to re-drive data signals from the NVM devices to the storage controller, including synchronizing the data signals to the protocol timing of the storage controller interface. In one embodiment, multiple storage circuits are organized in a cascaded manner, wherein a first data buffer and a second data buffer are coupled to a first plurality of NVM devices and a second plurality of NVM devices, respectively, and a third data buffer is coupled between the first and second data buffers and the storage controller. In one embodiment, the multiple storage circuits further include a command buffer coupled on a command bus between the NVM device group and the storage controller, the command buffer being used to redrive command signals on the command bus and synchronize command signals to a clock signal.

[0118] In one aspect, a method for data access includes: receiving a buffer command at a buffer coupled between a non-volatile memory (NVM) device group and a storage controller, the buffer command being issued after a data access command is issued to the NVM device group; and in response to receiving the buffer command, re-driving a data signal on a data bus between the NVM device and the storage controller, including synchronizing the data signal to a clock signal.

[0119] In one embodiment, receiving buffer commands includes receiving two consecutive commands, and in response to receiving the two consecutive commands, re-driving two consecutive bursts of data signals into a double-length burst of data signals. In one embodiment, it further includes: retiming data signals to internally eliminate pause loops to generate a double-length burst of continuous data transmission in response to the consecutive commands. In one embodiment, it further includes: training a host interface coupled to the storage controller to configure settings for the host interface; and training a memory interface coupled to the NVM device to configure settings for the memory interface, wherein training the memory interface includes writing a fixed data pattern to registers on the buffer via the host interface. In one embodiment, re-driving data signals on the data bus includes: re-driving write data signals from the storage controller to the NVM device. In one embodiment, re-driving write data signals includes: synchronizing the write data signals to the protocol timing of the interface of the NVM device. In one embodiment, re-driving data signals on the data bus includes: re-driving read data signals from the NVM device to the storage controller. In one embodiment, re-driving read data signals includes synchronizing the read data signals to the protocol timing of the storage controller interface. In one embodiment, re-driving data signals on the data bus includes re-driving write data signals from the storage controller to the NVM device. In one embodiment, the buffer includes a data buffer and further includes: receiving a buffer command at a command buffer coupled between a non-volatile memory (NVM) device group and a memory controller; and, in response to receiving the buffer command, re-driving the data access command on a command bus between the NVM device and the memory controller, including synchronizing the data access command to a clock signal. In one aspect, an apparatus includes units for performing operations for performing a method for data access according to any embodiment of the above methods. In one aspect, an article of manufacture includes a computer-readable storage medium having content stored thereon, the content, when accessed, causing a machine to perform operations to perform a method for data access according to any embodiment of the above methods.

[0120] In one aspect, the buffer device includes: memory interface logic for coupling to a group of non-volatile memory (NVM) devices; host interface logic for coupling to a storage controller for managing reads and writes to the NVM devices; and control logic for re-driving data signals between the NVM devices and the storage controller on a data bus and synchronizing the data signals to a clock signal.

[0121] In one embodiment, the storage controller is configured to first send a command signal to the NVM device group and then send a control signal to the data buffer, wherein the control signal is used to trigger the data buffer to transmit data signals to the NVM device group. In one embodiment, the NVM devices are configured to operate in burst mode to transmit data over 2N cycles, and the data buffer is configured to operate to transmit data over N cycles, wherein the storage controller is configured to issue continuous commands to the data buffer to cause the data buffer to operate within the 2N cycles in response to the continuous commands. In one embodiment, the data buffer is configured to internally eliminate pause cycles to generate 2N continuous data transmission cycles in response to continuous commands. In one embodiment, the data buffer includes a host interface to the storage controller and a memory interface to the NVM device group, wherein the data buffer is applied to a configuration setting of the host interface different from that of the memory interface, wherein the different configuration settings include at least different timing configuration settings. In one embodiment, the data buffer is configured to re-drive data signals from the storage controller to the NVM devices, including synchronizing the data signals to the protocol timing of the NVM device interface. In one embodiment, the data buffer is configured to re-drive data signals from the NVM devices to the storage controller, including synchronizing the data signals to the protocol timing of the storage controller interface. In one embodiment, the NVM device group includes a first group and a data buffer including a first data buffer, and also includes a second NVM device group and a second data buffer coupled between the second NVM device group and the storage controller. In another embodiment, a third data buffer is further included, wherein the first and second groups are cascaded and coupled to the storage controller, and the third data buffer is coupled between the storage controller and the first and second data buffers. In yet another embodiment, a command buffer is further included, coupled on a command bus between the NVM device group and the storage controller, the command buffer being used to redrive command signals on the command bus and synchronize command signals to a clock signal.

[0122] The flowcharts shown herein provide examples of sequences of various process actions. Flowcharts can indicate operations performed by software or firmware routines as well as physical operations. In one embodiment, the flowchart can show the states of a finite state machine (FSM), which can be implemented in hardware, software, or a combination thereof. Although shown in a specific order or sequence, the order of actions can be modified unless otherwise stated. Therefore, the illustrated embodiments should be understood as examples only, and processes can be performed in different orders, and some actions can be performed in parallel. Furthermore, one or more actions may be omitted in various embodiments; therefore, not all actions are necessary in every embodiment. Other processes are possible.

[0123] To the extent described herein, various operations or functions can be described or defined as software code, instructions, configuration, data, or combinations thereof. Content can be directly executable (“object” or “executable” form), source code, or differential code (“incremental” or “patch” code). The software content of the embodiments described herein can be provided via an article of art on which content is stored, or via a method of operating a communication interface to send data via the communication interface. Machine-readable storage media can enable a machine to perform the described functions or operations and includes any mechanism that stores information in a form accessible by a machine (e.g., computing device, electronic system, etc.), such as recordable / non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), disk storage media, optical storage media, flash memory devices, etc.). Communication interfaces include any mechanism that engages with a hardwired, wireless, optical, etc., medium to communicate with another device, such as a memory bus interface, processor bus interface, internet connection, disk controller, etc. Communication interfaces can be configured by providing configuration parameters or sending signals, or both, to prepare the communication interface to provide data signals describing the software content. The communication interface can be accessed via one or more commands or signals sent to it.

[0124] The various components described herein can be units used to perform the described operations or functions. Each component described herein includes software, hardware, or a combination thereof. Components can be implemented as software modules, hardware modules, special-purpose hardware (e.g., application-specific hardware, application-specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, hardwired circuits, etc.

[0125] In addition to the content described herein, various modifications can be made to the disclosed embodiments and implementations of the present invention without departing from its scope. Therefore, the descriptions and examples herein should be interpreted as illustrative rather than restrictive. The scope of the invention should be considered solely by reference to the following claims.

Claims

1. A system for reducing load, comprising: Multiple non-volatile memory (NVM) devices; A storage controller for managing reads and writes to the NVM device; as well as A data buffer, coupled to the storage controller via a host-side data bus interface on a Double Data Rate (DDR) data bus and coupled to the NVM device via a memory-side data bus interface, is used to buffer data between the storage controller and the NVM device. The data buffer is configured to: train the host-side data bus interface for a DDR Double Data Rate protocol between the storage controller and the data buffer; and separately train the memory-side data bus interface for the non-volatile media of the NVM device. The storage controller is configured to: firstly send a command to the NVM device using a command signal and a clock signal, wherein the command signal bypasses the data buffer and the clock signal is provided to the data buffer; and subsequently send a separate control signal to the data buffer to trigger the data buffer to transmit data between the storage controller and the NVM device, wherein the data buffer is configured to transmit the data based on the clock signal.

2. The system as claimed in claim 1, wherein, The storage controller is used to first send a command signal to the NVM device, and then send a control signal to the data buffer, wherein the control signal is used to trigger the data buffer to transmit data to the NVM device.

3. The system as described in claim 1, wherein, The NVM device is configured to operate in burst mode to transmit data over 2N cycles, and the data buffer is configured to operate to transmit data over N cycles, wherein the storage controller is configured to issue continuous commands to the data buffer to cause the data buffer to operate over 2N cycles in response to the continuous commands.

4. The system as described in claim 3, wherein, The data buffer is used to internally eliminate pause cycles in order to generate 2N cycles of continuous data transmission in response to the continuous commands.

5. The system as claimed in claim 1, wherein, The data buffer is used to: apply a first configuration setting to align the data signals on the data signal lines of the host-side data bus interface with the strobe signals of the host-side data bus interface; And apply a second configuration setting to align the data signals on the data signal lines of the memory-side data bus interface with the strobe signals of the memory-side data bus interface.

6. The system as claimed in claim 1, wherein, The data buffer is used to redrive data signals from the storage controller to the NVM device, including protocol timing for synchronizing data to the interface of the NVM device.

7. The system as claimed in claim 1, wherein, The data buffer is used to redrive data signals from the NVM device to the storage controller, including protocol timing for synchronizing data to the storage controller interface.

8. The system of claim 1, wherein, The NVM device includes a first NVM device group and the data buffer includes a first data buffer, and also includes a second NVM device group and a second data buffer coupled between the second NVM device group and the storage controller.

9. The system of claim 8, further comprising a third data buffer, wherein, The first NVM device group and the second NVM device group are coupled to the storage controller in a cascaded manner, wherein the third data buffer is coupled between the storage controller and the first data buffer and the second data buffer.

10. The system of claim 1, further comprising a command buffer coupled on a command bus between the NVM device and the storage controller, the command buffer being configured to redrive command signals on the command bus and synchronize command signals to a clock signal.

11. The system of claim 1, further comprising one or more of the following: At least one processor communicatively coupled to the memory controller; A memory controller, communicatively coupled to the memory controller; A display communicatively coupled to at least one processor; A battery, which is used to power the system; or A network interface that is communicatively coupled to at least one processor.

12. The system of claim 1, wherein, The non-volatile medium includes NAND flash memory.

13. A dual in-line memory module (DIMM), comprising: A storage controller for managing read and write requests to the non-volatile memory of the DIMM; as well as Multiple storage circuits coupled to the storage controller, the multiple storage circuits comprising: Multiple non-volatile memory (NVM) devices; and A data buffer, coupled to the storage controller via a host-side data bus interface on a double data rate data bus, and coupled to the NVM devices via a memory-side data bus interface, is used to buffer data between the storage controller and the plurality of NVM devices. The data buffer is configured to: train the host-side data bus interface for the DDR protocol between the storage controller and the data buffer; and separately train the memory-side data bus interface specifically for the non-volatile media of the plurality of NVM devices. The storage controller is configured to: firstly send a command to the NVM device using a command signal and a clock signal, wherein the command signal bypasses the data buffer and the clock signal is provided to the data buffer; and subsequently send a separate control signal to the data buffer to trigger the data buffer to transmit data between the storage controller and the plurality of NVM devices, wherein the data buffer is configured to transmit the data based on the clock signal.

14. The dual in-line memory module (DIMM) as described in claim 13, wherein, The storage controller is used to first send command signals to the plurality of NVM devices, and then send control signals to the data buffer, wherein the control signals are used to trigger the data buffer to transmit data to the plurality of NVM devices.

15. The dual in-line memory module (DIMM) as described in claim 13, wherein, The data buffer is used to redrive data signals from the storage controller to the plurality of NVM devices, including protocol timing for synchronizing data to the interfaces of the plurality of NVM devices.

16. The dual in-line memory module (DIMM) as described in claim 13, wherein, The data buffer is used to redrive data signals from the plurality of NVM devices to the storage controller, including protocol timing for synchronizing data to the storage controller interface.

17. The dual in-line memory module (DIMM) as described in claim 13, wherein, The plurality of storage circuits are organized in a cascaded manner, wherein a first data buffer and a second data buffer are respectively coupled to a first plurality of NVM devices and a second plurality of NVM devices, and a third data buffer is coupled between the first data buffer and the second data buffer and the storage controller.

18. The dual in-line memory module (DIMM) as described in claim 13, wherein, The plurality of storage circuits also include: A command buffer, coupled on the command bus between the plurality of NVM devices and the storage controller, is used to redrive command signals on the command bus and synchronize command signals to clock signals.

19. The dual in-line memory module (DIMM) as described in claim 13, wherein, The data buffer is used to: apply a first configuration setting to align the data signals on the data signal lines of the host-side data bus interface with the strobe signals of the host-side data bus interface; And apply a second configuration setting to align the data signals on the data signal lines of the memory-side data bus interface with the strobe signals of the memory-side data bus interface.

20. The dual in-line memory module (DIMM) as described in claim 13, wherein, The non-volatile medium includes NAND flash memory.

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